+ .ifge \mhz - 800
+ /* implement workaround for ENGcm12051 */
+ mov r1, #0 @ Disable auto-restart (AREN)
+ str r1, [r2, #PLL_DP_CONFIG]
+
+ ldr r1, =DP_OP_864
+ str r1, [r2, #PLL_DP_OP]
+ str r1, [r2, #PLL_DP_HFS_OP]
+
+ ldr r1, =DP_MFD_864
+ str r1, [r2, #PLL_DP_MFD]
+ str r1, [r2, #PLL_DP_HFS_MFD]
+
+ ldr r1, =DP_MFN_864
+ str r1, [r2, #PLL_DP_MFN]
+ str r1, [r2, #PLL_DP_HFS_MFN]
+
+ ldr r1, =((1 << 2) | 0x1232) @ Set DPLL ON; UPEN=1 BRMO=1 PLM=1
+ str r1, [r2, #PLL_DP_CTL]
+100:
+ ldr r1, [r2, #PLL_DP_CTL] @ Poll LRF
+ tst r1, #(1 << 0)
+ beq 100b
+
+ ldr r1, =60
+ str r1, [r2, #PLL_DP_MFN]
+ str r1, [r2, #PLL_DP_HFS_MFN]
+
+ mov r1, #(1 << 0)
+ str r1, [r2, #PLL_DP_CONFIG] @ Assert LDREQ
+101:
+ ldr r1, [r2, #PLL_DP_CONFIG] @ Poll LDREQ
+ tst r1, #(1 << 0)
+ bne 101b
+
+ mov r1, #4
+ /*
+ * delay for 4 µs
+ * since cache is disabled, this loop is more than enough
+ */
+102:
+ subs r1, r1, #1
+ bne 102b
+ .else
+ ldr r1, =0x1232 @ Set DPLL ON (set UPEN bit); BRMO=1
+ str r1, [r2, #PLL_DP_CTL]
+
+ mov r1, #(1 << 1) @ Enable auto-restart (AREN)
+ str r1, [r2, #PLL_DP_CONFIG]