Liu Ying [Tue, 18 Feb 2014 04:49:32 +0000 (12:49 +0800)]
ENGR00298052-7 ARM: imx6q: remove function imx6q_lvds_cabc_init()
This patch removes the function imx6q_lvds_cabc_init() from the
machine layer since we have a dedicated Hannstar CABC driver to
control the CABC feature.
Liu Ying [Tue, 18 Feb 2014 04:44:35 +0000 (12:44 +0800)]
ENGR00298052-5 ARM: dts: imx6qdl-sabresd: support Hannstar CABC
This patch adds a device tree node for the Hannstar CABC function.
We currently disable the CABC feature since it makes a panel's
backlight unstable when display content varies considerably from
time to time.
Liu Ying [Tue, 18 Feb 2014 02:59:09 +0000 (10:59 +0800)]
ENGR00298052-4 ARM: dts: imx6qdl-sabreauto: support Hannstar CABC
This patch adds a device tree node for the Hannstar CABC function.
The LVDS0 and LVDS1 interfaces of the i.MX6dql Sabreauto platform
shares a control pin for the CABC function, but LVDS1's control
wire is invalid for the unpopulated resistor R265 on the main board.
We currently disable the CABC feature since it makes a panel's
backlight unstable when display content varies considerably from
time to time.
This patch adds Hannstar CABC driver support. The CABC
function turns the backlight density of a display panel
automatically according to the content shown on the panel.
It is controlled(enabled/disabled) by a GPIO.
ENGR00297285-1 [MX6x] Support IRAM page table when DDR is in self-refresh.
Whenever DDR is explicitly put into self-refresh, we need to ensure
that no access are made to the DDR. All the bus masters excpet ARM
are shutdown gracefully.
The ARM core can continue to access the DDR due to:
1. Speculative accesses
This can be prevented by flushing the Branch Target Address Cache
2. Aggressive Prefetching
This can be minimized by adding nops.
Apart from this the TLB architecture in ARM does not guarantee that
an entry remains in the TLB unless its explicitly locked. Even if
free slots are available an entry maybe evicted. So flushing the TLB
does not guarantee a page table walk will not happen.
The solution is to put a minimized page table in IRAM that can be used when
DDR is in self-refresh. The IRAM page tables should have entries for IRAM,
AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR
into self-refresh. It should not contain any entries that point to the DDR.
This patch set accomplishes the following:
1. Set the IRAM to be mapped as 1M sections in the high mem region.
This makes it possible to create entries for the IRAM code in the IRAM page table.
We need to ensure that both the DDR and IRAM page table have mapping for the IRAM code.
2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table.
3. Save TTBR1
4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using
TTBR1 before DDR is put into self-refresh. Ensure the following settings:
a. TTBCR.N = 1
This means the 0-2G virtual address space is translated using TTBR0
and 2G-4G is translated using TTBR1.
b. Set TTBCR.PD0 = 1
With this setting page table walks using TTBR0 are disabled.
4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will
be used for translations now).
5. Restore TTBR1
Even though TTBR1 is only used to decode the top 2G of virtual address
space, ARM requires that we allocate the entire 16KB for the page table.
To minimize IRAM/OCRAM required, we put the code in the bottom 8K and
page table entries in the top 8K.
This requires the low power code be optimized to occupy as little space
as possible.
Richard Zhu [Mon, 10 Feb 2014 06:56:46 +0000 (14:56 +0800)]
ENGR00298392 pcie: imx pcie ep rc msi demo
- add one imx pcie ep simple skeleton driver to demo
the msi trigger capability in imx6 pcie rc/ep validation
system
- in order to avoid the modification of common codes,
force the msi address to be 0x01ff8000
Test howto:
- Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images
- EP side(console command and kernel message):
root@sabresd_6dq:/ # memtool 0x1ff8000=0
Writing 32-bit value 0x0 to address 0x01FF8000
root@sabresd_6dq:/ #
Richard Zhu [Mon, 10 Feb 2014 04:34:33 +0000 (12:34 +0800)]
ENGR00298389 pcie: let rc can access mem of ep
- setup one new outbound memory region at rc side, used
to let imx6 pcie rc can access the memory of imx6 pcie ep
in imx6 pcie rc ep validation system.
- set the default address of the ddr memory to be 0x4000_0000
NOTE:
- default address 0x4000_0000 of ep side would be
accessed in this demo.
Test howto:
step1:
EP side:
1.1:
echo 0x40000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/ep_bar0_addr
1.2:
memtool -32 0x40000000 4
E
Reading 0x4 count starting at address 0x40000000
Peter Chen [Fri, 24 Jan 2014 06:59:30 +0000 (14:59 +0800)]
ENGR00296519 USB: EHCI: wait more than 3ms until the device enters full-speed idle
If the high-speed device does not enter full-speed idle after
wakeup on disconnect logic has effected, there will be an
unexpected disconnect wakeup interrupt due to the bus is still SE0.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Yuanyuan Zhong [Wed, 30 Oct 2013 16:31:49 +0000 (17:31 +0100)]
ARM: 7873/1: vfp: clear vfp_current_hw_state for dying cpu
The CPU_DYING notifier is called by cpu stopper task which
does not own the context held in the VFP hardware. Calling
vfp_force_reload() has no effect.
Replace it with clearing vfp_current_hw_state.
Signed-off-by: Yuanyuan Zhong <zyy@motorola.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 384b38b66947b06999b3e39a596d4f2fb94f77e4)
Huang Shijie [Fri, 24 Jan 2014 07:49:26 +0000 (15:49 +0800)]
ENGR00296510 ARM: dts: imx6qdl-sabreauto: use the gpio5_4 to enable the EIM_D18
The WEIN NOR needs the pin EIM_D18 which is controlled by the steering.
So we have to configurate the EIM_A24 to GPIO, and select the GPIO to LOW
status.
Richard Zhu [Fri, 10 Jan 2014 07:54:26 +0000 (15:54 +0800)]
ENGR00284938 sata: cr-rst workaround sata phy link issues
- add sata phy cr(offset:0x7f3f) reset in sata resume to
workaround imx6q sata kinds of suspend resume link
issues.
- add sata phy cr reset during imx6q sata initialization,
to initialize the sata phy to be an initialized state.
- add about 100us delay between mpll_clk enable and cr-rst,
make sure that the mpll_clk is stable.
- add about 100us delay between cr-rst and waiting for rx_pll
stable too, make sure that the cr-rst is finished.
- change the tx level setting from 1.025v to be the default
value 1.104v
- make sure the sata phy internal pll ref clk enable is
cleared before it is set, otherwise, the sata phy link
maybe failed when some devices are used.
Sandor Yu [Wed, 22 Jan 2014 07:09:37 +0000 (15:09 +0800)]
ENGR00296050 mxsfb: fb failed to work after suspend in console mode
When device boot into console, frame buffer failed to work after
suspend/resume.
That is caused by LCDIF IP lost all registers configuration
in suspend mode, and console didn't reconfiguration fb after resume.
Same issue didn't found with Yocto UI.
Reinitialize frame buffer driver after resume to fix the issue.
Sandor Yu [Wed, 15 Jan 2014 08:50:04 +0000 (16:50 +0800)]
ENGR00295201 ipuv3: vdic: kernel dump when run deinterlace stress test
Kernel will dump when run deinterlace stress test.
It is caused by vditmpbuf being reallocated by another thread
when one thread accesses it.
Issue is fixed by putting these code in mutex.
Sandor Yu [Fri, 27 Dec 2013 09:10:03 +0000 (17:10 +0800)]
ENGR00293488 ipu: vdi: Support more memory type
__va function only can handle frame buffer from low memory.
Use page_address function to replace it, that can handle
frame buffer from both lower and high memory.
Use ioremap_nocache function to handle Frame buffer
from GPU reserve memory pool.
Correct vdi data save buffer size, save both luma and chroma part for
interleaved YUV format.
For non-interleaved and partial-interleaved YUV format,
save luma part data, chroma part is not covered in the patch.
Robin Gong [Tue, 21 Jan 2014 02:41:46 +0000 (10:41 +0800)]
ENGR00295892-1: leds: leds-gpio: keep charger led state while system suspended
gpio-leds driver common framework didn't take care of this case if use CONFIG_OF
, add property "retain-state-suspended" in dts and check it while gpio-leds
device created.
Jay Monkman [Fri, 17 Jan 2014 19:06:46 +0000 (13:06 -0600)]
ENGR00291086 crypto kernel module speed test in single fail
The tcrypt module is used to test the crypto API by being passed a
mode=<value> during module load. The test runs to completion before
insmod/modprobe returns. That makes the RCU stall detection in newer
kernels unhappy.
The simple fix is to add CONFIG_PREEMPT to the kernel config. That's
what this patch does. If that introduces other problems,
crypto/tcrypt.c can be modified to call schedule() in the correct
places. Here's a patch that should work if this one has to be
reverted:
Dong Aisheng [Fri, 17 Jan 2014 02:23:22 +0000 (10:23 +0800)]
ENGR00295564 mmc: sdhci-esdhc-imx: no need busfreq for imx6qdl
The usdhc of i.MX6Q/DL can work well under low power mode without
request high bus freq. So we do not need request bus freq for i.MX6Q/DL.
It can save power for i.MX6D/DL due to it saves a lot busfreq switch
cost as well as the CPU time runing on high bus freq after switch
during low power mode.
A new flag ESDHC_FLAG_BUSFREQ is added to indicated this requirement.
Currently only i.MX6SL is using it.
The root cause of playback slow issue should be trying to get DSPCLK_DIV
before enabling SYSCLK of WM8962. Since we have a patch fixed it, we can
revert this work round.
This reverts commit 49a3ca545a88cdf4aa597c4dd7d904b4faaea555.
Nicolin Chen [Mon, 6 Jan 2014 09:25:09 +0000 (17:25 +0800)]
ENGR00295423-4 ASoC: fsl_ssi: Set the default slot number in startup()
Set a default slot number in startup() so that those who use I2S or other
2-channel DAI format would not need to call set_dai_tdm_slot() in their
machine drivers.
Nicolin Chen [Mon, 6 Jan 2014 08:55:07 +0000 (16:55 +0800)]
ENGR00295423-3 ASoC: fsl_ssi: Don't disable SSIEN if SSI is already enabled
If disabling SSI when SSI is already in the working state, the whole running
substream would be broken. Thus we here replace it to a safer way -- saving
the current SSIEN value and restore it afterward.
This patch also adds a slot number checking code before setting slot number.
Nicolin Chen [Mon, 6 Jan 2014 08:28:51 +0000 (16:28 +0800)]
ENGR00295423-1 ASoC: fsl_ssi: Implement full symmetry for synchronous mode
Since we introduced symmetric_channels and symmetric_samplebits, we can
implement these new feature to SSI synchronous mode and drop the useless
code accordingly.
Nicolin Chen [Wed, 4 Dec 2013 09:22:16 +0000 (17:22 +0800)]
ASoC: wm8962: Enable SYSCLK provisonally before fetching generated DSPCLK_DIV
DSPCLK_DIV can be only generated correctly after enabling SYSCLK. But if the
current bias_level hasn't reached SND_SOC_BIAS_ON, DAPM won't enable SYSCLK,
which would cause the calculation result from DSPCLK_DIV invalid since bit
DSPCLK_DIV will be finally turned to its true value after DAPM enables SYSCLK
while the driver won't calculate it again for the current instance. In this
circumstance, a playback which needs non-zero DSPCLK_DIV would be distorted
due to unexpected clock frequency resulted from an invalid DSPCLK_DIV value.
So this patch provisionally enables the SYSCLK to get a valid DSPCLK_DIV for
calculation and then disables it afterward.
Nicolin Chen [Wed, 20 Nov 2013 10:37:09 +0000 (18:37 +0800)]
ASoC: soc-pcm: move DAIs parameters cleaning into hw_free()
We're now applying soc_hw_params_symmetry() to reject unmatched parameters
while we clear parameters in soc_pcm_close(). So here's a use case might be
broken by this mechanism: aplay -Dhw:0 44100.wav 48000.wav 32000.wav
In this case, we call soc_pcm_open()->soc_pcm_hw_params()->soc_pcm_hw_free()
->soc_pcm_hw_params()->soc_pcm_hw_free()->soc_pcm_close() in order. As we
only clear parameters in soc_pcm_close(). The parameters would be remained
in the system even if the playback of 44100.wav is finished.
Thus, this patch is trying to move parameters cleaning into hw_free() so that
the system can continue to serve this kind of use case.
Also, since we set them in hw_params(), it should be better to clear them in
hw_free() for symmetry.
Nicolin Chen [Wed, 13 Nov 2013 10:56:24 +0000 (18:56 +0800)]
ASoC: soc-pcm: add symmetry for channels and sample bits
Some SoCs can only work in mono or stereo mode at one time. So if
we let them capture a mono stream while playing a stereo stream,
there might be a problem occur to one of these two streams: double
paced or slowed down.
In soc-pcm.c, we have soc_pcm_apply_symmetry() to apply the rate
symmetry. But we don't have one for channels.
Likewise, we can treat symmetric_rate as a solution for those SoCs
or CODECs which can not handle asymmetrical LRCLK. But it's also
impossible for them to handle asymmetrical BCLK. And accodring to
BCLK = LRCLK * channel number * slot size(fixed or sample bits),
sample bits might also be a problem if they are not using a fixed
slot size.
Thus, this patch applys symmetry for channels and sample bits.
Meanwhile, there might be a race between two substreams if starting
simultaneously. Previously, we only added warning to compalin but
still using conservative way to let it carry on. However, this patch
rejects the second stream with any unmatched parameter to make sure
the first existing stream won't be broken.
Loren Huang [Thu, 16 Jan 2014 08:23:37 +0000 (16:23 +0800)]
ENGR00295218-2 gpu: Allow allocate vg memory from small block reserved memory
-Most vg memory must requires reserved memory, when reserved memory is
used up by 3d appliction. vg hardware can't be constructed successfully,
which cause whole context creation failure(including 3d context).
-Allow allocating vg memory from small block reserved memory can help such
multi context cases.
Fabio Estevam [Thu, 5 Dec 2013 07:20:49 +0000 (15:20 +0800)]
usb: chipidea: host: Only disable the vbus regulator if it is not NULL
Commit 40ed51a4b (usb: chipidea: host: add vbus regulator
control) introduced a smatch complaint because regulator_disable() is called
without checking whether ci->platdata->reg_vbus is not NULL.
Fix this by adding the check.
This patch is needed for 3.12 stable
Cc: stable <stable@vger.kernel.org> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit ae93fad5728e08f7cde89f628be2703ad249930d)
Peter Chen [Fri, 10 Jan 2014 05:51:32 +0000 (13:51 +0800)]
usb: chipidea: udc: using MultO at TD as real mult value for ISO-TX
We have met a bug that the high bandwidth ISO-TX transfer has failed
at the last packet if it is less than 1024, the TD status shows it
is "Transaction Error".
The root cause of this problem is: the mult value at qh is not correct
for current TD's transfer length. We use TD list to queue un-transfer
TDs, and change mult for new adding TDs. If new adding TDs transfer length
less than 1024, but the queued un-transfer TDs transfer length is larger
than 1024, the transfer error will occur, and vice versa.
Usually, this problem occurs at the last packet, and the first packet for
new frame.
We fixed this problem by setting Mult at QH as the largest value (3), and
set MultO (Multiplier Override) at TD according to every transfer length.
It can cover both hardware version less than 2.3 (the real mult is MultO
if it is not 0) and 2.3+ (the real mult is min(qh.mult, td.multo)).
Since the MultO bits are only existed at TX TD, we keep the ISO-RX behavior
unchanged.
For stable tree: 3.11+.
Cc: stable <stable@vger.kernel.org> Cc: Michael Grzeschik <m.grzeschik@pengutronix.de> Reported-by: Matthieu Vanin <b47495@freescale.com> Tested-by: Matthieu Vanin <b47495@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 1c91f7e338e24fe86e5dba384337f19e49348430)
Chris Ruehl [Fri, 10 Jan 2014 05:51:30 +0000 (13:51 +0800)]
usb: chipidea: put hw_phymode_configure before ci_usb_phy_init
hw_phymode_configure configures the PORTSC registers and allow the
following phy_inits to operate on the right parameters. This fix a problem
where the UPLI (ISP1504) could not be detected, because the Viewport was not
available and read the viewport return 0's only.
Signed-off-by: Chris Ruehl <chris.ruehl@gtsys.com.hk> Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit fda8a80b7e944ec29f4438d6e6f159f691ae41a6)
Chris Ruehl [Fri, 10 Jan 2014 05:51:29 +0000 (13:51 +0800)]
usb: chipidea: Fix Internal error: : 808 [#1] ARM related to STS flag
* init the sts flag to 0 (missed)
* fix write the real bit not sts value
* Set PORTCS_STS and DEVLC_STS only if sts = 1
[Peter Chen: This one and the next patch fix the problem occurred imx27
and imx31, and imx27 and imx31 usb support are enabled until 3.14, so
these two patches isn't needed for -stable]
Signed-off-by: Chris Ruehl <chris.ruehl@gtsys.com.hk> Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 4cf40dc3d21cd9a482d969d1468fd265ec9921dd)
Dong Aisheng [Fri, 10 Jan 2014 13:31:21 +0000 (21:31 +0800)]
ENGR00295184-2 dts: imx6qdl-sabreauto: use external vmmc for sd3 optionally
SD3.0 cards require power cycle the card during suspend/resume,
or the card re-enumeration after resume will fail to be identified
as UHS card since the card is already working on 1.8v mode and refuse
to ack the S18R request, thus, it will then work on normal high speed
mode instead.
We have to use external vmmc regulator to power cycle the card during
suspend/resume to reset card signal voltage to 3.3v frist for the later
1.8v voltage switch.
However, due to the sabreauto board limitation, we can not use external
regulator to powere off card by default since the card power is shared
with card detect pullup. Disabling the vmmc regulator will also shutdown
the cd pullup which causes incorrect illusion of card exist.
(e.g. plug out the card, mmc core wll think the card is exist since cd pin
is low but it never can find the card)
HW rework removing R695 and enable PAD internal pullup is needed to
fix this isssue.
User can manually open the mask of vmmc in dts to enable using external
regulator if your board has done the rework as said above.
Or by default we still do not power off card during suspend.
Dong Aisheng [Tue, 31 Dec 2013 08:22:44 +0000 (16:22 +0800)]
ENGR00295184-1 mmc: sdhci: do not enable card detect interrupt for gpio cd type
Except SDHCI_QUIRK_BROKEN_CARD_DETECTION and MMC_CAP_NONREMOVABLE,
we also do not need to handle controller native card detect interrupt
for gpio as card detect case.
If we wrong enabled the card detect interrupt for gpio case,
it will cause a lot of unexpected card detect interrupts during data transfer
which should not happen.
Liu Ying [Wed, 8 Jan 2014 07:44:52 +0000 (15:44 +0800)]
ENGR00293505 ARM: dtsi: imx6qdl-sabresd: Change disp id for mipi dsi
Currently, by default, we assign ipu display ports for the following
5 types of display devices on the imx6q sabresd platform in this way:
----------------------------------------
| | ipu | di |
|----------------------------------------|
| ldb channel0 | 1(0 for imx6dl) | 0 |
|----------------------------------------|
| ldb channel1 | 1(0 for imx6dl) | 1 |
|----------------------------------------|
| hdmi | 0 | 0 |
|----------------------------------------|
| mipi dsi | 0 | 0 |
|----------------------------------------|
| parallel output | 0 | 0 |
----------------------------------------
So, the ipu0 di1 display port is not used by any display device.
This patch assigns this unused display port to mipi dsi by default.
Acked-by: Robby Cai <R63905@freescale.com> Cc: Oliver Brown <oliver.brown@freescale.com> Cc: Sandor Yu <R01008@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Loren Huang [Thu, 9 Jan 2014 09:38:37 +0000 (17:38 +0800)]
ENGR00294354 gpu:Using vitural memory cause AXI bus error
There are two possible reasons to cause AXI bus error
1.Allocate Tile status buffer from virtual memory. It seems gc2000
and gc880 doesn't support tile status buffer from virtual memory.
2.Stream buffer using very beginning gpu mmu address. In this condition,
a faked non gpu mmu address maybe generated and fill into gpu which cause
AXI bus error.
Loren Huang [Thu, 9 Jan 2014 09:36:27 +0000 (17:36 +0800)]
ENGR00292154-3 gpu:Adjust logic for non_paged memory cache
non_page memory cache will only be freed when application exit.
It will have waste when contiguous memory used up.
Add logic to free it when contiguous memory is used up.
Loren Huang [Thu, 9 Jan 2014 09:35:07 +0000 (17:35 +0800)]
ENGR00292154-1 gpu:Fix kernel panic when ctrl+c an application
When application is using virtual memory, ctrl+c it will have
kernel panic caused by null pointer.
The reason is hardware struture already is freed when driver wants
to use it.
Loren Huang [Thu, 9 Jan 2014 09:41:50 +0000 (17:41 +0800)]
ENGR00286762 gpu: enable swap rectange and fix a bug
add eglSetSwapRectangleANDROID back and enable swap rectange,
fix a swap rectange bug which will swap whole screen instead
of the indicate swap region if region's left and top is (0,0).
Signed-off-by: Richard Liu <r66033@freescale.com> Acked-by: Shawn Guo
Xianzhong [Thu, 28 Nov 2013 14:37:16 +0000 (22:37 +0800)]
ENGR00289999 gpu: fixed gc880 invalid command state message
gpu kernel dump the error message when enable DEBUG mode:
gckCONTEXT_Update(1493): State 0x0518 is not mapped.
gckCONTEXT_Update(1493): State 0x0520 is not mapped.
gckCONTEXT_Update(1493): State 0x0518 is not mapped.
gckCONTEXT_Update(1493): State 0x0520 is not mapped.
align gpu kernel driver to fix the error message
Signed-off-by: Xianzhong <b07117@freescale.com> Acked-by: Jason Liu
Loren Huang [Thu, 9 Jan 2014 09:03:08 +0000 (17:03 +0800)]
ENGR00284988 gpu:Sync gpu kernel driver code
Sync the code with commit 255ee1de in gpu-viv git.
Mainly covered tickets:
ENGR00288588 fixed system reboot when run webGL test
ENGR00284988 Camera recording kernel crash on WFD source
ENGR00283494 Modify Status to status to avoid build error
ENGR00278179-1 query video memory with seperate types
Fancy Fang [Wed, 8 Jan 2014 02:32:52 +0000 (10:32 +0800)]
ENGR00294114 PXP: correct the PS U/V buffer settings when format is YVU420P
The PXP itself doesn't support YVU420P default. But we can get the
U and V address according to the format when we try to set PS_UBUF
and PS_VBUF registers. So the YVU420P can be supported indirectly.
Terry Lv [Tue, 16 Aug 2011 08:06:24 +0000 (16:06 +0800)]
ENGR00154889-2: Add virtual iim driver
Add virtual iim driver.
This driver will be used by MM team.
Signed-off-by: Terry Lv <r65388@freescale.com>
(cherry picked from commit 6637e480585112bb310fcbd7ccd1cbf1d67cf9ff) Signed-off-by: Robin Gong <b38343@freescale.com>
Peter Chen [Tue, 7 Jan 2014 07:25:26 +0000 (15:25 +0800)]
ENGR00292062 usb: chipidea: need to mask INT_STATUS when write otgsc
For otgsc, both enable bits and status bits are in it. So we need
to make sure the status bits are not be cleared when write enable
bits. It can fix one bug that we plug in/out Micro AB cable fast,
and sometimes, the IDIS will be cleared wrongly when handle last
ID interrupt (ID 0->1), so the current interrupt will not occur.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Fri, 3 Jan 2014 05:45:30 +0000 (13:45 +0800)]
ENGR00292408-2 usb: chipidea: imx: enable different wakeup setting
We have different wakeup setting for different roles:
For peripheral-only mode, we may only enable vbus wakeup.
The Micro-AB cable should not be considered as wakeup source.
For host-only mode, the ID change or vbus change should not be
considered as wakeup source.
For OTG mode, all wakeup setting should be considered as wakeup
source.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Thu, 26 Dec 2013 08:16:44 +0000 (16:16 +0800)]
ENGR00291282-6 usb: phy-nop: add the implementation of .set_suspend
Add clock enable/disable at .set_suspend if the PHY has
suspend requirement, it can be benefit of power saving for
phy and the whole system (parent clock may also be disabled).
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Thu, 26 Dec 2013 08:06:16 +0000 (16:06 +0800)]
ENGR00291282-5 usb: phy-nop: defer clock prepare until PHY init
It can avoid the problem that the prepare count is non-zero even
nop PHY is un-used. In fact, the same operation is already
at the lastest mainline code:
Peter Chen [Tue, 10 Dec 2013 02:17:02 +0000 (10:17 +0800)]
ENGR00291282-3 ARM: imx6q-arm2-hsic: add usb hsic dts
Since hsic has pin conflict with ethernet, we disable ethernet
at this dts. Besides, please make sure the line of data and strobe
has unchanged between board boots up and hsic controller has
benn enabled.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Fancy Fang [Mon, 6 Jan 2014 08:26:52 +0000 (16:26 +0800)]
ENGR00293898 PXP: set the pxp_dispatch kernel thread to be freezable to avoid hang
By default, the kernel thread cannot be freezed during pm suspend.
So during pm suspend, the pxp_dipatch thread is still handling pxp
task and setting pxp registers. And in some time, this pxp register
setting may happen after the pxp_suspend done. So the hang issue
happens. This patch set the thread to be freezable to freeze it
before pxp_suspend called to avoid this hang issue.
Fancy Fang [Wed, 25 Dec 2013 10:04:56 +0000 (18:04 +0800)]
ENGR00293323 PXP: add WC and cacheable dma buffer support for PXP device
This change add support for new dma buffer type(writecombine and cacheable)
which allows user application has more choices for the buffer type. And if
the dma buffer is cacheable, then add flush interfaces to make it cache
coherent when necessary.
Fancy Fang [Wed, 25 Dec 2013 02:03:35 +0000 (10:03 +0800)]
ENGR00293292 PXP: enhance channel and buffer reclaim for PXP device
Enhance channel and buffer reclaim to make sure that all the
allocated resources which are not freed yet to be freed
when the device file descriptor release() function called.
Fancy Fang [Tue, 24 Dec 2013 08:05:53 +0000 (16:05 +0800)]
ENGR00293211 PXP: bind allocated DMA channels to opened device file descriptor
The allocated DMA channels via some opened file descriptor is better
to be bound to this descriptor. Since this can avoid some application
to fake a channel id which may be requested by other applications to
request PXP service. And also, this make it easier to release the dma
channel when application exists abnormally or forgets to release it
explicitly.
Robby Cai [Wed, 25 Dec 2013 07:46:37 +0000 (15:46 +0800)]
ENGR00293132-2 pxp/v4l2: restore smem_start for framebuffer even exit abnormally
Previously, the framebuffer for UI display may only be restored after
STREAMOFF ioctl is called. But sometimes the application may exit abnormally
(without call STREAMOFF) for some reason. Now restore previously-saved
smem_start in release function to make sure it's set correctly, to avoid some
video frame remain.
Robby Cai [Fri, 20 Dec 2013 10:20:47 +0000 (18:20 +0800)]
ENGR00293132-1 pxp/v4l2: change memory alloc policy for PxP output buffer
In previous implementation, the memory allocation/free for PxP output buffer is
done each time v4l2 output device is opened/closed. This is not necessary and
may cause memory fragmentation issue after running many many times. Now we
re-allocate the memory for it only if the existing memory size is not sufficent
for new case.
Ezequiel Garcia [Mon, 25 Nov 2013 11:30:31 +0000 (08:30 -0300)]
mtd: nand: refactor print messages
Add a nice "nand:" prefix to all pr_xxx() messages. This allows
to get rid of the "NAND" words in messages, given the context
is already given by the prefix.
Remove the __func__ report from messages where it's not needed and refactor
the device detection messages to show itself in several lines.
Fancy Fang [Tue, 24 Dec 2013 02:36:17 +0000 (10:36 +0800)]
ENGR00293170 PXP: remove cpu_addr field from struct pxp_mem_desc
The cpu_addr field in struct pxp_mem_desc cannot be used
by user application, so it is not necessary to pass this
field data to user. Now the similar field 'virtual' in
struct pxp_buf_obj is used to store the kernel space
virtual addr for allocated dma buffer.
Liu Ying [Tue, 24 Dec 2013 08:26:35 +0000 (16:26 +0800)]
ENGR00293235 IPUv3: Refine register access
The original IPUv3 driver uses readl()/writel() to
access the IPUv3 registers in the following way where
ipu->reg_base is a pointer which points to a 32 bit
I/O memory cell of a certain IPUv3 deblock's base address:
writel(value, ipu->reg_base + offset);
readl(ipu->reg_base + offset);
This makes the register offset values shrink 4 times,
comparing to the offset values documented in the
reference manual. For example, we need to change the
offset value from 0x003C to 0x003C/4 so that we may
access the register IPU_INT_CTRL_1 correctly.
This patch redefines the type of ipu->reg_base to
'void __iomem *', then the offset values can be the
same to what they are documented.
Also, this patch corrects some register relevant
macros by wrapping their arguments with parentheses
to avoid any unsafe decipher.
Reviewed-by: Robby Cai <R63905@freescale.com> Cc: Oliver Brown <oliver.brown@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Liu Ying [Tue, 24 Dec 2013 08:18:56 +0000 (16:18 +0800)]
ENGR00293231 IPUv3 reg: Remove some unused macros
This patch removes two unused macros IPU_INT_CTRL_IRQ(irq)
and IPU_INT_STAT_IRQ(irq) to save two lines of code. The
existing another two macros IPUIRQ_2_STATREG(irq) and
IPUIRQ_2_CTRLREG(irq) are the surrogates for them.
Reviewed-by: Robby Cai <R63905@freescale.com> Cc: Oliver Brown <oliver.brown@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Fancy Fang [Fri, 20 Dec 2013 10:14:21 +0000 (18:14 +0800)]
ENGR00293119 PXP: change the dma buffer lists management for PXP device
Create pxp_info struct data for each opened device file descriptor.
And bind all the allocated dma buffers to this struct for each opened
file. This makes the dma buffer lists management safer, more effective
and more flexible.
Fancy Fang [Thu, 19 Dec 2013 10:32:42 +0000 (18:32 +0800)]
ENGR00292816 PXP: move two struct definitions to pxp_device.h
Move two struct definitions defined in pxp_device.c to pxp_device.h.
Now the pxp_device.h has been created for PXP device driver. So all
the type definition should stay in header file not c source file.
Luwei Zhou [Mon, 23 Dec 2013 06:09:25 +0000 (14:09 +0800)]
ENGR00293101 hwmon: mma8451: add sys interface to set sensor scale mode.
mma8451 sensor driver on i.MX6Q/DL SabreSD/AUTO doesn't provide the
interface to set sensor scale. The new sys interface name is "scalemode".
The mode is defined as:
MODE_2G : 0, MODE_4G : 1, MODE_8G : 2
Luwei Zhou [Fri, 20 Dec 2013 02:23:39 +0000 (10:23 +0800)]
ENGR00281813 input: mma8450: evbug module will keep print message.
evbug will open the mma8450 on i.MX6SL_EVK and mma8450 will work in 2G mode by default.
That is the reason why mma8450 logs will be printed out. The main changes is below:
* Remove the open(), close() hook out of the drivers. The open() and close()
hook in input framwork is defined as void type. It isn't strictly safe in
logic when some error happends. So remove them out.
* Modify the mma8450 to standby mode by default. It will be more power saving
and there would be no log printing out after booting up.
* Provide the sys interface to modify the mma8450 work modes. Then the higher
layer can modify the the mma8450 work mode via the interface. It would be
much safer.There would be a sclaemode interface in the folder of
/sys/devices/soc0/soc.1/2100000.aips-bus/21a0000.i2c/i2c-0/0-001c/scalemode
User can use cat to read the current scalemode and echo to write. The mode
is defined as: MODE_STANDBY: 0 MODE_2G:1 MODE_4G:2 MODE_8G:3
* Add mutex to protect and some error handling.
Liu Ying [Thu, 19 Dec 2013 05:54:28 +0000 (13:54 +0800)]
ENGR00292775 mipi csi2: Refine register access
The original mipi csi2 driver uses readl()/writel()
to access the 32 bit mipi csi2 registers in the
following way where info->mipi_csi2_base is a pointer
which points to a 32 bit I/O memory cell of the mipi
csi2's base address:
writel(value, info->mipi_csi2_base + offset);
readl(info->mipi_csi2_base + offset);
This makes the register offset values shrink 4 times,
comparing to the offset values documented in the
reference manual. For example, we need to change the
offset value from 0x004 to 0x001 so that we may access
the register MIPI_CSI2_N_LANES correctly.
This patch redefines the type of info->mipi_csi2_base
to 'void __iomem *', then the offset values can be the
same to what they are documented. Also, the macro names
for the registers are aligned to the documentation.
Acked-by: Robby Cai <R63905@freescale.com> Cc: Oliver Brown <oliver.brown@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Eric Dumazet [Thu, 19 Dec 2013 18:53:02 +0000 (10:53 -0800)]
net: fec: fix potential use after free
skb_tx_timestamp(skb) should be called _before_ TX completion
has a chance to trigger, otherwise it is too late and we access
freed memory.
Signed-off-by: Eric Dumazet <edumazet@google.com> Fixes: de5fb0a05348 ("net: fec: put tx to napi poll function to fix dead lock") Cc: Frank Li <Frank.Li@freescale.com> Cc: Richard Cochran <richardcochran@gmail.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Acked-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Oliver Brown [Thu, 19 Dec 2013 18:59:05 +0000 (12:59 -0600)]
ENGR00292585 IPUv3: Fix a horizontal line at the middle playing 1080i
Added additional check to handle stripe limits differently for upscaling
and downscaling. Upscaling requires relaxed checking because input stripe
may fall slighty outside of the input window. Downscaling requires strict
limit checking.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
Fancy Fang [Wed, 18 Dec 2013 05:38:23 +0000 (13:38 +0800)]
ENGR00292562 PXP: move the definitions used only by PXP device to a new header file
Some definitions used only by PXP device driver should not stay in
pxp_dma.h which is shared by PXP, EPDC and V4L2. So the patch creates
a new header file pxp_device.h to hold these definitions.
Fancy Fang [Tue, 17 Dec 2013 08:58:26 +0000 (16:58 +0800)]
ENGR00292398 PXP: refine two spin locks usage in PXP dma driver
This patch provides the following refinements:
1. For pxp channel lock, use spin_lock() instead of spin_lock_irqsave().
Since this lock is not used in any ISR. Moreover, this can increase the
driver's concurrency with no local irq disabled.
2. Narrow down the pxp lock's locking range in pxp_issue_pending().
Since this lock is also used in PXP ISR, so its hold time should be as
few as possible to reduce the time when local irq disabled.
Peter Chen [Thu, 12 Dec 2013 06:33:02 +0000 (14:33 +0800)]
ENGR00291876 usb: phy-mxs: add delay before set phyctrl.clkgate
There is a request from IC engineer that if we doesn't
set phypwd as 0xffffffff, we need to delay about five
32Khz cycles before set phypwd, otherwise, the wakeup
signal may can't wake up controller.
projects / karo-tx-linux.git / log