ENGR00296547-2 ARM: dts: imx6qdl-sabreauto: add a new pinctrl for ECSPI1

The ECSPI1 needs the GPIO3_19 to select/de-select the SPI NOR chip.

This patch adds a new pinctrl for this GPIO, and select this pinctrl
when we enable the ECSPI1.

Signed-off-by: Huang Shijie <b32955@freescale.com>

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 461e18a0b7bb88b50848de5dd8701ce8742af81e..9e9e8b78d32b50d8a5c2b822964fb36471f3d94c 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -273,7 +273,7 @@
        fsl,spi-num-chipselects = <1>;
        cs-gpios = <&gpio3 19 0>;
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_ecspi1_1>;
+       pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
 
        flash: m25p80@0 {
                #address-cells = <1>;

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 8ccdeb10a581889cab17780ec00f7bbab0043677..ea8ec2a501d0eb541b5c27787cc3b6dadb7710a3 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1072,6 +1072,12 @@
        };
 
        ecspi1 {
+               pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
+                       fsl,pins = <
+                               MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
+                       >;
+               };
+
                pinctrl_ecspi1_1: ecspi1grp-1 {
                        fsl,pins = <
                                MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1