Olof Johansson [Wed, 1 Apr 2015 23:37:30 +0000 (16:37 -0700)]
Merge tag 'renesas-sh73a0-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/multiplatform
Merge "Renesas ARM Based SoC sh73a0 Multiplatform Updates for v4.1" from Simon
Horman:
* Add multiplatform support to sh73a0 and its kzm9g board
* Use Bus State Controller to enable ethernet for multiplatform sh73a0/kzm9g
* Add PM domain support to multiplatform sh73a0
* tag 'renesas-sh73a0-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (43 commits)
ARM: shmobile: sh73a0: Remove restart callback
ARM: shmobile: sh73a0 dtsi: Add PM domain support
ARM: shmobile: sh73a0: Remove unused sh73a0_add_standard_devices_dt()
ARM: shmobile: sh73a0 dtsi: Add Cortex-A9 TWD node
ARM: shmobile: kzm9g-reference: Remove board C code and DT file
ARM: shmobile: kzm9g dts: Move Ethernet node to BSC
ARM: shmobile: sh73a0 dtsi: Add Bus State Controller node
ARM: shmobile: kzm9g: Build DTS for Multiplatform
ARM: shmobile: kzm9g dts: Sync with kzm9g-reference dts
ARM: shmobile: sh73a0: Add Multiplatform support
ARM: shmobile: sh73a0: Introduce generic setup callback
ARM: shmobile: r8a7794: add SDHI DT support
ARM: shmobile: r8a7790: add ADSP clocks
ARM: shmobile: r8a7791: add ADSP clocks
ARM: shmobile: henninger: add CAN0 DT support
ARM: shmobile: r8a7791: add CAN DT support
ARM: shmobile: r8a7791: add CAN clocks
ARM: shmobile: r8a7790: add CAN DT support
ARM: shmobile: r8a7790: add CAN clocks
ARM: shmobile: emev2-kzm9d dts: Add PFC information for uart1
...
Gregory CLEMENT [Fri, 30 Jan 2015 11:34:25 +0000 (12:34 +0100)]
ARM: mvebu: Disable CPU Idle on Armada 38x
On Armada 38x SoCs, under heavy I/O load, the system hangs when CPU
Idle is enabled. Waiting for a solution to this issue, this patch
disables the CPU Idle support for this SoC.
As CPU Hot plug support also uses some of the CPU Idle functions it is
also affected by the same issue. This patch disables it also for the
Armada 38x SoCs.
Tomeu Vizoso [Thu, 12 Mar 2015 14:48:09 +0000 (15:48 +0100)]
ARM: tegra: Add EMC timings to Nyan Blaze device tree
This adds a new file, tegra124-nyan-blaze-emc.dtsi that contains
valid timings for the EMC memory clock. The file is included to the
main device tree file for the Nyan Blaze.
The frequency 528MHz is missing because we don't currently have a timing
configuration that works.
Additionally, only the timings for the ram-code 1 is present as that's
what could be tested currently, though downstream has timings for more
ram-codes.
Tomeu Vizoso [Thu, 12 Mar 2015 14:48:08 +0000 (15:48 +0100)]
ARM: tegra: Add EMC timings to Nyan Big device tree
This adds a new file, tegra124-nyan-big-emc.dtsi that contains
valid timings for the EMC memory clock. The file is included to the
main device tree file for the Nyan Big.
The frequency 528MHz is missing because we don't currently have a timing
configuration that works.
Additionally, only the timings for the ram-code 1 is present as that's
what could be tested currently, though downstream has timings for more
ram-codes.
Mikko Perttunen [Thu, 12 Mar 2015 14:48:01 +0000 (15:48 +0100)]
ARM: tegra: Add EMC timings to Jetson TK1 device tree
This adds a new file, tegra124-jetson-tk1-emc.dtsi that contains
valid timings for the EMC memory clock. The file is included to the
main Jetson TK1 device tree.
The data is generated from the V5.0.17 version of the DVFS tables.
Olof Johansson [Sun, 29 Mar 2015 21:00:53 +0000 (14:00 -0700)]
Merge tag 'sunxi-fixes-for-4.0' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into fixes
Allwinner fixes for 4.0
There's a few fixes to merge for 4.0, one to add a select in the machine
Kconfig option to fix a potential build failure, and two fixing cpufreq related
issues.
* tag 'sunxi-fixes-for-4.0' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: dts: sunxi: Remove overclocked/overvoltaged OPP
ARM: dts: sun4i: a10-lime: Override and remove 1008MHz OPP setting
ARM: sunxi: Have ARCH_SUNXI select RESET_CONTROLLER for clock driver usage
Olof Johansson [Sun, 29 Mar 2015 20:58:54 +0000 (13:58 -0700)]
Merge tag 'fixes-v4.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Fixes for omaps for the -rc cycle:
- Fix a device tree based booting vs legacy booting regression for
omap3 crypto hardware by adding the missing DMA channels.
- Fix /sys/bus/soc/devices/soc0/family for am33xx devices.
- Fix two timer issues that can cause hangs if the timer related
hwmod data is missing like it often initially is for new SoCs.
- Remove pcie hwmods entry from dts as that causes runtime PM to
fail for the PHYs.
- A paper bag type dts configuration fix for dm816x GPIO
interrupts that I just noticed. This is most of the changes
diffstat wise, but as it's a basic feature for connecting
devices and things work otherwise, it should be fixed.
* tag 'fixes-v4.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: Fix gpio interrupts for dm816x
ARM: dts: dra7: remove ti,hwmod property from pcie phy
ARM: OMAP: dmtimer: disable pm runtime on remove
ARM: OMAP: dmtimer: check for pm_runtime_get_sync() failure
ARM: OMAP2+: Fix socbus family info for AM33xx devices
ARM: dts: omap3: Add missing dmas for crypto
Olof Johansson [Sun, 29 Mar 2015 20:47:21 +0000 (13:47 -0700)]
Merge tag 'fixes-for-v4.0-rc5' of https://github.com/rjarzmik/linux into fixes
arm: pxa: fixes for v4.0-rc5
There are only 2 fixes, one for the zeus board about the regulator changes,
where a typo prevented the zeus board from having a working can regulator,
and one regression triggered by the interrupts IRQ shift of 16 affecting all
boards.
* tag 'fixes-for-v4.0-rc5' of https://github.com/rjarzmik/linux:
ARM: pxa: fix pxa interrupts handling in DT
ARM: pxa: Fix typo in zeus.c
Praneeth Bajjuri [Wed, 25 Mar 2015 23:25:09 +0000 (18:25 -0500)]
ARM: DRA7: Enable Cortex A15 errata 798181
ARM errata 798181 is applicable for OMAP5/DRA7 based devices. So enable
the same in the build.
DRA7xx is based on Cortex-A15 r2p2 revision.
ARM Errata extract and workaround information is as below.
On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
adequately shooting down all use of the old entries. The
ARM_ERRATA_798181 option enables the Linux kernel workaround
for this erratum which sends an IPI to the CPUs that are running
the same ASID as the one being invalidated.
Stephen Boyd [Fri, 13 Mar 2015 18:09:39 +0000 (11:09 -0700)]
mmc: Remove msm_sdcc driver
This driver is orphaned now that mach-msm has been removed.
Delete it.
Cc: Chris Ball <chris@printf.net> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
Stephen Boyd [Fri, 13 Mar 2015 18:09:34 +0000 (11:09 -0700)]
ARM: Remove mach-msm and associated ARM architecture code
The maintainers for mach-msm no longer have any plans to support
or test the platforms supported by this architecture[1]. Most likely
there aren't any active users of this code anyway, so let's
delete it.
[1] http://lkml.kernel.org/r/20150307031212.GA8434@fifo99.com Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
We mask the event with the CCI_PMU_EVENT_MASK, before passing
the config to pmu_validate_hw_event(), which causes extra bits
to be ignored and qualifies an invalid event code as valid.
e.g,
$ perf stat -a -C 0 -e CCI_400/config=0x1ff,name=cycles/ sleep 1
Performance counter stats for 'system wide':
where, cycles has an event coding of 0xff. This patch also removes
the unnecessary 'event' mask in pmu_write_register, since the config_base
is set by the pmu code after the event is validated.
Acked-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This patch separates the PMU driver code from the low level
CCI driver code and enables the PMU driver for ARM64.
Introduces config options for both.
ARM_CCI400_PORT_CTRL - controls the low level driver code for
CCI400 ports.
ARM_CCI400_PMU - controls the PMU driver code
ARM_CCI400_COMMON - Common defintions for CCI400
This patch also changes:
ARM_CCI - common code for probing the CCI devices. This can be
used for adding support for newer CCI versions(e.g, CCI-500).
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
arm-cci: Get rid of secure transactions for PMU driver
Avoid secure transactions while probing the CCI PMU. The
existing code makes use of the Peripheral ID2 (PID2) register
to determine the revision of the CCI400, which requires a
secure transaction. This puts a limitation on the usage of the
driver on systems running non-secure Linux(e.g, ARM64).
Updated the device-tree binding for cci pmu node to add the explicit
revision number for the compatible field.
The supported strings are :
arm,cci-400-pmu,r0
arm,cci-400-pmu,r1
arm,cci-400-pmu - DEPRECATED. See NOTE below
NOTE: If the revision is not mentioned, we need to probe the cci revision,
which could be fatal on a platform running non-secure. We need a reliable way
to know if we can poke the CCI registers at runtime on ARM32. We depend on
'mcpm_is_available()' when it is available. mcpm_is_available() returns true
only when there is a registered driver for mcpm. Otherwise, we assume that we
don't have secure access, and skips probing the revision number(ARM64 case).
The MCPM should figure out if it is safe to access the CCI. Unfortunately
there isn't a reliable way to indicate the same via dtb. This patch doesn't
address/change the current situation. It only deals with the CCI-PMU, leaving
the assumptions about the secure access as it has been, prior to this patch.
Cc: devicetree@vger.kernel.org Cc: Punit Agrawal <punit.agrawal@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
arm-cci: Abstract the CCI400 PMU specific definitions
CCI400 has different event specifications for PMU, for revsion
0 and revision 1. As of now, we check the revision every single
time before using the parameters for the PMU. This patch abstracts
the details of the pmu models in a struct (cci_pmu_model) and
stores the information in cci_pmu at initialisation time, avoiding
multiple probe operations.
Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
arm-cci: Rearrange code for splitting PMU vs driver code
No functional changes, only code re-arrangements for easier split of the
PMU code vs low level driver code. Extracts the port handling code
to cci_probe_ports().
Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
drivers: cci: reject groups spanning multiple HW PMUs
The perf core implicitly rejects events spanning multiple HW PMUs, as in
these cases the event->ctx will differ. However this validation is
performed after pmu::event_init() is called in perf_init_event(), and
thus pmu::event_init() may be called with a group leader from a
different HW PMU.
The CCI PMU driver does not take this fact into account, and assumes
that the any other hardware event belongs to the CCI. There are two
issues with it :
1) It is wrong and we should reject such groups.
2) Validation allocates an temporary idx for this non-cci event, which leads
to wrong calculation of the counter availability, and eventually lesser
number of events in the group.
This patch updates the CCI PMU driver to first test for and reject
events from other PMUs, which is the right thing to do.
Cc: Will Deacon <will.deacon@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Peter Ziljstra (Intel) <peterz@infradead.org> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Nishanth Menon [Mon, 23 Mar 2015 19:39:39 +0000 (14:39 -0500)]
ARM: dts: am57xx-beagle-x15: Add thermal map to include fan and tmp102
BeagleBoard-X15 has capability for a fan and has an onboard TMP102
temperature sensor as well. This allows us to create a new thermal
zone (called, un-imaginatively "board"), and allows us to use some
active cooling as temperatures start edge upward in the system by
creating a new alert temperature (emperically 50C) for cpu.
NOTE: Fan is NOT mounted by default on the platform, in such a case,
all we end up doing is switch on a regulator and leak very minimal
current.
Keerthy [Mon, 23 Mar 2015 19:39:38 +0000 (14:39 -0500)]
ARM: dts: DRA7: Add bandgap and related thermal nodes
Add bandgap and related thermal nodes. The patch adds 5 thermal
sensors. Only one cooling device for mpu as of now. The sensors are
the exact same on both dra72 and dra7. Introduce CPU, GPU, core nodes
for the moment as they are direct reuse of OMAP5 entities.
NOTE: OMAP4 has a finer counter granularity, which allows for a delay
of 1000ms in the thermal zone polling intervals. DRA7 have different
counter mechanism, which allows at maximum a 500ms timer. Adjust the
cpu thermal zone accordingly for DRA7.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[t-kristo@ti.com: few reuse from OMAP5 entities] Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
bus: ocp2scp: SYNC2 value should be changed to 0x6
As per the TRMs of AM572x, OMAP4430, OMAP4460, OMAP543x, the value of
SYNC2 must be set to 0x6 in order to ensure correct operation.
So modified the SYNC2 value of OCP2SCP TIMING register to 0x6 in all the
platforms that use OCP2SCP driver except AM437x. Also introduced a new
compatible property since we don't want to modify the OCP2SCP TIMING
register for AM437x.
The sections in TRM where the above caution can be found is mentioned below.
AM572x TRM SPRUHZ6 (http://www.ti.com/lit/ug/spruhz6/spruhz6.pdf) under
section 26.3.2.2, table 26-26.
OMAP4430 TRM SWPU231AP (http://www.ti.com/lit/ug/swpu231ap/swpu231ap.pdf)
under section 23.12.6.2.2 , Table 23-1213.
OMAP4460 TRM SWPU235AB (http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf)
under section 23.12.6.2.2, Table 23-1213.
OMAP543x TRM SWPU249 (http://www.ti.com/lit/pdf/swpu249)
under section 27.3.2.2, Table 27-27.
Cc: Arnd Bergmann <arnd@arndb.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: dts: am4372: Add "ti,am437x-ocp2scp" as compatible string for OCP2SCP
Added a new compatible string "ti,am437x-ocp2scp" for OCP2SCP module.
This is needed since except for the OCP2SCP used in AM437x, SYNC2 value
in OCP2SCP TIMING should be changed whereas the default value is sufficient
in AM437x.
Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
The NULL pointer check for superset->muxnames will always evaluate
true since muxnames is an array within struct omap_mux. Remove the
superfluous check to avoid warnings when using LLVM/clang.
Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tony Lindgren <tony@atomide.com>
Georgi Djakov [Thu, 9 Oct 2014 08:33:34 +0000 (11:33 +0300)]
ARM: qcom: Increase MMC_BLOCK_MINORS in defconfig
There are currently more than 16 partitions on the eMMC of all recent
Qualcomm devices. Increase the number of minors per block device to
detect all available partitions.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Signed-off-by: Kumar Gala <galak@codeaurora.org>
Chen-Yu Tsai [Tue, 24 Mar 2015 16:53:27 +0000 (00:53 +0800)]
ARM: dts: sunxi: Remove overclocked/overvoltaged OPP
Without proper regulator support for individual boards, it is dangerous
to have overclocked/overvoltaged OPPs in the list. Cpufreq will increase
the frequency without the accompanying voltage increase, resulting in
an unstable system.
Remove them for now. We can revisit them with the new version of OPP
bindings, which support boost settings and frequency ranges, among
other things.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Suman Anna [Mon, 16 Mar 2015 20:54:54 +0000 (15:54 -0500)]
ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4
GPTimer 4 is a regular timer and not a secure timer, so fix
the hwmod to use the correct hwmod class (even though there
are no differences in the class definition itself).
Signed-off-by: Suman Anna <s-anna@ti.com>
[paul@pwsan.com: dropped dra7xx_timer_secure_hwmod_class and
dra7xx_timer_secure_sysc to avoid compiler warnings] Signed-off-by: Paul Walmsley <paul@pwsan.com>
Eliad Peller [Wed, 18 Mar 2015 16:38:30 +0000 (18:38 +0200)]
wlcore: remove wl12xx_platform_data
Now that we have wlcore device-tree bindings in place
(for both wl12xx and wl18xx), remove the legacy
wl12xx_platform_data struct, and move its members
into the platform device data (that is passed to wlcore)
Davinci 850 is the only platform that still set
the platform data in the legacy way (and doesn't
have DT bindings), so remove the relevant
code/Kconfig option from the board file (as suggested
by Sekhar Nori)
Since no one currently uses wlcore_spi, simply remove its
platform data support (DT bindings will have to be added
if someone actually needs it)
Signed-off-by: Luciano Coelho <luca@coelho.fi> Signed-off-by: Eliad Peller <eliad@wizery.com> Tested-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Kalle Valo <kvalo@codeaurora.org> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Luciano Coelho [Wed, 18 Mar 2015 16:38:26 +0000 (18:38 +0200)]
wl12xx: use frequency instead of enumerations for pdata clocks
Instead of defining an enumeration with the FW specific values for the
different clock rates, use the actual frequency instead. Also add a
boolean to specify whether the clock is XTAL or not.
Change all board files to reflect this.
Signed-off-by: Luciano Coelho <luca@coelho.fi>
[Eliad - small fixes, update board file changes] Signed-off-by: Eliad Peller <eliad@wizery.com> Tested-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Kalle Valo <kvalo@codeaurora.org> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Tomeu Vizoso [Wed, 18 Mar 2015 09:52:22 +0000 (10:52 +0100)]
ARM: tegra: Use generated pinmux data for Nyan Big
Google has submitted a board config for the pinmux programming of the
Nyan Big board. Use the whole of it as it's generated to make it easier
to update as the configuration gets fixed in the future.
Tomeu Vizoso [Wed, 18 Mar 2015 09:52:21 +0000 (10:52 +0100)]
ARM: tegra: Use pwrseq-simple for the wifi in Nyan
The Nyan boards have a Marvell 88w8897 wifi card connected through SDIO
that needs the reset line to be asserted before mmc power up and deasserted
afterwards.
This patch also adds references to the power supplies of the card so that
the regulators are enabled when it's probed.
Stephen Warren [Tue, 17 Feb 2015 18:57:45 +0000 (11:57 -0700)]
ARM: tegra: Import latest Jetson TK1 pinmux
syseng has revamped the Jetson TK1 pinmux spreadsheet, basing the content
completely on correct configuration for the board/schematic, rather than
the previous version which was based on the bare minimum changes relative
to another reference board.
This content comes from Jetson_TK1_customer_pinmux.xlsm (v09) downloaded
from https://developer.nvidia.com/hardware-design-and-development.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Nicolas Ferre [Wed, 25 Feb 2015 18:04:05 +0000 (19:04 +0100)]
ARM: at91/dt: sama5d4: add rgb777 LCD line configuration
For the SAMA5D4 SoC, some LCD lines are in conflict with useful peripherals.
Remove these lines and the lowest significant bit of a 24 bit LCD. It gives
us a RGB 777 configuration.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris Brezillon [Mon, 7 Jul 2014 16:32:24 +0000 (18:32 +0200)]
ARM: at91/dt: define the HLCDC node available on sama5d3 SoCs
Define the HLCDC (HLCD Controller) IP available on some sama5d3 SoCs
(i.e. sama5d31, sama5d33, sama5d34 and sama5d36) in sama5d3 dtsi file.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Anthony Harivel <anthony.harivel@emtrion.de> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris Brezillon [Fri, 4 Jul 2014 14:43:53 +0000 (16:43 +0200)]
ARM: at91/dt: add alternative pin muxing for sama5d3 lcd pins
Define alternative pin muxing for the LCDC pins.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Anthony Harivel <anthony.harivel@emtrion.de> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris Brezillon [Mon, 7 Jul 2014 16:31:49 +0000 (18:31 +0200)]
ARM: at91/dt: split sama5d3 lcd pin definitions to match RGB mode configs
The HLCDC (HLCD Controller) IP supports 4 different output mode (RGB444,
RGB565, RGB666 and RGB888) and the pin muxing will depend on the chosen
RGB mode.
Split pin definitions to be able to set pin config according to the
selected mode.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Anthony Harivel <anthony.harivel@emtrion.de> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Luciano Coelho [Wed, 18 Mar 2015 16:38:25 +0000 (18:38 +0200)]
wlcore: set irq_trigger in board files instead of hiding behind a quirk
The platform_quirk element in the platform data was used
to change the way the IRQ is triggered. When set,
the EDGE_IRQ quirk would change the irqflags used
and treat edge trigger differently from the rest.
Instead of hiding this irq flag setting behind the quirk,
have the board files set the irq_trigger explicitly.
This will allow us to use standard irq DT definitions
later on.
Signed-off-by: Luciano Coelho <luca@coelho.fi>
[Eliad - rebase, add irq_trigger field and pass it,
update board file changes] Signed-off-by: Eliad Peller <eliad@wizery.com> Tested-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Kalle Valo <kvalo@codeaurora.org> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Mark Jackson [Thu, 19 Mar 2015 15:07:43 +0000 (15:07 +0000)]
ARM: dts: Update Nanobone dts file
Update dts file to reflect:-
* new flash memory layout
* add missing phy-mode property
* dual_emac now just a boolean
* rename mcp to microchip
* update gpio definition
Signed-off-by: Mark Jackson <mpfj@newflow.co.uk> Signed-off-by: Tony Lindgren <tony@atomide.com>
Sakari Ailus [Wed, 18 Mar 2015 23:50:23 +0000 (01:50 +0200)]
ARM: dts: omap3: Add DT entries for OMAP 3 ISP
The resources the ISP needs are slightly different on 3[45]xx and 3[67]xx.
Especially the phy-type property is different.
Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[tony@atomide.com: use omap3_scm_general instead of scm_conf for now] Signed-off-by: Tony Lindgren <tony@atomide.com>
Pali Rohár [Thu, 26 Feb 2015 13:49:59 +0000 (14:49 +0100)]
ARM: dts: omap3-tao3530: Include directly omap34xx.dtsi
This patch just move content of file omap34xx-hs.dtsi into omap3-tao3530.dts.
There is no code change, patch is just preparation for removing -hs file.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Tony Lindgren <tony@atomide.com>
Pali Rohár [Thu, 26 Feb 2015 13:49:58 +0000 (14:49 +0100)]
ARM: dts: n900: Enable omap sham and include directly omap34xx.dtsi
This patch moves content of file omap34xx-hs.dtsi into omap3-n900.dts and enable
omap sham support (omap HW support for SHA + MD5). After testing both omap hwmod
and omap-sham.ko drivers it looks like signed Nokia X-Loader enable L3 firewall
for omap sham. There is no kernel crash with both official bootloader and crypto
enable bootloader. So we can safely enable sham code.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Tony Lindgren <tony@atomide.com>
Pali Rohár [Thu, 26 Feb 2015 13:49:57 +0000 (14:49 +0100)]
ARM: dts: n9/n950: Enable omap crypto support
Harmattan system on Nokia N9 and N950 devices uses omap crypto support.
Bootloader on those devices is known that it enables HW crypto support.
This patch just include omap36xx.dtsi directly, so aes and sham is enabled.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Thu, 19 Mar 2015 16:14:36 +0000 (09:14 -0700)]
ARM: dts: Add cppi41 support for dm816x MUSB
Looks like we have cppi41 on dm816x just like on am335x.
Cc: Bin Liu <binmlist@gmail.com> Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Thu, 19 Mar 2015 16:14:35 +0000 (09:14 -0700)]
ARM: dts: Fix typo for dm816x usb0_pins
Commit a54879a00859 ("ARM: dts: Fix USB dts configuration for dm816x")
attempted to fix the USB features introduced by commit 7800064ba507
("ARM: dts: Add basic dm816x device tree configuration") but obviously
I did not read the dmesg as more USB issues still keep trickling in.
It should be usb1_pins instead not usb0_pins for the second interface
to avoid warnings from pinctrl framework.
Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Mark James [Tue, 17 Mar 2015 21:35:23 +0000 (21:35 +0000)]
ARM: socfpga: dts: fix spi1 interrupt
The socfpga.dtsi currently has the wrong interrupt number set for SPI master 1
Trying to use the master without this change results in the kernel boot
process waiting forever for an interrupt that will never occur while
attempting to probe any slave devices configured in the device tree as being
under SPI master 1.
The change works for the Cyclone V, and according to the Arria 5 handbook
should be good there too.
Signed-off-by: Mark James <maj@jamers.net> Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Drop AT91_TIMER_HZ as this can be handled using HZ_FIXED. Initial help message
was:
On AT91rm9200 chips where you're using a system clock derived
from the 32768 Hz hardware clock, this tick rate should divide
it exactly: use a power-of-two value, such as 128 or 256, to
reduce timing errors caused by rounding.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Daniel Lezcano [Tue, 17 Mar 2015 15:25:12 +0000 (16:25 +0100)]
ARM: shmobile: cpuidle: Remove the pointless default driver
The default idle driver uses one state with the WFI instruction.
The default idle routine invokes WFI when no cpuidle driver is present.
The default cpuidle driver is pointless and does not give more than the
default idle routine and moreover it pulls all the mathematics tied with
the cpuidle governor for nothing, hence consuming more energy.
Remove the default driver, the related code and register the driver directly.
[compiled only - no board - no test]
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Tony Lindgren [Wed, 18 Mar 2015 20:41:34 +0000 (13:41 -0700)]
ARM: dts: Fix gpio interrupts for dm816x
Commit 7800064ba507 ("ARM: dts: Add basic dm816x device tree
configuration") added basic devices for dm816x, but I was not able
to test the GPIO interrupts earlier until I found some suitable pins
to test with. We can mux the MMC card detect and write protect pins
from SD_SDCD and SD_SDWP mode to use a normal GPIO interrupts that
are also suitable for the MMC subsystem.
This turned out several issues that need to be fixed:
- I set the GPIO type wrong to be compatible with omap3 instead
of omap4. The GPIO controller on dm816x has EOI interrupt
register like omap4 and am335x.
- I got the GPIO interrupt numbers wrong as each bank has two
and we only use one. They need to be set up the same way as
on am335x.
- The gpio banks are missing interrupt controller related
properties.
With these changes the GPIO interrupts can be used with the
MMC card detect pin, so let's wire that up. Let's also mux all
the MMC lines for completeness while at it.
For the first GPIO bank I tested using GPMC lines temporarily
muxed to GPIOs on the dip switch 10.
Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Peter Ujfalusi [Thu, 12 Mar 2015 08:06:30 +0000 (10:06 +0200)]
ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x
McASP1 TX interrupt is 30, not 32 on DM646x DMSoC.
While at it remove the bogus AEMIF interrupt entry from
dm646x_default_priorities[]. AEMIF interrupt on DM6467 is
60 not 30 and the entry for the correct interrupt number
is already present in the same table.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: remove bogus entry from dm646x_default_priorities[]] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
projects / karo-tx-linux.git / log