ARM: dts: DRA7: Add bandgap and related thermal nodes

Add bandgap and related thermal nodes. The patch adds 5 thermal
sensors. Only one cooling device for mpu as of now. The sensors are
the exact same on both dra72 and dra7. Introduce CPU, GPU, core nodes
for the moment as they are direct reuse of OMAP5 entities.

NOTE: OMAP4 has a finer counter granularity, which allows for a delay
of 1000ms in the thermal zone polling intervals. DRA7 have different
counter mechanism, which allows at maximum a 500ms timer. Adjust the
cpu thermal zone accordingly for DRA7.

Signed-off-by: Keerthy <j-keerthy@ti.com>
[t-kristo@ti.com: few reuse from OMAP5 entities]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5827fedafd43d58a00169a4186cbb595d6f11234..098916f93811755ec1ce16048eba523d8b44994c 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -177,6 +177,18 @@
                        };
                };
 
+               bandgap: bandgap@4a0021e0 {
+                       reg = <0x4a0021e0 0xc
+                               0x4a00232c 0xc
+                               0x4a002380 0x2c
+                               0x4a0023C0 0x3c
+                               0x4a002564 0x8
+                               0x4a002574 0x50>;
+                               compatible = "ti,dra752-bandgap";
+                               interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+                               #thermal-sensor-cells = <1>;
+               };
+
                cm_core_aon: cm_core_aon@4a005000 {
                        compatible = "ti,dra7-cm-core-aon";
                        reg = <0x4a005000 0x2000>;
@@ -1426,6 +1438,17 @@
                        status = "disabled";
                };
        };
+
+       thermal_zones: thermal-zones {
+               #include "omap4-cpu-thermal.dtsi"
+               #include "omap5-gpu-thermal.dtsi"
+               #include "omap5-core-thermal.dtsi"
+       };
+
+};
+
+&cpu_thermal {
+       polling-delay = <500>; /* milliseconds */
 };
 
 /include/ "dra7xx-clocks.dtsi"

diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index e5a3d23a3df122895fc0672667e3cc41ac2b25e6..6ac8e36014999991d9ccc08c6ba39771de9cc289 100644 (file)
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -20,6 +20,11 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
                        reg = <0>;
+
+                       /* cooling options */
+                       cooling-min-level = <0>;
+                       cooling-max-level = <2>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
        };
 

diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 10173fab1a15b72983d43fddf453ed5d4105f73a..eef981f4bcd5a6f68c7e739b0650d76cc5f78a4b 100644 (file)
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -31,6 +31,11 @@
                        clock-names = "cpu";
 
                        clock-latency = <300000>; /* From omap-cpufreq driver */
+
+                       /* cooling options */
+                       cooling-min-level = <0>;
+                       cooling-max-level = <2>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
                cpu@1 {
                        device_type = "cpu";