Dong Aisheng [Wed, 7 Aug 2013 12:20:27 +0000 (20:20 +0800)]
ENGR00274382 imx6q: fix can transceiver unwork on AI RevE baseboard
The transceiver TJA1041A on sabreauto RevE baseboard will
fail to transit to Normal state if EN/STBY is high by default
after board power up. So we set the EN/STBY initial state to low
first then to high to guarantee the state transition successfully.
Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Jason Liu <r64343@freescale.com>
CONFIG_USB_EHCI_TT_NEWSCHED introduces a new schedule method
for periodic transfer, it can cover more peridic transfers which
introduced recently years.
Meanwhile, both PC and our 3.5.7 (and coming 3.10) enable it,
and have not found any issues, this commit also fixes a bug
this CR reported.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Thu, 25 Jul 2013 06:28:04 +0000 (14:28 +0800)]
ENGR00272597 mx6-msl: usb: fix building warning when only build host driver
CC arch/arm/mach-mx6/usb_h1.o
/home/b29397/work/projects/linux-2.6-imx/arch/arm/mach-mx6/usb_dr.c:
In function '_host_wakeup_enable':
/home/b29397/work/projects/linux-2.6-imx/arch/arm/mach-mx6/usb_dr.c:
522: warning: unused variable 'phy_reg'
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Tue, 23 Jul 2013 00:22:01 +0000 (08:22 +0800)]
ENGR00272135 msl-mx6: usb-h1: Fix the bug that using the wrong register
At host 1 code, we should use UH1_XXXX. The wrong register
access causing a bug that the u-disk disconnion at host 1
can't be recognized after system resume.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
At mx6, if usb wakeup is not enabled, the PHY's power
will be off during the system suspend, so the dp/dm
will be unknown after the system resumes, it may wake up
controller at some boards since dp/dm's status satisfies
wake up condition. If the controller is waken up, the
PHCD will be cleared automatically.
According to IC requirement, after PHCD is cleared, we
need to wait 1ms before clear PHY's clock gate to wait
PHY's clock stable. At above condition, the PHCD is cleared
automatically, it may less than 1ms before we clear
PHY's clock gate, then, software operation to clear PHY's
clock gate will be useless. At this case, the PHY will works
abnormal, and cause the controller hang when we write some registers
(eg, portsc).
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Simon Horman [Fri, 28 Sep 2012 01:12:45 +0000 (02:12 +0100)]
ARM: 7541/1: Add ARM ERRATA 775420 workaround
arm: Add ARM ERRATA 775420 workaround
Workaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0) erratum.
In case a date cache maintenance operation aborts with MMU exception, it
might cause the processor to deadlock. This workaround puts DSB before
executing ISB if an abort may occur on cache maintenance.
Based on work by Kouei Abe and feedback from Catalin Marinas.
Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
[ horms@verge.net.au: Changed to implementation
suggested by catalin.marinas@arm.com ] Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Simon Horman <horms@verge.net.au> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ENGR00270573-2 [MX6SL]Add support for dynamic Power Gating of the display MIX
The display MIX can be power gated when EPDC, PXP and LCDIF are all inactive.
This will save around 1.5mW-1.8mW of power in system IDLE mode.
Need to re-initialize the EPDC and PXP whenever the display MIX is
powered up as all the register state is lost when the display MIX is
power gated.
Signed-off-by: Hudson Winston <B45308@freescale.com> Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Peter Chen [Wed, 17 Jul 2013 08:05:17 +0000 (16:05 +0800)]
ENGR00271566 usb: otg: comment otg_statemachine which we do not need
We have not implemented fully OTG support, so we can't call
otg_statemachine since the state machine may incorrect at current
dual-role switch design.
At existed code, it will call otg_statemachine, in fact, it doesn't
need. Besides, it causes one kernel dump at Sabreauto board due
to it calls gpio API at spin lock, but at Sabreauto board the
USB power GPIO is expanded by MAX7310 which calls i2c read/write
and will schedule itself.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
The ASoC core tries to not enforce symmetric rates when
two streams open simultaneously. It does so by checking
rtd->rate being zero. This works exactly once after booting
because it is not set to zero again when the streams close.
Fix this by setting rtd->rate when no active stream is left.
[This leads to lots of warnings about not enforcing the symmetry in some
situations as there's a race in the userspace API where we know we've
got two applications but don't know what rates they want to set.
-- broonie ]
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
In the imx6sl, we meet the compiling warning shows below:
--------------------------------------------------------------------
drivers/dma/imx-sdma.c: In function Pleasesdma_iram_free:
drivers/dma/imx-sdma.c:366: warning: passing argument 2 of
Pleasegen_pool_free makes integer from pointer without a cast
include/linux/genalloc.h:58: note: expected Pleaselong unsigned integer
but argument is of type Pleaselong unsigned int *Please
drivers/dma/imx-sdma.c: In function Pleasesdma_load_script:
drivers/dma/imx-sdma.c:452: warning: passing argument 2 of
Pleasesdma_iram_malloc makes pointer from integer without a cast
drivers/dma/imx-sdma.c:352: note: expected Pleaselong unsigned
int *Please but argument is of type Pleaselong unsigned integer
drivers/dma/imx-sdma.c:475: warning: passing argument 1 of
Pleasesdma_iram_free makes pointer from integer without a cast
drivers/dma/imx-sdma.c:361: note: expected Pleaselong unsigned
int *Please but argument is of type Pleasedma_addr_t
drivers/dma/imx-sdma.c: In function Pleasesdma_request_channel:
drivers/dma/imx-sdma.c:942: warning: passing argument 2 of
Pleasesdma_iram_malloc makes pointer from integer without a cast
drivers/dma/imx-sdma.c:352: note: expected Pleaselong unsigned int
*Please but argument is of type Pleaselong unsigned integer
drivers/dma/imx-sdma.c: In function Pleasesdma_free_chan_resources:
drivers/dma/imx-sdma.c:1109: warning: passing argument 1 of
Pleasesdma_iram_free makes pointer from integer without a cast
drivers/dma/imx-sdma.c:361: note: expected Pleaselong unsigned int
*Please but argument is of type Pleasedma_addr_t
drivers/dma/imx-sdma.c: In function Pleasesdma_init:
drivers/dma/imx-sdma.c:1505: warning: passing argument 2 of
Pleasesdma_iram_malloc from incompatible pointer type
drivers/dma/imx-sdma.c:352: note: expected Pleaselong unsigned int
*Please but argument is of type Pleasedma_addr_t *Please
--------------------------------------------------------------------
ENGR00261419 MX6Q HDMI CEC: Unit test failed put TV to powerdown.
TV will been setting powerdown state when first run HDMI CEC unit
test on MX6Q, but failed in the secondly run and loop in print
message:
sleep for ready!
sleep for ready!
sleep for ready!
...
It is cause by cec interrupter been enabled before interrupter
polarity setting, controler will received fake interrupter,
and cec unit test will get wrong device state.
Fix the issue with move interrupter polarity setting code before
interrupter enabled.
CC [M] drivers/gpu/drm/drm_global.o
drivers/mxc/mlb/mxc_mlb150.c: In function 'mxc_mlb150_open':
drivers/mxc/mlb/mxc_mlb150.c:1910: warning: format '%x'
expects type 'unsigned int', but argument 2 has type 'void *'
....
Peter Chen [Fri, 12 Jul 2013 05:45:49 +0000 (13:45 +0800)]
ENGR00270802 usb: otg: delete redundant vbus off operation
The problem locates at:
fsl_otg_start_host(fsm, 0);
if (pdata->wake_up_enable)
pdata->wake_up_enable(pdata, false);
otg_drv_vbus(fsm, 0);
fsl_otg_start_host(fsm, 0) internally calls fsl_otg_drv_vbus(), which does
the same thing as otg_drv_vbus(fsm, 0). More critically, we need disable
VBUS wakeup before close VBUS operation, otherwise unexpected VBUS
wakeup will occur. The solution is to remove the call of fsl_otg_drv_vbus()
in fsl_otg_start_host().
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Liu Ying [Fri, 12 Jul 2013 07:44:18 +0000 (15:44 +0800)]
ENGR00269468 IPUv3 dev:Silence an annoying warning message
We call the function ipu_calc_stripes_sizes() to calculate
stripe settings for vdi split mode. Chances are that the
parameters output_frame_width and maximal_stripe_width for the
function satisfy the relationship 'output_frame_width <=
maximal_stripe_width' and make the function return non-zero
value. This causes the IPU device driver generates an annoying
warning message, though the default stripe settings still can
work. This patch simply silences the warning message by reducing
the print log level from error to debug.
ENGR00270996 net:fec: fix fec probe fail due to gpio_irq check error
Board files correctly define fec gpio irq to wake up wait mode since FEC
interrupt cannot connect to GPC, otherwise board files define fec gpio irq
to -1. So, fec probe function check the gpio irq to decide whether fec use
gpio irq or fec irq.
Current irq checking logic is incorrect. Correct the gpio irq checking.
For imx6 serial silicon, fec MDC clock parent is ipg 66MHz.
The current clock file define the clock source is enet_pll8 50Mhz.
So, the MDC clock is more than 2.5Mhz after divider.
The phy Ar8031 work fine in current MDC clock, which shows the phy
have exceeding flexibility. Correct the parent clock source to make
MDC clock little than 2.5Mhz.
For imx6 serial silicon, fec MDC clock parent is ipg 66MHz.
The current clock file define the clock source is enet_pll8 50Mhz.
So, the MDC clock is more than 2.5Mhz after divider.
The phy Ar8031 work fine in current MDC clock, which shows the phy
have exceeding flexibility. Correct the parent clock source to make
MDC clock little than 2.5Mhz.
ENGR00262502-2 [MX6Q/MX6DLS]Add commandline option to route enet irq to gpio
Add a command line option to route the ENET interrupts to the GPIO_1_6.
To route the ENET interrupts to GPIO_6 add "enet_gpio_6" to the
kernel command line.
Also remove the CONFIG option (MX6_ENET_IRQ_TO_GPIO).
ENGR00262502-1 [MX6Q/MX6DLS]Add commandline option to route enet irq to gpio
Add a command line option to route the ENET interrupts to the GPIO_1_6.
To route the ENET interrupts to GPIO_6 add "enet_gpio_6" to the
kernel command line.
Also remove the CONFIG option (MX6_ENET_IRQ_TO_GPIO).
Liu Ying [Thu, 11 Jul 2013 08:21:48 +0000 (16:21 +0800)]
ENGR00269619 mxc vout:improve vb handling for 3 field deinterlacing
We need 2 video buffers to get a deinterlaced frame in VDI low motion
mode or medium motion mode. When there is no enough video buffer in
the active list, no one triggers the video buffer timer, then users
may be blocked at dqueue buffer ioctrl if they are in blocking mode.
In order to fix this issue, we may peek the first available video
buffer in the queue list so that the buffer may be taken as a reference
video buffer to do deinterlacing. If there is no video buffer in the
queue list, we should make users be able to trigger the timer again
when they queue buffers to the driver.
Robby Cai [Wed, 10 Jul 2013 12:46:47 +0000 (20:46 +0800)]
ENGR00263553 fb: Change type uint to unsigned int in struct mxcfb_update_data
This file could be included in user-space application while uint is not quite
standard type. This patch changed to unsigned int to avoid to include specific
header file. This is requested from mm team.
Robby Cai [Fri, 5 Jul 2013 07:38:08 +0000 (15:38 +0800)]
ENGR00269827 mx6sl: lcdif: fix lcd timing setting
The commit 0c0334779a08cca6c5a509570c944fe229837a21
corrected the v_period/v_wait_cnt, h_period/h_wait_cnt caculation in elcdif
framebuffer driver but in WVGA panel timing setting the left_margin and
upper_margin includes the length of hsyn_len and vsyn_len.
Thus the timing setting for lcd panel is not correct.
This patch fixes it.
Robby Cai [Mon, 1 Jul 2013 06:28:22 +0000 (14:28 +0800)]
ENGR00261293-1 mx6sl: csi/v4l2: resize function not work for v4l2 capture
- the root cause is pxp input/output buffer for csi post-processing is
same one, some part of content is overridded.
- use S_CROP ioctl to control crop, S_FMT to control output size.
ASRC driver allows users to set channel number via PROC interface,
but only passes the total number equal 10.
This's not reasonable because ASRC can use total number lower than 10
if user assure each of them is an even number.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
(cherry picked from commit d76d08c93550cf2de9b1eff569ad6c0928ba122c)
Set bit18 of gpr1 before enter into supend, and clean it
after resume, can fix the following errata.
Errata ERR005723_PCIe PCIe does not support L2 Power Down.
Liu Ying [Wed, 10 Jul 2013 03:27:28 +0000 (11:27 +0800)]
ENGR00255920-2 mxc vout:wait for 2 vsyncs when streamoff
Some expiring video buffers may have been rendered to
display triple buffers for display. The relevant triple
buffers are set to be ready and depend on the display
hardware engine to switch them to be active on screen in
turn automatically. So, we need to wait for at least 2
vsyncs to make sure all of the expiring video buffers be
shown on display already.
Liu Ying [Wed, 10 Jul 2013 02:56:45 +0000 (10:56 +0800)]
ENGR00255920-1 mxc vout:Remove cancel_work_sync() when streamoff
We hope the queued works can be done before streamoff, since the
works will render expiring video buffers to display. But, the
function cancel_work_sync() cannot guarantee this. Instead, it
may cancel some queued works before they starts to work. This
patch removes the function call cancel_work_sync() when streamoff.
We rely on the function flush_workqueue() right after it to make
sure queued works be done before streamoff.
ENGR00270045: thermal: Add timeout for temperature update
Need to add timeout for temperature update, otherwise, if suspend
comes during thermal sensor measurement, its power will be turned
off, and after resume, the delay work thread will never get
finish flag and result in thread forever loop, temperature will
never get updated. And if we wait for the measurement finish before
suspend, the time is too long for suspend, as one single measurement
would take as long as 100ms which is not good for suspend, so just
add a timeout.
Hongzhang Yang [Wed, 3 Jul 2013 07:20:12 +0000 (15:20 +0800)]
ENGR00264650 VPU can not playback after driver reload
Picked from 3.5.7 branch and removed linux version check
Bug: VPU can not playback after driver reload
- To reproduce (if VPU is never powered off)
0. Build VPU driver as a loadable module
1. Playback
2. Unload driver
3. Reload driver
4. Playback
VPU was blocked in vpu_DecGetInitialInfo.
Root cause:
VPU is still alive after unload
Solution:
Reset VPU state before unload
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
Mahesh Mahadevan [Wed, 26 Jun 2013 14:44:59 +0000 (09:44 -0500)]
ENGR00269604 Fix the set clock-rate for audio & video
There is single method to set clock-rate for both audio and video pll-s
in i.MX6q clock system implementation. That's possible due to they have
similar set of registers with a different bases. But there is also one
common register: CCM_ANALOG_MISC2, which contains post-dividers.
In current implementation, independently of whether audio or video clock
is going to be set, the mask 0xc0000000 is applied to MISC2 register.
This means, that if the audio clock rate is changed, the video clock
post-dividers possibly will be corrupted.
This patch fixes the issue described above.
Signed-off-by: Alexander Smirnov <alex.bluesman.smirnov@gmail.com> Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>
ENGR00269616 mx6: Unexpected enter WAIT mode cause IPU underrun
CCM state machine has restriction that, everytime enable
LPM mode, we need to make sure last wakeup from LPM mode
is a dsm_wakeup_signal, which means the wakeup source
must be seen by GPC, then CCM will clean its state machine
and re-sample necessary signal to decide whether it can
enter LPM mode. Here we use the forever pending irq #125,
unmask it before we enable LPM mode and mask it after LPM
is enabled, this flow will make sure CCM state machine in
reliable state before we enter LPM mode.
Enable "CONFIG_DMA_API_DEBUG" in kernel, and system generate
warning when run up.
WARNING:
/home/b29397/work/projects/linux-2.6-imx/lib/dma-debug.c:865
check_unmap+0x6f8/0x7d8()
net eth0: DMA-API: device driver tries to free DMA memory it
has not allocated [device address=0x00000000443d7040] [size=2048]
[<80025f60>] (warn_slowpath_common+0x0/0x6c) from [<80026070>]
(warn_slowpath_fmt+0x38/0x40) r9:00000000 r8:00000800 r7:807bfb0c
r6:807a3d48 r5:00000000
It is dma memory map/unmap mismatch issue caused by kernel upgrade.
Liu Ying [Wed, 3 Jul 2013 02:51:36 +0000 (10:51 +0800)]
ENGR00269449 mx6q/sdl clk:Correct register writing for aclk_podf
We need to pay attention to writing the 'CCM Serial Clock Multiplexer
Register 1' register since the write value/divider map and the read
value/divider for aclk_podf field are different. In order to keep
the divider value unchanged when writing the other fields of the
register, we need to fixup the write value.
ENGR00269245 MX6SL HDMI: print error message when HDMI cable plugin
When HDMI cable plugin, the frame buffer driver will print error
message "can't do pan display when fb is blank", it is cause by
sii902x driver call fb_set_var after fb power down.
sii902x driver should not mangement fb blank state, it should only
care its own power state.
Remove fb_blank function and replace it
with sii902x power management function.
ENGR00261285-02 Lcdif FB: Fix video timing setting
Correct HSYNC_PERIOD, VSYNC_PERIOD, HORIZONTAL_WAIT_CNT and
VERTICAL_WAIT_CNT setting.
In MX6SL RM, these parmeters define as followed:
- HSYNC_PERIOD: Total number of CLK_DIS_LCDIFn cycles between
two positive or two negative edges of the HSYNC signal.
- VSYNC_PERIOD: Total number of units between two positive
or two negative edges of the VSYNC signal.
- HORIZONTAL_WAIT_CNT:In the DOTCLK mode, wait for this number
of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC
signal to account for horizontal back porch plus the number of
DOTCLKs before the moving picture information begins.
- VERTICAL_WAIT_CNT: In the DOTCLK mode, it accounts for
the veritcal back porch lines plus the number of horizontal lines
before the moving picture begins.
After apply the patch, run HDMI CTS with video mode 480p,720p and 1080p
test case 7-16~7-19, 7-21~7-27 and 7-33 pass.
Liu Ying [Fri, 28 Jun 2013 04:31:45 +0000 (12:31 +0800)]
ENGR00268893 mx6q/sdl clock:Correct emi_clk set/get rate in aclk_podf
The read/write values of aclk_podf[20:22] field in register 'CCM Serial
Clock Multiplexer Register 1' do not match with each other. The read/
write/divider values have the relationship described by the following
table:
============================================================
write value read value description
3b'000 3b'110 divided by 7
3b'001 3b'111 divided by 8
3b'010 3b'100 divided by 5
3b'011 3b'101 divided by 6
3b'100 3b'010 divided by 3
3b'101 3b'011 divided by 4
3b'110 3b'000 divided by 1
3b'111 3b'001 divided by 2(default)
============================================================
This patch corrects the emi_clk set/get rate functions according to
the above table. On i.MX6Q, emi_clk is used by MIPI CSI2 module as
ccm_pixel_clk, while on i.MX6SDL, it is not used by any module.
The patch may resolve the 1080P30 MIPI camera preview blur issue
indirectly by increasing ccm_pixel_clk for i.MX6Q.
The patch include HDMI HDCP patch kernel part:
- Add HDMI DDC pin config function.
- Add HDCP enable/disable system file.
- Read EDID via HDMI internal I2C when HDCP enable.
- Add hdcp_enable in the struct of hdmi_data_info.
- Handle HDCP interrupter and set device event
when HDCP state changed.
- Add IOCTL for HDCP application to get HDMI configuration.
Sandor [Tue, 4 Jun 2013 08:12:08 +0000 (16:12 +0800)]
ENGR00265476 MX6 SabreSD HDMI Compliance test 7-15 failed
MX6DQ/DL SabreSD board HDMI compliance test 7-15 failed, because VCEC2 is
0.276V, but the HDMI compliance test specification 1.4a requried
the VCEC2 should in the range 0.196V to 0.274V.
Remove R657(47K pull up resistance) in SabreSD board and setting
KEY_ROW2_HDMI_TX_CEC pin internal pull up to 100K, the VCEC2 is 0.245V,
pass 7-15 test.
Richard Zhu [Mon, 24 Jun 2013 04:51:41 +0000 (12:51 +0800)]
ENGR00268442 mmc: remove the boot partition access codes on 3.0.35
Regarding to the following community commit, remove all the boot
partition access codes added before.
- 371a689f64b0da140c3bcd3f55305ffa1c3a58ef
mmc: MMC boot partitions support.
Allows device MMC boot partitions to be accessed. MMC partitions are
treated effectively as separate block devices on the same MMC card.
-
Boot partition access howto:
-
To enable write access to /dev/mmcblkXbootY, disable the forced
read-only access with:
Anson Huang [Fri, 21 Jun 2013 00:41:27 +0000 (08:41 +0800)]
ENGR00268110 mx6: eim_clk div can't be used directly
1. eim_clk's divider is bit[22:20], when read from this register,
the value of bit22 and bit21 are the opposite value of actual
value, so we need to handle it in clk get rate function of eim_clk.
2. For VPU running at 352M case on i.MX6Q, we need to set eim
clk to 176M, as its parent's freq is 352M. Otherwise, it is set
to 198M.
Terry Lv [Mon, 24 Jun 2013 12:02:34 +0000 (20:02 +0800)]
ENGR00258998: mlb unit test should exit after click stop on mitb
This patch will do the following:
1. For mlb will not be able to know whether the final package is
completely sent, add a delay for final package to be sent.
2. Adjust MLB's iram buffer usage. Old code will add addtional
usage of iram buffer.
3. Code format change.
4. In resume function, calling init function after clock is enabled.
Liu Ying [Mon, 24 Jun 2013 08:38:32 +0000 (16:38 +0800)]
ENGR00268385 v4l2 fg overlay:disable fb ywrap when enable overlay
This patch disables framebuffer ywrap flag when we enable overlay,
because the display double buffers are not ywrapped. This may avoid
wrong preview pictures on platforms which use NV12 pixel format for
overlay framebuffer.
Richard Zhu [Fri, 14 Jun 2013 01:18:09 +0000 (09:18 +0800)]
ENGR00268112 pcie: emaluate the pcie ep as ram device, configure the bar#
0x0110_0000 ~ 0x01EF_FFFF 14MB would be used for MEM allocation.
But the "IORESOURCE_SIZEALIGN" would be used during the Linux PCI/PCIe
subsystem probe/scan the bus and allocate the resources.
If the 8MB MEM is required, the start address 0x0180_0000 would be used
by Linux PCI/PCIe subsystem, trying to allocate the 8MB MEM space
(0x0180_0000 ~ 0x01FF_FFFF), this operation would be failed.
Because the address if outof 0x0110_0000 ~ 0x01EF_FFFF limitaion.
solution:
One method to allocate the 8MB(the biggest size of IO/MEM space) MEM
space on iMX6 PCIe RC.
Adjust the layout of the 16MB address space of iMX6 PCIe RC, like this:
* RC:
* 0x0100_0000 --- 0x01DF_FFFF 14MB IORESOURCE_MEM
* 0x01E0_0000 --- 0x01EF_FFFF 1MB IORESOURCE_IO
* 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + MSI + Registers
The 8MB space would be allocated from 0x0100_0000 ~ 0x017F_FFFF.
Anson Huang [Tue, 18 Jun 2013 05:57:33 +0000 (13:57 +0800)]
ENGR00267442 mx6: clk: some clock settings are incorrect
1. The ipg_per clock rate setting should be done after
its parent initilization done, otherwise it will get wrong
parent rate and lead to incorrect rate setting;
2. The parent info of emi_clk has been changed in latest RM,
need to update it according to RM, the parent info is as below:
ENGR00240112-1 caam: fix user space crypto API support.
This patch fix the CAAM support for Crypto User Space API support.
in the dma_map_sg_chained() function, the chained mode will loop
until the scatter list end, but when the scatter list end, it will
return null and orignal code will set this to the sg list point
used by dma_sync, so it will panic.
When do chain dma, use a tmp do going through the list.
b02247 [Mon, 14 May 2012 01:54:27 +0000 (09:54 +0800)]
ENGR00181680-2 No audio when play 3 streams after 3~10 seconds sometimes
sdma: bd is bufferable dma buffer, interrupt handler can not get correct
data after sdma script updated. Which will cause there is no interrupt
after failed period number times in the interrupt handler.
This is a workaround.
b02247 [Wed, 9 May 2012 09:30:41 +0000 (17:30 +0800)]
ENGR00181680-1 No audio when play 3 streams after 3~10 seconds sometimes
sdma: bd is bufferable dma buffer, interrupt handler can not get correct
data after sdma script updated. Which will cause there is no interrupt
after failed period number times in the interrupt handler.
This is a workaround.
Jay Monkman [Fri, 14 Jun 2013 16:47:50 +0000 (11:47 -0500)]
ENGR00267024 mx6q: Stop DMA memory fragmentation
Applied patch from customer to prevent DMA memory
fragmentation. Customer reported system crashes due to running out of
DMA-able memory while playing videos. Reported in CT42391649.
Signed-off-by: Jay Monkman <jay.monkman@freescale.com>
Liu Ying [Thu, 13 Jun 2013 04:50:27 +0000 (12:50 +0800)]
ENGR00266881 mxc vout:Flush workqueue when change is needed for streaming
We currently call cancel_work_sync() to have all left work be done. But,
this is not safe to make sure all left work being done successfully.
Instead, chances are that some work may be cancelled before starting
to be done, which may cause frame lost and make us hang at upcoming
wait_event_interruptible() in videobuf_waiton() called from video buffer
core v1 framework's dqbuf API. This patch replaces the function
call cancel_work_sync() with flush_workqueue() to fix the issue.
Liu Ying [Thu, 13 Jun 2013 03:49:56 +0000 (11:49 +0800)]
ENGR00266873 mxc vout:Release or invalidate previous buffers correctly
Users may call VIDIOC_S_CTRL ioctrl to do rotation, such as 90 degree
rotation, when a video is streaming in IC bypass mode. The runtime
rotation setting may make the vout driver lose the track for a previous
video buffer and finally cause the streaming hang. This patch releases
that video buffer in this case and invalidates previous video buffers
when necessary.
Fugang Duan [Sun, 9 Jun 2013 06:43:52 +0000 (14:43 +0800)]
ENGR00266312 mx6dl: add i2c4 bus support for sabresd/auto, arm2 platforms
imx6dq have 3 i2c controllers and 5 ecspi,imx6dl have 4 i2c4
controllers and 4 ecspi. imx6dl i2c4 clock source is routed
from pll3 through to ecspi_root gate.
Add i2c4 bus support for sabresd/auto, and arm2 platforms.
Loren Huang [Tue, 4 Jun 2013 07:08:15 +0000 (15:08 +0800)]
ENGR00265465 gpu:Add global value for minimum 3D clock export
Add global value gpu3DMinClock so that minimum 3D clock can be change by user.
When gpu min clock is too low, it may cause IPU starvation issue in certain case.
Use echo x > /sys/module/galcore/parameters/gpu3DMinClock to change it.
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