4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_WANT_IPC_PARSE_VERSION
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CLONE_BACKWARDS
13 select CPU_PM if (SUSPEND || CPU_IDLE)
14 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
15 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
16 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
17 select GENERIC_IDLE_POLL_SETUP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PCI_IOMAP
21 select GENERIC_SCHED_CLOCK
22 select GENERIC_SMP_IDLE_THREAD
23 select GENERIC_STRNCPY_FROM_USER
24 select GENERIC_STRNLEN_USER
25 select HARDIRQS_SW_RESEND
26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
28 select HAVE_ARCH_SECCOMP_FILTER
29 select HAVE_ARCH_TRACEHOOK
31 select HAVE_CONTEXT_TRACKING
32 select HAVE_C_RECORDMCOUNT
33 select HAVE_DEBUG_KMEMLEAK
34 select HAVE_DMA_API_DEBUG
36 select HAVE_DMA_CONTIGUOUS if MMU
37 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
38 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
39 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
40 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
41 select HAVE_GENERIC_DMA_COHERENT
42 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
43 select HAVE_IDE if PCI || ISA || PCMCIA
44 select HAVE_IRQ_TIME_ACCOUNTING
45 select HAVE_KERNEL_GZIP
46 select HAVE_KERNEL_LZ4
47 select HAVE_KERNEL_LZMA
48 select HAVE_KERNEL_LZO
50 select HAVE_KPROBES if !XIP_KERNEL
51 select HAVE_KRETPROBES if (HAVE_KPROBES)
53 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
54 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
55 select HAVE_PERF_EVENTS
57 select HAVE_PERF_USER_STACK_DUMP
58 select HAVE_REGS_AND_STACK_ACCESS_API
59 select HAVE_SYSCALL_TRACEPOINTS
61 select HAVE_VIRT_CPU_ACCOUNTING_GEN
62 select IRQ_FORCED_THREADING
64 select MODULES_USE_ELF_REL
66 select OLD_SIGSUSPEND3
67 select PERF_USE_VMALLOC
69 select SYS_SUPPORTS_APM_EMULATION
70 # Above selects are sorted alphabetically; please add new ones
71 # according to that. Thanks.
73 The ARM series is a line of low-power-consumption RISC chip designs
74 licensed by ARM Ltd and targeted at embedded applications and
75 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
76 manufactured, but legacy ARM-based PC hardware remains popular in
77 Europe. There is an ARM Linux project with a web page at
78 <http://www.arm.linux.org.uk/>.
80 config ARM_HAS_SG_CHAIN
83 config NEED_SG_DMA_LENGTH
86 config ARM_DMA_USE_IOMMU
88 select ARM_HAS_SG_CHAIN
89 select NEED_SG_DMA_LENGTH
93 config ARM_DMA_IOMMU_ALIGNMENT
94 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
98 DMA mapping framework by default aligns all buffers to the smallest
99 PAGE_SIZE order which is greater than or equal to the requested buffer
100 size. This works well for buffers up to a few hundreds kilobytes, but
101 for larger buffers it just a waste of address space. Drivers which has
102 relatively small addressing window (like 64Mib) might run out of
103 virtual space with just a few allocations.
105 With this parameter you can specify the maximum PAGE_SIZE order for
106 DMA IOMMU buffers. Larger buffers will be aligned only to this
107 specified order. The order is expressed as a power of two multiplied
115 config MIGHT_HAVE_PCI
118 config SYS_SUPPORTS_APM_EMULATION
123 select GENERIC_ALLOCATOR
134 The Extended Industry Standard Architecture (EISA) bus was
135 developed as an open alternative to the IBM MicroChannel bus.
137 The EISA bus provided some of the features of the IBM MicroChannel
138 bus while maintaining backward compatibility with cards made for
139 the older ISA bus. The EISA bus saw limited use between 1988 and
140 1995 when it was made obsolete by the PCI bus.
142 Say Y here if you are building a kernel for an EISA-based machine.
149 config STACKTRACE_SUPPORT
153 config HAVE_LATENCYTOP_SUPPORT
158 config LOCKDEP_SUPPORT
162 config TRACE_IRQFLAGS_SUPPORT
166 config RWSEM_GENERIC_SPINLOCK
170 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_CPUFREQ
182 Internal node to signify that the ARCH has CPUFREQ support
183 and that the relevant menu configurations are displayed for
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_HAS_DMA_SET_COHERENT_MASK
209 config GENERIC_ISA_DMA
215 config NEED_RET_TO_USER
223 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
224 default DRAM_BASE if REMAP_VECTORS_TO_RAM
227 The base address of exception vectors. This must be two pages
230 config ARM_PATCH_PHYS_VIRT
231 bool "Patch physical to virtual translations at runtime" if EMBEDDED
233 depends on !XIP_KERNEL && MMU
234 depends on !ARCH_REALVIEW || !SPARSEMEM
236 Patch phys-to-virt and virt-to-phys translation functions at
237 boot and module load time according to the position of the
238 kernel in system memory.
240 This can only be used with non-XIP MMU kernels where the base
241 of physical memory is at a 16MB boundary.
243 Only disable this option if you know that you do not require
244 this feature (eg, building a kernel for a single machine) and
245 you need to shrink the kernel to the minimal size.
247 config NEED_MACH_GPIO_H
250 Select this when mach/gpio.h is required to provide special
251 definitions for this platform. The need for mach/gpio.h should
252 be avoided when possible.
254 config NEED_MACH_IO_H
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
261 config NEED_MACH_MEMORY_H
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
271 default DRAM_BASE if !MMU
273 Please provide the physical address corresponding to the
274 location of main memory in your system.
280 source "init/Kconfig"
282 source "kernel/Kconfig.freezer"
287 bool "MMU-based Paged Memory Management Support"
290 Select if you want MMU-based virtualised addressing space
291 support by paged memory management. If unsure, say 'Y'.
294 # The "ARM system type" choice list is ordered alphabetically by option
295 # text. Please add new entries in the option alphabetic order.
298 prompt "ARM system type"
299 default ARCH_VERSATILE if !MMU
300 default ARCH_MULTIPLATFORM if MMU
302 config ARCH_MULTIPLATFORM
303 bool "Allow multiple platforms to be selected"
305 select ARM_PATCH_PHYS_VIRT
308 select MULTI_IRQ_HANDLER
312 config ARCH_INTEGRATOR
313 bool "ARM Ltd. Integrator family"
314 select ARCH_HAS_CPUFREQ
317 select COMMON_CLK_VERSATILE
318 select GENERIC_CLOCKEVENTS
321 select MULTI_IRQ_HANDLER
322 select NEED_MACH_MEMORY_H
323 select PLAT_VERSATILE
325 select VERSATILE_FPGA_IRQ
327 Support for ARM's Integrator platform.
330 bool "ARM Ltd. RealView family"
331 select ARCH_WANT_OPTIONAL_GPIOLIB
333 select ARM_TIMER_SP804
335 select COMMON_CLK_VERSATILE
336 select GENERIC_CLOCKEVENTS
337 select GPIO_PL061 if GPIOLIB
339 select NEED_MACH_MEMORY_H
340 select PLAT_VERSATILE
341 select PLAT_VERSATILE_CLCD
343 This enables support for ARM Ltd RealView boards.
345 config ARCH_VERSATILE
346 bool "ARM Ltd. Versatile family"
347 select ARCH_WANT_OPTIONAL_GPIOLIB
349 select ARM_TIMER_SP804
352 select GENERIC_CLOCKEVENTS
353 select HAVE_MACH_CLKDEV
355 select PLAT_VERSATILE
356 select PLAT_VERSATILE_CLCD
357 select PLAT_VERSATILE_CLOCK
358 select VERSATILE_FPGA_IRQ
360 This enables support for ARM Ltd Versatile board.
364 select ARCH_REQUIRE_GPIOLIB
368 select NEED_MACH_GPIO_H
369 select NEED_MACH_IO_H if PCCARD
371 select PINCTRL_AT91 if USE_OF
373 This enables support for systems based on Atmel
374 AT91RM9200 and AT91SAM9* processors.
377 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
378 select ARCH_REQUIRE_GPIOLIB
384 select GENERIC_CLOCKEVENTS
386 select MULTI_IRQ_HANDLER
389 Support for Cirrus Logic 711x/721x/731x based boards.
392 bool "Cortina Systems Gemini"
393 select ARCH_REQUIRE_GPIOLIB
394 select ARCH_USES_GETTIMEOFFSET
396 select NEED_MACH_GPIO_H
398 Support for the Cortina Systems Gemini family SoCs
402 select ARCH_USES_GETTIMEOFFSET
405 select NEED_MACH_IO_H
406 select NEED_MACH_MEMORY_H
409 This is an evaluation board for the StrongARM processor available
410 from Digital. It has limited hardware on-board, including an
411 Ethernet interface, two PCMCIA sockets, two serial ports and a
416 select ARCH_HAS_HOLES_MEMORYMODEL
417 select ARCH_REQUIRE_GPIOLIB
418 select ARCH_USES_GETTIMEOFFSET
423 select NEED_MACH_MEMORY_H
425 This enables support for the Cirrus EP93xx series of CPUs.
427 config ARCH_FOOTBRIDGE
431 select GENERIC_CLOCKEVENTS
433 select NEED_MACH_IO_H if !MMU
434 select NEED_MACH_MEMORY_H
436 Support for systems based on the DC21285 companion chip
437 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
440 bool "Hilscher NetX based"
444 select GENERIC_CLOCKEVENTS
446 This enables support for systems based on the Hilscher NetX Soc
452 select NEED_MACH_MEMORY_H
453 select NEED_RET_TO_USER
458 Support for Intel's IOP13XX (XScale) family of processors.
463 select ARCH_REQUIRE_GPIOLIB
465 select NEED_MACH_GPIO_H
466 select NEED_RET_TO_USER
470 Support for Intel's 80219 and IOP32X (XScale) family of
476 select ARCH_REQUIRE_GPIOLIB
478 select NEED_MACH_GPIO_H
479 select NEED_RET_TO_USER
483 Support for Intel's IOP33X (XScale) family of processors.
488 select ARCH_HAS_DMA_SET_COHERENT_MASK
489 select ARCH_REQUIRE_GPIOLIB
492 select DMABOUNCE if PCI
493 select GENERIC_CLOCKEVENTS
494 select MIGHT_HAVE_PCI
495 select NEED_MACH_IO_H
496 select USB_EHCI_BIG_ENDIAN_DESC
497 select USB_EHCI_BIG_ENDIAN_MMIO
499 Support for Intel's IXP4XX (XScale) family of processors.
503 select ARCH_REQUIRE_GPIOLIB
505 select GENERIC_CLOCKEVENTS
506 select MIGHT_HAVE_PCI
510 select PLAT_ORION_LEGACY
511 select USB_ARCH_HAS_EHCI
513 Support for the Marvell Dove SoC 88AP510
516 bool "Marvell Kirkwood"
517 select ARCH_HAS_CPUFREQ
518 select ARCH_REQUIRE_GPIOLIB
520 select GENERIC_CLOCKEVENTS
525 select PINCTRL_KIRKWOOD
526 select PLAT_ORION_LEGACY
528 Support for the following Marvell Kirkwood series SoCs:
529 88F6180, 88F6192 and 88F6281.
532 bool "Marvell MV78xx0"
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
538 select PLAT_ORION_LEGACY
540 Support for the following Marvell MV78xx0 series SoCs:
546 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
551 select PLAT_ORION_LEGACY
553 Support for the following Marvell Orion 5x series SoCs:
554 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
555 Orion-2 (5281), Orion-1-90 (6183).
558 bool "Marvell PXA168/910/MMP2"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_ALLOCATOR
563 select GENERIC_CLOCKEVENTS
566 select MULTI_IRQ_HANDLER
567 select NEED_MACH_GPIO_H
572 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
575 bool "Micrel/Kendin KS8695"
576 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
580 select NEED_MACH_MEMORY_H
582 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
583 System-on-Chip devices.
586 bool "Nuvoton W90X900 CPU"
587 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_CLOCKEVENTS
593 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
594 At present, the w90x900 has been renamed nuc900, regarding
595 the ARM series product line, you can login the following
596 link address to know more.
598 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
599 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
603 select ARCH_REQUIRE_GPIOLIB
608 select GENERIC_CLOCKEVENTS
611 select USB_ARCH_HAS_OHCI
614 Support for the NXP LPC32XX family of processors
617 bool "PXA2xx/PXA3xx-based"
619 select ARCH_HAS_CPUFREQ
621 select ARCH_REQUIRE_GPIOLIB
622 select ARM_CPU_SUSPEND if PM
626 select GENERIC_CLOCKEVENTS
629 select MULTI_IRQ_HANDLER
630 select NEED_MACH_GPIO_H
634 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
638 select ARCH_REQUIRE_GPIOLIB
640 select CLKSRC_OF if OF
642 select GENERIC_CLOCKEVENTS
644 Support for Qualcomm MSM/QSD based systems. This runs on the
645 apps processor of the MSM/QSD and depends on a shared memory
646 interface to the modem processor which runs the baseband
647 stack and controls some vital subsystems
648 (clock and power control, etc).
651 bool "Renesas SH-Mobile / R-Mobile"
652 select ARM_PATCH_PHYS_VIRT
654 select GENERIC_CLOCKEVENTS
655 select HAVE_ARM_SCU if SMP
656 select HAVE_ARM_TWD if SMP
658 select HAVE_MACH_CLKDEV
660 select MIGHT_HAVE_CACHE_L2X0
661 select MULTI_IRQ_HANDLER
664 select PM_GENERIC_DOMAINS if PM
667 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
672 select ARCH_MAY_HAVE_PC_FDC
673 select ARCH_SPARSEMEM_ENABLE
674 select ARCH_USES_GETTIMEOFFSET
677 select HAVE_PATA_PLATFORM
679 select NEED_MACH_IO_H
680 select NEED_MACH_MEMORY_H
684 On the Acorn Risc-PC, Linux can support the internal IDE disk and
685 CD-ROM interface, serial and parallel port, and the floppy drive.
689 select ARCH_HAS_CPUFREQ
691 select ARCH_REQUIRE_GPIOLIB
692 select ARCH_SPARSEMEM_ENABLE
697 select GENERIC_CLOCKEVENTS
700 select NEED_MACH_MEMORY_H
703 Support for StrongARM 11x0 based boards.
706 bool "Samsung S3C24XX SoCs"
707 select ARCH_HAS_CPUFREQ
708 select ARCH_REQUIRE_GPIOLIB
710 select CLKSRC_SAMSUNG_PWM
711 select GENERIC_CLOCKEVENTS
714 select HAVE_S3C2410_I2C if I2C
715 select HAVE_S3C2410_WATCHDOG if WATCHDOG
716 select HAVE_S3C_RTC if RTC_CLASS
717 select MULTI_IRQ_HANDLER
718 select NEED_MACH_GPIO_H
719 select NEED_MACH_IO_H
722 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
723 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
724 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
725 Samsung SMDK2410 development board (and derivatives).
728 bool "Samsung S3C64XX"
729 select ARCH_HAS_CPUFREQ
730 select ARCH_REQUIRE_GPIOLIB
733 select CLKSRC_SAMSUNG_PWM
735 select GENERIC_CLOCKEVENTS
738 select HAVE_S3C2410_I2C if I2C
739 select HAVE_S3C2410_WATCHDOG if WATCHDOG
741 select NEED_MACH_GPIO_H
745 select S3C_GPIO_TRACK
747 select SAMSUNG_CLKSRC
748 select SAMSUNG_GPIOLIB_4BIT
749 select SAMSUNG_WDT_RESET
750 select USB_ARCH_HAS_OHCI
752 Samsung S3C64XX series based systems
755 bool "Samsung S5P6440 S5P6450"
757 select CLKSRC_SAMSUNG_PWM
759 select GENERIC_CLOCKEVENTS
762 select HAVE_S3C2410_I2C if I2C
763 select HAVE_S3C2410_WATCHDOG if WATCHDOG
764 select HAVE_S3C_RTC if RTC_CLASS
765 select NEED_MACH_GPIO_H
767 select SAMSUNG_WDT_RESET
769 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
773 bool "Samsung S5PC100"
774 select ARCH_REQUIRE_GPIOLIB
776 select CLKSRC_SAMSUNG_PWM
778 select GENERIC_CLOCKEVENTS
781 select HAVE_S3C2410_I2C if I2C
782 select HAVE_S3C2410_WATCHDOG if WATCHDOG
783 select HAVE_S3C_RTC if RTC_CLASS
784 select NEED_MACH_GPIO_H
786 select SAMSUNG_WDT_RESET
788 Samsung S5PC100 series based systems
791 bool "Samsung S5PV210/S5PC110"
792 select ARCH_HAS_CPUFREQ
793 select ARCH_HAS_HOLES_MEMORYMODEL
794 select ARCH_SPARSEMEM_ENABLE
796 select CLKSRC_SAMSUNG_PWM
798 select GENERIC_CLOCKEVENTS
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 select HAVE_S3C_RTC if RTC_CLASS
804 select NEED_MACH_GPIO_H
805 select NEED_MACH_MEMORY_H
808 Samsung S5PV210/S5PC110 series based systems
811 bool "Samsung EXYNOS"
812 select ARCH_HAS_CPUFREQ
813 select ARCH_HAS_HOLES_MEMORYMODEL
814 select ARCH_REQUIRE_GPIOLIB
815 select ARCH_SPARSEMEM_ENABLE
820 select GENERIC_CLOCKEVENTS
822 select HAVE_S3C2410_I2C if I2C
823 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 select HAVE_S3C_RTC if RTC_CLASS
825 select NEED_MACH_MEMORY_H
829 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
833 select ARCH_USES_GETTIMEOFFSET
837 select NEED_MACH_MEMORY_H
842 Support for the StrongARM based Digital DNARD machine, also known
843 as "Shark" (<http://www.shark-linux.de/shark.html>).
847 select ARCH_HAS_HOLES_MEMORYMODEL
848 select ARCH_REQUIRE_GPIOLIB
850 select GENERIC_ALLOCATOR
851 select GENERIC_CLOCKEVENTS
852 select GENERIC_IRQ_CHIP
854 select NEED_MACH_GPIO_H
859 Support for TI's DaVinci platform.
864 select ARCH_HAS_CPUFREQ
865 select ARCH_HAS_HOLES_MEMORYMODEL
867 select ARCH_REQUIRE_GPIOLIB
870 select GENERIC_CLOCKEVENTS
871 select GENERIC_IRQ_CHIP
875 select NEED_MACH_IO_H if PCCARD
876 select NEED_MACH_MEMORY_H
878 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
882 menu "Multiple platform selection"
883 depends on ARCH_MULTIPLATFORM
885 comment "CPU Core family selection"
887 config ARCH_MULTI_V4T
888 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
889 depends on !ARCH_MULTI_V6_V7
890 select ARCH_MULTI_V4_V5
891 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
892 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
893 CPU_ARM925T || CPU_ARM940T)
896 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
897 depends on !ARCH_MULTI_V6_V7
898 select ARCH_MULTI_V4_V5
899 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
900 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
901 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
903 config ARCH_MULTI_V4_V5
907 bool "ARMv6 based platforms (ARM11)"
908 select ARCH_MULTI_V6_V7
912 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
914 select ARCH_MULTI_V6_V7
917 config ARCH_MULTI_V6_V7
920 config ARCH_MULTI_CPU_AUTO
921 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
927 # This is sorted alphabetically by mach-* pathname. However, plat-*
928 # Kconfigs may be included either alphabetically (according to the
929 # plat- suffix) or along side the corresponding mach-* source.
931 source "arch/arm/mach-mvebu/Kconfig"
933 source "arch/arm/mach-at91/Kconfig"
935 source "arch/arm/mach-bcm/Kconfig"
937 source "arch/arm/mach-bcm2835/Kconfig"
939 source "arch/arm/mach-clps711x/Kconfig"
941 source "arch/arm/mach-cns3xxx/Kconfig"
943 source "arch/arm/mach-davinci/Kconfig"
945 source "arch/arm/mach-dove/Kconfig"
947 source "arch/arm/mach-ep93xx/Kconfig"
949 source "arch/arm/mach-footbridge/Kconfig"
951 source "arch/arm/mach-gemini/Kconfig"
953 source "arch/arm/mach-highbank/Kconfig"
955 source "arch/arm/mach-integrator/Kconfig"
957 source "arch/arm/mach-iop32x/Kconfig"
959 source "arch/arm/mach-iop33x/Kconfig"
961 source "arch/arm/mach-iop13xx/Kconfig"
963 source "arch/arm/mach-ixp4xx/Kconfig"
965 source "arch/arm/mach-keystone/Kconfig"
967 source "arch/arm/mach-kirkwood/Kconfig"
969 source "arch/arm/mach-ks8695/Kconfig"
971 source "arch/arm/mach-msm/Kconfig"
973 source "arch/arm/mach-mv78xx0/Kconfig"
975 source "arch/arm/mach-imx/Kconfig"
977 source "arch/arm/mach-mxs/Kconfig"
979 source "arch/arm/mach-netx/Kconfig"
981 source "arch/arm/mach-nomadik/Kconfig"
983 source "arch/arm/mach-nspire/Kconfig"
985 source "arch/arm/plat-omap/Kconfig"
987 source "arch/arm/mach-omap1/Kconfig"
989 source "arch/arm/mach-omap2/Kconfig"
991 source "arch/arm/mach-orion5x/Kconfig"
993 source "arch/arm/mach-picoxcell/Kconfig"
995 source "arch/arm/mach-pxa/Kconfig"
996 source "arch/arm/plat-pxa/Kconfig"
998 source "arch/arm/mach-mmp/Kconfig"
1000 source "arch/arm/mach-realview/Kconfig"
1002 source "arch/arm/mach-rockchip/Kconfig"
1004 source "arch/arm/mach-sa1100/Kconfig"
1006 source "arch/arm/plat-samsung/Kconfig"
1008 source "arch/arm/mach-socfpga/Kconfig"
1010 source "arch/arm/mach-spear/Kconfig"
1012 source "arch/arm/mach-sti/Kconfig"
1014 source "arch/arm/mach-s3c24xx/Kconfig"
1017 source "arch/arm/mach-s3c64xx/Kconfig"
1020 source "arch/arm/mach-s5p64x0/Kconfig"
1022 source "arch/arm/mach-s5pc100/Kconfig"
1024 source "arch/arm/mach-s5pv210/Kconfig"
1026 source "arch/arm/mach-exynos/Kconfig"
1028 source "arch/arm/mach-shmobile/Kconfig"
1030 source "arch/arm/mach-sunxi/Kconfig"
1032 source "arch/arm/mach-prima2/Kconfig"
1034 source "arch/arm/mach-tegra/Kconfig"
1036 source "arch/arm/mach-u300/Kconfig"
1038 source "arch/arm/mach-ux500/Kconfig"
1040 source "arch/arm/mach-versatile/Kconfig"
1042 source "arch/arm/mach-vexpress/Kconfig"
1043 source "arch/arm/plat-versatile/Kconfig"
1045 source "arch/arm/mach-virt/Kconfig"
1047 source "arch/arm/mach-vt8500/Kconfig"
1049 source "arch/arm/mach-w90x900/Kconfig"
1051 source "arch/arm/mach-zynq/Kconfig"
1053 # Definitions to make life easier
1059 select GENERIC_CLOCKEVENTS
1065 select GENERIC_IRQ_CHIP
1068 config PLAT_ORION_LEGACY
1075 config PLAT_VERSATILE
1078 config ARM_TIMER_SP804
1081 select CLKSRC_OF if OF
1083 source arch/arm/mm/Kconfig
1087 default 16 if ARCH_EP93XX
1091 bool "Enable iWMMXt support" if !CPU_PJ4
1092 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1093 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1095 Enable support for iWMMXt context switching at run time if
1096 running on a CPU that supports it.
1100 depends on CPU_XSCALE
1103 config MULTI_IRQ_HANDLER
1106 Allow each machine to specify it's own IRQ handler at run time.
1109 source "arch/arm/Kconfig-nommu"
1112 config PJ4B_ERRATA_4742
1113 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1114 depends on CPU_PJ4B && MACH_ARMADA_370
1117 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1118 Event (WFE) IDLE states, a specific timing sensitivity exists between
1119 the retiring WFI/WFE instructions and the newly issued subsequent
1120 instructions. This sensitivity can result in a CPU hang scenario.
1122 The software must insert either a Data Synchronization Barrier (DSB)
1123 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1126 config ARM_ERRATA_326103
1127 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1130 Executing a SWP instruction to read-only memory does not set bit 11
1131 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1132 treat the access as a read, preventing a COW from occurring and
1133 causing the faulting task to livelock.
1135 config ARM_ERRATA_411920
1136 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1137 depends on CPU_V6 || CPU_V6K
1139 Invalidation of the Instruction Cache operation can
1140 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1141 It does not affect the MPCore. This option enables the ARM Ltd.
1142 recommended workaround.
1144 config ARM_ERRATA_430973
1145 bool "ARM errata: Stale prediction on replaced interworking branch"
1148 This option enables the workaround for the 430973 Cortex-A8
1149 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1150 interworking branch is replaced with another code sequence at the
1151 same virtual address, whether due to self-modifying code or virtual
1152 to physical address re-mapping, Cortex-A8 does not recover from the
1153 stale interworking branch prediction. This results in Cortex-A8
1154 executing the new code sequence in the incorrect ARM or Thumb state.
1155 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1156 and also flushes the branch target cache at every context switch.
1157 Note that setting specific bits in the ACTLR register may not be
1158 available in non-secure mode.
1160 config ARM_ERRATA_458693
1161 bool "ARM errata: Processor deadlock when a false hazard is created"
1163 depends on !ARCH_MULTIPLATFORM
1165 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1166 erratum. For very specific sequences of memory operations, it is
1167 possible for a hazard condition intended for a cache line to instead
1168 be incorrectly associated with a different cache line. This false
1169 hazard might then cause a processor deadlock. The workaround enables
1170 the L1 caching of the NEON accesses and disables the PLD instruction
1171 in the ACTLR register. Note that setting specific bits in the ACTLR
1172 register may not be available in non-secure mode.
1174 config ARM_ERRATA_460075
1175 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1177 depends on !ARCH_MULTIPLATFORM
1179 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1180 erratum. Any asynchronous access to the L2 cache may encounter a
1181 situation in which recent store transactions to the L2 cache are lost
1182 and overwritten with stale memory contents from external memory. The
1183 workaround disables the write-allocate mode for the L2 cache via the
1184 ACTLR register. Note that setting specific bits in the ACTLR register
1185 may not be available in non-secure mode.
1187 config ARM_ERRATA_742230
1188 bool "ARM errata: DMB operation may be faulty"
1189 depends on CPU_V7 && SMP
1190 depends on !ARCH_MULTIPLATFORM
1192 This option enables the workaround for the 742230 Cortex-A9
1193 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1194 between two write operations may not ensure the correct visibility
1195 ordering of the two writes. This workaround sets a specific bit in
1196 the diagnostic register of the Cortex-A9 which causes the DMB
1197 instruction to behave as a DSB, ensuring the correct behaviour of
1200 config ARM_ERRATA_742231
1201 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1202 depends on CPU_V7 && SMP
1203 depends on !ARCH_MULTIPLATFORM
1205 This option enables the workaround for the 742231 Cortex-A9
1206 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1207 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1208 accessing some data located in the same cache line, may get corrupted
1209 data due to bad handling of the address hazard when the line gets
1210 replaced from one of the CPUs at the same time as another CPU is
1211 accessing it. This workaround sets specific bits in the diagnostic
1212 register of the Cortex-A9 which reduces the linefill issuing
1213 capabilities of the processor.
1215 config PL310_ERRATA_588369
1216 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1217 depends on CACHE_L2X0
1219 The PL310 L2 cache controller implements three types of Clean &
1220 Invalidate maintenance operations: by Physical Address
1221 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1222 They are architecturally defined to behave as the execution of a
1223 clean operation followed immediately by an invalidate operation,
1224 both performing to the same memory location. This functionality
1225 is not correctly implemented in PL310 as clean lines are not
1226 invalidated as a result of these operations.
1228 config ARM_ERRATA_643719
1229 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1230 depends on CPU_V7 && SMP
1232 This option enables the workaround for the 643719 Cortex-A9 (prior to
1233 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1234 register returns zero when it should return one. The workaround
1235 corrects this value, ensuring cache maintenance operations which use
1236 it behave as intended and avoiding data corruption.
1238 config ARM_ERRATA_720789
1239 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1242 This option enables the workaround for the 720789 Cortex-A9 (prior to
1243 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1244 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1245 As a consequence of this erratum, some TLB entries which should be
1246 invalidated are not, resulting in an incoherency in the system page
1247 tables. The workaround changes the TLB flushing routines to invalidate
1248 entries regardless of the ASID.
1250 config PL310_ERRATA_727915
1251 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1252 depends on CACHE_L2X0
1254 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1255 operation (offset 0x7FC). This operation runs in background so that
1256 PL310 can handle normal accesses while it is in progress. Under very
1257 rare circumstances, due to this erratum, write data can be lost when
1258 PL310 treats a cacheable write transaction during a Clean &
1259 Invalidate by Way operation.
1261 config ARM_ERRATA_743622
1262 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1264 depends on !ARCH_MULTIPLATFORM
1266 This option enables the workaround for the 743622 Cortex-A9
1267 (r2p*) erratum. Under very rare conditions, a faulty
1268 optimisation in the Cortex-A9 Store Buffer may lead to data
1269 corruption. This workaround sets a specific bit in the diagnostic
1270 register of the Cortex-A9 which disables the Store Buffer
1271 optimisation, preventing the defect from occurring. This has no
1272 visible impact on the overall performance or power consumption of the
1275 config ARM_ERRATA_751472
1276 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1278 depends on !ARCH_MULTIPLATFORM
1280 This option enables the workaround for the 751472 Cortex-A9 (prior
1281 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1282 completion of a following broadcasted operation if the second
1283 operation is received by a CPU before the ICIALLUIS has completed,
1284 potentially leading to corrupted entries in the cache or TLB.
1286 config PL310_ERRATA_753970
1287 bool "PL310 errata: cache sync operation may be faulty"
1288 depends on CACHE_PL310
1290 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1292 Under some condition the effect of cache sync operation on
1293 the store buffer still remains when the operation completes.
1294 This means that the store buffer is always asked to drain and
1295 this prevents it from merging any further writes. The workaround
1296 is to replace the normal offset of cache sync operation (0x730)
1297 by another offset targeting an unmapped PL310 register 0x740.
1298 This has the same effect as the cache sync operation: store buffer
1299 drain and waiting for all buffers empty.
1301 config ARM_ERRATA_754322
1302 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1305 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1306 r3p*) erratum. A speculative memory access may cause a page table walk
1307 which starts prior to an ASID switch but completes afterwards. This
1308 can populate the micro-TLB with a stale entry which may be hit with
1309 the new ASID. This workaround places two dsb instructions in the mm
1310 switching code so that no page table walks can cross the ASID switch.
1312 config ARM_ERRATA_754327
1313 bool "ARM errata: no automatic Store Buffer drain"
1314 depends on CPU_V7 && SMP
1316 This option enables the workaround for the 754327 Cortex-A9 (prior to
1317 r2p0) erratum. The Store Buffer does not have any automatic draining
1318 mechanism and therefore a livelock may occur if an external agent
1319 continuously polls a memory location waiting to observe an update.
1320 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1321 written polling loops from denying visibility of updates to memory.
1323 config ARM_ERRATA_364296
1324 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1327 This options enables the workaround for the 364296 ARM1136
1328 r0p2 erratum (possible cache data corruption with
1329 hit-under-miss enabled). It sets the undocumented bit 31 in
1330 the auxiliary control register and the FI bit in the control
1331 register, thus disabling hit-under-miss without putting the
1332 processor into full low interrupt latency mode. ARM11MPCore
1335 config ARM_ERRATA_764369
1336 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1337 depends on CPU_V7 && SMP
1339 This option enables the workaround for erratum 764369
1340 affecting Cortex-A9 MPCore with two or more processors (all
1341 current revisions). Under certain timing circumstances, a data
1342 cache line maintenance operation by MVA targeting an Inner
1343 Shareable memory region may fail to proceed up to either the
1344 Point of Coherency or to the Point of Unification of the
1345 system. This workaround adds a DSB instruction before the
1346 relevant cache maintenance functions and sets a specific bit
1347 in the diagnostic control register of the SCU.
1349 config PL310_ERRATA_769419
1350 bool "PL310 errata: no automatic Store Buffer drain"
1351 depends on CACHE_L2X0
1353 On revisions of the PL310 prior to r3p2, the Store Buffer does
1354 not automatically drain. This can cause normal, non-cacheable
1355 writes to be retained when the memory system is idle, leading
1356 to suboptimal I/O performance for drivers using coherent DMA.
1357 This option adds a write barrier to the cpu_idle loop so that,
1358 on systems with an outer cache, the store buffer is drained
1361 config ARM_ERRATA_775420
1362 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1365 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1366 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1367 operation aborts with MMU exception, it might cause the processor
1368 to deadlock. This workaround puts DSB before executing ISB if
1369 an abort may occur on cache maintenance.
1371 config ARM_ERRATA_798181
1372 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1373 depends on CPU_V7 && SMP
1375 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1376 adequately shooting down all use of the old entries. This
1377 option enables the Linux kernel workaround for this erratum
1378 which sends an IPI to the CPUs that are running the same ASID
1379 as the one being invalidated.
1381 config ARM_ERRATA_773022
1382 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1385 This option enables the workaround for the 773022 Cortex-A15
1386 (up to r0p4) erratum. In certain rare sequences of code, the
1387 loop buffer may deliver incorrect instructions. This
1388 workaround disables the loop buffer to avoid the erratum.
1392 source "arch/arm/common/Kconfig"
1402 Find out whether you have ISA slots on your motherboard. ISA is the
1403 name of a bus system, i.e. the way the CPU talks to the other stuff
1404 inside your box. Other bus systems are PCI, EISA, MicroChannel
1405 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1406 newer boards don't support it. If you have ISA, say Y, otherwise N.
1408 # Select ISA DMA controller support
1413 # Select ISA DMA interface
1418 bool "PCI support" if MIGHT_HAVE_PCI
1420 Find out whether you have a PCI motherboard. PCI is the name of a
1421 bus system, i.e. the way the CPU talks to the other stuff inside
1422 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1423 VESA. If you have PCI, say Y, otherwise N.
1429 config PCI_NANOENGINE
1430 bool "BSE nanoEngine PCI support"
1431 depends on SA1100_NANOENGINE
1433 Enable PCI on the BSE nanoEngine board.
1438 # Select the host bridge type
1439 config PCI_HOST_VIA82C505
1441 depends on PCI && ARCH_SHARK
1444 config PCI_HOST_ITE8152
1446 depends on PCI && MACH_ARMCORE
1450 source "drivers/pci/Kconfig"
1451 source "drivers/pci/pcie/Kconfig"
1453 source "drivers/pcmcia/Kconfig"
1457 menu "Kernel Features"
1462 This option should be selected by machines which have an SMP-
1465 The only effect of this option is to make the SMP-related
1466 options available to the user for configuration.
1469 bool "Symmetric Multi-Processing"
1470 depends on CPU_V6K || CPU_V7
1471 depends on GENERIC_CLOCKEVENTS
1473 depends on MMU || ARM_MPU
1474 select USE_GENERIC_SMP_HELPERS
1476 This enables support for systems with more than one CPU. If you have
1477 a system with only one CPU, like most personal computers, say N. If
1478 you have a system with more than one CPU, say Y.
1480 If you say N here, the kernel will run on single and multiprocessor
1481 machines, but will use only one CPU of a multiprocessor machine. If
1482 you say Y here, the kernel will run on many, but not all, single
1483 processor machines. On a single processor machine, the kernel will
1484 run faster if you say N here.
1486 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1487 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1488 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1490 If you don't know what to do here, say N.
1493 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1494 depends on SMP && !XIP_KERNEL && MMU
1497 SMP kernels contain instructions which fail on non-SMP processors.
1498 Enabling this option allows the kernel to modify itself to make
1499 these instructions safe. Disabling it allows about 1K of space
1502 If you don't know what to do here, say Y.
1504 config ARM_CPU_TOPOLOGY
1505 bool "Support cpu topology definition"
1506 depends on SMP && CPU_V7
1509 Support ARM cpu topology definition. The MPIDR register defines
1510 affinity between processors which is then used to describe the cpu
1511 topology of an ARM System.
1514 bool "Multi-core scheduler support"
1515 depends on ARM_CPU_TOPOLOGY
1517 Multi-core scheduler support improves the CPU scheduler's decision
1518 making when dealing with multi-core CPU chips at a cost of slightly
1519 increased overhead in some places. If unsure say N here.
1522 bool "SMT scheduler support"
1523 depends on ARM_CPU_TOPOLOGY
1525 Improves the CPU scheduler's decision making when dealing with
1526 MultiThreading at a cost of slightly increased overhead in some
1527 places. If unsure say N here.
1532 This option enables support for the ARM system coherency unit
1534 config HAVE_ARM_ARCH_TIMER
1535 bool "Architected timer support"
1537 select ARM_ARCH_TIMER
1539 This option enables support for the ARM architected timer
1544 select CLKSRC_OF if OF
1546 This options enables support for the ARM timer and watchdog unit
1549 bool "Multi-Cluster Power Management"
1550 depends on CPU_V7 && SMP
1552 This option provides the common power management infrastructure
1553 for (multi-)cluster based systems, such as big.LITTLE based
1557 bool "big.LITTLE support (Experimental)"
1558 depends on CPU_V7 && SMP
1561 This option enables support selections for the big.LITTLE
1562 system architecture.
1565 bool "big.LITTLE switcher support"
1566 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1568 select ARM_CPU_SUSPEND
1570 The big.LITTLE "switcher" provides the core functionality to
1571 transparently handle transition between a cluster of A15's
1572 and a cluster of A7's in a big.LITTLE system.
1574 config BL_SWITCHER_DUMMY_IF
1575 tristate "Simple big.LITTLE switcher user interface"
1576 depends on BL_SWITCHER && DEBUG_KERNEL
1578 This is a simple and dummy char dev interface to control
1579 the big.LITTLE switcher core code. It is meant for
1580 debugging purposes only.
1583 prompt "Memory split"
1586 Select the desired split between kernel and user memory.
1588 If you are not absolutely sure what you are doing, leave this
1592 bool "3G/1G user/kernel split"
1594 bool "2G/2G user/kernel split"
1596 bool "1G/3G user/kernel split"
1601 default 0x40000000 if VMSPLIT_1G
1602 default 0x80000000 if VMSPLIT_2G
1606 int "Maximum number of CPUs (2-32)"
1612 bool "Support for hot-pluggable CPUs"
1615 Say Y here to experiment with turning CPUs off and on. CPUs
1616 can be controlled through /sys/devices/system/cpu.
1619 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1622 Say Y here if you want Linux to communicate with system firmware
1623 implementing the PSCI specification for CPU-centric power
1624 management operations described in ARM document number ARM DEN
1625 0022A ("Power State Coordination Interface System Software on
1628 # The GPIO number here must be sorted by descending number. In case of
1629 # a multiplatform kernel, we just want the highest value required by the
1630 # selected platforms.
1633 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1634 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1635 default 392 if ARCH_U8500
1636 default 352 if ARCH_VT8500
1637 default 288 if ARCH_SUNXI
1638 default 264 if MACH_H4700
1641 Maximum number of GPIOs in the system.
1643 If unsure, leave the default value.
1645 source kernel/Kconfig.preempt
1649 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1650 ARCH_S5PV210 || ARCH_EXYNOS4
1651 default AT91_TIMER_HZ if ARCH_AT91
1652 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1656 depends on HZ_FIXED = 0
1657 prompt "Timer frequency"
1681 default HZ_FIXED if HZ_FIXED != 0
1682 default 100 if HZ_100
1683 default 200 if HZ_200
1684 default 250 if HZ_250
1685 default 300 if HZ_300
1686 default 500 if HZ_500
1690 def_bool HIGH_RES_TIMERS
1693 def_bool HIGH_RES_TIMERS
1695 config THUMB2_KERNEL
1696 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1697 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1698 default y if CPU_THUMBONLY
1700 select ARM_ASM_UNIFIED
1703 By enabling this option, the kernel will be compiled in
1704 Thumb-2 mode. A compiler/assembler that understand the unified
1705 ARM-Thumb syntax is needed.
1709 config THUMB2_AVOID_R_ARM_THM_JUMP11
1710 bool "Work around buggy Thumb-2 short branch relocations in gas"
1711 depends on THUMB2_KERNEL && MODULES
1714 Various binutils versions can resolve Thumb-2 branches to
1715 locally-defined, preemptible global symbols as short-range "b.n"
1716 branch instructions.
1718 This is a problem, because there's no guarantee the final
1719 destination of the symbol, or any candidate locations for a
1720 trampoline, are within range of the branch. For this reason, the
1721 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1722 relocation in modules at all, and it makes little sense to add
1725 The symptom is that the kernel fails with an "unsupported
1726 relocation" error when loading some modules.
1728 Until fixed tools are available, passing
1729 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1730 code which hits this problem, at the cost of a bit of extra runtime
1731 stack usage in some cases.
1733 The problem is described in more detail at:
1734 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1736 Only Thumb-2 kernels are affected.
1738 Unless you are sure your tools don't have this problem, say Y.
1740 config ARM_ASM_UNIFIED
1744 bool "Use the ARM EABI to compile the kernel"
1746 This option allows for the kernel to be compiled using the latest
1747 ARM ABI (aka EABI). This is only useful if you are using a user
1748 space environment that is also compiled with EABI.
1750 Since there are major incompatibilities between the legacy ABI and
1751 EABI, especially with regard to structure member alignment, this
1752 option also changes the kernel syscall calling convention to
1753 disambiguate both ABIs and allow for backward compatibility support
1754 (selected with CONFIG_OABI_COMPAT).
1756 To use this you need GCC version 4.0.0 or later.
1759 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1760 depends on AEABI && !THUMB2_KERNEL
1763 This option preserves the old syscall interface along with the
1764 new (ARM EABI) one. It also provides a compatibility layer to
1765 intercept syscalls that have structure arguments which layout
1766 in memory differs between the legacy ABI and the new ARM EABI
1767 (only for non "thumb" binaries). This option adds a tiny
1768 overhead to all syscalls and produces a slightly larger kernel.
1769 If you know you'll be using only pure EABI user space then you
1770 can say N here. If this option is not selected and you attempt
1771 to execute a legacy ABI binary then the result will be
1772 UNPREDICTABLE (in fact it can be predicted that it won't work
1773 at all). If in doubt say Y.
1775 config ARCH_HAS_HOLES_MEMORYMODEL
1778 config ARCH_SPARSEMEM_ENABLE
1781 config ARCH_SPARSEMEM_DEFAULT
1782 def_bool ARCH_SPARSEMEM_ENABLE
1784 config ARCH_SELECT_MEMORY_MODEL
1785 def_bool ARCH_SPARSEMEM_ENABLE
1787 config HAVE_ARCH_PFN_VALID
1788 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1791 bool "High Memory Support"
1794 The address space of ARM processors is only 4 Gigabytes large
1795 and it has to accommodate user address space, kernel address
1796 space as well as some memory mapped IO. That means that, if you
1797 have a large amount of physical memory and/or IO, not all of the
1798 memory can be "permanently mapped" by the kernel. The physical
1799 memory that is not permanently mapped is called "high memory".
1801 Depending on the selected kernel/user memory split, minimum
1802 vmalloc space and actual amount of RAM, you may not need this
1803 option which should result in a slightly faster kernel.
1808 bool "Allocate 2nd-level pagetables from highmem"
1811 config HW_PERF_EVENTS
1812 bool "Enable hardware performance counter support for perf events"
1813 depends on PERF_EVENTS
1816 Enable hardware performance counter support for perf events. If
1817 disabled, perf events will use software events only.
1819 config SYS_SUPPORTS_HUGETLBFS
1823 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1827 config ARCH_WANT_GENERAL_HUGETLB
1832 config FORCE_MAX_ZONEORDER
1833 int "Maximum zone order" if ARCH_SHMOBILE
1834 range 11 64 if ARCH_SHMOBILE
1835 default "12" if SOC_AM33XX
1836 default "9" if SA1111
1839 The kernel memory allocator divides physically contiguous memory
1840 blocks into "zones", where each zone is a power of two number of
1841 pages. This option selects the largest power of two that the kernel
1842 keeps in the memory allocator. If you need to allocate very large
1843 blocks of physically contiguous memory, then you may need to
1844 increase this value.
1846 This config option is actually maximum order plus one. For example,
1847 a value of 11 means that the largest free memory block is 2^10 pages.
1849 config ALIGNMENT_TRAP
1851 depends on CPU_CP15_MMU
1852 default y if !ARCH_EBSA110
1853 select HAVE_PROC_CPU if PROC_FS
1855 ARM processors cannot fetch/store information which is not
1856 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1857 address divisible by 4. On 32-bit ARM processors, these non-aligned
1858 fetch/store instructions will be emulated in software if you say
1859 here, which has a severe performance impact. This is necessary for
1860 correct operation of some network protocols. With an IP-only
1861 configuration it is safe to say N, otherwise say Y.
1863 config UACCESS_WITH_MEMCPY
1864 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1866 default y if CPU_FEROCEON
1868 Implement faster copy_to_user and clear_user methods for CPU
1869 cores where a 8-word STM instruction give significantly higher
1870 memory write throughput than a sequence of individual 32bit stores.
1872 A possible side effect is a slight increase in scheduling latency
1873 between threads sharing the same address space if they invoke
1874 such copy operations with large buffers.
1876 However, if the CPU data cache is using a write-allocate mode,
1877 this option is unlikely to provide any performance gain.
1881 prompt "Enable seccomp to safely compute untrusted bytecode"
1883 This kernel feature is useful for number crunching applications
1884 that may need to compute untrusted bytecode during their
1885 execution. By using pipes or other transports made available to
1886 the process as file descriptors supporting the read/write
1887 syscalls, it's possible to isolate those applications in
1888 their own address space using seccomp. Once seccomp is
1889 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1890 and the task is only allowed to execute a few safe syscalls
1891 defined by each seccomp mode.
1893 config CC_STACKPROTECTOR
1894 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1896 This option turns on the -fstack-protector GCC feature. This
1897 feature puts, at the beginning of functions, a canary value on
1898 the stack just before the return address, and validates
1899 the value just before actually returning. Stack based buffer
1900 overflows (that need to overwrite this return address) now also
1901 overwrite the canary, which gets detected and the attack is then
1902 neutralized via a kernel panic.
1903 This feature requires gcc version 4.2 or above.
1910 bool "Xen guest support on ARM (EXPERIMENTAL)"
1911 depends on ARM && AEABI && OF
1912 depends on CPU_V7 && !CPU_V6
1913 depends on !GENERIC_ATOMIC64
1916 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1923 bool "Flattened Device Tree support"
1926 select OF_EARLY_FLATTREE
1928 Include support for flattened device tree machine descriptions.
1931 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1934 This is the traditional way of passing data to the kernel at boot
1935 time. If you are solely relying on the flattened device tree (or
1936 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1937 to remove ATAGS support from your kernel binary. If unsure,
1940 config DEPRECATED_PARAM_STRUCT
1941 bool "Provide old way to pass kernel parameters"
1944 This was deprecated in 2001 and announced to live on for 5 years.
1945 Some old boot loaders still use this way.
1947 # Compressed boot loader in ROM. Yes, we really want to ask about
1948 # TEXT and BSS so we preserve their values in the config files.
1949 config ZBOOT_ROM_TEXT
1950 hex "Compressed ROM boot loader base address"
1953 The physical address at which the ROM-able zImage is to be
1954 placed in the target. Platforms which normally make use of
1955 ROM-able zImage formats normally set this to a suitable
1956 value in their defconfig file.
1958 If ZBOOT_ROM is not enabled, this has no effect.
1960 config ZBOOT_ROM_BSS
1961 hex "Compressed ROM boot loader BSS address"
1964 The base address of an area of read/write memory in the target
1965 for the ROM-able zImage which must be available while the
1966 decompressor is running. It must be large enough to hold the
1967 entire decompressed kernel plus an additional 128 KiB.
1968 Platforms which normally make use of ROM-able zImage formats
1969 normally set this to a suitable value in their defconfig file.
1971 If ZBOOT_ROM is not enabled, this has no effect.
1974 bool "Compressed boot loader in ROM/flash"
1975 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1977 Say Y here if you intend to execute your compressed kernel image
1978 (zImage) directly from ROM or flash. If unsure, say N.
1981 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1982 depends on ZBOOT_ROM && ARCH_SH7372
1983 default ZBOOT_ROM_NONE
1985 Include experimental SD/MMC loading code in the ROM-able zImage.
1986 With this enabled it is possible to write the ROM-able zImage
1987 kernel image to an MMC or SD card and boot the kernel straight
1988 from the reset vector. At reset the processor Mask ROM will load
1989 the first part of the ROM-able zImage which in turn loads the
1990 rest the kernel image to RAM.
1992 config ZBOOT_ROM_NONE
1993 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1995 Do not load image from SD or MMC
1997 config ZBOOT_ROM_MMCIF
1998 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2000 Load image from MMCIF hardware block.
2002 config ZBOOT_ROM_SH_MOBILE_SDHI
2003 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2005 Load image from SDHI hardware block
2009 config ARM_APPENDED_DTB
2010 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2011 depends on OF && !ZBOOT_ROM
2013 With this option, the boot code will look for a device tree binary
2014 (DTB) appended to zImage
2015 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2017 This is meant as a backward compatibility convenience for those
2018 systems with a bootloader that can't be upgraded to accommodate
2019 the documented boot protocol using a device tree.
2021 Beware that there is very little in terms of protection against
2022 this option being confused by leftover garbage in memory that might
2023 look like a DTB header after a reboot if no actual DTB is appended
2024 to zImage. Do not leave this option active in a production kernel
2025 if you don't intend to always append a DTB. Proper passing of the
2026 location into r2 of a bootloader provided DTB is always preferable
2029 config ARM_ATAG_DTB_COMPAT
2030 bool "Supplement the appended DTB with traditional ATAG information"
2031 depends on ARM_APPENDED_DTB
2033 Some old bootloaders can't be updated to a DTB capable one, yet
2034 they provide ATAGs with memory configuration, the ramdisk address,
2035 the kernel cmdline string, etc. Such information is dynamically
2036 provided by the bootloader and can't always be stored in a static
2037 DTB. To allow a device tree enabled kernel to be used with such
2038 bootloaders, this option allows zImage to extract the information
2039 from the ATAG list and store it at run time into the appended DTB.
2042 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2043 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2045 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2046 bool "Use bootloader kernel arguments if available"
2048 Uses the command-line options passed by the boot loader instead of
2049 the device tree bootargs property. If the boot loader doesn't provide
2050 any, the device tree bootargs property will be used.
2052 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2053 bool "Extend with bootloader kernel arguments"
2055 The command-line arguments provided by the boot loader will be
2056 appended to the the device tree bootargs property.
2061 string "Default kernel command string"
2064 On some architectures (EBSA110 and CATS), there is currently no way
2065 for the boot loader to pass arguments to the kernel. For these
2066 architectures, you should supply some command-line options at build
2067 time by entering them here. As a minimum, you should specify the
2068 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2071 prompt "Kernel command line type" if CMDLINE != ""
2072 default CMDLINE_FROM_BOOTLOADER
2075 config CMDLINE_FROM_BOOTLOADER
2076 bool "Use bootloader kernel arguments if available"
2078 Uses the command-line options passed by the boot loader. If
2079 the boot loader doesn't provide any, the default kernel command
2080 string provided in CMDLINE will be used.
2082 config CMDLINE_EXTEND
2083 bool "Extend bootloader kernel arguments"
2085 The command-line arguments provided by the boot loader will be
2086 appended to the default kernel command string.
2088 config CMDLINE_FORCE
2089 bool "Always use the default kernel command string"
2091 Always use the default kernel command string, even if the boot
2092 loader passes other arguments to the kernel.
2093 This is useful if you cannot or don't want to change the
2094 command-line options your boot loader passes to the kernel.
2098 bool "Kernel Execute-In-Place from ROM"
2099 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2101 Execute-In-Place allows the kernel to run from non-volatile storage
2102 directly addressable by the CPU, such as NOR flash. This saves RAM
2103 space since the text section of the kernel is not loaded from flash
2104 to RAM. Read-write sections, such as the data section and stack,
2105 are still copied to RAM. The XIP kernel is not compressed since
2106 it has to run directly from flash, so it will take more space to
2107 store it. The flash address used to link the kernel object files,
2108 and for storing it, is configuration dependent. Therefore, if you
2109 say Y here, you must know the proper physical address where to
2110 store the kernel image depending on your own flash memory usage.
2112 Also note that the make target becomes "make xipImage" rather than
2113 "make zImage" or "make Image". The final kernel binary to put in
2114 ROM memory will be arch/arm/boot/xipImage.
2118 config XIP_PHYS_ADDR
2119 hex "XIP Kernel Physical Location"
2120 depends on XIP_KERNEL
2121 default "0x00080000"
2123 This is the physical address in your flash memory the kernel will
2124 be linked for and stored to. This address is dependent on your
2128 bool "Kexec system call (EXPERIMENTAL)"
2129 depends on (!SMP || PM_SLEEP_SMP)
2131 kexec is a system call that implements the ability to shutdown your
2132 current kernel, and to start another kernel. It is like a reboot
2133 but it is independent of the system firmware. And like a reboot
2134 you can start any kernel with it, not just Linux.
2136 It is an ongoing process to be certain the hardware in a machine
2137 is properly shutdown, so do not be surprised if this code does not
2138 initially work for you.
2141 bool "Export atags in procfs"
2142 depends on ATAGS && KEXEC
2145 Should the atags used to boot the kernel be exported in an "atags"
2146 file in procfs. Useful with kexec.
2149 bool "Build kdump crash kernel (EXPERIMENTAL)"
2151 Generate crash dump after being started by kexec. This should
2152 be normally only set in special crash dump kernels which are
2153 loaded in the main kernel with kexec-tools into a specially
2154 reserved region and then later executed after a crash by
2155 kdump/kexec. The crash dump kernel must be compiled to a
2156 memory address not used by the main kernel
2158 For more details see Documentation/kdump/kdump.txt
2160 config AUTO_ZRELADDR
2161 bool "Auto calculation of the decompressed kernel image address"
2162 depends on !ZBOOT_ROM
2164 ZRELADDR is the physical address where the decompressed kernel
2165 image will be placed. If AUTO_ZRELADDR is selected, the address
2166 will be determined at run-time by masking the current IP with
2167 0xf8000000. This assumes the zImage being placed in the first 128MB
2168 from start of memory.
2172 menu "CPU Power Management"
2175 source "drivers/cpufreq/Kconfig"
2178 source "drivers/cpuidle/Kconfig"
2182 menu "Floating point emulation"
2184 comment "At least one emulation must be selected"
2187 bool "NWFPE math emulation"
2188 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2190 Say Y to include the NWFPE floating point emulator in the kernel.
2191 This is necessary to run most binaries. Linux does not currently
2192 support floating point hardware so you need to say Y here even if
2193 your machine has an FPA or floating point co-processor podule.
2195 You may say N here if you are going to load the Acorn FPEmulator
2196 early in the bootup.
2199 bool "Support extended precision"
2200 depends on FPE_NWFPE
2202 Say Y to include 80-bit support in the kernel floating-point
2203 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2204 Note that gcc does not generate 80-bit operations by default,
2205 so in most cases this option only enlarges the size of the
2206 floating point emulator without any good reason.
2208 You almost surely want to say N here.
2211 bool "FastFPE math emulation (EXPERIMENTAL)"
2212 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2214 Say Y here to include the FAST floating point emulator in the kernel.
2215 This is an experimental much faster emulator which now also has full
2216 precision for the mantissa. It does not support any exceptions.
2217 It is very simple, and approximately 3-6 times faster than NWFPE.
2219 It should be sufficient for most programs. It may be not suitable
2220 for scientific calculations, but you have to check this for yourself.
2221 If you do not feel you need a faster FP emulation you should better
2225 bool "VFP-format floating point maths"
2226 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2228 Say Y to include VFP support code in the kernel. This is needed
2229 if your hardware includes a VFP unit.
2231 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2232 release notes and additional status information.
2234 Say N if your target does not have VFP hardware.
2242 bool "Advanced SIMD (NEON) Extension support"
2243 depends on VFPv3 && CPU_V7
2245 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2248 config KERNEL_MODE_NEON
2249 bool "Support for NEON in kernel mode"
2250 depends on NEON && AEABI
2252 Say Y to include support for NEON in kernel mode.
2256 menu "Userspace binary formats"
2258 source "fs/Kconfig.binfmt"
2261 tristate "RISC OS personality"
2264 Say Y here to include the kernel code necessary if you want to run
2265 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2266 experimental; if this sounds frightening, say N and sleep in peace.
2267 You can also say M here to compile this support as a module (which
2268 will be called arthur).
2272 menu "Power management options"
2274 source "kernel/power/Kconfig"
2276 config ARCH_SUSPEND_POSSIBLE
2277 depends on !ARCH_S5PC100
2278 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2279 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2282 config ARM_CPU_SUSPEND
2287 source "net/Kconfig"
2289 source "drivers/Kconfig"
2293 source "arch/arm/Kconfig.debug"
2295 source "security/Kconfig"
2297 source "crypto/Kconfig"
2299 source "lib/Kconfig"
2301 source "arch/arm/kvm/Kconfig"