4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CLONE_BACKWARDS
11 select CPU_PM if (SUSPEND || CPU_IDLE)
12 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
13 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
14 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
15 select GENERIC_IDLE_POLL_SETUP
16 select GENERIC_IRQ_PROBE
17 select GENERIC_IRQ_SHOW
18 select GENERIC_PCI_IOMAP
19 select GENERIC_SCHED_CLOCK
20 select GENERIC_SMP_IDLE_THREAD
21 select GENERIC_STRNCPY_FROM_USER
22 select GENERIC_STRNLEN_USER
23 select HARDIRQS_SW_RESEND
24 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
26 select HAVE_ARCH_SECCOMP_FILTER
27 select HAVE_ARCH_TRACEHOOK
29 select HAVE_CONTEXT_TRACKING
30 select HAVE_C_RECORDMCOUNT
31 select HAVE_DEBUG_KMEMLEAK
32 select HAVE_DMA_API_DEBUG
34 select HAVE_DMA_CONTIGUOUS if MMU
35 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
36 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
37 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
38 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
39 select HAVE_GENERIC_DMA_COHERENT
40 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
41 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_IRQ_TIME_ACCOUNTING
43 select HAVE_KERNEL_GZIP
44 select HAVE_KERNEL_LZ4
45 select HAVE_KERNEL_LZMA
46 select HAVE_KERNEL_LZO
48 select HAVE_KPROBES if !XIP_KERNEL
49 select HAVE_KRETPROBES if (HAVE_KPROBES)
51 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
52 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
53 select HAVE_PERF_EVENTS
54 select HAVE_REGS_AND_STACK_ACCESS_API
55 select HAVE_SYSCALL_TRACEPOINTS
57 select IRQ_FORCED_THREADING
59 select MODULES_USE_ELF_REL
61 select OLD_SIGSUSPEND3
62 select PERF_USE_VMALLOC
64 select SYS_SUPPORTS_APM_EMULATION
65 # Above selects are sorted alphabetically; please add new ones
66 # according to that. Thanks.
68 The ARM series is a line of low-power-consumption RISC chip designs
69 licensed by ARM Ltd and targeted at embedded applications and
70 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
71 manufactured, but legacy ARM-based PC hardware remains popular in
72 Europe. There is an ARM Linux project with a web page at
73 <http://www.arm.linux.org.uk/>.
75 config ARM_HAS_SG_CHAIN
78 config NEED_SG_DMA_LENGTH
81 config ARM_DMA_USE_IOMMU
83 select ARM_HAS_SG_CHAIN
84 select NEED_SG_DMA_LENGTH
88 config ARM_DMA_IOMMU_ALIGNMENT
89 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
93 DMA mapping framework by default aligns all buffers to the smallest
94 PAGE_SIZE order which is greater than or equal to the requested buffer
95 size. This works well for buffers up to a few hundreds kilobytes, but
96 for larger buffers it just a waste of address space. Drivers which has
97 relatively small addressing window (like 64Mib) might run out of
98 virtual space with just a few allocations.
100 With this parameter you can specify the maximum PAGE_SIZE order for
101 DMA IOMMU buffers. Larger buffers will be aligned only to this
102 specified order. The order is expressed as a power of two multiplied
110 config MIGHT_HAVE_PCI
113 config SYS_SUPPORTS_APM_EMULATION
118 select GENERIC_ALLOCATOR
129 The Extended Industry Standard Architecture (EISA) bus was
130 developed as an open alternative to the IBM MicroChannel bus.
132 The EISA bus provided some of the features of the IBM MicroChannel
133 bus while maintaining backward compatibility with cards made for
134 the older ISA bus. The EISA bus saw limited use between 1988 and
135 1995 when it was made obsolete by the PCI bus.
137 Say Y here if you are building a kernel for an EISA-based machine.
144 config STACKTRACE_SUPPORT
148 config HAVE_LATENCYTOP_SUPPORT
153 config LOCKDEP_SUPPORT
157 config TRACE_IRQFLAGS_SUPPORT
161 config RWSEM_GENERIC_SPINLOCK
165 config RWSEM_XCHGADD_ALGORITHM
168 config ARCH_HAS_ILOG2_U32
171 config ARCH_HAS_ILOG2_U64
174 config ARCH_HAS_CPUFREQ
177 Internal node to signify that the ARCH has CPUFREQ support
178 and that the relevant menu configurations are displayed for
181 config ARCH_HAS_BANDGAP
184 config GENERIC_HWEIGHT
188 config GENERIC_CALIBRATE_DELAY
192 config ARCH_MAY_HAVE_PC_FDC
198 config NEED_DMA_MAP_STATE
201 config ARCH_HAS_DMA_SET_COHERENT_MASK
204 config GENERIC_ISA_DMA
210 config NEED_RET_TO_USER
218 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
219 default DRAM_BASE if REMAP_VECTORS_TO_RAM
222 The base address of exception vectors. This must be two pages
225 config ARM_PATCH_PHYS_VIRT
226 bool "Patch physical to virtual translations at runtime" if EMBEDDED
228 depends on !XIP_KERNEL && MMU
229 depends on !ARCH_REALVIEW || !SPARSEMEM
231 Patch phys-to-virt and virt-to-phys translation functions at
232 boot and module load time according to the position of the
233 kernel in system memory.
235 This can only be used with non-XIP MMU kernels where the base
236 of physical memory is at a 16MB boundary.
238 Only disable this option if you know that you do not require
239 this feature (eg, building a kernel for a single machine) and
240 you need to shrink the kernel to the minimal size.
242 config NEED_MACH_GPIO_H
245 Select this when mach/gpio.h is required to provide special
246 definitions for this platform. The need for mach/gpio.h should
247 be avoided when possible.
249 config NEED_MACH_IO_H
252 Select this when mach/io.h is required to provide special
253 definitions for this platform. The need for mach/io.h should
254 be avoided when possible.
256 config NEED_MACH_MEMORY_H
259 Select this when mach/memory.h is required to provide special
260 definitions for this platform. The need for mach/memory.h should
261 be avoided when possible.
264 hex "Physical address of main memory" if MMU
265 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
266 default DRAM_BASE if !MMU
268 Please provide the physical address corresponding to the
269 location of main memory in your system.
275 source "init/Kconfig"
277 source "kernel/Kconfig.freezer"
282 bool "MMU-based Paged Memory Management Support"
285 Select if you want MMU-based virtualised addressing space
286 support by paged memory management. If unsure, say 'Y'.
289 # The "ARM system type" choice list is ordered alphabetically by option
290 # text. Please add new entries in the option alphabetic order.
293 prompt "ARM system type"
294 default ARCH_VERSATILE if !MMU
295 default ARCH_MULTIPLATFORM if MMU
297 config ARCH_MULTIPLATFORM
298 bool "Allow multiple platforms to be selected"
300 select ARM_PATCH_PHYS_VIRT
303 select MULTI_IRQ_HANDLER
307 config ARCH_INTEGRATOR
308 bool "ARM Ltd. Integrator family"
309 select ARCH_HAS_CPUFREQ
312 select COMMON_CLK_VERSATILE
313 select GENERIC_CLOCKEVENTS
316 select MULTI_IRQ_HANDLER
317 select NEED_MACH_MEMORY_H
318 select PLAT_VERSATILE
320 select VERSATILE_FPGA_IRQ
322 Support for ARM's Integrator platform.
325 bool "ARM Ltd. RealView family"
326 select ARCH_WANT_OPTIONAL_GPIOLIB
328 select ARM_TIMER_SP804
330 select COMMON_CLK_VERSATILE
331 select GENERIC_CLOCKEVENTS
332 select GPIO_PL061 if GPIOLIB
334 select NEED_MACH_MEMORY_H
335 select PLAT_VERSATILE
336 select PLAT_VERSATILE_CLCD
338 This enables support for ARM Ltd RealView boards.
340 config ARCH_VERSATILE
341 bool "ARM Ltd. Versatile family"
342 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_TIMER_SP804
347 select GENERIC_CLOCKEVENTS
348 select HAVE_MACH_CLKDEV
350 select PLAT_VERSATILE
351 select PLAT_VERSATILE_CLCD
352 select PLAT_VERSATILE_CLOCK
353 select VERSATILE_FPGA_IRQ
355 This enables support for ARM Ltd Versatile board.
359 select ARCH_REQUIRE_GPIOLIB
363 select NEED_MACH_GPIO_H
364 select NEED_MACH_IO_H if PCCARD
366 select PINCTRL_AT91 if USE_OF
368 This enables support for systems based on Atmel
369 AT91RM9200 and AT91SAM9* processors.
372 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
373 select ARCH_REQUIRE_GPIOLIB
379 select GENERIC_CLOCKEVENTS
381 select MULTI_IRQ_HANDLER
384 Support for Cirrus Logic 711x/721x/731x based boards.
387 bool "Cortina Systems Gemini"
388 select ARCH_REQUIRE_GPIOLIB
389 select ARCH_USES_GETTIMEOFFSET
391 select NEED_MACH_GPIO_H
393 Support for the Cortina Systems Gemini family SoCs
397 select ARCH_USES_GETTIMEOFFSET
400 select NEED_MACH_IO_H
401 select NEED_MACH_MEMORY_H
404 This is an evaluation board for the StrongARM processor available
405 from Digital. It has limited hardware on-board, including an
406 Ethernet interface, two PCMCIA sockets, two serial ports and a
411 select ARCH_HAS_HOLES_MEMORYMODEL
412 select ARCH_REQUIRE_GPIOLIB
413 select ARCH_USES_GETTIMEOFFSET
418 select NEED_MACH_MEMORY_H
420 This enables support for the Cirrus EP93xx series of CPUs.
422 config ARCH_FOOTBRIDGE
426 select GENERIC_CLOCKEVENTS
428 select NEED_MACH_IO_H if !MMU
429 select NEED_MACH_MEMORY_H
431 Support for systems based on the DC21285 companion chip
432 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
435 bool "Hilscher NetX based"
439 select GENERIC_CLOCKEVENTS
441 This enables support for systems based on the Hilscher NetX Soc
447 select NEED_MACH_MEMORY_H
448 select NEED_RET_TO_USER
453 Support for Intel's IOP13XX (XScale) family of processors.
458 select ARCH_REQUIRE_GPIOLIB
460 select NEED_MACH_GPIO_H
461 select NEED_RET_TO_USER
465 Support for Intel's 80219 and IOP32X (XScale) family of
471 select ARCH_REQUIRE_GPIOLIB
473 select NEED_MACH_GPIO_H
474 select NEED_RET_TO_USER
478 Support for Intel's IOP33X (XScale) family of processors.
483 select ARCH_HAS_DMA_SET_COHERENT_MASK
484 select ARCH_REQUIRE_GPIOLIB
487 select DMABOUNCE if PCI
488 select GENERIC_CLOCKEVENTS
489 select MIGHT_HAVE_PCI
490 select NEED_MACH_IO_H
491 select USB_EHCI_BIG_ENDIAN_DESC
492 select USB_EHCI_BIG_ENDIAN_MMIO
494 Support for Intel's IXP4XX (XScale) family of processors.
498 select ARCH_REQUIRE_GPIOLIB
500 select GENERIC_CLOCKEVENTS
501 select MIGHT_HAVE_PCI
505 select PLAT_ORION_LEGACY
506 select USB_ARCH_HAS_EHCI
508 Support for the Marvell Dove SoC 88AP510
511 bool "Marvell Kirkwood"
512 select ARCH_HAS_CPUFREQ
513 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
520 select PINCTRL_KIRKWOOD
521 select PLAT_ORION_LEGACY
523 Support for the following Marvell Kirkwood series SoCs:
524 88F6180, 88F6192 and 88F6281.
527 bool "Marvell MV78xx0"
528 select ARCH_REQUIRE_GPIOLIB
530 select GENERIC_CLOCKEVENTS
533 select PLAT_ORION_LEGACY
535 Support for the following Marvell MV78xx0 series SoCs:
541 select ARCH_REQUIRE_GPIOLIB
543 select GENERIC_CLOCKEVENTS
546 select PLAT_ORION_LEGACY
548 Support for the following Marvell Orion 5x series SoCs:
549 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
550 Orion-2 (5281), Orion-1-90 (6183).
553 bool "Marvell PXA168/910/MMP2"
555 select ARCH_REQUIRE_GPIOLIB
557 select GENERIC_ALLOCATOR
558 select GENERIC_CLOCKEVENTS
561 select MULTI_IRQ_HANDLER
562 select NEED_MACH_GPIO_H
567 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
570 bool "Micrel/Kendin KS8695"
571 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
575 select NEED_MACH_MEMORY_H
577 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
578 System-on-Chip devices.
581 bool "Nuvoton W90X900 CPU"
582 select ARCH_REQUIRE_GPIOLIB
586 select GENERIC_CLOCKEVENTS
588 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
589 At present, the w90x900 has been renamed nuc900, regarding
590 the ARM series product line, you can login the following
591 link address to know more.
593 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
594 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
598 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
606 select USB_ARCH_HAS_OHCI
609 Support for the NXP LPC32XX family of processors
612 bool "PXA2xx/PXA3xx-based"
614 select ARCH_HAS_CPUFREQ
616 select ARCH_REQUIRE_GPIOLIB
617 select ARM_CPU_SUSPEND if PM
621 select GENERIC_CLOCKEVENTS
624 select MULTI_IRQ_HANDLER
625 select NEED_MACH_GPIO_H
629 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
633 select ARCH_REQUIRE_GPIOLIB
635 select CLKSRC_OF if OF
637 select GENERIC_CLOCKEVENTS
639 Support for Qualcomm MSM/QSD based systems. This runs on the
640 apps processor of the MSM/QSD and depends on a shared memory
641 interface to the modem processor which runs the baseband
642 stack and controls some vital subsystems
643 (clock and power control, etc).
646 bool "Renesas SH-Mobile / R-Mobile"
647 select ARM_PATCH_PHYS_VIRT
649 select GENERIC_CLOCKEVENTS
650 select HAVE_ARM_SCU if SMP
651 select HAVE_ARM_TWD if SMP
653 select HAVE_MACH_CLKDEV
655 select MIGHT_HAVE_CACHE_L2X0
656 select MULTI_IRQ_HANDLER
659 select PM_GENERIC_DOMAINS if PM
662 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
667 select ARCH_MAY_HAVE_PC_FDC
668 select ARCH_SPARSEMEM_ENABLE
669 select ARCH_USES_GETTIMEOFFSET
672 select HAVE_PATA_PLATFORM
674 select NEED_MACH_IO_H
675 select NEED_MACH_MEMORY_H
679 On the Acorn Risc-PC, Linux can support the internal IDE disk and
680 CD-ROM interface, serial and parallel port, and the floppy drive.
684 select ARCH_HAS_CPUFREQ
686 select ARCH_REQUIRE_GPIOLIB
687 select ARCH_SPARSEMEM_ENABLE
692 select GENERIC_CLOCKEVENTS
695 select NEED_MACH_GPIO_H
696 select NEED_MACH_MEMORY_H
699 Support for StrongARM 11x0 based boards.
702 bool "Samsung S3C24XX SoCs"
703 select ARCH_HAS_CPUFREQ
704 select ARCH_REQUIRE_GPIOLIB
706 select CLKSRC_SAMSUNG_PWM
707 select GENERIC_CLOCKEVENTS
710 select HAVE_S3C2410_I2C if I2C
711 select HAVE_S3C2410_WATCHDOG if WATCHDOG
712 select HAVE_S3C_RTC if RTC_CLASS
713 select MULTI_IRQ_HANDLER
714 select NEED_MACH_GPIO_H
715 select NEED_MACH_IO_H
718 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
719 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
720 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
721 Samsung SMDK2410 development board (and derivatives).
724 bool "Samsung S3C64XX"
725 select ARCH_HAS_CPUFREQ
726 select ARCH_REQUIRE_GPIOLIB
729 select CLKSRC_SAMSUNG_PWM
731 select GENERIC_CLOCKEVENTS
734 select HAVE_S3C2410_I2C if I2C
735 select HAVE_S3C2410_WATCHDOG if WATCHDOG
737 select NEED_MACH_GPIO_H
741 select S3C_GPIO_TRACK
743 select SAMSUNG_CLKSRC
744 select SAMSUNG_GPIOLIB_4BIT
745 select SAMSUNG_WDT_RESET
746 select USB_ARCH_HAS_OHCI
748 Samsung S3C64XX series based systems
751 bool "Samsung S5P6440 S5P6450"
753 select CLKSRC_SAMSUNG_PWM
755 select GENERIC_CLOCKEVENTS
758 select HAVE_S3C2410_I2C if I2C
759 select HAVE_S3C2410_WATCHDOG if WATCHDOG
760 select HAVE_S3C_RTC if RTC_CLASS
761 select NEED_MACH_GPIO_H
763 select SAMSUNG_WDT_RESET
765 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
769 bool "Samsung S5PC100"
770 select ARCH_REQUIRE_GPIOLIB
772 select CLKSRC_SAMSUNG_PWM
774 select GENERIC_CLOCKEVENTS
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
779 select HAVE_S3C_RTC if RTC_CLASS
780 select NEED_MACH_GPIO_H
782 select SAMSUNG_WDT_RESET
784 Samsung S5PC100 series based systems
787 bool "Samsung S5PV210/S5PC110"
788 select ARCH_HAS_CPUFREQ
789 select ARCH_HAS_HOLES_MEMORYMODEL
790 select ARCH_SPARSEMEM_ENABLE
792 select CLKSRC_SAMSUNG_PWM
794 select GENERIC_CLOCKEVENTS
797 select HAVE_S3C2410_I2C if I2C
798 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 select HAVE_S3C_RTC if RTC_CLASS
800 select NEED_MACH_GPIO_H
801 select NEED_MACH_MEMORY_H
804 Samsung S5PV210/S5PC110 series based systems
807 bool "Samsung EXYNOS"
808 select ARCH_HAS_CPUFREQ
809 select ARCH_HAS_HOLES_MEMORYMODEL
810 select ARCH_REQUIRE_GPIOLIB
811 select ARCH_SPARSEMEM_ENABLE
816 select GENERIC_CLOCKEVENTS
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 select HAVE_S3C_RTC if RTC_CLASS
821 select NEED_MACH_MEMORY_H
825 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
829 select ARCH_USES_GETTIMEOFFSET
833 select NEED_MACH_MEMORY_H
838 Support for the StrongARM based Digital DNARD machine, also known
839 as "Shark" (<http://www.shark-linux.de/shark.html>).
843 select ARCH_HAS_HOLES_MEMORYMODEL
844 select ARCH_REQUIRE_GPIOLIB
846 select GENERIC_ALLOCATOR
847 select GENERIC_CLOCKEVENTS
848 select GENERIC_IRQ_CHIP
850 select NEED_MACH_GPIO_H
855 Support for TI's DaVinci platform.
860 select ARCH_HAS_CPUFREQ
861 select ARCH_HAS_HOLES_MEMORYMODEL
863 select ARCH_REQUIRE_GPIOLIB
866 select GENERIC_CLOCKEVENTS
867 select GENERIC_IRQ_CHIP
871 select NEED_MACH_IO_H if PCCARD
872 select NEED_MACH_MEMORY_H
874 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
878 menu "Multiple platform selection"
879 depends on ARCH_MULTIPLATFORM
881 comment "CPU Core family selection"
883 config ARCH_MULTI_V4T
884 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
885 depends on !ARCH_MULTI_V6_V7
886 select ARCH_MULTI_V4_V5
887 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
888 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
889 CPU_ARM925T || CPU_ARM940T)
892 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
893 depends on !ARCH_MULTI_V6_V7
894 select ARCH_MULTI_V4_V5
895 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
896 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
897 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
899 config ARCH_MULTI_V4_V5
903 bool "ARMv6 based platforms (ARM11)"
904 select ARCH_MULTI_V6_V7
908 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
910 select ARCH_MULTI_V6_V7
913 config ARCH_MULTI_V6_V7
916 config ARCH_MULTI_CPU_AUTO
917 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
923 # This is sorted alphabetically by mach-* pathname. However, plat-*
924 # Kconfigs may be included either alphabetically (according to the
925 # plat- suffix) or along side the corresponding mach-* source.
927 source "arch/arm/mach-mvebu/Kconfig"
929 source "arch/arm/mach-at91/Kconfig"
931 source "arch/arm/mach-bcm/Kconfig"
933 source "arch/arm/mach-bcm2835/Kconfig"
935 source "arch/arm/mach-clps711x/Kconfig"
937 source "arch/arm/mach-cns3xxx/Kconfig"
939 source "arch/arm/mach-davinci/Kconfig"
941 source "arch/arm/mach-dove/Kconfig"
943 source "arch/arm/mach-ep93xx/Kconfig"
945 source "arch/arm/mach-footbridge/Kconfig"
947 source "arch/arm/mach-gemini/Kconfig"
949 source "arch/arm/mach-highbank/Kconfig"
951 source "arch/arm/mach-integrator/Kconfig"
953 source "arch/arm/mach-iop32x/Kconfig"
955 source "arch/arm/mach-iop33x/Kconfig"
957 source "arch/arm/mach-iop13xx/Kconfig"
959 source "arch/arm/mach-ixp4xx/Kconfig"
961 source "arch/arm/mach-keystone/Kconfig"
963 source "arch/arm/mach-kirkwood/Kconfig"
965 source "arch/arm/mach-ks8695/Kconfig"
967 source "arch/arm/mach-msm/Kconfig"
969 source "arch/arm/mach-mv78xx0/Kconfig"
971 source "arch/arm/mach-imx/Kconfig"
973 source "arch/arm/mach-mxs/Kconfig"
975 source "arch/arm/mach-netx/Kconfig"
977 source "arch/arm/mach-nomadik/Kconfig"
979 source "arch/arm/mach-nspire/Kconfig"
981 source "arch/arm/plat-omap/Kconfig"
983 source "arch/arm/mach-omap1/Kconfig"
985 source "arch/arm/mach-omap2/Kconfig"
987 source "arch/arm/mach-orion5x/Kconfig"
989 source "arch/arm/mach-picoxcell/Kconfig"
991 source "arch/arm/mach-pxa/Kconfig"
992 source "arch/arm/plat-pxa/Kconfig"
994 source "arch/arm/mach-mmp/Kconfig"
996 source "arch/arm/mach-realview/Kconfig"
998 source "arch/arm/mach-rockchip/Kconfig"
1000 source "arch/arm/mach-sa1100/Kconfig"
1002 source "arch/arm/plat-samsung/Kconfig"
1004 source "arch/arm/mach-socfpga/Kconfig"
1006 source "arch/arm/mach-spear/Kconfig"
1008 source "arch/arm/mach-sti/Kconfig"
1010 source "arch/arm/mach-s3c24xx/Kconfig"
1013 source "arch/arm/mach-s3c64xx/Kconfig"
1016 source "arch/arm/mach-s5p64x0/Kconfig"
1018 source "arch/arm/mach-s5pc100/Kconfig"
1020 source "arch/arm/mach-s5pv210/Kconfig"
1022 source "arch/arm/mach-exynos/Kconfig"
1024 source "arch/arm/mach-shmobile/Kconfig"
1026 source "arch/arm/mach-sunxi/Kconfig"
1028 source "arch/arm/mach-prima2/Kconfig"
1030 source "arch/arm/mach-tegra/Kconfig"
1032 source "arch/arm/mach-u300/Kconfig"
1034 source "arch/arm/mach-ux500/Kconfig"
1036 source "arch/arm/mach-versatile/Kconfig"
1038 source "arch/arm/mach-vexpress/Kconfig"
1039 source "arch/arm/plat-versatile/Kconfig"
1041 source "arch/arm/mach-virt/Kconfig"
1043 source "arch/arm/mach-vt8500/Kconfig"
1045 source "arch/arm/mach-w90x900/Kconfig"
1047 source "arch/arm/mach-zynq/Kconfig"
1049 # Definitions to make life easier
1055 select GENERIC_CLOCKEVENTS
1061 select GENERIC_IRQ_CHIP
1064 config PLAT_ORION_LEGACY
1071 config PLAT_VERSATILE
1074 config ARM_TIMER_SP804
1077 select CLKSRC_OF if OF
1079 source arch/arm/mm/Kconfig
1083 default 16 if ARCH_EP93XX
1087 bool "Enable iWMMXt support" if !CPU_PJ4
1088 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1089 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1091 Enable support for iWMMXt context switching at run time if
1092 running on a CPU that supports it.
1096 depends on CPU_XSCALE
1099 config MULTI_IRQ_HANDLER
1102 Allow each machine to specify it's own IRQ handler at run time.
1105 source "arch/arm/Kconfig-nommu"
1108 config PJ4B_ERRATA_4742
1109 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1110 depends on CPU_PJ4B && MACH_ARMADA_370
1113 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1114 Event (WFE) IDLE states, a specific timing sensitivity exists between
1115 the retiring WFI/WFE instructions and the newly issued subsequent
1116 instructions. This sensitivity can result in a CPU hang scenario.
1118 The software must insert either a Data Synchronization Barrier (DSB)
1119 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1122 config ARM_ERRATA_326103
1123 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1126 Executing a SWP instruction to read-only memory does not set bit 11
1127 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1128 treat the access as a read, preventing a COW from occurring and
1129 causing the faulting task to livelock.
1131 config ARM_ERRATA_411920
1132 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1133 depends on CPU_V6 || CPU_V6K
1135 Invalidation of the Instruction Cache operation can
1136 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1137 It does not affect the MPCore. This option enables the ARM Ltd.
1138 recommended workaround.
1140 config ARM_ERRATA_430973
1141 bool "ARM errata: Stale prediction on replaced interworking branch"
1144 This option enables the workaround for the 430973 Cortex-A8
1145 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1146 interworking branch is replaced with another code sequence at the
1147 same virtual address, whether due to self-modifying code or virtual
1148 to physical address re-mapping, Cortex-A8 does not recover from the
1149 stale interworking branch prediction. This results in Cortex-A8
1150 executing the new code sequence in the incorrect ARM or Thumb state.
1151 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1152 and also flushes the branch target cache at every context switch.
1153 Note that setting specific bits in the ACTLR register may not be
1154 available in non-secure mode.
1156 config ARM_ERRATA_458693
1157 bool "ARM errata: Processor deadlock when a false hazard is created"
1159 depends on !ARCH_MULTIPLATFORM
1161 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1162 erratum. For very specific sequences of memory operations, it is
1163 possible for a hazard condition intended for a cache line to instead
1164 be incorrectly associated with a different cache line. This false
1165 hazard might then cause a processor deadlock. The workaround enables
1166 the L1 caching of the NEON accesses and disables the PLD instruction
1167 in the ACTLR register. Note that setting specific bits in the ACTLR
1168 register may not be available in non-secure mode.
1170 config ARM_ERRATA_460075
1171 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1173 depends on !ARCH_MULTIPLATFORM
1175 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1176 erratum. Any asynchronous access to the L2 cache may encounter a
1177 situation in which recent store transactions to the L2 cache are lost
1178 and overwritten with stale memory contents from external memory. The
1179 workaround disables the write-allocate mode for the L2 cache via the
1180 ACTLR register. Note that setting specific bits in the ACTLR register
1181 may not be available in non-secure mode.
1183 config ARM_ERRATA_742230
1184 bool "ARM errata: DMB operation may be faulty"
1185 depends on CPU_V7 && SMP
1186 depends on !ARCH_MULTIPLATFORM
1188 This option enables the workaround for the 742230 Cortex-A9
1189 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1190 between two write operations may not ensure the correct visibility
1191 ordering of the two writes. This workaround sets a specific bit in
1192 the diagnostic register of the Cortex-A9 which causes the DMB
1193 instruction to behave as a DSB, ensuring the correct behaviour of
1196 config ARM_ERRATA_742231
1197 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1198 depends on CPU_V7 && SMP
1199 depends on !ARCH_MULTIPLATFORM
1201 This option enables the workaround for the 742231 Cortex-A9
1202 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1203 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1204 accessing some data located in the same cache line, may get corrupted
1205 data due to bad handling of the address hazard when the line gets
1206 replaced from one of the CPUs at the same time as another CPU is
1207 accessing it. This workaround sets specific bits in the diagnostic
1208 register of the Cortex-A9 which reduces the linefill issuing
1209 capabilities of the processor.
1211 config PL310_ERRATA_588369
1212 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1213 depends on CACHE_L2X0
1215 The PL310 L2 cache controller implements three types of Clean &
1216 Invalidate maintenance operations: by Physical Address
1217 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1218 They are architecturally defined to behave as the execution of a
1219 clean operation followed immediately by an invalidate operation,
1220 both performing to the same memory location. This functionality
1221 is not correctly implemented in PL310 as clean lines are not
1222 invalidated as a result of these operations.
1224 config ARM_ERRATA_643719
1225 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1226 depends on CPU_V7 && SMP
1228 This option enables the workaround for the 643719 Cortex-A9 (prior to
1229 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1230 register returns zero when it should return one. The workaround
1231 corrects this value, ensuring cache maintenance operations which use
1232 it behave as intended and avoiding data corruption.
1234 config ARM_ERRATA_720789
1235 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1238 This option enables the workaround for the 720789 Cortex-A9 (prior to
1239 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1240 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1241 As a consequence of this erratum, some TLB entries which should be
1242 invalidated are not, resulting in an incoherency in the system page
1243 tables. The workaround changes the TLB flushing routines to invalidate
1244 entries regardless of the ASID.
1246 config PL310_ERRATA_727915
1247 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1248 depends on CACHE_L2X0
1250 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1251 operation (offset 0x7FC). This operation runs in background so that
1252 PL310 can handle normal accesses while it is in progress. Under very
1253 rare circumstances, due to this erratum, write data can be lost when
1254 PL310 treats a cacheable write transaction during a Clean &
1255 Invalidate by Way operation.
1257 config ARM_ERRATA_743622
1258 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1260 depends on !ARCH_MULTIPLATFORM
1262 This option enables the workaround for the 743622 Cortex-A9
1263 (r2p*) erratum. Under very rare conditions, a faulty
1264 optimisation in the Cortex-A9 Store Buffer may lead to data
1265 corruption. This workaround sets a specific bit in the diagnostic
1266 register of the Cortex-A9 which disables the Store Buffer
1267 optimisation, preventing the defect from occurring. This has no
1268 visible impact on the overall performance or power consumption of the
1271 config ARM_ERRATA_751472
1272 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1274 depends on !ARCH_MULTIPLATFORM
1276 This option enables the workaround for the 751472 Cortex-A9 (prior
1277 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1278 completion of a following broadcasted operation if the second
1279 operation is received by a CPU before the ICIALLUIS has completed,
1280 potentially leading to corrupted entries in the cache or TLB.
1282 config PL310_ERRATA_753970
1283 bool "PL310 errata: cache sync operation may be faulty"
1284 depends on CACHE_PL310
1286 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1288 Under some condition the effect of cache sync operation on
1289 the store buffer still remains when the operation completes.
1290 This means that the store buffer is always asked to drain and
1291 this prevents it from merging any further writes. The workaround
1292 is to replace the normal offset of cache sync operation (0x730)
1293 by another offset targeting an unmapped PL310 register 0x740.
1294 This has the same effect as the cache sync operation: store buffer
1295 drain and waiting for all buffers empty.
1297 config ARM_ERRATA_754322
1298 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1301 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1302 r3p*) erratum. A speculative memory access may cause a page table walk
1303 which starts prior to an ASID switch but completes afterwards. This
1304 can populate the micro-TLB with a stale entry which may be hit with
1305 the new ASID. This workaround places two dsb instructions in the mm
1306 switching code so that no page table walks can cross the ASID switch.
1308 config ARM_ERRATA_754327
1309 bool "ARM errata: no automatic Store Buffer drain"
1310 depends on CPU_V7 && SMP
1312 This option enables the workaround for the 754327 Cortex-A9 (prior to
1313 r2p0) erratum. The Store Buffer does not have any automatic draining
1314 mechanism and therefore a livelock may occur if an external agent
1315 continuously polls a memory location waiting to observe an update.
1316 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1317 written polling loops from denying visibility of updates to memory.
1319 config ARM_ERRATA_364296
1320 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1323 This options enables the workaround for the 364296 ARM1136
1324 r0p2 erratum (possible cache data corruption with
1325 hit-under-miss enabled). It sets the undocumented bit 31 in
1326 the auxiliary control register and the FI bit in the control
1327 register, thus disabling hit-under-miss without putting the
1328 processor into full low interrupt latency mode. ARM11MPCore
1331 config ARM_ERRATA_764369
1332 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1333 depends on CPU_V7 && SMP
1335 This option enables the workaround for erratum 764369
1336 affecting Cortex-A9 MPCore with two or more processors (all
1337 current revisions). Under certain timing circumstances, a data
1338 cache line maintenance operation by MVA targeting an Inner
1339 Shareable memory region may fail to proceed up to either the
1340 Point of Coherency or to the Point of Unification of the
1341 system. This workaround adds a DSB instruction before the
1342 relevant cache maintenance functions and sets a specific bit
1343 in the diagnostic control register of the SCU.
1345 config PL310_ERRATA_769419
1346 bool "PL310 errata: no automatic Store Buffer drain"
1347 depends on CACHE_L2X0
1349 On revisions of the PL310 prior to r3p2, the Store Buffer does
1350 not automatically drain. This can cause normal, non-cacheable
1351 writes to be retained when the memory system is idle, leading
1352 to suboptimal I/O performance for drivers using coherent DMA.
1353 This option adds a write barrier to the cpu_idle loop so that,
1354 on systems with an outer cache, the store buffer is drained
1357 config ARM_ERRATA_775420
1358 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1361 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1362 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1363 operation aborts with MMU exception, it might cause the processor
1364 to deadlock. This workaround puts DSB before executing ISB if
1365 an abort may occur on cache maintenance.
1367 config ARM_ERRATA_798181
1368 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1369 depends on CPU_V7 && SMP
1371 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1372 adequately shooting down all use of the old entries. This
1373 option enables the Linux kernel workaround for this erratum
1374 which sends an IPI to the CPUs that are running the same ASID
1375 as the one being invalidated.
1377 config ARM_ERRATA_773022
1378 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1381 This option enables the workaround for the 773022 Cortex-A15
1382 (up to r0p4) erratum. In certain rare sequences of code, the
1383 loop buffer may deliver incorrect instructions. This
1384 workaround disables the loop buffer to avoid the erratum.
1388 source "arch/arm/common/Kconfig"
1398 Find out whether you have ISA slots on your motherboard. ISA is the
1399 name of a bus system, i.e. the way the CPU talks to the other stuff
1400 inside your box. Other bus systems are PCI, EISA, MicroChannel
1401 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1402 newer boards don't support it. If you have ISA, say Y, otherwise N.
1404 # Select ISA DMA controller support
1409 # Select ISA DMA interface
1414 bool "PCI support" if MIGHT_HAVE_PCI
1416 Find out whether you have a PCI motherboard. PCI is the name of a
1417 bus system, i.e. the way the CPU talks to the other stuff inside
1418 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1419 VESA. If you have PCI, say Y, otherwise N.
1425 config PCI_NANOENGINE
1426 bool "BSE nanoEngine PCI support"
1427 depends on SA1100_NANOENGINE
1429 Enable PCI on the BSE nanoEngine board.
1434 # Select the host bridge type
1435 config PCI_HOST_VIA82C505
1437 depends on PCI && ARCH_SHARK
1440 config PCI_HOST_ITE8152
1442 depends on PCI && MACH_ARMCORE
1446 source "drivers/pci/Kconfig"
1447 source "drivers/pci/pcie/Kconfig"
1449 source "drivers/pcmcia/Kconfig"
1453 menu "Kernel Features"
1458 This option should be selected by machines which have an SMP-
1461 The only effect of this option is to make the SMP-related
1462 options available to the user for configuration.
1465 bool "Symmetric Multi-Processing"
1466 depends on CPU_V6K || CPU_V7
1467 depends on GENERIC_CLOCKEVENTS
1469 depends on MMU || ARM_MPU
1470 select USE_GENERIC_SMP_HELPERS
1472 This enables support for systems with more than one CPU. If you have
1473 a system with only one CPU, like most personal computers, say N. If
1474 you have a system with more than one CPU, say Y.
1476 If you say N here, the kernel will run on single and multiprocessor
1477 machines, but will use only one CPU of a multiprocessor machine. If
1478 you say Y here, the kernel will run on many, but not all, single
1479 processor machines. On a single processor machine, the kernel will
1480 run faster if you say N here.
1482 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1483 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1484 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1486 If you don't know what to do here, say N.
1489 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1490 depends on SMP && !XIP_KERNEL && MMU
1493 SMP kernels contain instructions which fail on non-SMP processors.
1494 Enabling this option allows the kernel to modify itself to make
1495 these instructions safe. Disabling it allows about 1K of space
1498 If you don't know what to do here, say Y.
1500 config ARM_CPU_TOPOLOGY
1501 bool "Support cpu topology definition"
1502 depends on SMP && CPU_V7
1505 Support ARM cpu topology definition. The MPIDR register defines
1506 affinity between processors which is then used to describe the cpu
1507 topology of an ARM System.
1510 bool "Multi-core scheduler support"
1511 depends on ARM_CPU_TOPOLOGY
1513 Multi-core scheduler support improves the CPU scheduler's decision
1514 making when dealing with multi-core CPU chips at a cost of slightly
1515 increased overhead in some places. If unsure say N here.
1518 bool "SMT scheduler support"
1519 depends on ARM_CPU_TOPOLOGY
1521 Improves the CPU scheduler's decision making when dealing with
1522 MultiThreading at a cost of slightly increased overhead in some
1523 places. If unsure say N here.
1528 This option enables support for the ARM system coherency unit
1530 config HAVE_ARM_ARCH_TIMER
1531 bool "Architected timer support"
1533 select ARM_ARCH_TIMER
1535 This option enables support for the ARM architected timer
1540 select CLKSRC_OF if OF
1542 This options enables support for the ARM timer and watchdog unit
1545 bool "Multi-Cluster Power Management"
1546 depends on CPU_V7 && SMP
1548 This option provides the common power management infrastructure
1549 for (multi-)cluster based systems, such as big.LITTLE based
1553 bool "big.LITTLE support (Experimental)"
1554 depends on CPU_V7 && SMP
1557 This option enables support selections for the big.LITTLE
1558 system architecture.
1561 bool "big.LITTLE switcher support"
1562 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1564 select ARM_CPU_SUSPEND
1566 The big.LITTLE "switcher" provides the core functionality to
1567 transparently handle transition between a cluster of A15's
1568 and a cluster of A7's in a big.LITTLE system.
1570 config BL_SWITCHER_DUMMY_IF
1571 tristate "Simple big.LITTLE switcher user interface"
1572 depends on BL_SWITCHER && DEBUG_KERNEL
1574 This is a simple and dummy char dev interface to control
1575 the big.LITTLE switcher core code. It is meant for
1576 debugging purposes only.
1579 prompt "Memory split"
1582 Select the desired split between kernel and user memory.
1584 If you are not absolutely sure what you are doing, leave this
1588 bool "3G/1G user/kernel split"
1590 bool "2G/2G user/kernel split"
1592 bool "1G/3G user/kernel split"
1597 default 0x40000000 if VMSPLIT_1G
1598 default 0x80000000 if VMSPLIT_2G
1602 int "Maximum number of CPUs (2-32)"
1608 bool "Support for hot-pluggable CPUs"
1611 Say Y here to experiment with turning CPUs off and on. CPUs
1612 can be controlled through /sys/devices/system/cpu.
1615 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1618 Say Y here if you want Linux to communicate with system firmware
1619 implementing the PSCI specification for CPU-centric power
1620 management operations described in ARM document number ARM DEN
1621 0022A ("Power State Coordination Interface System Software on
1624 # The GPIO number here must be sorted by descending number. In case of
1625 # a multiplatform kernel, we just want the highest value required by the
1626 # selected platforms.
1629 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1630 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1631 default 392 if ARCH_U8500
1632 default 352 if ARCH_VT8500
1633 default 288 if ARCH_SUNXI
1634 default 264 if MACH_H4700
1637 Maximum number of GPIOs in the system.
1639 If unsure, leave the default value.
1641 source kernel/Kconfig.preempt
1645 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1646 ARCH_S5PV210 || ARCH_EXYNOS4
1647 default AT91_TIMER_HZ if ARCH_AT91
1648 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1652 depends on HZ_FIXED = 0
1653 prompt "Timer frequency"
1677 default HZ_FIXED if HZ_FIXED != 0
1678 default 100 if HZ_100
1679 default 200 if HZ_200
1680 default 250 if HZ_250
1681 default 300 if HZ_300
1682 default 500 if HZ_500
1686 def_bool HIGH_RES_TIMERS
1689 def_bool HIGH_RES_TIMERS
1691 config THUMB2_KERNEL
1692 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1693 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1694 default y if CPU_THUMBONLY
1696 select ARM_ASM_UNIFIED
1699 By enabling this option, the kernel will be compiled in
1700 Thumb-2 mode. A compiler/assembler that understand the unified
1701 ARM-Thumb syntax is needed.
1705 config THUMB2_AVOID_R_ARM_THM_JUMP11
1706 bool "Work around buggy Thumb-2 short branch relocations in gas"
1707 depends on THUMB2_KERNEL && MODULES
1710 Various binutils versions can resolve Thumb-2 branches to
1711 locally-defined, preemptible global symbols as short-range "b.n"
1712 branch instructions.
1714 This is a problem, because there's no guarantee the final
1715 destination of the symbol, or any candidate locations for a
1716 trampoline, are within range of the branch. For this reason, the
1717 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1718 relocation in modules at all, and it makes little sense to add
1721 The symptom is that the kernel fails with an "unsupported
1722 relocation" error when loading some modules.
1724 Until fixed tools are available, passing
1725 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1726 code which hits this problem, at the cost of a bit of extra runtime
1727 stack usage in some cases.
1729 The problem is described in more detail at:
1730 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1732 Only Thumb-2 kernels are affected.
1734 Unless you are sure your tools don't have this problem, say Y.
1736 config ARM_ASM_UNIFIED
1740 bool "Use the ARM EABI to compile the kernel"
1742 This option allows for the kernel to be compiled using the latest
1743 ARM ABI (aka EABI). This is only useful if you are using a user
1744 space environment that is also compiled with EABI.
1746 Since there are major incompatibilities between the legacy ABI and
1747 EABI, especially with regard to structure member alignment, this
1748 option also changes the kernel syscall calling convention to
1749 disambiguate both ABIs and allow for backward compatibility support
1750 (selected with CONFIG_OABI_COMPAT).
1752 To use this you need GCC version 4.0.0 or later.
1755 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1756 depends on AEABI && !THUMB2_KERNEL
1759 This option preserves the old syscall interface along with the
1760 new (ARM EABI) one. It also provides a compatibility layer to
1761 intercept syscalls that have structure arguments which layout
1762 in memory differs between the legacy ABI and the new ARM EABI
1763 (only for non "thumb" binaries). This option adds a tiny
1764 overhead to all syscalls and produces a slightly larger kernel.
1765 If you know you'll be using only pure EABI user space then you
1766 can say N here. If this option is not selected and you attempt
1767 to execute a legacy ABI binary then the result will be
1768 UNPREDICTABLE (in fact it can be predicted that it won't work
1769 at all). If in doubt say Y.
1771 config ARCH_HAS_HOLES_MEMORYMODEL
1774 config ARCH_SPARSEMEM_ENABLE
1777 config ARCH_SPARSEMEM_DEFAULT
1778 def_bool ARCH_SPARSEMEM_ENABLE
1780 config ARCH_SELECT_MEMORY_MODEL
1781 def_bool ARCH_SPARSEMEM_ENABLE
1783 config HAVE_ARCH_PFN_VALID
1784 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1787 bool "High Memory Support"
1790 The address space of ARM processors is only 4 Gigabytes large
1791 and it has to accommodate user address space, kernel address
1792 space as well as some memory mapped IO. That means that, if you
1793 have a large amount of physical memory and/or IO, not all of the
1794 memory can be "permanently mapped" by the kernel. The physical
1795 memory that is not permanently mapped is called "high memory".
1797 Depending on the selected kernel/user memory split, minimum
1798 vmalloc space and actual amount of RAM, you may not need this
1799 option which should result in a slightly faster kernel.
1804 bool "Allocate 2nd-level pagetables from highmem"
1807 config HW_PERF_EVENTS
1808 bool "Enable hardware performance counter support for perf events"
1809 depends on PERF_EVENTS
1812 Enable hardware performance counter support for perf events. If
1813 disabled, perf events will use software events only.
1815 config SYS_SUPPORTS_HUGETLBFS
1819 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1823 config ARCH_WANT_GENERAL_HUGETLB
1828 config FORCE_MAX_ZONEORDER
1829 int "Maximum zone order" if ARCH_SHMOBILE
1830 range 11 64 if ARCH_SHMOBILE
1831 default "12" if SOC_AM33XX
1832 default "9" if SA1111
1835 The kernel memory allocator divides physically contiguous memory
1836 blocks into "zones", where each zone is a power of two number of
1837 pages. This option selects the largest power of two that the kernel
1838 keeps in the memory allocator. If you need to allocate very large
1839 blocks of physically contiguous memory, then you may need to
1840 increase this value.
1842 This config option is actually maximum order plus one. For example,
1843 a value of 11 means that the largest free memory block is 2^10 pages.
1845 config ALIGNMENT_TRAP
1847 depends on CPU_CP15_MMU
1848 default y if !ARCH_EBSA110
1849 select HAVE_PROC_CPU if PROC_FS
1851 ARM processors cannot fetch/store information which is not
1852 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1853 address divisible by 4. On 32-bit ARM processors, these non-aligned
1854 fetch/store instructions will be emulated in software if you say
1855 here, which has a severe performance impact. This is necessary for
1856 correct operation of some network protocols. With an IP-only
1857 configuration it is safe to say N, otherwise say Y.
1859 config UACCESS_WITH_MEMCPY
1860 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1862 default y if CPU_FEROCEON
1864 Implement faster copy_to_user and clear_user methods for CPU
1865 cores where a 8-word STM instruction give significantly higher
1866 memory write throughput than a sequence of individual 32bit stores.
1868 A possible side effect is a slight increase in scheduling latency
1869 between threads sharing the same address space if they invoke
1870 such copy operations with large buffers.
1872 However, if the CPU data cache is using a write-allocate mode,
1873 this option is unlikely to provide any performance gain.
1877 prompt "Enable seccomp to safely compute untrusted bytecode"
1879 This kernel feature is useful for number crunching applications
1880 that may need to compute untrusted bytecode during their
1881 execution. By using pipes or other transports made available to
1882 the process as file descriptors supporting the read/write
1883 syscalls, it's possible to isolate those applications in
1884 their own address space using seccomp. Once seccomp is
1885 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1886 and the task is only allowed to execute a few safe syscalls
1887 defined by each seccomp mode.
1889 config CC_STACKPROTECTOR
1890 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1892 This option turns on the -fstack-protector GCC feature. This
1893 feature puts, at the beginning of functions, a canary value on
1894 the stack just before the return address, and validates
1895 the value just before actually returning. Stack based buffer
1896 overflows (that need to overwrite this return address) now also
1897 overwrite the canary, which gets detected and the attack is then
1898 neutralized via a kernel panic.
1899 This feature requires gcc version 4.2 or above.
1906 bool "Xen guest support on ARM (EXPERIMENTAL)"
1907 depends on ARM && AEABI && OF
1908 depends on CPU_V7 && !CPU_V6
1909 depends on !GENERIC_ATOMIC64
1912 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1919 bool "Flattened Device Tree support"
1922 select OF_EARLY_FLATTREE
1924 Include support for flattened device tree machine descriptions.
1927 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1930 This is the traditional way of passing data to the kernel at boot
1931 time. If you are solely relying on the flattened device tree (or
1932 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1933 to remove ATAGS support from your kernel binary. If unsure,
1936 config DEPRECATED_PARAM_STRUCT
1937 bool "Provide old way to pass kernel parameters"
1940 This was deprecated in 2001 and announced to live on for 5 years.
1941 Some old boot loaders still use this way.
1943 # Compressed boot loader in ROM. Yes, we really want to ask about
1944 # TEXT and BSS so we preserve their values in the config files.
1945 config ZBOOT_ROM_TEXT
1946 hex "Compressed ROM boot loader base address"
1949 The physical address at which the ROM-able zImage is to be
1950 placed in the target. Platforms which normally make use of
1951 ROM-able zImage formats normally set this to a suitable
1952 value in their defconfig file.
1954 If ZBOOT_ROM is not enabled, this has no effect.
1956 config ZBOOT_ROM_BSS
1957 hex "Compressed ROM boot loader BSS address"
1960 The base address of an area of read/write memory in the target
1961 for the ROM-able zImage which must be available while the
1962 decompressor is running. It must be large enough to hold the
1963 entire decompressed kernel plus an additional 128 KiB.
1964 Platforms which normally make use of ROM-able zImage formats
1965 normally set this to a suitable value in their defconfig file.
1967 If ZBOOT_ROM is not enabled, this has no effect.
1970 bool "Compressed boot loader in ROM/flash"
1971 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1973 Say Y here if you intend to execute your compressed kernel image
1974 (zImage) directly from ROM or flash. If unsure, say N.
1977 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1978 depends on ZBOOT_ROM && ARCH_SH7372
1979 default ZBOOT_ROM_NONE
1981 Include experimental SD/MMC loading code in the ROM-able zImage.
1982 With this enabled it is possible to write the ROM-able zImage
1983 kernel image to an MMC or SD card and boot the kernel straight
1984 from the reset vector. At reset the processor Mask ROM will load
1985 the first part of the ROM-able zImage which in turn loads the
1986 rest the kernel image to RAM.
1988 config ZBOOT_ROM_NONE
1989 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1991 Do not load image from SD or MMC
1993 config ZBOOT_ROM_MMCIF
1994 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1996 Load image from MMCIF hardware block.
1998 config ZBOOT_ROM_SH_MOBILE_SDHI
1999 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2001 Load image from SDHI hardware block
2005 config ARM_APPENDED_DTB
2006 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2007 depends on OF && !ZBOOT_ROM
2009 With this option, the boot code will look for a device tree binary
2010 (DTB) appended to zImage
2011 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2013 This is meant as a backward compatibility convenience for those
2014 systems with a bootloader that can't be upgraded to accommodate
2015 the documented boot protocol using a device tree.
2017 Beware that there is very little in terms of protection against
2018 this option being confused by leftover garbage in memory that might
2019 look like a DTB header after a reboot if no actual DTB is appended
2020 to zImage. Do not leave this option active in a production kernel
2021 if you don't intend to always append a DTB. Proper passing of the
2022 location into r2 of a bootloader provided DTB is always preferable
2025 config ARM_ATAG_DTB_COMPAT
2026 bool "Supplement the appended DTB with traditional ATAG information"
2027 depends on ARM_APPENDED_DTB
2029 Some old bootloaders can't be updated to a DTB capable one, yet
2030 they provide ATAGs with memory configuration, the ramdisk address,
2031 the kernel cmdline string, etc. Such information is dynamically
2032 provided by the bootloader and can't always be stored in a static
2033 DTB. To allow a device tree enabled kernel to be used with such
2034 bootloaders, this option allows zImage to extract the information
2035 from the ATAG list and store it at run time into the appended DTB.
2038 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2039 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2041 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2042 bool "Use bootloader kernel arguments if available"
2044 Uses the command-line options passed by the boot loader instead of
2045 the device tree bootargs property. If the boot loader doesn't provide
2046 any, the device tree bootargs property will be used.
2048 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2049 bool "Extend with bootloader kernel arguments"
2051 The command-line arguments provided by the boot loader will be
2052 appended to the the device tree bootargs property.
2057 string "Default kernel command string"
2060 On some architectures (EBSA110 and CATS), there is currently no way
2061 for the boot loader to pass arguments to the kernel. For these
2062 architectures, you should supply some command-line options at build
2063 time by entering them here. As a minimum, you should specify the
2064 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2067 prompt "Kernel command line type" if CMDLINE != ""
2068 default CMDLINE_FROM_BOOTLOADER
2071 config CMDLINE_FROM_BOOTLOADER
2072 bool "Use bootloader kernel arguments if available"
2074 Uses the command-line options passed by the boot loader. If
2075 the boot loader doesn't provide any, the default kernel command
2076 string provided in CMDLINE will be used.
2078 config CMDLINE_EXTEND
2079 bool "Extend bootloader kernel arguments"
2081 The command-line arguments provided by the boot loader will be
2082 appended to the default kernel command string.
2084 config CMDLINE_FORCE
2085 bool "Always use the default kernel command string"
2087 Always use the default kernel command string, even if the boot
2088 loader passes other arguments to the kernel.
2089 This is useful if you cannot or don't want to change the
2090 command-line options your boot loader passes to the kernel.
2094 bool "Kernel Execute-In-Place from ROM"
2095 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2097 Execute-In-Place allows the kernel to run from non-volatile storage
2098 directly addressable by the CPU, such as NOR flash. This saves RAM
2099 space since the text section of the kernel is not loaded from flash
2100 to RAM. Read-write sections, such as the data section and stack,
2101 are still copied to RAM. The XIP kernel is not compressed since
2102 it has to run directly from flash, so it will take more space to
2103 store it. The flash address used to link the kernel object files,
2104 and for storing it, is configuration dependent. Therefore, if you
2105 say Y here, you must know the proper physical address where to
2106 store the kernel image depending on your own flash memory usage.
2108 Also note that the make target becomes "make xipImage" rather than
2109 "make zImage" or "make Image". The final kernel binary to put in
2110 ROM memory will be arch/arm/boot/xipImage.
2114 config XIP_PHYS_ADDR
2115 hex "XIP Kernel Physical Location"
2116 depends on XIP_KERNEL
2117 default "0x00080000"
2119 This is the physical address in your flash memory the kernel will
2120 be linked for and stored to. This address is dependent on your
2124 bool "Kexec system call (EXPERIMENTAL)"
2125 depends on (!SMP || PM_SLEEP_SMP)
2127 kexec is a system call that implements the ability to shutdown your
2128 current kernel, and to start another kernel. It is like a reboot
2129 but it is independent of the system firmware. And like a reboot
2130 you can start any kernel with it, not just Linux.
2132 It is an ongoing process to be certain the hardware in a machine
2133 is properly shutdown, so do not be surprised if this code does not
2134 initially work for you.
2137 bool "Export atags in procfs"
2138 depends on ATAGS && KEXEC
2141 Should the atags used to boot the kernel be exported in an "atags"
2142 file in procfs. Useful with kexec.
2145 bool "Build kdump crash kernel (EXPERIMENTAL)"
2147 Generate crash dump after being started by kexec. This should
2148 be normally only set in special crash dump kernels which are
2149 loaded in the main kernel with kexec-tools into a specially
2150 reserved region and then later executed after a crash by
2151 kdump/kexec. The crash dump kernel must be compiled to a
2152 memory address not used by the main kernel
2154 For more details see Documentation/kdump/kdump.txt
2156 config AUTO_ZRELADDR
2157 bool "Auto calculation of the decompressed kernel image address"
2158 depends on !ZBOOT_ROM
2160 ZRELADDR is the physical address where the decompressed kernel
2161 image will be placed. If AUTO_ZRELADDR is selected, the address
2162 will be determined at run-time by masking the current IP with
2163 0xf8000000. This assumes the zImage being placed in the first 128MB
2164 from start of memory.
2168 menu "CPU Power Management"
2171 source "drivers/cpufreq/Kconfig"
2174 source "drivers/cpuidle/Kconfig"
2178 menu "Floating point emulation"
2180 comment "At least one emulation must be selected"
2183 bool "NWFPE math emulation"
2184 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2186 Say Y to include the NWFPE floating point emulator in the kernel.
2187 This is necessary to run most binaries. Linux does not currently
2188 support floating point hardware so you need to say Y here even if
2189 your machine has an FPA or floating point co-processor podule.
2191 You may say N here if you are going to load the Acorn FPEmulator
2192 early in the bootup.
2195 bool "Support extended precision"
2196 depends on FPE_NWFPE
2198 Say Y to include 80-bit support in the kernel floating-point
2199 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2200 Note that gcc does not generate 80-bit operations by default,
2201 so in most cases this option only enlarges the size of the
2202 floating point emulator without any good reason.
2204 You almost surely want to say N here.
2207 bool "FastFPE math emulation (EXPERIMENTAL)"
2208 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2210 Say Y here to include the FAST floating point emulator in the kernel.
2211 This is an experimental much faster emulator which now also has full
2212 precision for the mantissa. It does not support any exceptions.
2213 It is very simple, and approximately 3-6 times faster than NWFPE.
2215 It should be sufficient for most programs. It may be not suitable
2216 for scientific calculations, but you have to check this for yourself.
2217 If you do not feel you need a faster FP emulation you should better
2221 bool "VFP-format floating point maths"
2222 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2224 Say Y to include VFP support code in the kernel. This is needed
2225 if your hardware includes a VFP unit.
2227 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2228 release notes and additional status information.
2230 Say N if your target does not have VFP hardware.
2238 bool "Advanced SIMD (NEON) Extension support"
2239 depends on VFPv3 && CPU_V7
2241 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2244 config KERNEL_MODE_NEON
2245 bool "Support for NEON in kernel mode"
2249 Say Y to include support for NEON in kernel mode.
2253 menu "Userspace binary formats"
2255 source "fs/Kconfig.binfmt"
2258 tristate "RISC OS personality"
2261 Say Y here to include the kernel code necessary if you want to run
2262 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2263 experimental; if this sounds frightening, say N and sleep in peace.
2264 You can also say M here to compile this support as a module (which
2265 will be called arthur).
2269 menu "Power management options"
2271 source "kernel/power/Kconfig"
2273 config ARCH_SUSPEND_POSSIBLE
2274 depends on !ARCH_S5PC100
2275 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2276 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2279 config ARM_CPU_SUSPEND
2284 source "net/Kconfig"
2286 source "drivers/Kconfig"
2290 source "arch/arm/Kconfig.debug"
2292 source "security/Kconfig"
2294 source "crypto/Kconfig"
2296 source "lib/Kconfig"
2298 source "arch/arm/kvm/Kconfig"