4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_WANT_IPC_PARSE_VERSION
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CLONE_BACKWARDS
13 select CPU_PM if (SUSPEND || CPU_IDLE)
14 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
15 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
16 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
17 select GENERIC_IDLE_POLL_SETUP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PCI_IOMAP
21 select GENERIC_SCHED_CLOCK
22 select GENERIC_SMP_IDLE_THREAD
23 select GENERIC_STRNCPY_FROM_USER
24 select GENERIC_STRNLEN_USER
25 select HARDIRQS_SW_RESEND
26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
28 select HAVE_ARCH_SECCOMP_FILTER
29 select HAVE_ARCH_TRACEHOOK
31 select HAVE_CONTEXT_TRACKING
32 select HAVE_C_RECORDMCOUNT
33 select HAVE_DEBUG_KMEMLEAK
34 select HAVE_DMA_API_DEBUG
36 select HAVE_DMA_CONTIGUOUS if MMU
37 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
38 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
39 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
40 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
41 select HAVE_GENERIC_DMA_COHERENT
42 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
43 select HAVE_IDE if PCI || ISA || PCMCIA
44 select HAVE_IRQ_TIME_ACCOUNTING
45 select HAVE_KERNEL_GZIP
46 select HAVE_KERNEL_LZ4
47 select HAVE_KERNEL_LZMA
48 select HAVE_KERNEL_LZO
50 select HAVE_KPROBES if !XIP_KERNEL
51 select HAVE_KRETPROBES if (HAVE_KPROBES)
53 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
54 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
55 select HAVE_PERF_EVENTS
57 select HAVE_PERF_USER_STACK_DUMP
58 select HAVE_REGS_AND_STACK_ACCESS_API
59 select HAVE_SYSCALL_TRACEPOINTS
61 select HAVE_VIRT_CPU_ACCOUNTING_GEN
62 select IRQ_FORCED_THREADING
64 select MODULES_USE_ELF_REL
66 select OLD_SIGSUSPEND3
67 select PERF_USE_VMALLOC
69 select SYS_SUPPORTS_APM_EMULATION
70 # Above selects are sorted alphabetically; please add new ones
71 # according to that. Thanks.
73 The ARM series is a line of low-power-consumption RISC chip designs
74 licensed by ARM Ltd and targeted at embedded applications and
75 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
76 manufactured, but legacy ARM-based PC hardware remains popular in
77 Europe. There is an ARM Linux project with a web page at
78 <http://www.arm.linux.org.uk/>.
80 config ARM_HAS_SG_CHAIN
83 config NEED_SG_DMA_LENGTH
86 config ARM_DMA_USE_IOMMU
88 select ARM_HAS_SG_CHAIN
89 select NEED_SG_DMA_LENGTH
93 config ARM_DMA_IOMMU_ALIGNMENT
94 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
98 DMA mapping framework by default aligns all buffers to the smallest
99 PAGE_SIZE order which is greater than or equal to the requested buffer
100 size. This works well for buffers up to a few hundreds kilobytes, but
101 for larger buffers it just a waste of address space. Drivers which has
102 relatively small addressing window (like 64Mib) might run out of
103 virtual space with just a few allocations.
105 With this parameter you can specify the maximum PAGE_SIZE order for
106 DMA IOMMU buffers. Larger buffers will be aligned only to this
107 specified order. The order is expressed as a power of two multiplied
115 config MIGHT_HAVE_PCI
118 config SYS_SUPPORTS_APM_EMULATION
123 select GENERIC_ALLOCATOR
134 The Extended Industry Standard Architecture (EISA) bus was
135 developed as an open alternative to the IBM MicroChannel bus.
137 The EISA bus provided some of the features of the IBM MicroChannel
138 bus while maintaining backward compatibility with cards made for
139 the older ISA bus. The EISA bus saw limited use between 1988 and
140 1995 when it was made obsolete by the PCI bus.
142 Say Y here if you are building a kernel for an EISA-based machine.
149 config STACKTRACE_SUPPORT
153 config HAVE_LATENCYTOP_SUPPORT
158 config LOCKDEP_SUPPORT
162 config TRACE_IRQFLAGS_SUPPORT
166 config RWSEM_GENERIC_SPINLOCK
170 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_CPUFREQ
182 Internal node to signify that the ARCH has CPUFREQ support
183 and that the relevant menu configurations are displayed for
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_HAS_DMA_SET_COHERENT_MASK
209 config GENERIC_ISA_DMA
215 config NEED_RET_TO_USER
223 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
224 default DRAM_BASE if REMAP_VECTORS_TO_RAM
227 The base address of exception vectors. This must be two pages
230 config ARM_PATCH_PHYS_VIRT
231 bool "Patch physical to virtual translations at runtime" if EMBEDDED
233 depends on !XIP_KERNEL && MMU
234 depends on !ARCH_REALVIEW || !SPARSEMEM
236 Patch phys-to-virt and virt-to-phys translation functions at
237 boot and module load time according to the position of the
238 kernel in system memory.
240 This can only be used with non-XIP MMU kernels where the base
241 of physical memory is at a 16MB boundary.
243 Only disable this option if you know that you do not require
244 this feature (eg, building a kernel for a single machine) and
245 you need to shrink the kernel to the minimal size.
247 config NEED_MACH_GPIO_H
250 Select this when mach/gpio.h is required to provide special
251 definitions for this platform. The need for mach/gpio.h should
252 be avoided when possible.
254 config NEED_MACH_IO_H
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
261 config NEED_MACH_MEMORY_H
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
271 default DRAM_BASE if !MMU
273 Please provide the physical address corresponding to the
274 location of main memory in your system.
280 source "init/Kconfig"
282 source "kernel/Kconfig.freezer"
287 bool "MMU-based Paged Memory Management Support"
290 Select if you want MMU-based virtualised addressing space
291 support by paged memory management. If unsure, say 'Y'.
294 # The "ARM system type" choice list is ordered alphabetically by option
295 # text. Please add new entries in the option alphabetic order.
298 prompt "ARM system type"
299 default ARCH_VERSATILE if !MMU
300 default ARCH_MULTIPLATFORM if MMU
302 config ARCH_MULTIPLATFORM
303 bool "Allow multiple platforms to be selected"
305 select ARM_PATCH_PHYS_VIRT
308 select MULTI_IRQ_HANDLER
312 config ARCH_INTEGRATOR
313 bool "ARM Ltd. Integrator family"
314 select ARCH_HAS_CPUFREQ
317 select COMMON_CLK_VERSATILE
318 select GENERIC_CLOCKEVENTS
321 select MULTI_IRQ_HANDLER
322 select NEED_MACH_MEMORY_H
323 select PLAT_VERSATILE
326 select VERSATILE_FPGA_IRQ
328 Support for ARM's Integrator platform.
331 bool "ARM Ltd. RealView family"
332 select ARCH_WANT_OPTIONAL_GPIOLIB
334 select ARM_TIMER_SP804
336 select COMMON_CLK_VERSATILE
337 select GENERIC_CLOCKEVENTS
338 select GPIO_PL061 if GPIOLIB
340 select NEED_MACH_MEMORY_H
341 select PLAT_VERSATILE
342 select PLAT_VERSATILE_CLCD
344 This enables support for ARM Ltd RealView boards.
346 config ARCH_VERSATILE
347 bool "ARM Ltd. Versatile family"
348 select ARCH_WANT_OPTIONAL_GPIOLIB
350 select ARM_TIMER_SP804
353 select GENERIC_CLOCKEVENTS
354 select HAVE_MACH_CLKDEV
356 select PLAT_VERSATILE
357 select PLAT_VERSATILE_CLCD
358 select PLAT_VERSATILE_CLOCK
359 select VERSATILE_FPGA_IRQ
361 This enables support for ARM Ltd Versatile board.
365 select ARCH_REQUIRE_GPIOLIB
368 select NEED_MACH_GPIO_H
369 select NEED_MACH_IO_H if PCCARD
371 select PINCTRL_AT91 if USE_OF
373 This enables support for systems based on Atmel
374 AT91RM9200 and AT91SAM9* processors.
377 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
378 select ARCH_REQUIRE_GPIOLIB
383 select GENERIC_CLOCKEVENTS
385 select MULTI_IRQ_HANDLER
388 Support for Cirrus Logic 711x/721x/731x based boards.
391 bool "Cortina Systems Gemini"
392 select ARCH_REQUIRE_GPIOLIB
393 select ARCH_USES_GETTIMEOFFSET
396 Support for the Cortina Systems Gemini family SoCs
400 select ARCH_USES_GETTIMEOFFSET
403 select NEED_MACH_IO_H
404 select NEED_MACH_MEMORY_H
407 This is an evaluation board for the StrongARM processor available
408 from Digital. It has limited hardware on-board, including an
409 Ethernet interface, two PCMCIA sockets, two serial ports and a
414 select ARCH_HAS_HOLES_MEMORYMODEL
415 select ARCH_REQUIRE_GPIOLIB
416 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_MEMORY_H
423 This enables support for the Cirrus EP93xx series of CPUs.
425 config ARCH_FOOTBRIDGE
429 select GENERIC_CLOCKEVENTS
431 select NEED_MACH_IO_H if !MMU
432 select NEED_MACH_MEMORY_H
434 Support for systems based on the DC21285 companion chip
435 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
438 bool "Hilscher NetX based"
442 select GENERIC_CLOCKEVENTS
444 This enables support for systems based on the Hilscher NetX Soc
450 select NEED_MACH_MEMORY_H
451 select NEED_RET_TO_USER
456 Support for Intel's IOP13XX (XScale) family of processors.
461 select ARCH_REQUIRE_GPIOLIB
464 select NEED_RET_TO_USER
468 Support for Intel's 80219 and IOP32X (XScale) family of
474 select ARCH_REQUIRE_GPIOLIB
477 select NEED_RET_TO_USER
481 Support for Intel's IOP33X (XScale) family of processors.
486 select ARCH_HAS_DMA_SET_COHERENT_MASK
487 select ARCH_REQUIRE_GPIOLIB
490 select DMABOUNCE if PCI
491 select GENERIC_CLOCKEVENTS
492 select MIGHT_HAVE_PCI
493 select NEED_MACH_IO_H
494 select USB_EHCI_BIG_ENDIAN_DESC
495 select USB_EHCI_BIG_ENDIAN_MMIO
497 Support for Intel's IXP4XX (XScale) family of processors.
501 select ARCH_REQUIRE_GPIOLIB
503 select GENERIC_CLOCKEVENTS
504 select MIGHT_HAVE_PCI
508 select PLAT_ORION_LEGACY
509 select USB_ARCH_HAS_EHCI
511 Support for the Marvell Dove SoC 88AP510
514 bool "Marvell Kirkwood"
515 select ARCH_HAS_CPUFREQ
516 select ARCH_REQUIRE_GPIOLIB
518 select GENERIC_CLOCKEVENTS
523 select PINCTRL_KIRKWOOD
524 select PLAT_ORION_LEGACY
526 Support for the following Marvell Kirkwood series SoCs:
527 88F6180, 88F6192 and 88F6281.
530 bool "Marvell MV78xx0"
531 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
536 select PLAT_ORION_LEGACY
538 Support for the following Marvell MV78xx0 series SoCs:
544 select ARCH_REQUIRE_GPIOLIB
546 select GENERIC_CLOCKEVENTS
549 select PLAT_ORION_LEGACY
551 Support for the following Marvell Orion 5x series SoCs:
552 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
553 Orion-2 (5281), Orion-1-90 (6183).
556 bool "Marvell PXA168/910/MMP2"
558 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_ALLOCATOR
561 select GENERIC_CLOCKEVENTS
564 select MULTI_IRQ_HANDLER
569 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
572 bool "Micrel/Kendin KS8695"
573 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
577 select NEED_MACH_MEMORY_H
579 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
580 System-on-Chip devices.
583 bool "Nuvoton W90X900 CPU"
584 select ARCH_REQUIRE_GPIOLIB
588 select GENERIC_CLOCKEVENTS
590 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
591 At present, the w90x900 has been renamed nuc900, regarding
592 the ARM series product line, you can login the following
593 link address to know more.
595 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
596 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
600 select ARCH_REQUIRE_GPIOLIB
605 select GENERIC_CLOCKEVENTS
608 select USB_ARCH_HAS_OHCI
611 Support for the NXP LPC32XX family of processors
614 bool "PXA2xx/PXA3xx-based"
616 select ARCH_HAS_CPUFREQ
618 select ARCH_REQUIRE_GPIOLIB
619 select ARM_CPU_SUSPEND if PM
623 select GENERIC_CLOCKEVENTS
626 select MULTI_IRQ_HANDLER
630 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
634 select ARCH_REQUIRE_GPIOLIB
635 select CLKSRC_OF if OF
637 select GENERIC_CLOCKEVENTS
639 Support for Qualcomm MSM/QSD based systems. This runs on the
640 apps processor of the MSM/QSD and depends on a shared memory
641 interface to the modem processor which runs the baseband
642 stack and controls some vital subsystems
643 (clock and power control, etc).
646 bool "Renesas SH-Mobile / R-Mobile"
647 select ARM_PATCH_PHYS_VIRT
649 select GENERIC_CLOCKEVENTS
650 select HAVE_ARM_SCU if SMP
651 select HAVE_ARM_TWD if SMP
652 select HAVE_MACH_CLKDEV
654 select MIGHT_HAVE_CACHE_L2X0
655 select MULTI_IRQ_HANDLER
658 select PM_GENERIC_DOMAINS if PM
661 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
666 select ARCH_MAY_HAVE_PC_FDC
667 select ARCH_SPARSEMEM_ENABLE
668 select ARCH_USES_GETTIMEOFFSET
671 select HAVE_PATA_PLATFORM
673 select NEED_MACH_IO_H
674 select NEED_MACH_MEMORY_H
678 On the Acorn Risc-PC, Linux can support the internal IDE disk and
679 CD-ROM interface, serial and parallel port, and the floppy drive.
683 select ARCH_HAS_CPUFREQ
685 select ARCH_REQUIRE_GPIOLIB
686 select ARCH_SPARSEMEM_ENABLE
691 select GENERIC_CLOCKEVENTS
694 select NEED_MACH_MEMORY_H
697 Support for StrongARM 11x0 based boards.
700 bool "Samsung S3C24XX SoCs"
701 select ARCH_HAS_CPUFREQ
702 select ARCH_REQUIRE_GPIOLIB
704 select CLKSRC_SAMSUNG_PWM
705 select GENERIC_CLOCKEVENTS
707 select HAVE_S3C2410_I2C if I2C
708 select HAVE_S3C2410_WATCHDOG if WATCHDOG
709 select HAVE_S3C_RTC if RTC_CLASS
710 select MULTI_IRQ_HANDLER
711 select NEED_MACH_GPIO_H
712 select NEED_MACH_IO_H
715 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
716 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
717 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
718 Samsung SMDK2410 development board (and derivatives).
721 bool "Samsung S3C64XX"
722 select ARCH_HAS_CPUFREQ
723 select ARCH_REQUIRE_GPIOLIB
726 select CLKSRC_SAMSUNG_PWM
729 select GENERIC_CLOCKEVENTS
731 select HAVE_S3C2410_I2C if I2C
732 select HAVE_S3C2410_WATCHDOG if WATCHDOG
734 select NEED_MACH_GPIO_H
737 select PM_GENERIC_DOMAINS
739 select S3C_GPIO_TRACK
741 select SAMSUNG_GPIOLIB_4BIT
742 select SAMSUNG_WAKEMASK
743 select SAMSUNG_WDT_RESET
744 select USB_ARCH_HAS_OHCI
746 Samsung S3C64XX series based systems
749 bool "Samsung S5P6440 S5P6450"
751 select CLKSRC_SAMSUNG_PWM
753 select GENERIC_CLOCKEVENTS
755 select HAVE_S3C2410_I2C if I2C
756 select HAVE_S3C2410_WATCHDOG if WATCHDOG
757 select HAVE_S3C_RTC if RTC_CLASS
758 select NEED_MACH_GPIO_H
760 select SAMSUNG_WDT_RESET
762 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
766 bool "Samsung S5PC100"
767 select ARCH_REQUIRE_GPIOLIB
769 select CLKSRC_SAMSUNG_PWM
771 select GENERIC_CLOCKEVENTS
773 select HAVE_S3C2410_I2C if I2C
774 select HAVE_S3C2410_WATCHDOG if WATCHDOG
775 select HAVE_S3C_RTC if RTC_CLASS
776 select NEED_MACH_GPIO_H
778 select SAMSUNG_WDT_RESET
780 Samsung S5PC100 series based systems
783 bool "Samsung S5PV210/S5PC110"
784 select ARCH_HAS_CPUFREQ
785 select ARCH_HAS_HOLES_MEMORYMODEL
786 select ARCH_SPARSEMEM_ENABLE
788 select CLKSRC_SAMSUNG_PWM
790 select GENERIC_CLOCKEVENTS
792 select HAVE_S3C2410_I2C if I2C
793 select HAVE_S3C2410_WATCHDOG if WATCHDOG
794 select HAVE_S3C_RTC if RTC_CLASS
795 select NEED_MACH_GPIO_H
796 select NEED_MACH_MEMORY_H
799 Samsung S5PV210/S5PC110 series based systems
802 bool "Samsung EXYNOS"
803 select ARCH_HAS_CPUFREQ
804 select ARCH_HAS_HOLES_MEMORYMODEL
805 select ARCH_REQUIRE_GPIOLIB
806 select ARCH_SPARSEMEM_ENABLE
810 select GENERIC_CLOCKEVENTS
811 select HAVE_S3C2410_I2C if I2C
812 select HAVE_S3C2410_WATCHDOG if WATCHDOG
813 select HAVE_S3C_RTC if RTC_CLASS
814 select NEED_MACH_MEMORY_H
818 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
822 select ARCH_HAS_HOLES_MEMORYMODEL
823 select ARCH_REQUIRE_GPIOLIB
825 select GENERIC_ALLOCATOR
826 select GENERIC_CLOCKEVENTS
827 select GENERIC_IRQ_CHIP
833 Support for TI's DaVinci platform.
838 select ARCH_HAS_CPUFREQ
839 select ARCH_HAS_HOLES_MEMORYMODEL
841 select ARCH_REQUIRE_GPIOLIB
844 select GENERIC_CLOCKEVENTS
845 select GENERIC_IRQ_CHIP
848 select NEED_MACH_IO_H if PCCARD
849 select NEED_MACH_MEMORY_H
851 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
855 menu "Multiple platform selection"
856 depends on ARCH_MULTIPLATFORM
858 comment "CPU Core family selection"
860 config ARCH_MULTI_V4T
861 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
862 depends on !ARCH_MULTI_V6_V7
863 select ARCH_MULTI_V4_V5
864 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
865 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
866 CPU_ARM925T || CPU_ARM940T)
869 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
870 depends on !ARCH_MULTI_V6_V7
871 select ARCH_MULTI_V4_V5
872 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
873 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
874 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
876 config ARCH_MULTI_V4_V5
880 bool "ARMv6 based platforms (ARM11)"
881 select ARCH_MULTI_V6_V7
885 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
887 select ARCH_MULTI_V6_V7
890 config ARCH_MULTI_V6_V7
893 config ARCH_MULTI_CPU_AUTO
894 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
900 # This is sorted alphabetically by mach-* pathname. However, plat-*
901 # Kconfigs may be included either alphabetically (according to the
902 # plat- suffix) or along side the corresponding mach-* source.
904 source "arch/arm/mach-mvebu/Kconfig"
906 source "arch/arm/mach-at91/Kconfig"
908 source "arch/arm/mach-bcm/Kconfig"
910 source "arch/arm/mach-bcm2835/Kconfig"
912 source "arch/arm/mach-clps711x/Kconfig"
914 source "arch/arm/mach-cns3xxx/Kconfig"
916 source "arch/arm/mach-davinci/Kconfig"
918 source "arch/arm/mach-dove/Kconfig"
920 source "arch/arm/mach-ep93xx/Kconfig"
922 source "arch/arm/mach-footbridge/Kconfig"
924 source "arch/arm/mach-gemini/Kconfig"
926 source "arch/arm/mach-highbank/Kconfig"
928 source "arch/arm/mach-integrator/Kconfig"
930 source "arch/arm/mach-iop32x/Kconfig"
932 source "arch/arm/mach-iop33x/Kconfig"
934 source "arch/arm/mach-iop13xx/Kconfig"
936 source "arch/arm/mach-ixp4xx/Kconfig"
938 source "arch/arm/mach-keystone/Kconfig"
940 source "arch/arm/mach-kirkwood/Kconfig"
942 source "arch/arm/mach-ks8695/Kconfig"
944 source "arch/arm/mach-msm/Kconfig"
946 source "arch/arm/mach-mv78xx0/Kconfig"
948 source "arch/arm/mach-imx/Kconfig"
950 source "arch/arm/mach-mxs/Kconfig"
952 source "arch/arm/mach-netx/Kconfig"
954 source "arch/arm/mach-nomadik/Kconfig"
956 source "arch/arm/mach-nspire/Kconfig"
958 source "arch/arm/plat-omap/Kconfig"
960 source "arch/arm/mach-omap1/Kconfig"
962 source "arch/arm/mach-omap2/Kconfig"
964 source "arch/arm/mach-orion5x/Kconfig"
966 source "arch/arm/mach-picoxcell/Kconfig"
968 source "arch/arm/mach-pxa/Kconfig"
969 source "arch/arm/plat-pxa/Kconfig"
971 source "arch/arm/mach-mmp/Kconfig"
973 source "arch/arm/mach-realview/Kconfig"
975 source "arch/arm/mach-rockchip/Kconfig"
977 source "arch/arm/mach-sa1100/Kconfig"
979 source "arch/arm/plat-samsung/Kconfig"
981 source "arch/arm/mach-socfpga/Kconfig"
983 source "arch/arm/mach-spear/Kconfig"
985 source "arch/arm/mach-sti/Kconfig"
987 source "arch/arm/mach-s3c24xx/Kconfig"
989 source "arch/arm/mach-s3c64xx/Kconfig"
991 source "arch/arm/mach-s5p64x0/Kconfig"
993 source "arch/arm/mach-s5pc100/Kconfig"
995 source "arch/arm/mach-s5pv210/Kconfig"
997 source "arch/arm/mach-exynos/Kconfig"
999 source "arch/arm/mach-shmobile/Kconfig"
1001 source "arch/arm/mach-sunxi/Kconfig"
1003 source "arch/arm/mach-prima2/Kconfig"
1005 source "arch/arm/mach-tegra/Kconfig"
1007 source "arch/arm/mach-u300/Kconfig"
1009 source "arch/arm/mach-ux500/Kconfig"
1011 source "arch/arm/mach-versatile/Kconfig"
1013 source "arch/arm/mach-vexpress/Kconfig"
1014 source "arch/arm/plat-versatile/Kconfig"
1016 source "arch/arm/mach-virt/Kconfig"
1018 source "arch/arm/mach-vt8500/Kconfig"
1020 source "arch/arm/mach-w90x900/Kconfig"
1022 source "arch/arm/mach-zynq/Kconfig"
1024 # Definitions to make life easier
1030 select GENERIC_CLOCKEVENTS
1036 select GENERIC_IRQ_CHIP
1039 config PLAT_ORION_LEGACY
1046 config PLAT_VERSATILE
1049 config ARM_TIMER_SP804
1052 select CLKSRC_OF if OF
1054 source arch/arm/mm/Kconfig
1058 default 16 if ARCH_EP93XX
1062 bool "Enable iWMMXt support" if !CPU_PJ4
1063 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1064 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1066 Enable support for iWMMXt context switching at run time if
1067 running on a CPU that supports it.
1071 depends on CPU_XSCALE
1074 config MULTI_IRQ_HANDLER
1077 Allow each machine to specify it's own IRQ handler at run time.
1080 source "arch/arm/Kconfig-nommu"
1083 config PJ4B_ERRATA_4742
1084 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1085 depends on CPU_PJ4B && MACH_ARMADA_370
1088 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1089 Event (WFE) IDLE states, a specific timing sensitivity exists between
1090 the retiring WFI/WFE instructions and the newly issued subsequent
1091 instructions. This sensitivity can result in a CPU hang scenario.
1093 The software must insert either a Data Synchronization Barrier (DSB)
1094 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1097 config ARM_ERRATA_326103
1098 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1101 Executing a SWP instruction to read-only memory does not set bit 11
1102 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1103 treat the access as a read, preventing a COW from occurring and
1104 causing the faulting task to livelock.
1106 config ARM_ERRATA_411920
1107 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1108 depends on CPU_V6 || CPU_V6K
1110 Invalidation of the Instruction Cache operation can
1111 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1112 It does not affect the MPCore. This option enables the ARM Ltd.
1113 recommended workaround.
1115 config ARM_ERRATA_430973
1116 bool "ARM errata: Stale prediction on replaced interworking branch"
1119 This option enables the workaround for the 430973 Cortex-A8
1120 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1121 interworking branch is replaced with another code sequence at the
1122 same virtual address, whether due to self-modifying code or virtual
1123 to physical address re-mapping, Cortex-A8 does not recover from the
1124 stale interworking branch prediction. This results in Cortex-A8
1125 executing the new code sequence in the incorrect ARM or Thumb state.
1126 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1127 and also flushes the branch target cache at every context switch.
1128 Note that setting specific bits in the ACTLR register may not be
1129 available in non-secure mode.
1131 config ARM_ERRATA_458693
1132 bool "ARM errata: Processor deadlock when a false hazard is created"
1134 depends on !ARCH_MULTIPLATFORM
1136 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1137 erratum. For very specific sequences of memory operations, it is
1138 possible for a hazard condition intended for a cache line to instead
1139 be incorrectly associated with a different cache line. This false
1140 hazard might then cause a processor deadlock. The workaround enables
1141 the L1 caching of the NEON accesses and disables the PLD instruction
1142 in the ACTLR register. Note that setting specific bits in the ACTLR
1143 register may not be available in non-secure mode.
1145 config ARM_ERRATA_460075
1146 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1148 depends on !ARCH_MULTIPLATFORM
1150 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1151 erratum. Any asynchronous access to the L2 cache may encounter a
1152 situation in which recent store transactions to the L2 cache are lost
1153 and overwritten with stale memory contents from external memory. The
1154 workaround disables the write-allocate mode for the L2 cache via the
1155 ACTLR register. Note that setting specific bits in the ACTLR register
1156 may not be available in non-secure mode.
1158 config ARM_ERRATA_742230
1159 bool "ARM errata: DMB operation may be faulty"
1160 depends on CPU_V7 && SMP
1161 depends on !ARCH_MULTIPLATFORM
1163 This option enables the workaround for the 742230 Cortex-A9
1164 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1165 between two write operations may not ensure the correct visibility
1166 ordering of the two writes. This workaround sets a specific bit in
1167 the diagnostic register of the Cortex-A9 which causes the DMB
1168 instruction to behave as a DSB, ensuring the correct behaviour of
1171 config ARM_ERRATA_742231
1172 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1173 depends on CPU_V7 && SMP
1174 depends on !ARCH_MULTIPLATFORM
1176 This option enables the workaround for the 742231 Cortex-A9
1177 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1178 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1179 accessing some data located in the same cache line, may get corrupted
1180 data due to bad handling of the address hazard when the line gets
1181 replaced from one of the CPUs at the same time as another CPU is
1182 accessing it. This workaround sets specific bits in the diagnostic
1183 register of the Cortex-A9 which reduces the linefill issuing
1184 capabilities of the processor.
1186 config PL310_ERRATA_588369
1187 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1188 depends on CACHE_L2X0
1190 The PL310 L2 cache controller implements three types of Clean &
1191 Invalidate maintenance operations: by Physical Address
1192 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1193 They are architecturally defined to behave as the execution of a
1194 clean operation followed immediately by an invalidate operation,
1195 both performing to the same memory location. This functionality
1196 is not correctly implemented in PL310 as clean lines are not
1197 invalidated as a result of these operations.
1199 config ARM_ERRATA_643719
1200 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1201 depends on CPU_V7 && SMP
1203 This option enables the workaround for the 643719 Cortex-A9 (prior to
1204 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1205 register returns zero when it should return one. The workaround
1206 corrects this value, ensuring cache maintenance operations which use
1207 it behave as intended and avoiding data corruption.
1209 config ARM_ERRATA_720789
1210 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1213 This option enables the workaround for the 720789 Cortex-A9 (prior to
1214 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1215 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1216 As a consequence of this erratum, some TLB entries which should be
1217 invalidated are not, resulting in an incoherency in the system page
1218 tables. The workaround changes the TLB flushing routines to invalidate
1219 entries regardless of the ASID.
1221 config PL310_ERRATA_727915
1222 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1223 depends on CACHE_L2X0
1225 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1226 operation (offset 0x7FC). This operation runs in background so that
1227 PL310 can handle normal accesses while it is in progress. Under very
1228 rare circumstances, due to this erratum, write data can be lost when
1229 PL310 treats a cacheable write transaction during a Clean &
1230 Invalidate by Way operation.
1232 config ARM_ERRATA_743622
1233 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1235 depends on !ARCH_MULTIPLATFORM
1237 This option enables the workaround for the 743622 Cortex-A9
1238 (r2p*) erratum. Under very rare conditions, a faulty
1239 optimisation in the Cortex-A9 Store Buffer may lead to data
1240 corruption. This workaround sets a specific bit in the diagnostic
1241 register of the Cortex-A9 which disables the Store Buffer
1242 optimisation, preventing the defect from occurring. This has no
1243 visible impact on the overall performance or power consumption of the
1246 config ARM_ERRATA_751472
1247 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1249 depends on !ARCH_MULTIPLATFORM
1251 This option enables the workaround for the 751472 Cortex-A9 (prior
1252 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1253 completion of a following broadcasted operation if the second
1254 operation is received by a CPU before the ICIALLUIS has completed,
1255 potentially leading to corrupted entries in the cache or TLB.
1257 config PL310_ERRATA_753970
1258 bool "PL310 errata: cache sync operation may be faulty"
1259 depends on CACHE_PL310
1261 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1263 Under some condition the effect of cache sync operation on
1264 the store buffer still remains when the operation completes.
1265 This means that the store buffer is always asked to drain and
1266 this prevents it from merging any further writes. The workaround
1267 is to replace the normal offset of cache sync operation (0x730)
1268 by another offset targeting an unmapped PL310 register 0x740.
1269 This has the same effect as the cache sync operation: store buffer
1270 drain and waiting for all buffers empty.
1272 config ARM_ERRATA_754322
1273 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1276 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1277 r3p*) erratum. A speculative memory access may cause a page table walk
1278 which starts prior to an ASID switch but completes afterwards. This
1279 can populate the micro-TLB with a stale entry which may be hit with
1280 the new ASID. This workaround places two dsb instructions in the mm
1281 switching code so that no page table walks can cross the ASID switch.
1283 config ARM_ERRATA_754327
1284 bool "ARM errata: no automatic Store Buffer drain"
1285 depends on CPU_V7 && SMP
1287 This option enables the workaround for the 754327 Cortex-A9 (prior to
1288 r2p0) erratum. The Store Buffer does not have any automatic draining
1289 mechanism and therefore a livelock may occur if an external agent
1290 continuously polls a memory location waiting to observe an update.
1291 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1292 written polling loops from denying visibility of updates to memory.
1294 config ARM_ERRATA_364296
1295 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1298 This options enables the workaround for the 364296 ARM1136
1299 r0p2 erratum (possible cache data corruption with
1300 hit-under-miss enabled). It sets the undocumented bit 31 in
1301 the auxiliary control register and the FI bit in the control
1302 register, thus disabling hit-under-miss without putting the
1303 processor into full low interrupt latency mode. ARM11MPCore
1306 config ARM_ERRATA_764369
1307 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1308 depends on CPU_V7 && SMP
1310 This option enables the workaround for erratum 764369
1311 affecting Cortex-A9 MPCore with two or more processors (all
1312 current revisions). Under certain timing circumstances, a data
1313 cache line maintenance operation by MVA targeting an Inner
1314 Shareable memory region may fail to proceed up to either the
1315 Point of Coherency or to the Point of Unification of the
1316 system. This workaround adds a DSB instruction before the
1317 relevant cache maintenance functions and sets a specific bit
1318 in the diagnostic control register of the SCU.
1320 config PL310_ERRATA_769419
1321 bool "PL310 errata: no automatic Store Buffer drain"
1322 depends on CACHE_L2X0
1324 On revisions of the PL310 prior to r3p2, the Store Buffer does
1325 not automatically drain. This can cause normal, non-cacheable
1326 writes to be retained when the memory system is idle, leading
1327 to suboptimal I/O performance for drivers using coherent DMA.
1328 This option adds a write barrier to the cpu_idle loop so that,
1329 on systems with an outer cache, the store buffer is drained
1332 config ARM_ERRATA_775420
1333 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1336 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1337 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1338 operation aborts with MMU exception, it might cause the processor
1339 to deadlock. This workaround puts DSB before executing ISB if
1340 an abort may occur on cache maintenance.
1342 config ARM_ERRATA_798181
1343 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1344 depends on CPU_V7 && SMP
1346 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1347 adequately shooting down all use of the old entries. This
1348 option enables the Linux kernel workaround for this erratum
1349 which sends an IPI to the CPUs that are running the same ASID
1350 as the one being invalidated.
1352 config ARM_ERRATA_773022
1353 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1356 This option enables the workaround for the 773022 Cortex-A15
1357 (up to r0p4) erratum. In certain rare sequences of code, the
1358 loop buffer may deliver incorrect instructions. This
1359 workaround disables the loop buffer to avoid the erratum.
1363 source "arch/arm/common/Kconfig"
1373 Find out whether you have ISA slots on your motherboard. ISA is the
1374 name of a bus system, i.e. the way the CPU talks to the other stuff
1375 inside your box. Other bus systems are PCI, EISA, MicroChannel
1376 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1377 newer boards don't support it. If you have ISA, say Y, otherwise N.
1379 # Select ISA DMA controller support
1384 # Select ISA DMA interface
1389 bool "PCI support" if MIGHT_HAVE_PCI
1391 Find out whether you have a PCI motherboard. PCI is the name of a
1392 bus system, i.e. the way the CPU talks to the other stuff inside
1393 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1394 VESA. If you have PCI, say Y, otherwise N.
1400 config PCI_NANOENGINE
1401 bool "BSE nanoEngine PCI support"
1402 depends on SA1100_NANOENGINE
1404 Enable PCI on the BSE nanoEngine board.
1409 config PCI_HOST_ITE8152
1411 depends on PCI && MACH_ARMCORE
1415 source "drivers/pci/Kconfig"
1416 source "drivers/pci/pcie/Kconfig"
1418 source "drivers/pcmcia/Kconfig"
1422 menu "Kernel Features"
1427 This option should be selected by machines which have an SMP-
1430 The only effect of this option is to make the SMP-related
1431 options available to the user for configuration.
1434 bool "Symmetric Multi-Processing"
1435 depends on CPU_V6K || CPU_V7
1436 depends on GENERIC_CLOCKEVENTS
1438 depends on MMU || ARM_MPU
1439 select USE_GENERIC_SMP_HELPERS
1441 This enables support for systems with more than one CPU. If you have
1442 a system with only one CPU, like most personal computers, say N. If
1443 you have a system with more than one CPU, say Y.
1445 If you say N here, the kernel will run on single and multiprocessor
1446 machines, but will use only one CPU of a multiprocessor machine. If
1447 you say Y here, the kernel will run on many, but not all, single
1448 processor machines. On a single processor machine, the kernel will
1449 run faster if you say N here.
1451 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1452 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1453 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1455 If you don't know what to do here, say N.
1458 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1459 depends on SMP && !XIP_KERNEL && MMU
1462 SMP kernels contain instructions which fail on non-SMP processors.
1463 Enabling this option allows the kernel to modify itself to make
1464 these instructions safe. Disabling it allows about 1K of space
1467 If you don't know what to do here, say Y.
1469 config ARM_CPU_TOPOLOGY
1470 bool "Support cpu topology definition"
1471 depends on SMP && CPU_V7
1474 Support ARM cpu topology definition. The MPIDR register defines
1475 affinity between processors which is then used to describe the cpu
1476 topology of an ARM System.
1479 bool "Multi-core scheduler support"
1480 depends on ARM_CPU_TOPOLOGY
1482 Multi-core scheduler support improves the CPU scheduler's decision
1483 making when dealing with multi-core CPU chips at a cost of slightly
1484 increased overhead in some places. If unsure say N here.
1487 bool "SMT scheduler support"
1488 depends on ARM_CPU_TOPOLOGY
1490 Improves the CPU scheduler's decision making when dealing with
1491 MultiThreading at a cost of slightly increased overhead in some
1492 places. If unsure say N here.
1497 This option enables support for the ARM system coherency unit
1499 config HAVE_ARM_ARCH_TIMER
1500 bool "Architected timer support"
1502 select ARM_ARCH_TIMER
1504 This option enables support for the ARM architected timer
1509 select CLKSRC_OF if OF
1511 This options enables support for the ARM timer and watchdog unit
1514 bool "Multi-Cluster Power Management"
1515 depends on CPU_V7 && SMP
1517 This option provides the common power management infrastructure
1518 for (multi-)cluster based systems, such as big.LITTLE based
1522 bool "big.LITTLE support (Experimental)"
1523 depends on CPU_V7 && SMP
1526 This option enables support selections for the big.LITTLE
1527 system architecture.
1530 bool "big.LITTLE switcher support"
1531 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1533 select ARM_CPU_SUSPEND
1535 The big.LITTLE "switcher" provides the core functionality to
1536 transparently handle transition between a cluster of A15's
1537 and a cluster of A7's in a big.LITTLE system.
1539 config BL_SWITCHER_DUMMY_IF
1540 tristate "Simple big.LITTLE switcher user interface"
1541 depends on BL_SWITCHER && DEBUG_KERNEL
1543 This is a simple and dummy char dev interface to control
1544 the big.LITTLE switcher core code. It is meant for
1545 debugging purposes only.
1548 prompt "Memory split"
1551 Select the desired split between kernel and user memory.
1553 If you are not absolutely sure what you are doing, leave this
1557 bool "3G/1G user/kernel split"
1559 bool "2G/2G user/kernel split"
1561 bool "1G/3G user/kernel split"
1566 default 0x40000000 if VMSPLIT_1G
1567 default 0x80000000 if VMSPLIT_2G
1571 int "Maximum number of CPUs (2-32)"
1577 bool "Support for hot-pluggable CPUs"
1580 Say Y here to experiment with turning CPUs off and on. CPUs
1581 can be controlled through /sys/devices/system/cpu.
1584 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1587 Say Y here if you want Linux to communicate with system firmware
1588 implementing the PSCI specification for CPU-centric power
1589 management operations described in ARM document number ARM DEN
1590 0022A ("Power State Coordination Interface System Software on
1593 # The GPIO number here must be sorted by descending number. In case of
1594 # a multiplatform kernel, we just want the highest value required by the
1595 # selected platforms.
1598 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1599 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1600 default 392 if ARCH_U8500
1601 default 352 if ARCH_VT8500
1602 default 288 if ARCH_SUNXI
1603 default 264 if MACH_H4700
1606 Maximum number of GPIOs in the system.
1608 If unsure, leave the default value.
1610 source kernel/Kconfig.preempt
1614 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1615 ARCH_S5PV210 || ARCH_EXYNOS4
1616 default AT91_TIMER_HZ if ARCH_AT91
1617 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1621 depends on HZ_FIXED = 0
1622 prompt "Timer frequency"
1646 default HZ_FIXED if HZ_FIXED != 0
1647 default 100 if HZ_100
1648 default 200 if HZ_200
1649 default 250 if HZ_250
1650 default 300 if HZ_300
1651 default 500 if HZ_500
1655 def_bool HIGH_RES_TIMERS
1658 def_bool HIGH_RES_TIMERS
1660 config THUMB2_KERNEL
1661 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1662 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1663 default y if CPU_THUMBONLY
1665 select ARM_ASM_UNIFIED
1668 By enabling this option, the kernel will be compiled in
1669 Thumb-2 mode. A compiler/assembler that understand the unified
1670 ARM-Thumb syntax is needed.
1674 config THUMB2_AVOID_R_ARM_THM_JUMP11
1675 bool "Work around buggy Thumb-2 short branch relocations in gas"
1676 depends on THUMB2_KERNEL && MODULES
1679 Various binutils versions can resolve Thumb-2 branches to
1680 locally-defined, preemptible global symbols as short-range "b.n"
1681 branch instructions.
1683 This is a problem, because there's no guarantee the final
1684 destination of the symbol, or any candidate locations for a
1685 trampoline, are within range of the branch. For this reason, the
1686 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1687 relocation in modules at all, and it makes little sense to add
1690 The symptom is that the kernel fails with an "unsupported
1691 relocation" error when loading some modules.
1693 Until fixed tools are available, passing
1694 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1695 code which hits this problem, at the cost of a bit of extra runtime
1696 stack usage in some cases.
1698 The problem is described in more detail at:
1699 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1701 Only Thumb-2 kernels are affected.
1703 Unless you are sure your tools don't have this problem, say Y.
1705 config ARM_ASM_UNIFIED
1709 bool "Use the ARM EABI to compile the kernel"
1711 This option allows for the kernel to be compiled using the latest
1712 ARM ABI (aka EABI). This is only useful if you are using a user
1713 space environment that is also compiled with EABI.
1715 Since there are major incompatibilities between the legacy ABI and
1716 EABI, especially with regard to structure member alignment, this
1717 option also changes the kernel syscall calling convention to
1718 disambiguate both ABIs and allow for backward compatibility support
1719 (selected with CONFIG_OABI_COMPAT).
1721 To use this you need GCC version 4.0.0 or later.
1724 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1725 depends on AEABI && !THUMB2_KERNEL
1728 This option preserves the old syscall interface along with the
1729 new (ARM EABI) one. It also provides a compatibility layer to
1730 intercept syscalls that have structure arguments which layout
1731 in memory differs between the legacy ABI and the new ARM EABI
1732 (only for non "thumb" binaries). This option adds a tiny
1733 overhead to all syscalls and produces a slightly larger kernel.
1734 If you know you'll be using only pure EABI user space then you
1735 can say N here. If this option is not selected and you attempt
1736 to execute a legacy ABI binary then the result will be
1737 UNPREDICTABLE (in fact it can be predicted that it won't work
1738 at all). If in doubt say Y.
1740 config ARCH_HAS_HOLES_MEMORYMODEL
1743 config ARCH_SPARSEMEM_ENABLE
1746 config ARCH_SPARSEMEM_DEFAULT
1747 def_bool ARCH_SPARSEMEM_ENABLE
1749 config ARCH_SELECT_MEMORY_MODEL
1750 def_bool ARCH_SPARSEMEM_ENABLE
1752 config HAVE_ARCH_PFN_VALID
1753 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1756 bool "High Memory Support"
1759 The address space of ARM processors is only 4 Gigabytes large
1760 and it has to accommodate user address space, kernel address
1761 space as well as some memory mapped IO. That means that, if you
1762 have a large amount of physical memory and/or IO, not all of the
1763 memory can be "permanently mapped" by the kernel. The physical
1764 memory that is not permanently mapped is called "high memory".
1766 Depending on the selected kernel/user memory split, minimum
1767 vmalloc space and actual amount of RAM, you may not need this
1768 option which should result in a slightly faster kernel.
1773 bool "Allocate 2nd-level pagetables from highmem"
1776 config HW_PERF_EVENTS
1777 bool "Enable hardware performance counter support for perf events"
1778 depends on PERF_EVENTS
1781 Enable hardware performance counter support for perf events. If
1782 disabled, perf events will use software events only.
1784 config SYS_SUPPORTS_HUGETLBFS
1788 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1792 config ARCH_WANT_GENERAL_HUGETLB
1797 config FORCE_MAX_ZONEORDER
1798 int "Maximum zone order" if ARCH_SHMOBILE
1799 range 11 64 if ARCH_SHMOBILE
1800 default "12" if SOC_AM33XX
1801 default "9" if SA1111
1804 The kernel memory allocator divides physically contiguous memory
1805 blocks into "zones", where each zone is a power of two number of
1806 pages. This option selects the largest power of two that the kernel
1807 keeps in the memory allocator. If you need to allocate very large
1808 blocks of physically contiguous memory, then you may need to
1809 increase this value.
1811 This config option is actually maximum order plus one. For example,
1812 a value of 11 means that the largest free memory block is 2^10 pages.
1814 config ALIGNMENT_TRAP
1816 depends on CPU_CP15_MMU
1817 default y if !ARCH_EBSA110
1818 select HAVE_PROC_CPU if PROC_FS
1820 ARM processors cannot fetch/store information which is not
1821 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1822 address divisible by 4. On 32-bit ARM processors, these non-aligned
1823 fetch/store instructions will be emulated in software if you say
1824 here, which has a severe performance impact. This is necessary for
1825 correct operation of some network protocols. With an IP-only
1826 configuration it is safe to say N, otherwise say Y.
1828 config UACCESS_WITH_MEMCPY
1829 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1831 default y if CPU_FEROCEON
1833 Implement faster copy_to_user and clear_user methods for CPU
1834 cores where a 8-word STM instruction give significantly higher
1835 memory write throughput than a sequence of individual 32bit stores.
1837 A possible side effect is a slight increase in scheduling latency
1838 between threads sharing the same address space if they invoke
1839 such copy operations with large buffers.
1841 However, if the CPU data cache is using a write-allocate mode,
1842 this option is unlikely to provide any performance gain.
1846 prompt "Enable seccomp to safely compute untrusted bytecode"
1848 This kernel feature is useful for number crunching applications
1849 that may need to compute untrusted bytecode during their
1850 execution. By using pipes or other transports made available to
1851 the process as file descriptors supporting the read/write
1852 syscalls, it's possible to isolate those applications in
1853 their own address space using seccomp. Once seccomp is
1854 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1855 and the task is only allowed to execute a few safe syscalls
1856 defined by each seccomp mode.
1858 config CC_STACKPROTECTOR
1859 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1861 This option turns on the -fstack-protector GCC feature. This
1862 feature puts, at the beginning of functions, a canary value on
1863 the stack just before the return address, and validates
1864 the value just before actually returning. Stack based buffer
1865 overflows (that need to overwrite this return address) now also
1866 overwrite the canary, which gets detected and the attack is then
1867 neutralized via a kernel panic.
1868 This feature requires gcc version 4.2 or above.
1875 bool "Xen guest support on ARM (EXPERIMENTAL)"
1876 depends on ARM && AEABI && OF
1877 depends on CPU_V7 && !CPU_V6
1878 depends on !GENERIC_ATOMIC64
1881 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1888 bool "Flattened Device Tree support"
1891 select OF_EARLY_FLATTREE
1893 Include support for flattened device tree machine descriptions.
1896 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1899 This is the traditional way of passing data to the kernel at boot
1900 time. If you are solely relying on the flattened device tree (or
1901 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1902 to remove ATAGS support from your kernel binary. If unsure,
1905 config DEPRECATED_PARAM_STRUCT
1906 bool "Provide old way to pass kernel parameters"
1909 This was deprecated in 2001 and announced to live on for 5 years.
1910 Some old boot loaders still use this way.
1912 # Compressed boot loader in ROM. Yes, we really want to ask about
1913 # TEXT and BSS so we preserve their values in the config files.
1914 config ZBOOT_ROM_TEXT
1915 hex "Compressed ROM boot loader base address"
1918 The physical address at which the ROM-able zImage is to be
1919 placed in the target. Platforms which normally make use of
1920 ROM-able zImage formats normally set this to a suitable
1921 value in their defconfig file.
1923 If ZBOOT_ROM is not enabled, this has no effect.
1925 config ZBOOT_ROM_BSS
1926 hex "Compressed ROM boot loader BSS address"
1929 The base address of an area of read/write memory in the target
1930 for the ROM-able zImage which must be available while the
1931 decompressor is running. It must be large enough to hold the
1932 entire decompressed kernel plus an additional 128 KiB.
1933 Platforms which normally make use of ROM-able zImage formats
1934 normally set this to a suitable value in their defconfig file.
1936 If ZBOOT_ROM is not enabled, this has no effect.
1939 bool "Compressed boot loader in ROM/flash"
1940 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1942 Say Y here if you intend to execute your compressed kernel image
1943 (zImage) directly from ROM or flash. If unsure, say N.
1946 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1947 depends on ZBOOT_ROM && ARCH_SH7372
1948 default ZBOOT_ROM_NONE
1950 Include experimental SD/MMC loading code in the ROM-able zImage.
1951 With this enabled it is possible to write the ROM-able zImage
1952 kernel image to an MMC or SD card and boot the kernel straight
1953 from the reset vector. At reset the processor Mask ROM will load
1954 the first part of the ROM-able zImage which in turn loads the
1955 rest the kernel image to RAM.
1957 config ZBOOT_ROM_NONE
1958 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1960 Do not load image from SD or MMC
1962 config ZBOOT_ROM_MMCIF
1963 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1965 Load image from MMCIF hardware block.
1967 config ZBOOT_ROM_SH_MOBILE_SDHI
1968 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1970 Load image from SDHI hardware block
1974 config ARM_APPENDED_DTB
1975 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1976 depends on OF && !ZBOOT_ROM
1978 With this option, the boot code will look for a device tree binary
1979 (DTB) appended to zImage
1980 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1982 This is meant as a backward compatibility convenience for those
1983 systems with a bootloader that can't be upgraded to accommodate
1984 the documented boot protocol using a device tree.
1986 Beware that there is very little in terms of protection against
1987 this option being confused by leftover garbage in memory that might
1988 look like a DTB header after a reboot if no actual DTB is appended
1989 to zImage. Do not leave this option active in a production kernel
1990 if you don't intend to always append a DTB. Proper passing of the
1991 location into r2 of a bootloader provided DTB is always preferable
1994 config ARM_ATAG_DTB_COMPAT
1995 bool "Supplement the appended DTB with traditional ATAG information"
1996 depends on ARM_APPENDED_DTB
1998 Some old bootloaders can't be updated to a DTB capable one, yet
1999 they provide ATAGs with memory configuration, the ramdisk address,
2000 the kernel cmdline string, etc. Such information is dynamically
2001 provided by the bootloader and can't always be stored in a static
2002 DTB. To allow a device tree enabled kernel to be used with such
2003 bootloaders, this option allows zImage to extract the information
2004 from the ATAG list and store it at run time into the appended DTB.
2007 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2008 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2010 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2011 bool "Use bootloader kernel arguments if available"
2013 Uses the command-line options passed by the boot loader instead of
2014 the device tree bootargs property. If the boot loader doesn't provide
2015 any, the device tree bootargs property will be used.
2017 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2018 bool "Extend with bootloader kernel arguments"
2020 The command-line arguments provided by the boot loader will be
2021 appended to the the device tree bootargs property.
2026 string "Default kernel command string"
2029 On some architectures (EBSA110 and CATS), there is currently no way
2030 for the boot loader to pass arguments to the kernel. For these
2031 architectures, you should supply some command-line options at build
2032 time by entering them here. As a minimum, you should specify the
2033 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2036 prompt "Kernel command line type" if CMDLINE != ""
2037 default CMDLINE_FROM_BOOTLOADER
2040 config CMDLINE_FROM_BOOTLOADER
2041 bool "Use bootloader kernel arguments if available"
2043 Uses the command-line options passed by the boot loader. If
2044 the boot loader doesn't provide any, the default kernel command
2045 string provided in CMDLINE will be used.
2047 config CMDLINE_EXTEND
2048 bool "Extend bootloader kernel arguments"
2050 The command-line arguments provided by the boot loader will be
2051 appended to the default kernel command string.
2053 config CMDLINE_FORCE
2054 bool "Always use the default kernel command string"
2056 Always use the default kernel command string, even if the boot
2057 loader passes other arguments to the kernel.
2058 This is useful if you cannot or don't want to change the
2059 command-line options your boot loader passes to the kernel.
2063 bool "Kernel Execute-In-Place from ROM"
2064 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2066 Execute-In-Place allows the kernel to run from non-volatile storage
2067 directly addressable by the CPU, such as NOR flash. This saves RAM
2068 space since the text section of the kernel is not loaded from flash
2069 to RAM. Read-write sections, such as the data section and stack,
2070 are still copied to RAM. The XIP kernel is not compressed since
2071 it has to run directly from flash, so it will take more space to
2072 store it. The flash address used to link the kernel object files,
2073 and for storing it, is configuration dependent. Therefore, if you
2074 say Y here, you must know the proper physical address where to
2075 store the kernel image depending on your own flash memory usage.
2077 Also note that the make target becomes "make xipImage" rather than
2078 "make zImage" or "make Image". The final kernel binary to put in
2079 ROM memory will be arch/arm/boot/xipImage.
2083 config XIP_PHYS_ADDR
2084 hex "XIP Kernel Physical Location"
2085 depends on XIP_KERNEL
2086 default "0x00080000"
2088 This is the physical address in your flash memory the kernel will
2089 be linked for and stored to. This address is dependent on your
2093 bool "Kexec system call (EXPERIMENTAL)"
2094 depends on (!SMP || PM_SLEEP_SMP)
2096 kexec is a system call that implements the ability to shutdown your
2097 current kernel, and to start another kernel. It is like a reboot
2098 but it is independent of the system firmware. And like a reboot
2099 you can start any kernel with it, not just Linux.
2101 It is an ongoing process to be certain the hardware in a machine
2102 is properly shutdown, so do not be surprised if this code does not
2103 initially work for you.
2106 bool "Export atags in procfs"
2107 depends on ATAGS && KEXEC
2110 Should the atags used to boot the kernel be exported in an "atags"
2111 file in procfs. Useful with kexec.
2114 bool "Build kdump crash kernel (EXPERIMENTAL)"
2116 Generate crash dump after being started by kexec. This should
2117 be normally only set in special crash dump kernels which are
2118 loaded in the main kernel with kexec-tools into a specially
2119 reserved region and then later executed after a crash by
2120 kdump/kexec. The crash dump kernel must be compiled to a
2121 memory address not used by the main kernel
2123 For more details see Documentation/kdump/kdump.txt
2125 config AUTO_ZRELADDR
2126 bool "Auto calculation of the decompressed kernel image address"
2127 depends on !ZBOOT_ROM
2129 ZRELADDR is the physical address where the decompressed kernel
2130 image will be placed. If AUTO_ZRELADDR is selected, the address
2131 will be determined at run-time by masking the current IP with
2132 0xf8000000. This assumes the zImage being placed in the first 128MB
2133 from start of memory.
2137 menu "CPU Power Management"
2140 source "drivers/cpufreq/Kconfig"
2143 source "drivers/cpuidle/Kconfig"
2147 menu "Floating point emulation"
2149 comment "At least one emulation must be selected"
2152 bool "NWFPE math emulation"
2153 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2155 Say Y to include the NWFPE floating point emulator in the kernel.
2156 This is necessary to run most binaries. Linux does not currently
2157 support floating point hardware so you need to say Y here even if
2158 your machine has an FPA or floating point co-processor podule.
2160 You may say N here if you are going to load the Acorn FPEmulator
2161 early in the bootup.
2164 bool "Support extended precision"
2165 depends on FPE_NWFPE
2167 Say Y to include 80-bit support in the kernel floating-point
2168 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2169 Note that gcc does not generate 80-bit operations by default,
2170 so in most cases this option only enlarges the size of the
2171 floating point emulator without any good reason.
2173 You almost surely want to say N here.
2176 bool "FastFPE math emulation (EXPERIMENTAL)"
2177 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2179 Say Y here to include the FAST floating point emulator in the kernel.
2180 This is an experimental much faster emulator which now also has full
2181 precision for the mantissa. It does not support any exceptions.
2182 It is very simple, and approximately 3-6 times faster than NWFPE.
2184 It should be sufficient for most programs. It may be not suitable
2185 for scientific calculations, but you have to check this for yourself.
2186 If you do not feel you need a faster FP emulation you should better
2190 bool "VFP-format floating point maths"
2191 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2193 Say Y to include VFP support code in the kernel. This is needed
2194 if your hardware includes a VFP unit.
2196 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2197 release notes and additional status information.
2199 Say N if your target does not have VFP hardware.
2207 bool "Advanced SIMD (NEON) Extension support"
2208 depends on VFPv3 && CPU_V7
2210 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2213 config KERNEL_MODE_NEON
2214 bool "Support for NEON in kernel mode"
2215 depends on NEON && AEABI
2217 Say Y to include support for NEON in kernel mode.
2221 menu "Userspace binary formats"
2223 source "fs/Kconfig.binfmt"
2226 tristate "RISC OS personality"
2229 Say Y here to include the kernel code necessary if you want to run
2230 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2231 experimental; if this sounds frightening, say N and sleep in peace.
2232 You can also say M here to compile this support as a module (which
2233 will be called arthur).
2237 menu "Power management options"
2239 source "kernel/power/Kconfig"
2241 config ARCH_SUSPEND_POSSIBLE
2242 depends on !ARCH_S5PC100
2243 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2244 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2247 config ARM_CPU_SUSPEND
2252 source "net/Kconfig"
2254 source "drivers/Kconfig"
2258 source "arch/arm/Kconfig.debug"
2260 source "security/Kconfig"
2262 source "crypto/Kconfig"
2264 source "lib/Kconfig"
2266 source "arch/arm/kvm/Kconfig"