4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_WANT_IPC_PARSE_VERSION
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CLONE_BACKWARDS
13 select CPU_PM if (SUSPEND || CPU_IDLE)
14 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
15 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
16 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
17 select GENERIC_IDLE_POLL_SETUP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_PCI_IOMAP
21 select GENERIC_SCHED_CLOCK
22 select GENERIC_SMP_IDLE_THREAD
23 select GENERIC_STRNCPY_FROM_USER
24 select GENERIC_STRNLEN_USER
25 select HARDIRQS_SW_RESEND
26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
28 select HAVE_ARCH_SECCOMP_FILTER
29 select HAVE_ARCH_TRACEHOOK
31 select HAVE_CONTEXT_TRACKING
32 select HAVE_C_RECORDMCOUNT
33 select HAVE_DEBUG_KMEMLEAK
34 select HAVE_DMA_API_DEBUG
36 select HAVE_DMA_CONTIGUOUS if MMU
37 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
38 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
39 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
40 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
41 select HAVE_GENERIC_DMA_COHERENT
42 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
43 select HAVE_IDE if PCI || ISA || PCMCIA
44 select HAVE_IRQ_TIME_ACCOUNTING
45 select HAVE_KERNEL_GZIP
46 select HAVE_KERNEL_LZ4
47 select HAVE_KERNEL_LZMA
48 select HAVE_KERNEL_LZO
50 select HAVE_KPROBES if !XIP_KERNEL
51 select HAVE_KRETPROBES if (HAVE_KPROBES)
53 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
54 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
55 select HAVE_PERF_EVENTS
57 select HAVE_PERF_USER_STACK_DUMP
58 select HAVE_REGS_AND_STACK_ACCESS_API
59 select HAVE_SYSCALL_TRACEPOINTS
61 select HAVE_VIRT_CPU_ACCOUNTING_GEN
62 select IRQ_FORCED_THREADING
64 select MODULES_USE_ELF_REL
66 select OLD_SIGSUSPEND3
67 select PERF_USE_VMALLOC
69 select SYS_SUPPORTS_APM_EMULATION
70 # Above selects are sorted alphabetically; please add new ones
71 # according to that. Thanks.
73 The ARM series is a line of low-power-consumption RISC chip designs
74 licensed by ARM Ltd and targeted at embedded applications and
75 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
76 manufactured, but legacy ARM-based PC hardware remains popular in
77 Europe. There is an ARM Linux project with a web page at
78 <http://www.arm.linux.org.uk/>.
80 config ARM_HAS_SG_CHAIN
83 config NEED_SG_DMA_LENGTH
86 config ARM_DMA_USE_IOMMU
88 select ARM_HAS_SG_CHAIN
89 select NEED_SG_DMA_LENGTH
93 config ARM_DMA_IOMMU_ALIGNMENT
94 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
98 DMA mapping framework by default aligns all buffers to the smallest
99 PAGE_SIZE order which is greater than or equal to the requested buffer
100 size. This works well for buffers up to a few hundreds kilobytes, but
101 for larger buffers it just a waste of address space. Drivers which has
102 relatively small addressing window (like 64Mib) might run out of
103 virtual space with just a few allocations.
105 With this parameter you can specify the maximum PAGE_SIZE order for
106 DMA IOMMU buffers. Larger buffers will be aligned only to this
107 specified order. The order is expressed as a power of two multiplied
115 config MIGHT_HAVE_PCI
118 config SYS_SUPPORTS_APM_EMULATION
123 select GENERIC_ALLOCATOR
134 The Extended Industry Standard Architecture (EISA) bus was
135 developed as an open alternative to the IBM MicroChannel bus.
137 The EISA bus provided some of the features of the IBM MicroChannel
138 bus while maintaining backward compatibility with cards made for
139 the older ISA bus. The EISA bus saw limited use between 1988 and
140 1995 when it was made obsolete by the PCI bus.
142 Say Y here if you are building a kernel for an EISA-based machine.
149 config STACKTRACE_SUPPORT
153 config HAVE_LATENCYTOP_SUPPORT
158 config LOCKDEP_SUPPORT
162 config TRACE_IRQFLAGS_SUPPORT
166 config RWSEM_GENERIC_SPINLOCK
170 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_CPUFREQ
182 Internal node to signify that the ARCH has CPUFREQ support
183 and that the relevant menu configurations are displayed for
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_HAS_DMA_SET_COHERENT_MASK
209 config GENERIC_ISA_DMA
215 config NEED_RET_TO_USER
223 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
224 default DRAM_BASE if REMAP_VECTORS_TO_RAM
227 The base address of exception vectors. This must be two pages
230 config ARM_PATCH_PHYS_VIRT
231 bool "Patch physical to virtual translations at runtime" if EMBEDDED
233 depends on !XIP_KERNEL && MMU
234 depends on !ARCH_REALVIEW || !SPARSEMEM
236 Patch phys-to-virt and virt-to-phys translation functions at
237 boot and module load time according to the position of the
238 kernel in system memory.
240 This can only be used with non-XIP MMU kernels where the base
241 of physical memory is at a 16MB boundary.
243 Only disable this option if you know that you do not require
244 this feature (eg, building a kernel for a single machine) and
245 you need to shrink the kernel to the minimal size.
247 config NEED_MACH_GPIO_H
250 Select this when mach/gpio.h is required to provide special
251 definitions for this platform. The need for mach/gpio.h should
252 be avoided when possible.
254 config NEED_MACH_IO_H
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
261 config NEED_MACH_MEMORY_H
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
271 default DRAM_BASE if !MMU
273 Please provide the physical address corresponding to the
274 location of main memory in your system.
280 source "init/Kconfig"
282 source "kernel/Kconfig.freezer"
287 bool "MMU-based Paged Memory Management Support"
290 Select if you want MMU-based virtualised addressing space
291 support by paged memory management. If unsure, say 'Y'.
294 # The "ARM system type" choice list is ordered alphabetically by option
295 # text. Please add new entries in the option alphabetic order.
298 prompt "ARM system type"
299 default ARCH_VERSATILE if !MMU
300 default ARCH_MULTIPLATFORM if MMU
302 config ARCH_MULTIPLATFORM
303 bool "Allow multiple platforms to be selected"
305 select ARM_PATCH_PHYS_VIRT
308 select MULTI_IRQ_HANDLER
312 config ARCH_INTEGRATOR
313 bool "ARM Ltd. Integrator family"
314 select ARCH_HAS_CPUFREQ
317 select COMMON_CLK_VERSATILE
318 select GENERIC_CLOCKEVENTS
321 select MULTI_IRQ_HANDLER
322 select NEED_MACH_MEMORY_H
323 select PLAT_VERSATILE
325 select VERSATILE_FPGA_IRQ
327 Support for ARM's Integrator platform.
330 bool "ARM Ltd. RealView family"
331 select ARCH_WANT_OPTIONAL_GPIOLIB
333 select ARM_TIMER_SP804
335 select COMMON_CLK_VERSATILE
336 select GENERIC_CLOCKEVENTS
337 select GPIO_PL061 if GPIOLIB
339 select NEED_MACH_MEMORY_H
340 select PLAT_VERSATILE
341 select PLAT_VERSATILE_CLCD
343 This enables support for ARM Ltd RealView boards.
345 config ARCH_VERSATILE
346 bool "ARM Ltd. Versatile family"
347 select ARCH_WANT_OPTIONAL_GPIOLIB
349 select ARM_TIMER_SP804
352 select GENERIC_CLOCKEVENTS
353 select HAVE_MACH_CLKDEV
355 select PLAT_VERSATILE
356 select PLAT_VERSATILE_CLCD
357 select PLAT_VERSATILE_CLOCK
358 select VERSATILE_FPGA_IRQ
360 This enables support for ARM Ltd Versatile board.
364 select ARCH_REQUIRE_GPIOLIB
368 select NEED_MACH_GPIO_H
369 select NEED_MACH_IO_H if PCCARD
371 select PINCTRL_AT91 if USE_OF
373 This enables support for systems based on Atmel
374 AT91RM9200 and AT91SAM9* processors.
377 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
378 select ARCH_REQUIRE_GPIOLIB
384 select GENERIC_CLOCKEVENTS
386 select MULTI_IRQ_HANDLER
389 Support for Cirrus Logic 711x/721x/731x based boards.
392 bool "Cortina Systems Gemini"
393 select ARCH_REQUIRE_GPIOLIB
394 select ARCH_USES_GETTIMEOFFSET
397 Support for the Cortina Systems Gemini family SoCs
401 select ARCH_USES_GETTIMEOFFSET
404 select NEED_MACH_IO_H
405 select NEED_MACH_MEMORY_H
408 This is an evaluation board for the StrongARM processor available
409 from Digital. It has limited hardware on-board, including an
410 Ethernet interface, two PCMCIA sockets, two serial ports and a
415 select ARCH_HAS_HOLES_MEMORYMODEL
416 select ARCH_REQUIRE_GPIOLIB
417 select ARCH_USES_GETTIMEOFFSET
422 select NEED_MACH_MEMORY_H
424 This enables support for the Cirrus EP93xx series of CPUs.
426 config ARCH_FOOTBRIDGE
430 select GENERIC_CLOCKEVENTS
432 select NEED_MACH_IO_H if !MMU
433 select NEED_MACH_MEMORY_H
435 Support for systems based on the DC21285 companion chip
436 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
439 bool "Hilscher NetX based"
443 select GENERIC_CLOCKEVENTS
445 This enables support for systems based on the Hilscher NetX Soc
451 select NEED_MACH_MEMORY_H
452 select NEED_RET_TO_USER
457 Support for Intel's IOP13XX (XScale) family of processors.
462 select ARCH_REQUIRE_GPIOLIB
465 select NEED_RET_TO_USER
469 Support for Intel's 80219 and IOP32X (XScale) family of
475 select ARCH_REQUIRE_GPIOLIB
478 select NEED_RET_TO_USER
482 Support for Intel's IOP33X (XScale) family of processors.
487 select ARCH_HAS_DMA_SET_COHERENT_MASK
488 select ARCH_REQUIRE_GPIOLIB
491 select DMABOUNCE if PCI
492 select GENERIC_CLOCKEVENTS
493 select MIGHT_HAVE_PCI
494 select NEED_MACH_IO_H
495 select USB_EHCI_BIG_ENDIAN_DESC
496 select USB_EHCI_BIG_ENDIAN_MMIO
498 Support for Intel's IXP4XX (XScale) family of processors.
502 select ARCH_REQUIRE_GPIOLIB
504 select GENERIC_CLOCKEVENTS
505 select MIGHT_HAVE_PCI
509 select PLAT_ORION_LEGACY
510 select USB_ARCH_HAS_EHCI
512 Support for the Marvell Dove SoC 88AP510
515 bool "Marvell Kirkwood"
516 select ARCH_HAS_CPUFREQ
517 select ARCH_REQUIRE_GPIOLIB
519 select GENERIC_CLOCKEVENTS
524 select PINCTRL_KIRKWOOD
525 select PLAT_ORION_LEGACY
527 Support for the following Marvell Kirkwood series SoCs:
528 88F6180, 88F6192 and 88F6281.
531 bool "Marvell MV78xx0"
532 select ARCH_REQUIRE_GPIOLIB
534 select GENERIC_CLOCKEVENTS
537 select PLAT_ORION_LEGACY
539 Support for the following Marvell MV78xx0 series SoCs:
545 select ARCH_REQUIRE_GPIOLIB
547 select GENERIC_CLOCKEVENTS
550 select PLAT_ORION_LEGACY
552 Support for the following Marvell Orion 5x series SoCs:
553 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
554 Orion-2 (5281), Orion-1-90 (6183).
557 bool "Marvell PXA168/910/MMP2"
559 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_ALLOCATOR
562 select GENERIC_CLOCKEVENTS
565 select MULTI_IRQ_HANDLER
570 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
573 bool "Micrel/Kendin KS8695"
574 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
578 select NEED_MACH_MEMORY_H
580 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
581 System-on-Chip devices.
584 bool "Nuvoton W90X900 CPU"
585 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_CLOCKEVENTS
591 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
592 At present, the w90x900 has been renamed nuc900, regarding
593 the ARM series product line, you can login the following
594 link address to know more.
596 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
597 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
601 select ARCH_REQUIRE_GPIOLIB
606 select GENERIC_CLOCKEVENTS
609 select USB_ARCH_HAS_OHCI
612 Support for the NXP LPC32XX family of processors
615 bool "PXA2xx/PXA3xx-based"
617 select ARCH_HAS_CPUFREQ
619 select ARCH_REQUIRE_GPIOLIB
620 select ARM_CPU_SUSPEND if PM
624 select GENERIC_CLOCKEVENTS
627 select MULTI_IRQ_HANDLER
631 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
635 select ARCH_REQUIRE_GPIOLIB
637 select CLKSRC_OF if OF
639 select GENERIC_CLOCKEVENTS
641 Support for Qualcomm MSM/QSD based systems. This runs on the
642 apps processor of the MSM/QSD and depends on a shared memory
643 interface to the modem processor which runs the baseband
644 stack and controls some vital subsystems
645 (clock and power control, etc).
648 bool "Renesas SH-Mobile / R-Mobile"
649 select ARM_PATCH_PHYS_VIRT
651 select GENERIC_CLOCKEVENTS
652 select HAVE_ARM_SCU if SMP
653 select HAVE_ARM_TWD if SMP
655 select HAVE_MACH_CLKDEV
657 select MIGHT_HAVE_CACHE_L2X0
658 select MULTI_IRQ_HANDLER
661 select PM_GENERIC_DOMAINS if PM
664 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
669 select ARCH_MAY_HAVE_PC_FDC
670 select ARCH_SPARSEMEM_ENABLE
671 select ARCH_USES_GETTIMEOFFSET
674 select HAVE_PATA_PLATFORM
676 select NEED_MACH_IO_H
677 select NEED_MACH_MEMORY_H
681 On the Acorn Risc-PC, Linux can support the internal IDE disk and
682 CD-ROM interface, serial and parallel port, and the floppy drive.
686 select ARCH_HAS_CPUFREQ
688 select ARCH_REQUIRE_GPIOLIB
689 select ARCH_SPARSEMEM_ENABLE
694 select GENERIC_CLOCKEVENTS
697 select NEED_MACH_MEMORY_H
700 Support for StrongARM 11x0 based boards.
703 bool "Samsung S3C24XX SoCs"
704 select ARCH_HAS_CPUFREQ
705 select ARCH_REQUIRE_GPIOLIB
707 select CLKSRC_SAMSUNG_PWM
708 select GENERIC_CLOCKEVENTS
711 select HAVE_S3C2410_I2C if I2C
712 select HAVE_S3C2410_WATCHDOG if WATCHDOG
713 select HAVE_S3C_RTC if RTC_CLASS
714 select MULTI_IRQ_HANDLER
715 select NEED_MACH_GPIO_H
716 select NEED_MACH_IO_H
719 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
720 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
721 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
722 Samsung SMDK2410 development board (and derivatives).
725 bool "Samsung S3C64XX"
726 select ARCH_HAS_CPUFREQ
727 select ARCH_REQUIRE_GPIOLIB
730 select CLKSRC_SAMSUNG_PWM
732 select GENERIC_CLOCKEVENTS
735 select HAVE_S3C2410_I2C if I2C
736 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 select NEED_MACH_GPIO_H
742 select S3C_GPIO_TRACK
744 select SAMSUNG_CLKSRC
745 select SAMSUNG_GPIOLIB_4BIT
746 select SAMSUNG_WDT_RESET
747 select USB_ARCH_HAS_OHCI
749 Samsung S3C64XX series based systems
752 bool "Samsung S5P6440 S5P6450"
754 select CLKSRC_SAMSUNG_PWM
756 select GENERIC_CLOCKEVENTS
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C2410_WATCHDOG if WATCHDOG
761 select HAVE_S3C_RTC if RTC_CLASS
762 select NEED_MACH_GPIO_H
764 select SAMSUNG_WDT_RESET
766 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
770 bool "Samsung S5PC100"
771 select ARCH_REQUIRE_GPIOLIB
773 select CLKSRC_SAMSUNG_PWM
775 select GENERIC_CLOCKEVENTS
778 select HAVE_S3C2410_I2C if I2C
779 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 select HAVE_S3C_RTC if RTC_CLASS
781 select NEED_MACH_GPIO_H
783 select SAMSUNG_WDT_RESET
785 Samsung S5PC100 series based systems
788 bool "Samsung S5PV210/S5PC110"
789 select ARCH_HAS_CPUFREQ
790 select ARCH_HAS_HOLES_MEMORYMODEL
791 select ARCH_SPARSEMEM_ENABLE
793 select CLKSRC_SAMSUNG_PWM
795 select GENERIC_CLOCKEVENTS
798 select HAVE_S3C2410_I2C if I2C
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
800 select HAVE_S3C_RTC if RTC_CLASS
801 select NEED_MACH_GPIO_H
802 select NEED_MACH_MEMORY_H
805 Samsung S5PV210/S5PC110 series based systems
808 bool "Samsung EXYNOS"
809 select ARCH_HAS_CPUFREQ
810 select ARCH_HAS_HOLES_MEMORYMODEL
811 select ARCH_REQUIRE_GPIOLIB
812 select ARCH_SPARSEMEM_ENABLE
817 select GENERIC_CLOCKEVENTS
819 select HAVE_S3C2410_I2C if I2C
820 select HAVE_S3C2410_WATCHDOG if WATCHDOG
821 select HAVE_S3C_RTC if RTC_CLASS
822 select NEED_MACH_MEMORY_H
826 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
830 select ARCH_USES_GETTIMEOFFSET
834 select NEED_MACH_MEMORY_H
839 Support for the StrongARM based Digital DNARD machine, also known
840 as "Shark" (<http://www.shark-linux.de/shark.html>).
844 select ARCH_HAS_HOLES_MEMORYMODEL
845 select ARCH_REQUIRE_GPIOLIB
847 select GENERIC_ALLOCATOR
848 select GENERIC_CLOCKEVENTS
849 select GENERIC_IRQ_CHIP
851 select NEED_MACH_GPIO_H
856 Support for TI's DaVinci platform.
861 select ARCH_HAS_CPUFREQ
862 select ARCH_HAS_HOLES_MEMORYMODEL
864 select ARCH_REQUIRE_GPIOLIB
867 select GENERIC_CLOCKEVENTS
868 select GENERIC_IRQ_CHIP
872 select NEED_MACH_IO_H if PCCARD
873 select NEED_MACH_MEMORY_H
875 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
879 menu "Multiple platform selection"
880 depends on ARCH_MULTIPLATFORM
882 comment "CPU Core family selection"
884 config ARCH_MULTI_V4T
885 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
886 depends on !ARCH_MULTI_V6_V7
887 select ARCH_MULTI_V4_V5
888 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
889 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
890 CPU_ARM925T || CPU_ARM940T)
893 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
894 depends on !ARCH_MULTI_V6_V7
895 select ARCH_MULTI_V4_V5
896 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
897 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
898 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
900 config ARCH_MULTI_V4_V5
904 bool "ARMv6 based platforms (ARM11)"
905 select ARCH_MULTI_V6_V7
909 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
911 select ARCH_MULTI_V6_V7
914 config ARCH_MULTI_V6_V7
917 config ARCH_MULTI_CPU_AUTO
918 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
924 # This is sorted alphabetically by mach-* pathname. However, plat-*
925 # Kconfigs may be included either alphabetically (according to the
926 # plat- suffix) or along side the corresponding mach-* source.
928 source "arch/arm/mach-mvebu/Kconfig"
930 source "arch/arm/mach-at91/Kconfig"
932 source "arch/arm/mach-bcm/Kconfig"
934 source "arch/arm/mach-bcm2835/Kconfig"
936 source "arch/arm/mach-clps711x/Kconfig"
938 source "arch/arm/mach-cns3xxx/Kconfig"
940 source "arch/arm/mach-davinci/Kconfig"
942 source "arch/arm/mach-dove/Kconfig"
944 source "arch/arm/mach-ep93xx/Kconfig"
946 source "arch/arm/mach-footbridge/Kconfig"
948 source "arch/arm/mach-gemini/Kconfig"
950 source "arch/arm/mach-highbank/Kconfig"
952 source "arch/arm/mach-integrator/Kconfig"
954 source "arch/arm/mach-iop32x/Kconfig"
956 source "arch/arm/mach-iop33x/Kconfig"
958 source "arch/arm/mach-iop13xx/Kconfig"
960 source "arch/arm/mach-ixp4xx/Kconfig"
962 source "arch/arm/mach-keystone/Kconfig"
964 source "arch/arm/mach-kirkwood/Kconfig"
966 source "arch/arm/mach-ks8695/Kconfig"
968 source "arch/arm/mach-msm/Kconfig"
970 source "arch/arm/mach-mv78xx0/Kconfig"
972 source "arch/arm/mach-imx/Kconfig"
974 source "arch/arm/mach-mxs/Kconfig"
976 source "arch/arm/mach-netx/Kconfig"
978 source "arch/arm/mach-nomadik/Kconfig"
980 source "arch/arm/mach-nspire/Kconfig"
982 source "arch/arm/plat-omap/Kconfig"
984 source "arch/arm/mach-omap1/Kconfig"
986 source "arch/arm/mach-omap2/Kconfig"
988 source "arch/arm/mach-orion5x/Kconfig"
990 source "arch/arm/mach-picoxcell/Kconfig"
992 source "arch/arm/mach-pxa/Kconfig"
993 source "arch/arm/plat-pxa/Kconfig"
995 source "arch/arm/mach-mmp/Kconfig"
997 source "arch/arm/mach-realview/Kconfig"
999 source "arch/arm/mach-rockchip/Kconfig"
1001 source "arch/arm/mach-sa1100/Kconfig"
1003 source "arch/arm/plat-samsung/Kconfig"
1005 source "arch/arm/mach-socfpga/Kconfig"
1007 source "arch/arm/mach-spear/Kconfig"
1009 source "arch/arm/mach-sti/Kconfig"
1011 source "arch/arm/mach-s3c24xx/Kconfig"
1014 source "arch/arm/mach-s3c64xx/Kconfig"
1017 source "arch/arm/mach-s5p64x0/Kconfig"
1019 source "arch/arm/mach-s5pc100/Kconfig"
1021 source "arch/arm/mach-s5pv210/Kconfig"
1023 source "arch/arm/mach-exynos/Kconfig"
1025 source "arch/arm/mach-shmobile/Kconfig"
1027 source "arch/arm/mach-sunxi/Kconfig"
1029 source "arch/arm/mach-prima2/Kconfig"
1031 source "arch/arm/mach-tegra/Kconfig"
1033 source "arch/arm/mach-u300/Kconfig"
1035 source "arch/arm/mach-ux500/Kconfig"
1037 source "arch/arm/mach-versatile/Kconfig"
1039 source "arch/arm/mach-vexpress/Kconfig"
1040 source "arch/arm/plat-versatile/Kconfig"
1042 source "arch/arm/mach-virt/Kconfig"
1044 source "arch/arm/mach-vt8500/Kconfig"
1046 source "arch/arm/mach-w90x900/Kconfig"
1048 source "arch/arm/mach-zynq/Kconfig"
1050 # Definitions to make life easier
1056 select GENERIC_CLOCKEVENTS
1062 select GENERIC_IRQ_CHIP
1065 config PLAT_ORION_LEGACY
1072 config PLAT_VERSATILE
1075 config ARM_TIMER_SP804
1078 select CLKSRC_OF if OF
1080 source arch/arm/mm/Kconfig
1084 default 16 if ARCH_EP93XX
1088 bool "Enable iWMMXt support" if !CPU_PJ4
1089 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1090 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1092 Enable support for iWMMXt context switching at run time if
1093 running on a CPU that supports it.
1097 depends on CPU_XSCALE
1100 config MULTI_IRQ_HANDLER
1103 Allow each machine to specify it's own IRQ handler at run time.
1106 source "arch/arm/Kconfig-nommu"
1109 config PJ4B_ERRATA_4742
1110 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1111 depends on CPU_PJ4B && MACH_ARMADA_370
1114 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1115 Event (WFE) IDLE states, a specific timing sensitivity exists between
1116 the retiring WFI/WFE instructions and the newly issued subsequent
1117 instructions. This sensitivity can result in a CPU hang scenario.
1119 The software must insert either a Data Synchronization Barrier (DSB)
1120 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1123 config ARM_ERRATA_326103
1124 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1127 Executing a SWP instruction to read-only memory does not set bit 11
1128 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1129 treat the access as a read, preventing a COW from occurring and
1130 causing the faulting task to livelock.
1132 config ARM_ERRATA_411920
1133 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1134 depends on CPU_V6 || CPU_V6K
1136 Invalidation of the Instruction Cache operation can
1137 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1138 It does not affect the MPCore. This option enables the ARM Ltd.
1139 recommended workaround.
1141 config ARM_ERRATA_430973
1142 bool "ARM errata: Stale prediction on replaced interworking branch"
1145 This option enables the workaround for the 430973 Cortex-A8
1146 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1147 interworking branch is replaced with another code sequence at the
1148 same virtual address, whether due to self-modifying code or virtual
1149 to physical address re-mapping, Cortex-A8 does not recover from the
1150 stale interworking branch prediction. This results in Cortex-A8
1151 executing the new code sequence in the incorrect ARM or Thumb state.
1152 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1153 and also flushes the branch target cache at every context switch.
1154 Note that setting specific bits in the ACTLR register may not be
1155 available in non-secure mode.
1157 config ARM_ERRATA_458693
1158 bool "ARM errata: Processor deadlock when a false hazard is created"
1160 depends on !ARCH_MULTIPLATFORM
1162 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1163 erratum. For very specific sequences of memory operations, it is
1164 possible for a hazard condition intended for a cache line to instead
1165 be incorrectly associated with a different cache line. This false
1166 hazard might then cause a processor deadlock. The workaround enables
1167 the L1 caching of the NEON accesses and disables the PLD instruction
1168 in the ACTLR register. Note that setting specific bits in the ACTLR
1169 register may not be available in non-secure mode.
1171 config ARM_ERRATA_460075
1172 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1174 depends on !ARCH_MULTIPLATFORM
1176 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1177 erratum. Any asynchronous access to the L2 cache may encounter a
1178 situation in which recent store transactions to the L2 cache are lost
1179 and overwritten with stale memory contents from external memory. The
1180 workaround disables the write-allocate mode for the L2 cache via the
1181 ACTLR register. Note that setting specific bits in the ACTLR register
1182 may not be available in non-secure mode.
1184 config ARM_ERRATA_742230
1185 bool "ARM errata: DMB operation may be faulty"
1186 depends on CPU_V7 && SMP
1187 depends on !ARCH_MULTIPLATFORM
1189 This option enables the workaround for the 742230 Cortex-A9
1190 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1191 between two write operations may not ensure the correct visibility
1192 ordering of the two writes. This workaround sets a specific bit in
1193 the diagnostic register of the Cortex-A9 which causes the DMB
1194 instruction to behave as a DSB, ensuring the correct behaviour of
1197 config ARM_ERRATA_742231
1198 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1199 depends on CPU_V7 && SMP
1200 depends on !ARCH_MULTIPLATFORM
1202 This option enables the workaround for the 742231 Cortex-A9
1203 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1204 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1205 accessing some data located in the same cache line, may get corrupted
1206 data due to bad handling of the address hazard when the line gets
1207 replaced from one of the CPUs at the same time as another CPU is
1208 accessing it. This workaround sets specific bits in the diagnostic
1209 register of the Cortex-A9 which reduces the linefill issuing
1210 capabilities of the processor.
1212 config PL310_ERRATA_588369
1213 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1214 depends on CACHE_L2X0
1216 The PL310 L2 cache controller implements three types of Clean &
1217 Invalidate maintenance operations: by Physical Address
1218 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1219 They are architecturally defined to behave as the execution of a
1220 clean operation followed immediately by an invalidate operation,
1221 both performing to the same memory location. This functionality
1222 is not correctly implemented in PL310 as clean lines are not
1223 invalidated as a result of these operations.
1225 config ARM_ERRATA_643719
1226 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1227 depends on CPU_V7 && SMP
1229 This option enables the workaround for the 643719 Cortex-A9 (prior to
1230 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1231 register returns zero when it should return one. The workaround
1232 corrects this value, ensuring cache maintenance operations which use
1233 it behave as intended and avoiding data corruption.
1235 config ARM_ERRATA_720789
1236 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1239 This option enables the workaround for the 720789 Cortex-A9 (prior to
1240 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1241 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1242 As a consequence of this erratum, some TLB entries which should be
1243 invalidated are not, resulting in an incoherency in the system page
1244 tables. The workaround changes the TLB flushing routines to invalidate
1245 entries regardless of the ASID.
1247 config PL310_ERRATA_727915
1248 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1249 depends on CACHE_L2X0
1251 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1252 operation (offset 0x7FC). This operation runs in background so that
1253 PL310 can handle normal accesses while it is in progress. Under very
1254 rare circumstances, due to this erratum, write data can be lost when
1255 PL310 treats a cacheable write transaction during a Clean &
1256 Invalidate by Way operation.
1258 config ARM_ERRATA_743622
1259 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1261 depends on !ARCH_MULTIPLATFORM
1263 This option enables the workaround for the 743622 Cortex-A9
1264 (r2p*) erratum. Under very rare conditions, a faulty
1265 optimisation in the Cortex-A9 Store Buffer may lead to data
1266 corruption. This workaround sets a specific bit in the diagnostic
1267 register of the Cortex-A9 which disables the Store Buffer
1268 optimisation, preventing the defect from occurring. This has no
1269 visible impact on the overall performance or power consumption of the
1272 config ARM_ERRATA_751472
1273 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1275 depends on !ARCH_MULTIPLATFORM
1277 This option enables the workaround for the 751472 Cortex-A9 (prior
1278 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1279 completion of a following broadcasted operation if the second
1280 operation is received by a CPU before the ICIALLUIS has completed,
1281 potentially leading to corrupted entries in the cache or TLB.
1283 config PL310_ERRATA_753970
1284 bool "PL310 errata: cache sync operation may be faulty"
1285 depends on CACHE_PL310
1287 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1289 Under some condition the effect of cache sync operation on
1290 the store buffer still remains when the operation completes.
1291 This means that the store buffer is always asked to drain and
1292 this prevents it from merging any further writes. The workaround
1293 is to replace the normal offset of cache sync operation (0x730)
1294 by another offset targeting an unmapped PL310 register 0x740.
1295 This has the same effect as the cache sync operation: store buffer
1296 drain and waiting for all buffers empty.
1298 config ARM_ERRATA_754322
1299 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1302 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1303 r3p*) erratum. A speculative memory access may cause a page table walk
1304 which starts prior to an ASID switch but completes afterwards. This
1305 can populate the micro-TLB with a stale entry which may be hit with
1306 the new ASID. This workaround places two dsb instructions in the mm
1307 switching code so that no page table walks can cross the ASID switch.
1309 config ARM_ERRATA_754327
1310 bool "ARM errata: no automatic Store Buffer drain"
1311 depends on CPU_V7 && SMP
1313 This option enables the workaround for the 754327 Cortex-A9 (prior to
1314 r2p0) erratum. The Store Buffer does not have any automatic draining
1315 mechanism and therefore a livelock may occur if an external agent
1316 continuously polls a memory location waiting to observe an update.
1317 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1318 written polling loops from denying visibility of updates to memory.
1320 config ARM_ERRATA_364296
1321 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1324 This options enables the workaround for the 364296 ARM1136
1325 r0p2 erratum (possible cache data corruption with
1326 hit-under-miss enabled). It sets the undocumented bit 31 in
1327 the auxiliary control register and the FI bit in the control
1328 register, thus disabling hit-under-miss without putting the
1329 processor into full low interrupt latency mode. ARM11MPCore
1332 config ARM_ERRATA_764369
1333 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1334 depends on CPU_V7 && SMP
1336 This option enables the workaround for erratum 764369
1337 affecting Cortex-A9 MPCore with two or more processors (all
1338 current revisions). Under certain timing circumstances, a data
1339 cache line maintenance operation by MVA targeting an Inner
1340 Shareable memory region may fail to proceed up to either the
1341 Point of Coherency or to the Point of Unification of the
1342 system. This workaround adds a DSB instruction before the
1343 relevant cache maintenance functions and sets a specific bit
1344 in the diagnostic control register of the SCU.
1346 config PL310_ERRATA_769419
1347 bool "PL310 errata: no automatic Store Buffer drain"
1348 depends on CACHE_L2X0
1350 On revisions of the PL310 prior to r3p2, the Store Buffer does
1351 not automatically drain. This can cause normal, non-cacheable
1352 writes to be retained when the memory system is idle, leading
1353 to suboptimal I/O performance for drivers using coherent DMA.
1354 This option adds a write barrier to the cpu_idle loop so that,
1355 on systems with an outer cache, the store buffer is drained
1358 config ARM_ERRATA_775420
1359 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1362 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1363 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1364 operation aborts with MMU exception, it might cause the processor
1365 to deadlock. This workaround puts DSB before executing ISB if
1366 an abort may occur on cache maintenance.
1368 config ARM_ERRATA_798181
1369 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1370 depends on CPU_V7 && SMP
1372 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1373 adequately shooting down all use of the old entries. This
1374 option enables the Linux kernel workaround for this erratum
1375 which sends an IPI to the CPUs that are running the same ASID
1376 as the one being invalidated.
1378 config ARM_ERRATA_773022
1379 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1382 This option enables the workaround for the 773022 Cortex-A15
1383 (up to r0p4) erratum. In certain rare sequences of code, the
1384 loop buffer may deliver incorrect instructions. This
1385 workaround disables the loop buffer to avoid the erratum.
1389 source "arch/arm/common/Kconfig"
1399 Find out whether you have ISA slots on your motherboard. ISA is the
1400 name of a bus system, i.e. the way the CPU talks to the other stuff
1401 inside your box. Other bus systems are PCI, EISA, MicroChannel
1402 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1403 newer boards don't support it. If you have ISA, say Y, otherwise N.
1405 # Select ISA DMA controller support
1410 # Select ISA DMA interface
1415 bool "PCI support" if MIGHT_HAVE_PCI
1417 Find out whether you have a PCI motherboard. PCI is the name of a
1418 bus system, i.e. the way the CPU talks to the other stuff inside
1419 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1420 VESA. If you have PCI, say Y, otherwise N.
1426 config PCI_NANOENGINE
1427 bool "BSE nanoEngine PCI support"
1428 depends on SA1100_NANOENGINE
1430 Enable PCI on the BSE nanoEngine board.
1435 # Select the host bridge type
1436 config PCI_HOST_VIA82C505
1438 depends on PCI && ARCH_SHARK
1441 config PCI_HOST_ITE8152
1443 depends on PCI && MACH_ARMCORE
1447 source "drivers/pci/Kconfig"
1448 source "drivers/pci/pcie/Kconfig"
1450 source "drivers/pcmcia/Kconfig"
1454 menu "Kernel Features"
1459 This option should be selected by machines which have an SMP-
1462 The only effect of this option is to make the SMP-related
1463 options available to the user for configuration.
1466 bool "Symmetric Multi-Processing"
1467 depends on CPU_V6K || CPU_V7
1468 depends on GENERIC_CLOCKEVENTS
1470 depends on MMU || ARM_MPU
1471 select USE_GENERIC_SMP_HELPERS
1473 This enables support for systems with more than one CPU. If you have
1474 a system with only one CPU, like most personal computers, say N. If
1475 you have a system with more than one CPU, say Y.
1477 If you say N here, the kernel will run on single and multiprocessor
1478 machines, but will use only one CPU of a multiprocessor machine. If
1479 you say Y here, the kernel will run on many, but not all, single
1480 processor machines. On a single processor machine, the kernel will
1481 run faster if you say N here.
1483 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1484 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1485 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1487 If you don't know what to do here, say N.
1490 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1491 depends on SMP && !XIP_KERNEL && MMU
1494 SMP kernels contain instructions which fail on non-SMP processors.
1495 Enabling this option allows the kernel to modify itself to make
1496 these instructions safe. Disabling it allows about 1K of space
1499 If you don't know what to do here, say Y.
1501 config ARM_CPU_TOPOLOGY
1502 bool "Support cpu topology definition"
1503 depends on SMP && CPU_V7
1506 Support ARM cpu topology definition. The MPIDR register defines
1507 affinity between processors which is then used to describe the cpu
1508 topology of an ARM System.
1511 bool "Multi-core scheduler support"
1512 depends on ARM_CPU_TOPOLOGY
1514 Multi-core scheduler support improves the CPU scheduler's decision
1515 making when dealing with multi-core CPU chips at a cost of slightly
1516 increased overhead in some places. If unsure say N here.
1519 bool "SMT scheduler support"
1520 depends on ARM_CPU_TOPOLOGY
1522 Improves the CPU scheduler's decision making when dealing with
1523 MultiThreading at a cost of slightly increased overhead in some
1524 places. If unsure say N here.
1529 This option enables support for the ARM system coherency unit
1531 config HAVE_ARM_ARCH_TIMER
1532 bool "Architected timer support"
1534 select ARM_ARCH_TIMER
1536 This option enables support for the ARM architected timer
1541 select CLKSRC_OF if OF
1543 This options enables support for the ARM timer and watchdog unit
1546 bool "Multi-Cluster Power Management"
1547 depends on CPU_V7 && SMP
1549 This option provides the common power management infrastructure
1550 for (multi-)cluster based systems, such as big.LITTLE based
1554 bool "big.LITTLE support (Experimental)"
1555 depends on CPU_V7 && SMP
1558 This option enables support selections for the big.LITTLE
1559 system architecture.
1562 bool "big.LITTLE switcher support"
1563 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1565 select ARM_CPU_SUSPEND
1567 The big.LITTLE "switcher" provides the core functionality to
1568 transparently handle transition between a cluster of A15's
1569 and a cluster of A7's in a big.LITTLE system.
1571 config BL_SWITCHER_DUMMY_IF
1572 tristate "Simple big.LITTLE switcher user interface"
1573 depends on BL_SWITCHER && DEBUG_KERNEL
1575 This is a simple and dummy char dev interface to control
1576 the big.LITTLE switcher core code. It is meant for
1577 debugging purposes only.
1580 prompt "Memory split"
1583 Select the desired split between kernel and user memory.
1585 If you are not absolutely sure what you are doing, leave this
1589 bool "3G/1G user/kernel split"
1591 bool "2G/2G user/kernel split"
1593 bool "1G/3G user/kernel split"
1598 default 0x40000000 if VMSPLIT_1G
1599 default 0x80000000 if VMSPLIT_2G
1603 int "Maximum number of CPUs (2-32)"
1609 bool "Support for hot-pluggable CPUs"
1612 Say Y here to experiment with turning CPUs off and on. CPUs
1613 can be controlled through /sys/devices/system/cpu.
1616 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1619 Say Y here if you want Linux to communicate with system firmware
1620 implementing the PSCI specification for CPU-centric power
1621 management operations described in ARM document number ARM DEN
1622 0022A ("Power State Coordination Interface System Software on
1625 # The GPIO number here must be sorted by descending number. In case of
1626 # a multiplatform kernel, we just want the highest value required by the
1627 # selected platforms.
1630 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1631 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1632 default 392 if ARCH_U8500
1633 default 352 if ARCH_VT8500
1634 default 288 if ARCH_SUNXI
1635 default 264 if MACH_H4700
1638 Maximum number of GPIOs in the system.
1640 If unsure, leave the default value.
1642 source kernel/Kconfig.preempt
1646 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1647 ARCH_S5PV210 || ARCH_EXYNOS4
1648 default AT91_TIMER_HZ if ARCH_AT91
1649 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1653 depends on HZ_FIXED = 0
1654 prompt "Timer frequency"
1678 default HZ_FIXED if HZ_FIXED != 0
1679 default 100 if HZ_100
1680 default 200 if HZ_200
1681 default 250 if HZ_250
1682 default 300 if HZ_300
1683 default 500 if HZ_500
1687 def_bool HIGH_RES_TIMERS
1690 def_bool HIGH_RES_TIMERS
1692 config THUMB2_KERNEL
1693 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1694 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1695 default y if CPU_THUMBONLY
1697 select ARM_ASM_UNIFIED
1700 By enabling this option, the kernel will be compiled in
1701 Thumb-2 mode. A compiler/assembler that understand the unified
1702 ARM-Thumb syntax is needed.
1706 config THUMB2_AVOID_R_ARM_THM_JUMP11
1707 bool "Work around buggy Thumb-2 short branch relocations in gas"
1708 depends on THUMB2_KERNEL && MODULES
1711 Various binutils versions can resolve Thumb-2 branches to
1712 locally-defined, preemptible global symbols as short-range "b.n"
1713 branch instructions.
1715 This is a problem, because there's no guarantee the final
1716 destination of the symbol, or any candidate locations for a
1717 trampoline, are within range of the branch. For this reason, the
1718 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1719 relocation in modules at all, and it makes little sense to add
1722 The symptom is that the kernel fails with an "unsupported
1723 relocation" error when loading some modules.
1725 Until fixed tools are available, passing
1726 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1727 code which hits this problem, at the cost of a bit of extra runtime
1728 stack usage in some cases.
1730 The problem is described in more detail at:
1731 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1733 Only Thumb-2 kernels are affected.
1735 Unless you are sure your tools don't have this problem, say Y.
1737 config ARM_ASM_UNIFIED
1741 bool "Use the ARM EABI to compile the kernel"
1743 This option allows for the kernel to be compiled using the latest
1744 ARM ABI (aka EABI). This is only useful if you are using a user
1745 space environment that is also compiled with EABI.
1747 Since there are major incompatibilities between the legacy ABI and
1748 EABI, especially with regard to structure member alignment, this
1749 option also changes the kernel syscall calling convention to
1750 disambiguate both ABIs and allow for backward compatibility support
1751 (selected with CONFIG_OABI_COMPAT).
1753 To use this you need GCC version 4.0.0 or later.
1756 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1757 depends on AEABI && !THUMB2_KERNEL
1760 This option preserves the old syscall interface along with the
1761 new (ARM EABI) one. It also provides a compatibility layer to
1762 intercept syscalls that have structure arguments which layout
1763 in memory differs between the legacy ABI and the new ARM EABI
1764 (only for non "thumb" binaries). This option adds a tiny
1765 overhead to all syscalls and produces a slightly larger kernel.
1766 If you know you'll be using only pure EABI user space then you
1767 can say N here. If this option is not selected and you attempt
1768 to execute a legacy ABI binary then the result will be
1769 UNPREDICTABLE (in fact it can be predicted that it won't work
1770 at all). If in doubt say Y.
1772 config ARCH_HAS_HOLES_MEMORYMODEL
1775 config ARCH_SPARSEMEM_ENABLE
1778 config ARCH_SPARSEMEM_DEFAULT
1779 def_bool ARCH_SPARSEMEM_ENABLE
1781 config ARCH_SELECT_MEMORY_MODEL
1782 def_bool ARCH_SPARSEMEM_ENABLE
1784 config HAVE_ARCH_PFN_VALID
1785 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1788 bool "High Memory Support"
1791 The address space of ARM processors is only 4 Gigabytes large
1792 and it has to accommodate user address space, kernel address
1793 space as well as some memory mapped IO. That means that, if you
1794 have a large amount of physical memory and/or IO, not all of the
1795 memory can be "permanently mapped" by the kernel. The physical
1796 memory that is not permanently mapped is called "high memory".
1798 Depending on the selected kernel/user memory split, minimum
1799 vmalloc space and actual amount of RAM, you may not need this
1800 option which should result in a slightly faster kernel.
1805 bool "Allocate 2nd-level pagetables from highmem"
1808 config HW_PERF_EVENTS
1809 bool "Enable hardware performance counter support for perf events"
1810 depends on PERF_EVENTS
1813 Enable hardware performance counter support for perf events. If
1814 disabled, perf events will use software events only.
1816 config SYS_SUPPORTS_HUGETLBFS
1820 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1824 config ARCH_WANT_GENERAL_HUGETLB
1829 config FORCE_MAX_ZONEORDER
1830 int "Maximum zone order" if ARCH_SHMOBILE
1831 range 11 64 if ARCH_SHMOBILE
1832 default "12" if SOC_AM33XX
1833 default "9" if SA1111
1836 The kernel memory allocator divides physically contiguous memory
1837 blocks into "zones", where each zone is a power of two number of
1838 pages. This option selects the largest power of two that the kernel
1839 keeps in the memory allocator. If you need to allocate very large
1840 blocks of physically contiguous memory, then you may need to
1841 increase this value.
1843 This config option is actually maximum order plus one. For example,
1844 a value of 11 means that the largest free memory block is 2^10 pages.
1846 config ALIGNMENT_TRAP
1848 depends on CPU_CP15_MMU
1849 default y if !ARCH_EBSA110
1850 select HAVE_PROC_CPU if PROC_FS
1852 ARM processors cannot fetch/store information which is not
1853 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1854 address divisible by 4. On 32-bit ARM processors, these non-aligned
1855 fetch/store instructions will be emulated in software if you say
1856 here, which has a severe performance impact. This is necessary for
1857 correct operation of some network protocols. With an IP-only
1858 configuration it is safe to say N, otherwise say Y.
1860 config UACCESS_WITH_MEMCPY
1861 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1863 default y if CPU_FEROCEON
1865 Implement faster copy_to_user and clear_user methods for CPU
1866 cores where a 8-word STM instruction give significantly higher
1867 memory write throughput than a sequence of individual 32bit stores.
1869 A possible side effect is a slight increase in scheduling latency
1870 between threads sharing the same address space if they invoke
1871 such copy operations with large buffers.
1873 However, if the CPU data cache is using a write-allocate mode,
1874 this option is unlikely to provide any performance gain.
1878 prompt "Enable seccomp to safely compute untrusted bytecode"
1880 This kernel feature is useful for number crunching applications
1881 that may need to compute untrusted bytecode during their
1882 execution. By using pipes or other transports made available to
1883 the process as file descriptors supporting the read/write
1884 syscalls, it's possible to isolate those applications in
1885 their own address space using seccomp. Once seccomp is
1886 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1887 and the task is only allowed to execute a few safe syscalls
1888 defined by each seccomp mode.
1890 config CC_STACKPROTECTOR
1891 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1893 This option turns on the -fstack-protector GCC feature. This
1894 feature puts, at the beginning of functions, a canary value on
1895 the stack just before the return address, and validates
1896 the value just before actually returning. Stack based buffer
1897 overflows (that need to overwrite this return address) now also
1898 overwrite the canary, which gets detected and the attack is then
1899 neutralized via a kernel panic.
1900 This feature requires gcc version 4.2 or above.
1907 bool "Xen guest support on ARM (EXPERIMENTAL)"
1908 depends on ARM && AEABI && OF
1909 depends on CPU_V7 && !CPU_V6
1910 depends on !GENERIC_ATOMIC64
1913 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1920 bool "Flattened Device Tree support"
1923 select OF_EARLY_FLATTREE
1925 Include support for flattened device tree machine descriptions.
1928 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1931 This is the traditional way of passing data to the kernel at boot
1932 time. If you are solely relying on the flattened device tree (or
1933 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1934 to remove ATAGS support from your kernel binary. If unsure,
1937 config DEPRECATED_PARAM_STRUCT
1938 bool "Provide old way to pass kernel parameters"
1941 This was deprecated in 2001 and announced to live on for 5 years.
1942 Some old boot loaders still use this way.
1944 # Compressed boot loader in ROM. Yes, we really want to ask about
1945 # TEXT and BSS so we preserve their values in the config files.
1946 config ZBOOT_ROM_TEXT
1947 hex "Compressed ROM boot loader base address"
1950 The physical address at which the ROM-able zImage is to be
1951 placed in the target. Platforms which normally make use of
1952 ROM-able zImage formats normally set this to a suitable
1953 value in their defconfig file.
1955 If ZBOOT_ROM is not enabled, this has no effect.
1957 config ZBOOT_ROM_BSS
1958 hex "Compressed ROM boot loader BSS address"
1961 The base address of an area of read/write memory in the target
1962 for the ROM-able zImage which must be available while the
1963 decompressor is running. It must be large enough to hold the
1964 entire decompressed kernel plus an additional 128 KiB.
1965 Platforms which normally make use of ROM-able zImage formats
1966 normally set this to a suitable value in their defconfig file.
1968 If ZBOOT_ROM is not enabled, this has no effect.
1971 bool "Compressed boot loader in ROM/flash"
1972 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1974 Say Y here if you intend to execute your compressed kernel image
1975 (zImage) directly from ROM or flash. If unsure, say N.
1978 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1979 depends on ZBOOT_ROM && ARCH_SH7372
1980 default ZBOOT_ROM_NONE
1982 Include experimental SD/MMC loading code in the ROM-able zImage.
1983 With this enabled it is possible to write the ROM-able zImage
1984 kernel image to an MMC or SD card and boot the kernel straight
1985 from the reset vector. At reset the processor Mask ROM will load
1986 the first part of the ROM-able zImage which in turn loads the
1987 rest the kernel image to RAM.
1989 config ZBOOT_ROM_NONE
1990 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1992 Do not load image from SD or MMC
1994 config ZBOOT_ROM_MMCIF
1995 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1997 Load image from MMCIF hardware block.
1999 config ZBOOT_ROM_SH_MOBILE_SDHI
2000 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2002 Load image from SDHI hardware block
2006 config ARM_APPENDED_DTB
2007 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2008 depends on OF && !ZBOOT_ROM
2010 With this option, the boot code will look for a device tree binary
2011 (DTB) appended to zImage
2012 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2014 This is meant as a backward compatibility convenience for those
2015 systems with a bootloader that can't be upgraded to accommodate
2016 the documented boot protocol using a device tree.
2018 Beware that there is very little in terms of protection against
2019 this option being confused by leftover garbage in memory that might
2020 look like a DTB header after a reboot if no actual DTB is appended
2021 to zImage. Do not leave this option active in a production kernel
2022 if you don't intend to always append a DTB. Proper passing of the
2023 location into r2 of a bootloader provided DTB is always preferable
2026 config ARM_ATAG_DTB_COMPAT
2027 bool "Supplement the appended DTB with traditional ATAG information"
2028 depends on ARM_APPENDED_DTB
2030 Some old bootloaders can't be updated to a DTB capable one, yet
2031 they provide ATAGs with memory configuration, the ramdisk address,
2032 the kernel cmdline string, etc. Such information is dynamically
2033 provided by the bootloader and can't always be stored in a static
2034 DTB. To allow a device tree enabled kernel to be used with such
2035 bootloaders, this option allows zImage to extract the information
2036 from the ATAG list and store it at run time into the appended DTB.
2039 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2040 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2042 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2043 bool "Use bootloader kernel arguments if available"
2045 Uses the command-line options passed by the boot loader instead of
2046 the device tree bootargs property. If the boot loader doesn't provide
2047 any, the device tree bootargs property will be used.
2049 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2050 bool "Extend with bootloader kernel arguments"
2052 The command-line arguments provided by the boot loader will be
2053 appended to the the device tree bootargs property.
2058 string "Default kernel command string"
2061 On some architectures (EBSA110 and CATS), there is currently no way
2062 for the boot loader to pass arguments to the kernel. For these
2063 architectures, you should supply some command-line options at build
2064 time by entering them here. As a minimum, you should specify the
2065 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2068 prompt "Kernel command line type" if CMDLINE != ""
2069 default CMDLINE_FROM_BOOTLOADER
2072 config CMDLINE_FROM_BOOTLOADER
2073 bool "Use bootloader kernel arguments if available"
2075 Uses the command-line options passed by the boot loader. If
2076 the boot loader doesn't provide any, the default kernel command
2077 string provided in CMDLINE will be used.
2079 config CMDLINE_EXTEND
2080 bool "Extend bootloader kernel arguments"
2082 The command-line arguments provided by the boot loader will be
2083 appended to the default kernel command string.
2085 config CMDLINE_FORCE
2086 bool "Always use the default kernel command string"
2088 Always use the default kernel command string, even if the boot
2089 loader passes other arguments to the kernel.
2090 This is useful if you cannot or don't want to change the
2091 command-line options your boot loader passes to the kernel.
2095 bool "Kernel Execute-In-Place from ROM"
2096 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2098 Execute-In-Place allows the kernel to run from non-volatile storage
2099 directly addressable by the CPU, such as NOR flash. This saves RAM
2100 space since the text section of the kernel is not loaded from flash
2101 to RAM. Read-write sections, such as the data section and stack,
2102 are still copied to RAM. The XIP kernel is not compressed since
2103 it has to run directly from flash, so it will take more space to
2104 store it. The flash address used to link the kernel object files,
2105 and for storing it, is configuration dependent. Therefore, if you
2106 say Y here, you must know the proper physical address where to
2107 store the kernel image depending on your own flash memory usage.
2109 Also note that the make target becomes "make xipImage" rather than
2110 "make zImage" or "make Image". The final kernel binary to put in
2111 ROM memory will be arch/arm/boot/xipImage.
2115 config XIP_PHYS_ADDR
2116 hex "XIP Kernel Physical Location"
2117 depends on XIP_KERNEL
2118 default "0x00080000"
2120 This is the physical address in your flash memory the kernel will
2121 be linked for and stored to. This address is dependent on your
2125 bool "Kexec system call (EXPERIMENTAL)"
2126 depends on (!SMP || PM_SLEEP_SMP)
2128 kexec is a system call that implements the ability to shutdown your
2129 current kernel, and to start another kernel. It is like a reboot
2130 but it is independent of the system firmware. And like a reboot
2131 you can start any kernel with it, not just Linux.
2133 It is an ongoing process to be certain the hardware in a machine
2134 is properly shutdown, so do not be surprised if this code does not
2135 initially work for you.
2138 bool "Export atags in procfs"
2139 depends on ATAGS && KEXEC
2142 Should the atags used to boot the kernel be exported in an "atags"
2143 file in procfs. Useful with kexec.
2146 bool "Build kdump crash kernel (EXPERIMENTAL)"
2148 Generate crash dump after being started by kexec. This should
2149 be normally only set in special crash dump kernels which are
2150 loaded in the main kernel with kexec-tools into a specially
2151 reserved region and then later executed after a crash by
2152 kdump/kexec. The crash dump kernel must be compiled to a
2153 memory address not used by the main kernel
2155 For more details see Documentation/kdump/kdump.txt
2157 config AUTO_ZRELADDR
2158 bool "Auto calculation of the decompressed kernel image address"
2159 depends on !ZBOOT_ROM
2161 ZRELADDR is the physical address where the decompressed kernel
2162 image will be placed. If AUTO_ZRELADDR is selected, the address
2163 will be determined at run-time by masking the current IP with
2164 0xf8000000. This assumes the zImage being placed in the first 128MB
2165 from start of memory.
2169 menu "CPU Power Management"
2172 source "drivers/cpufreq/Kconfig"
2175 source "drivers/cpuidle/Kconfig"
2179 menu "Floating point emulation"
2181 comment "At least one emulation must be selected"
2184 bool "NWFPE math emulation"
2185 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2187 Say Y to include the NWFPE floating point emulator in the kernel.
2188 This is necessary to run most binaries. Linux does not currently
2189 support floating point hardware so you need to say Y here even if
2190 your machine has an FPA or floating point co-processor podule.
2192 You may say N here if you are going to load the Acorn FPEmulator
2193 early in the bootup.
2196 bool "Support extended precision"
2197 depends on FPE_NWFPE
2199 Say Y to include 80-bit support in the kernel floating-point
2200 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2201 Note that gcc does not generate 80-bit operations by default,
2202 so in most cases this option only enlarges the size of the
2203 floating point emulator without any good reason.
2205 You almost surely want to say N here.
2208 bool "FastFPE math emulation (EXPERIMENTAL)"
2209 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2211 Say Y here to include the FAST floating point emulator in the kernel.
2212 This is an experimental much faster emulator which now also has full
2213 precision for the mantissa. It does not support any exceptions.
2214 It is very simple, and approximately 3-6 times faster than NWFPE.
2216 It should be sufficient for most programs. It may be not suitable
2217 for scientific calculations, but you have to check this for yourself.
2218 If you do not feel you need a faster FP emulation you should better
2222 bool "VFP-format floating point maths"
2223 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2225 Say Y to include VFP support code in the kernel. This is needed
2226 if your hardware includes a VFP unit.
2228 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2229 release notes and additional status information.
2231 Say N if your target does not have VFP hardware.
2239 bool "Advanced SIMD (NEON) Extension support"
2240 depends on VFPv3 && CPU_V7
2242 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2245 config KERNEL_MODE_NEON
2246 bool "Support for NEON in kernel mode"
2247 depends on NEON && AEABI
2249 Say Y to include support for NEON in kernel mode.
2253 menu "Userspace binary formats"
2255 source "fs/Kconfig.binfmt"
2258 tristate "RISC OS personality"
2261 Say Y here to include the kernel code necessary if you want to run
2262 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2263 experimental; if this sounds frightening, say N and sleep in peace.
2264 You can also say M here to compile this support as a module (which
2265 will be called arthur).
2269 menu "Power management options"
2271 source "kernel/power/Kconfig"
2273 config ARCH_SUSPEND_POSSIBLE
2274 depends on !ARCH_S5PC100
2275 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2276 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2279 config ARM_CPU_SUSPEND
2284 source "net/Kconfig"
2286 source "drivers/Kconfig"
2290 source "arch/arm/Kconfig.debug"
2292 source "security/Kconfig"
2294 source "crypto/Kconfig"
2296 source "lib/Kconfig"
2298 source "arch/arm/kvm/Kconfig"