arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx53-pinfunc.h"
  15
  16 / {
  17         aliases {
  18                 gpio0 = &gpio1;
  19                 gpio1 = &gpio2;
  20                 gpio2 = &gpio3;
  21                 gpio3 = &gpio4;
  22                 gpio4 = &gpio5;
  23                 gpio5 = &gpio6;
  24                 gpio6 = &gpio7;
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 serial3 = &uart4;
  32                 serial4 = &uart5;
  33                 spi0 = &ecspi1;
  34                 spi1 = &ecspi2;
  35                 spi2 = &cspi;
  36         };
  37
  38         cpus {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41                 cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a8";
  44                         reg = <0x0>;
  45                 };
  46         };
  47
  48         tzic: tz-interrupt-controller@0fffc000 {
  49                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  50                 interrupt-controller;
  51                 #interrupt-cells = <1>;
  52                 reg = <0x0fffc000 0x4000>;
  53         };
  54
  55         clocks {
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58
  59                 ckil {
  60                         compatible = "fsl,imx-ckil", "fixed-clock";
  61                         clock-frequency = <32768>;
  62                 };
  63
  64                 ckih1 {
  65                         compatible = "fsl,imx-ckih1", "fixed-clock";
  66                         clock-frequency = <22579200>;
  67                 };
  68
  69                 ckih2 {
  70                         compatible = "fsl,imx-ckih2", "fixed-clock";
  71                         clock-frequency = <0>;
  72                 };
  73
  74                 osc {
  75                         compatible = "fsl,imx-osc", "fixed-clock";
  76                         clock-frequency = <24000000>;
  77                 };
  78         };
  79
  80         soc {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 compatible = "simple-bus";
  84                 interrupt-parent = <&tzic>;
  85                 ranges;
  86
  87                 ipu: ipu@18000000 {
  88                         #crtc-cells = <1>;
  89                         compatible = "fsl,imx53-ipu";
  90                         reg = <0x18000000 0x080000000>;
  91                         interrupts = <11 10>;
  92                         clocks = <&clks 59>, <&clks 110>, <&clks 61>;
  93                         clock-names = "bus", "di0", "di1";
  94                         resets = <&src 2>;
  95                 };
  96
  97                 aips@50000000 { /* AIPS1 */
  98                         compatible = "fsl,aips-bus", "simple-bus";
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101                         reg = <0x50000000 0x10000000>;
 102                         ranges;
 103
 104                         spba@50000000 {
 105                                 compatible = "fsl,spba-bus", "simple-bus";
 106                                 #address-cells = <1>;
 107                                 #size-cells = <1>;
 108                                 reg = <0x50000000 0x40000>;
 109                                 ranges;
 110
 111                                 esdhc1: esdhc@50004000 {
 112                                         compatible = "fsl,imx53-esdhc";
 113                                         reg = <0x50004000 0x4000>;
 114                                         interrupts = <1>;
 115                                         clocks = <&clks 44>, <&clks 0>, <&clks 71>;
 116                                         clock-names = "ipg", "ahb", "per";
 117                                         bus-width = <4>;
 118                                         status = "disabled";
 119                                 };
 120
 121                                 esdhc2: esdhc@50008000 {
 122                                         compatible = "fsl,imx53-esdhc";
 123                                         reg = <0x50008000 0x4000>;
 124                                         interrupts = <2>;
 125                                         clocks = <&clks 45>, <&clks 0>, <&clks 72>;
 126                                         clock-names = "ipg", "ahb", "per";
 127                                         bus-width = <4>;
 128                                         status = "disabled";
 129                                 };
 130
 131                                 uart3: serial@5000c000 {
 132                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 133                                         reg = <0x5000c000 0x4000>;
 134                                         interrupts = <33>;
 135                                         clocks = <&clks 32>, <&clks 33>;
 136                                         clock-names = "ipg", "per";
 137                                         status = "disabled";
 138                                 };
 139
 140                                 ecspi1: ecspi@50010000 {
 141                                         #address-cells = <1>;
 142                                         #size-cells = <0>;
 143                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 144                                         reg = <0x50010000 0x4000>;
 145                                         interrupts = <36>;
 146                                         clocks = <&clks 51>, <&clks 52>;
 147                                         clock-names = "ipg", "per";
 148                                         status = "disabled";
 149                                 };
 150
 151                                 ssi2: ssi@50014000 {
 152                                         compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 153                                         reg = <0x50014000 0x4000>;
 154                                         interrupts = <30>;
 155                                         clocks = <&clks 49>;
 156                                         dmas = <&sdma 24 1 0>,
 157                                                <&sdma 25 1 0>;
 158                                         dma-names = "rx", "tx";
 159                                         fsl,fifo-depth = <15>;
 160                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 161                                         status = "disabled";
 162                                 };
 163
 164                                 esdhc3: esdhc@50020000 {
 165                                         compatible = "fsl,imx53-esdhc";
 166                                         reg = <0x50020000 0x4000>;
 167                                         interrupts = <3>;
 168                                         clocks = <&clks 46>, <&clks 0>, <&clks 73>;
 169                                         clock-names = "ipg", "ahb", "per";
 170                                         bus-width = <4>;
 171                                         status = "disabled";
 172                                 };
 173
 174                                 esdhc4: esdhc@50024000 {
 175                                         compatible = "fsl,imx53-esdhc";
 176                                         reg = <0x50024000 0x4000>;
 177                                         interrupts = <4>;
 178                                         clocks = <&clks 47>, <&clks 0>, <&clks 74>;
 179                                         clock-names = "ipg", "ahb", "per";
 180                                         bus-width = <4>;
 181                                         status = "disabled";
 182                                 };
 183                         };
 184
 185                         usbphy0: usbphy@0 {
 186                                 compatible = "usb-nop-xceiv";
 187                                 clocks = <&clks 124>;
 188                                 clock-names = "main_clk";
 189                                 status = "okay";
 190                         };
 191
 192                         usbphy1: usbphy@1 {
 193                                 compatible = "usb-nop-xceiv";
 194                                 clocks = <&clks 125>;
 195                                 clock-names = "main_clk";
 196                                 status = "okay";
 197                         };
 198
 199                         usbotg: usb@53f80000 {
 200                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 201                                 reg = <0x53f80000 0x0200>;
 202                                 interrupts = <18>;
 203                                 clocks = <&clks 108>;
 204                                 fsl,usbmisc = <&usbmisc 0>;
 205                                 fsl,usbphy = <&usbphy0>;
 206                                 status = "disabled";
 207                         };
 208
 209                         usbh1: usb@53f80200 {
 210                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 211                                 reg = <0x53f80200 0x0200>;
 212                                 interrupts = <14>;
 213                                 clocks = <&clks 108>;
 214                                 fsl,usbmisc = <&usbmisc 1>;
 215                                 fsl,usbphy = <&usbphy1>;
 216                                 status = "disabled";
 217                         };
 218
 219                         usbh2: usb@53f80400 {
 220                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 221                                 reg = <0x53f80400 0x0200>;
 222                                 interrupts = <16>;
 223                                 clocks = <&clks 108>;
 224                                 fsl,usbmisc = <&usbmisc 2>;
 225                                 status = "disabled";
 226                         };
 227
 228                         usbh3: usb@53f80600 {
 229                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 230                                 reg = <0x53f80600 0x0200>;
 231                                 interrupts = <17>;
 232                                 clocks = <&clks 108>;
 233                                 fsl,usbmisc = <&usbmisc 3>;
 234                                 status = "disabled";
 235                         };
 236
 237                         usbmisc: usbmisc@53f80800 {
 238                                 #index-cells = <1>;
 239                                 compatible = "fsl,imx53-usbmisc";
 240                                 reg = <0x53f80800 0x200>;
 241                                 clocks = <&clks 108>;
 242                         };
 243
 244                         gpio1: gpio@53f84000 {
 245                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 246                                 reg = <0x53f84000 0x4000>;
 247                                 interrupts = <50 51>;
 248                                 gpio-controller;
 249                                 #gpio-cells = <2>;
 250                                 interrupt-controller;
 251                                 #interrupt-cells = <2>;
 252                         };
 253
 254                         gpio2: gpio@53f88000 {
 255                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 256                                 reg = <0x53f88000 0x4000>;
 257                                 interrupts = <52 53>;
 258                                 gpio-controller;
 259                                 #gpio-cells = <2>;
 260                                 interrupt-controller;
 261                                 #interrupt-cells = <2>;
 262                         };
 263
 264                         gpio3: gpio@53f8c000 {
 265                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 266                                 reg = <0x53f8c000 0x4000>;
 267                                 interrupts = <54 55>;
 268                                 gpio-controller;
 269                                 #gpio-cells = <2>;
 270                                 interrupt-controller;
 271                                 #interrupt-cells = <2>;
 272                         };
 273
 274                         gpio4: gpio@53f90000 {
 275                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 276                                 reg = <0x53f90000 0x4000>;
 277                                 interrupts = <56 57>;
 278                                 gpio-controller;
 279                                 #gpio-cells = <2>;
 280                                 interrupt-controller;
 281                                 #interrupt-cells = <2>;
 282                         };
 283
 284                         wdog1: wdog@53f98000 {
 285                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 286                                 reg = <0x53f98000 0x4000>;
 287                                 interrupts = <58>;
 288                                 clocks = <&clks 0>;
 289                         };
 290
 291                         wdog2: wdog@53f9c000 {
 292                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 293                                 reg = <0x53f9c000 0x4000>;
 294                                 interrupts = <59>;
 295                                 clocks = <&clks 0>;
 296                                 status = "disabled";
 297                         };
 298
 299                         gpt: timer@53fa0000 {
 300                                 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
 301                                 reg = <0x53fa0000 0x4000>;
 302                                 interrupts = <39>;
 303                                 clocks = <&clks 36>, <&clks 41>;
 304                                 clock-names = "ipg", "per";
 305                         };
 306
 307                         iomuxc: iomuxc@53fa8000 {
 308                                 compatible = "fsl,imx53-iomuxc";
 309                                 reg = <0x53fa8000 0x4000>;
 310
 311                                 audmux {
 312                                         pinctrl_audmux_1: audmuxgrp-1 {
 313                                                 fsl,pins = <
 314                                                         MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x80000000
 315                                                         MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x80000000
 316                                                         MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
 317                                                         MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000
 318                                                 >;
 319                                         };
 320
 321                                         pinctrl_audmux_2: audmuxgrp-2 {
 322                                                 fsl,pins = <
 323                                                         MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC     0x80000000
 324                                                         MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD     0x80000000
 325                                                         MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS    0x80000000
 326                                                         MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD     0x80000000
 327                                                 >;
 328                                         };
 329
 330                                         pinctrl_audmux_3: audmuxgrp-3 {
 331                                                 fsl,pins = <
 332                                                         MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC     0x80000000
 333                                                         MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD     0x80000000
 334                                                         MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS    0x80000000
 335                                                         MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD     0x80000000
 336                                                 >;
 337                                         };
 338                                 };
 339
 340                                 fec {
 341                                         pinctrl_fec_1: fecgrp-1 {
 342                                                 fsl,pins = <
 343                                                         MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
 344                                                         MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
 345                                                         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
 346                                                         MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
 347                                                         MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
 348                                                         MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
 349                                                         MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
 350                                                         MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
 351                                                         MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
 352                                                         MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
 353                                                 >;
 354                                         };
 355
 356                                         pinctrl_fec_2: fecgrp-2 {
 357                                                 fsl,pins = <
 358                                                         MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
 359                                                         MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
 360                                                         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
 361                                                         MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
 362                                                         MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
 363                                                         MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
 364                                                         MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
 365                                                         MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
 366                                                         MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
 367                                                         MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
 368                                                         MX53_PAD_KEY_ROW1__FEC_COL       0x80000000
 369                                                         MX53_PAD_KEY_COL3__FEC_CRS       0x80000000
 370                                                         MX53_PAD_KEY_COL2__FEC_RDATA_2   0x80000000
 371                                                         MX53_PAD_KEY_COL0__FEC_RDATA_3   0x80000000
 372                                                         MX53_PAD_KEY_COL1__FEC_RX_CLK    0x80000000
 373                                                         MX53_PAD_KEY_ROW2__FEC_TDATA_2   0x80000000
 374                                                         MX53_PAD_GPIO_19__FEC_TDATA_3    0x80000000
 375                                                         MX53_PAD_KEY_ROW0__FEC_TX_ER     0x80000000
 376                                                 >;
 377                                         };
 378                                 };
 379
 380                                 csi {
 381                                         pinctrl_csi_1: csigrp-1 {
 382                                                 fsl,pins = <
 383                                                         MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
 384                                                         MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
 385                                                         MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
 386                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 387                                                         MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
 388                                                         MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
 389                                                         MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
 390                                                         MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
 391                                                         MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
 392                                                         MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
 393                                                         MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
 394                                                         MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
 395                                                         MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11      0x1d5
 396                                                         MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10      0x1d5
 397                                                         MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9        0x1d5
 398                                                         MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8        0x1d5
 399                                                         MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7        0x1d5
 400                                                         MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6        0x1d5
 401                                                         MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5        0x1d5
 402                                                         MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4        0x1d5
 403                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 404                                                 >;
 405                                         };
 406
 407                                         pinctrl_csi_2: csigrp-2 {
 408                                                 fsl,pins = <
 409                                                         MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
 410                                                         MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
 411                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 412                                                         MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
 413                                                         MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
 414                                                         MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
 415                                                         MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
 416                                                         MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
 417                                                         MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
 418                                                         MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
 419                                                         MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
 420                                                 >;
 421                                         };
 422                                 };
 423
 424                                 cspi {
 425                                         pinctrl_cspi_1: cspigrp-1 {
 426                                                 fsl,pins = <
 427                                                         MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
 428                                                         MX53_PAD_SD1_CMD__CSPI_MOSI   0x1d5
 429                                                         MX53_PAD_SD1_CLK__CSPI_SCLK   0x1d5
 430                                                 >;
 431                                         };
 432
 433                                         pinctrl_cspi_2: cspigrp-2 {
 434                                                 fsl,pins = <
 435                                                         MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
 436                                                         MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
 437                                                         MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
 438                                                 >;
 439                                         };
 440                                 };
 441
 442                                 ecspi1 {
 443                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 444                                                 fsl,pins = <
 445                                                         MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
 446                                                         MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
 447                                                         MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
 448                                                 >;
 449                                         };
 450
 451                                         pinctrl_ecspi1_2: ecspi1grp-2 {
 452                                                 fsl,pins = <
 453                                                         MX53_PAD_GPIO_19__ECSPI1_RDY    0x80000000
 454                                                         MX53_PAD_EIM_EB2__ECSPI1_SS0    0x80000000
 455                                                         MX53_PAD_EIM_D16__ECSPI1_SCLK   0x80000000
 456                                                         MX53_PAD_EIM_D17__ECSPI1_MISO   0x80000000
 457                                                         MX53_PAD_EIM_D18__ECSPI1_MOSI   0x80000000
 458                                                         MX53_PAD_EIM_D19__ECSPI1_SS1    0x80000000
 459                                                 >;
 460                                         };
 461                                 };
 462
 463                                 ecspi2 {
 464                                         pinctrl_ecspi2_1: ecspi2grp-1 {
 465                                                 fsl,pins = <
 466                                                         MX53_PAD_EIM_OE__ECSPI2_MISO  0x80000000
 467                                                         MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
 468                                                         MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
 469                                                 >;
 470                                         };
 471                                 };
 472
 473                                 esdhc1 {
 474                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 475                                                 fsl,pins = <
 476                                                         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
 477                                                         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
 478                                                         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
 479                                                         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
 480                                                         MX53_PAD_SD1_CMD__ESDHC1_CMD    0x1d5
 481                                                         MX53_PAD_SD1_CLK__ESDHC1_CLK    0x1d5
 482                                                 >;
 483                                         };
 484
 485                                         pinctrl_esdhc1_2: esdhc1grp-2 {
 486                                                 fsl,pins = <
 487                                                         MX53_PAD_SD1_DATA0__ESDHC1_DAT0   0x1d5
 488                                                         MX53_PAD_SD1_DATA1__ESDHC1_DAT1   0x1d5
 489                                                         MX53_PAD_SD1_DATA2__ESDHC1_DAT2   0x1d5
 490                                                         MX53_PAD_SD1_DATA3__ESDHC1_DAT3   0x1d5
 491                                                         MX53_PAD_PATA_DATA8__ESDHC1_DAT4  0x1d5
 492                                                         MX53_PAD_PATA_DATA9__ESDHC1_DAT5  0x1d5
 493                                                         MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
 494                                                         MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
 495                                                         MX53_PAD_SD1_CMD__ESDHC1_CMD      0x1d5
 496                                                         MX53_PAD_SD1_CLK__ESDHC1_CLK      0x1d5
 497                                                 >;
 498                                         };
 499                                 };
 500
 501                                 esdhc2 {
 502                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 503                                                 fsl,pins = <
 504                                                         MX53_PAD_SD2_CMD__ESDHC2_CMD    0x1d5
 505                                                         MX53_PAD_SD2_CLK__ESDHC2_CLK    0x1d5
 506                                                         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
 507                                                         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
 508                                                         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
 509                                                         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
 510                                                 >;
 511                                         };
 512                                 };
 513
 514                                 esdhc3 {
 515                                         pinctrl_esdhc3_1: esdhc3grp-1 {
 516                                                 fsl,pins = <
 517                                                         MX53_PAD_PATA_DATA8__ESDHC3_DAT0  0x1d5
 518                                                         MX53_PAD_PATA_DATA9__ESDHC3_DAT1  0x1d5
 519                                                         MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
 520                                                         MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
 521                                                         MX53_PAD_PATA_DATA0__ESDHC3_DAT4  0x1d5
 522                                                         MX53_PAD_PATA_DATA1__ESDHC3_DAT5  0x1d5
 523                                                         MX53_PAD_PATA_DATA2__ESDHC3_DAT6  0x1d5
 524                                                         MX53_PAD_PATA_DATA3__ESDHC3_DAT7  0x1d5
 525                                                         MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
 526                                                         MX53_PAD_PATA_IORDY__ESDHC3_CLK   0x1d5
 527                                                 >;
 528                                         };
 529                                 };
 530
 531                                 can1 {
 532                                         pinctrl_can1_1: can1grp-1 {
 533                                                 fsl,pins = <
 534                                                         MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
 535                                                         MX53_PAD_PATA_DIOR__CAN1_RXCAN  0x80000000
 536                                                 >;
 537                                         };
 538
 539                                         pinctrl_can1_2: can1grp-2 {
 540                                                 fsl,pins = <
 541                                                         MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
 542                                                         MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
 543                                                 >;
 544                                         };
 545
 546                                         pinctrl_can1_3: can1grp-3 {
 547                                                 fsl,pins = <
 548                                                         MX53_PAD_GPIO_7__CAN1_TXCAN     0x80000000
 549                                                         MX53_PAD_GPIO_8__CAN1_RXCAN     0x80000000
 550                                                 >;
 551                                         };
 552                                 };
 553
 554                                 can2 {
 555                                         pinctrl_can2_1: can2grp-1 {
 556                                                 fsl,pins = <
 557                                                         MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
 558                                                         MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
 559                                                 >;
 560                                         };
 561                                 };
 562
 563                                 i2c1 {
 564                                         pinctrl_i2c1_1: i2c1grp-1 {
 565                                                 fsl,pins = <
 566                                                         MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
 567                                                         MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
 568                                                 >;
 569                                         };
 570
 571                                         pinctrl_i2c1_2: i2c1grp-2 {
 572                                                 fsl,pins = <
 573                                                         MX53_PAD_EIM_D21__I2C1_SCL      0xc0000000
 574                                                         MX53_PAD_EIM_D28__I2C1_SDA      0xc0000000
 575                                                 >;
 576                                         };
 577                                 };
 578
 579                                 i2c2 {
 580                                         pinctrl_i2c2_1: i2c2grp-1 {
 581                                                 fsl,pins = <
 582                                                         MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
 583                                                         MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
 584                                                 >;
 585                                         };
 586
 587                                         pinctrl_i2c2_2: i2c2grp-2 {
 588                                                 fsl,pins = <
 589                                                         MX53_PAD_EIM_D16__I2C2_SDA      0xc0000000
 590                                                         MX53_PAD_EIM_EB2__I2C2_SCL      0xc0000000
 591                                                 >;
 592                                         };
 593                                 };
 594
 595                                 i2c3 {
 596                                         pinctrl_i2c3_1: i2c3grp-1 {
 597                                                 fsl,pins = <
 598                                                         MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
 599                                                         MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
 600                                                 >;
 601                                         };
 602                                 };
 603
 604                                 ipu_disp0 {
 605                                         pinctrl_ipu_disp0_1: ipudisp0grp-1 {
 606                                                 fsl,pins = <
 607                                                 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
 608                                                 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               0x5
 609                                                 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         0x5
 610                                                 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 0x5
 611                                                 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            0x5
 612                                                 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            0x5
 613                                                 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            0x5
 614                                                 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            0x5
 615                                                 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            0x5
 616                                                 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            0x5
 617                                                 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            0x5
 618                                                 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            0x5
 619                                                 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            0x5
 620                                                 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            0x5
 621                                                 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          0x5
 622                                                 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          0x5
 623                                                 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          0x5
 624                                                 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          0x5
 625                                                 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          0x5
 626                                                 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          0x5
 627                                                 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          0x5
 628                                                 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          0x5
 629                                                 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          0x5
 630                                                 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          0x5
 631                                                 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          0x5
 632                                                 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          0x5
 633                                                 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          0x5
 634                                                 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          0x5
 635                                                 >;
 636                                         };
 637                                 };
 638
 639                                 ipu_disp1 {
 640                                         pinctrl_ipu_disp1_1: ipudisp1grp-1 {
 641                                                 fsl,pins = <
 642                                                         MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x5
 643                                                         MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x5
 644                                                         MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x5
 645                                                         MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x5
 646                                                         MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x5
 647                                                         MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x5
 648                                                         MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x5
 649                                                         MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x5
 650                                                         MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x5
 651                                                         MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x5
 652                                                         MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x5
 653                                                         MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x5
 654                                                         MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x5
 655                                                         MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x5
 656                                                         MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x5
 657                                                         MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x5
 658                                                         MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x5
 659                                                         MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x5
 660                                                         MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x5
 661                                                         MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x5
 662                                                         MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x5
 663                                                         MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x5
 664                                                         MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x5
 665                                                         MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x5
 666                                                         MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x5
 667                                                         MX53_PAD_EIM_DA13__IPU_DI1_D0_CS        0x5
 668                                                         MX53_PAD_EIM_DA14__IPU_DI1_D1_CS        0x5
 669                                                         MX53_PAD_EIM_DA15__IPU_DI1_PIN1         0x5
 670                                                         MX53_PAD_EIM_DA11__IPU_DI1_PIN2         0x5
 671                                                         MX53_PAD_EIM_DA12__IPU_DI1_PIN3         0x5
 672                                                         MX53_PAD_EIM_A25__IPU_DI1_PIN12         0x5
 673                                                         MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x5
 674                                                 >;
 675                                         };
 676                                 };
 677
 678                                 ipu_disp2 {
 679                                         pinctrl_ipu_disp2_1: ipudisp2grp-1 {
 680                                                 fsl,pins = <
 681                                                         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0     0x80000000
 682                                                         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1     0x80000000
 683                                                         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2     0x80000000
 684                                                         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3     0x80000000
 685                                                         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK     0x80000000
 686                                                         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0     0x80000000
 687                                                         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1     0x80000000
 688                                                         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2     0x80000000
 689                                                         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3     0x80000000
 690                                                         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK     0x80000000
 691                                                 >;
 692                                         };
 693                                 };
 694
 695                                 nand {
 696                                         pinctrl_nand_1: nandgrp-1 {
 697                                                 fsl,pins = <
 698                                                         MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
 699                                                         MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
 700                                                         MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
 701                                                         MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
 702                                                         MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
 703                                                         MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
 704                                                         MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
 705                                                         MX53_PAD_PATA_DATA0__EMI_NANDF_D_0      0xa4
 706                                                         MX53_PAD_PATA_DATA1__EMI_NANDF_D_1      0xa4
 707                                                         MX53_PAD_PATA_DATA2__EMI_NANDF_D_2      0xa4
 708                                                         MX53_PAD_PATA_DATA3__EMI_NANDF_D_3      0xa4
 709                                                         MX53_PAD_PATA_DATA4__EMI_NANDF_D_4      0xa4
 710                                                         MX53_PAD_PATA_DATA5__EMI_NANDF_D_5      0xa4
 711                                                         MX53_PAD_PATA_DATA6__EMI_NANDF_D_6      0xa4
 712                                                         MX53_PAD_PATA_DATA7__EMI_NANDF_D_7      0xa4
 713                                                 >;
 714                                         };
 715                                 };
 716
 717                                 owire {
 718                                         pinctrl_owire_1: owiregrp-1 {
 719                                                 fsl,pins = <
 720                                                         MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
 721                                                 >;
 722                                         };
 723                                 };
 724
 725                                 pwm1 {
 726                                         pinctrl_pwm1_1: pwm1grp-1 {
 727                                                 fsl,pins = <
 728                                                         MX53_PAD_DISP0_DAT8__PWM1_PWMO  0x5
 729                                                 >;
 730                                         };
 731                                 };
 732
 733                                 pwm2 {
 734                                         pinctrl_pwm2_1: pwm2grp-1 {
 735                                                 fsl,pins = <
 736                                                         MX53_PAD_GPIO_1__PWM2_PWMO      0x80000000
 737                                                 >;
 738                                         };
 739                                 };
 740
 741                                 uart1 {
 742                                         pinctrl_uart1_1: uart1grp-1 {
 743                                                 fsl,pins = <
 744                                                         MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
 745                                                         MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
 746                                                 >;
 747                                         };
 748
 749                                         pinctrl_uart1_2: uart1grp-2 {
 750                                                 fsl,pins = <
 751                                                         MX53_PAD_PATA_DIOW__UART1_TXD_MUX  0x1e4
 752                                                         MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
 753                                                 >;
 754                                         };
 755
 756                                         pinctrl_uart1_3: uart1grp-3 {
 757                                                 fsl,pins = <
 758                                                         MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
 759                                                         MX53_PAD_PATA_IORDY__UART1_RTS   0x1c5
 760                                                 >;
 761                                         };
 762                                 };
 763
 764                                 uart2 {
 765                                         pinctrl_uart2_1: uart2grp-1 {
 766                                                 fsl,pins = <
 767                                                         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
 768                                                         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1e4
 769                                                 >;
 770                                         };
 771
 772                                         pinctrl_uart2_2: uart2grp-2 {
 773                                                 fsl,pins = <
 774                                                         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1c5
 775                                                         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1c5
 776                                                         MX53_PAD_PATA_DIOR__UART2_RTS           0x1c5
 777                                                         MX53_PAD_PATA_INTRQ__UART2_CTS          0x1c5
 778                                                 >;
 779                                         };
 780                                 };
 781
 782                                 uart3 {
 783                                         pinctrl_uart3_1: uart3grp-1 {
 784                                                 fsl,pins = <
 785                                                         MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
 786                                                         MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
 787                                                         MX53_PAD_PATA_DA_1__UART3_CTS     0x1e4
 788                                                         MX53_PAD_PATA_DA_2__UART3_RTS     0x1e4
 789                                                 >;
 790                                         };
 791
 792                                         pinctrl_uart3_2: uart3grp-2 {
 793                                                 fsl,pins = <
 794                                                         MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
 795                                                         MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
 796                                                 >;
 797                                         };
 798
 799                                 };
 800
 801                                 uart4 {
 802                                         pinctrl_uart4_1: uart4grp-1 {
 803                                                 fsl,pins = <
 804                                                         MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
 805                                                         MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
 806                                                 >;
 807                                         };
 808                                 };
 809
 810                                 uart5 {
 811                                         pinctrl_uart5_1: uart5grp-1 {
 812                                                 fsl,pins = <
 813                                                         MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
 814                                                         MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
 815                                                 >;
 816                                         };
 817                                 };
 818                         };
 819
 820                         gpr: iomuxc-gpr@53fa8000 {
 821                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 822                                 reg = <0x53fa8000 0xc>;
 823                         };
 824
 825                         ldb: ldb@53fa8008 {
 826                                 #address-cells = <1>;
 827                                 #size-cells = <0>;
 828                                 compatible = "fsl,imx53-ldb";
 829                                 reg = <0x53fa8008 0x4>;
 830                                 gpr = <&gpr>;
 831                                 clocks = <&clks 122>, <&clks 120>,
 832                                          <&clks 115>, <&clks 116>,
 833                                          <&clks 123>, <&clks 85>;
 834                                 clock-names = "di0_pll", "di1_pll",
 835                                               "di0_sel", "di1_sel",
 836                                               "di0", "di1";
 837                                 status = "disabled";
 838
 839                                 lvds-channel@0 {
 840                                         reg = <0>;
 841                                         crtcs = <&ipu 0>;
 842                                         status = "disabled";
 843                                 };
 844
 845                                 lvds-channel@1 {
 846                                         reg = <1>;
 847                                         crtcs = <&ipu 1>;
 848                                         status = "disabled";
 849                                 };
 850                         };
 851
 852                         pwm1: pwm@53fb4000 {
 853                                 #pwm-cells = <2>;
 854                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 855                                 reg = <0x53fb4000 0x4000>;
 856                                 clocks = <&clks 37>, <&clks 38>;
 857                                 clock-names = "ipg", "per";
 858                                 interrupts = <61>;
 859                         };
 860
 861                         pwm2: pwm@53fb8000 {
 862                                 #pwm-cells = <2>;
 863                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 864                                 reg = <0x53fb8000 0x4000>;
 865                                 clocks = <&clks 39>, <&clks 40>;
 866                                 clock-names = "ipg", "per";
 867                                 interrupts = <94>;
 868                         };
 869
 870                         uart1: serial@53fbc000 {
 871                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 872                                 reg = <0x53fbc000 0x4000>;
 873                                 interrupts = <31>;
 874                                 clocks = <&clks 28>, <&clks 29>;
 875                                 clock-names = "ipg", "per";
 876                                 status = "disabled";
 877                         };
 878
 879                         uart2: serial@53fc0000 {
 880                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 881                                 reg = <0x53fc0000 0x4000>;
 882                                 interrupts = <32>;
 883                                 clocks = <&clks 30>, <&clks 31>;
 884                                 clock-names = "ipg", "per";
 885                                 status = "disabled";
 886                         };
 887
 888                         can1: can@53fc8000 {
 889                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 890                                 reg = <0x53fc8000 0x4000>;
 891                                 interrupts = <82>;
 892                                 clocks = <&clks 158>, <&clks 157>;
 893                                 clock-names = "ipg", "per";
 894                                 status = "disabled";
 895                         };
 896
 897                         can2: can@53fcc000 {
 898                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 899                                 reg = <0x53fcc000 0x4000>;
 900                                 interrupts = <83>;
 901                                 clocks = <&clks 87>, <&clks 86>;
 902                                 clock-names = "ipg", "per";
 903                                 status = "disabled";
 904                         };
 905
 906                         src: src@53fd0000 {
 907                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 908                                 reg = <0x53fd0000 0x4000>;
 909                                 #reset-cells = <1>;
 910                         };
 911
 912                         clks: ccm@53fd4000{
 913                                 compatible = "fsl,imx53-ccm";
 914                                 reg = <0x53fd4000 0x4000>;
 915                                 interrupts = <0 71 0x04 0 72 0x04>;
 916                                 #clock-cells = <1>;
 917                         };
 918
 919                         gpio5: gpio@53fdc000 {
 920                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 921                                 reg = <0x53fdc000 0x4000>;
 922                                 interrupts = <103 104>;
 923                                 gpio-controller;
 924                                 #gpio-cells = <2>;
 925                                 interrupt-controller;
 926                                 #interrupt-cells = <2>;
 927                         };
 928
 929                         gpio6: gpio@53fe0000 {
 930                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 931                                 reg = <0x53fe0000 0x4000>;
 932                                 interrupts = <105 106>;
 933                                 gpio-controller;
 934                                 #gpio-cells = <2>;
 935                                 interrupt-controller;
 936                                 #interrupt-cells = <2>;
 937                         };
 938
 939                         gpio7: gpio@53fe4000 {
 940                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 941                                 reg = <0x53fe4000 0x4000>;
 942                                 interrupts = <107 108>;
 943                                 gpio-controller;
 944                                 #gpio-cells = <2>;
 945                                 interrupt-controller;
 946                                 #interrupt-cells = <2>;
 947                         };
 948
 949                         i2c3: i2c@53fec000 {
 950                                 #address-cells = <1>;
 951                                 #size-cells = <0>;
 952                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 953                                 reg = <0x53fec000 0x4000>;
 954                                 interrupts = <64>;
 955                                 clocks = <&clks 88>;
 956                                 status = "disabled";
 957                         };
 958
 959                         uart4: serial@53ff0000 {
 960                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 961                                 reg = <0x53ff0000 0x4000>;
 962                                 interrupts = <13>;
 963                                 clocks = <&clks 65>, <&clks 66>;
 964                                 clock-names = "ipg", "per";
 965                                 status = "disabled";
 966                         };
 967                 };
 968
 969                 aips@60000000 { /* AIPS2 */
 970                         compatible = "fsl,aips-bus", "simple-bus";
 971                         #address-cells = <1>;
 972                         #size-cells = <1>;
 973                         reg = <0x60000000 0x10000000>;
 974                         ranges;
 975
 976                         iim: iim@63f98000 {
 977                                 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
 978                                 reg = <0x63f98000 0x4000>;
 979                                 interrupts = <69>;
 980                                 clocks = <&clks 107>;
 981                         };
 982
 983                         uart5: serial@63f90000 {
 984                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 985                                 reg = <0x63f90000 0x4000>;
 986                                 interrupts = <86>;
 987                                 clocks = <&clks 67>, <&clks 68>;
 988                                 clock-names = "ipg", "per";
 989                                 status = "disabled";
 990                         };
 991
 992                         owire: owire@63fa4000 {
 993                                 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
 994                                 reg = <0x63fa4000 0x4000>;
 995                                 clocks = <&clks 159>;
 996                                 status = "disabled";
 997                         };
 998
 999                         ecspi2: ecspi@63fac000 {
1000                                 #address-cells = <1>;
1001                                 #size-cells = <0>;
1002                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
1003                                 reg = <0x63fac000 0x4000>;
1004                                 interrupts = <37>;
1005                                 clocks = <&clks 53>, <&clks 54>;
1006                                 clock-names = "ipg", "per";
1007                                 status = "disabled";
1008                         };
1009
1010                         sdma: sdma@63fb0000 {
1011                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
1012                                 reg = <0x63fb0000 0x4000>;
1013                                 interrupts = <6>;
1014                                 clocks = <&clks 56>, <&clks 56>;
1015                                 clock-names = "ipg", "ahb";
1016                                 #dma-cells = <3>;
1017                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
1018                         };
1019
1020                         cspi: cspi@63fc0000 {
1021                                 #address-cells = <1>;
1022                                 #size-cells = <0>;
1023                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
1024                                 reg = <0x63fc0000 0x4000>;
1025                                 interrupts = <38>;
1026                                 clocks = <&clks 55>, <&clks 55>;
1027                                 clock-names = "ipg", "per";
1028                                 status = "disabled";
1029                         };
1030
1031                         i2c2: i2c@63fc4000 {
1032                                 #address-cells = <1>;
1033                                 #size-cells = <0>;
1034                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1035                                 reg = <0x63fc4000 0x4000>;
1036                                 interrupts = <63>;
1037                                 clocks = <&clks 35>;
1038                                 status = "disabled";
1039                         };
1040
1041                         i2c1: i2c@63fc8000 {
1042                                 #address-cells = <1>;
1043                                 #size-cells = <0>;
1044                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1045                                 reg = <0x63fc8000 0x4000>;
1046                                 interrupts = <62>;
1047                                 clocks = <&clks 34>;
1048                                 status = "disabled";
1049                         };
1050
1051                         ssi1: ssi@63fcc000 {
1052                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1053                                 reg = <0x63fcc000 0x4000>;
1054                                 interrupts = <29>;
1055                                 clocks = <&clks 48>;
1056                                 dmas = <&sdma 28 0 0>,
1057                                        <&sdma 29 0 0>;
1058                                 dma-names = "rx", "tx";
1059                                 fsl,fifo-depth = <15>;
1060                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
1061                                 status = "disabled";
1062                         };
1063
1064                         audmux: audmux@63fd0000 {
1065                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
1066                                 reg = <0x63fd0000 0x4000>;
1067                                 status = "disabled";
1068                         };
1069
1070                         nfc: nand@63fdb000 {
1071                                 compatible = "fsl,imx53-nand";
1072                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
1073                                 interrupts = <8>;
1074                                 clocks = <&clks 60>;
1075                                 status = "disabled";
1076                         };
1077
1078                         ssi3: ssi@63fe8000 {
1079                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1080                                 reg = <0x63fe8000 0x4000>;
1081                                 interrupts = <96>;
1082                                 clocks = <&clks 50>;
1083                                 dmas = <&sdma 46 0 0>,
1084                                        <&sdma 47 0 0>;
1085                                 dma-names = "rx", "tx";
1086                                 fsl,fifo-depth = <15>;
1087                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
1088                                 status = "disabled";
1089                         };
1090
1091                         fec: ethernet@63fec000 {
1092                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
1093                                 reg = <0x63fec000 0x4000>;
1094                                 interrupts = <87>;
1095                                 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
1096                                 clock-names = "ipg", "ahb", "ptp";
1097                                 status = "disabled";
1098                         };
1099
1100                         tve: tve@63ff0000 {
1101                                 compatible = "fsl,imx53-tve";
1102                                 reg = <0x63ff0000 0x1000>;
1103                                 interrupts = <92>;
1104                                 clocks = <&clks 69>, <&clks 116>;
1105                                 clock-names = "tve", "di_sel";
1106                                 crtcs = <&ipu 1>;
1107                                 status = "disabled";
1108                         };
1109
1110                         vpu: vpu@63ff4000 {
1111                                 compatible = "fsl,imx53-vpu";
1112                                 reg = <0x63ff4000 0x1000>;
1113                                 interrupts = <9>;
1114                                 clocks = <&clks 63>, <&clks 63>;
1115                                 clock-names = "per", "ahb";
1116                                 iram = <&ocram>;
1117                                 status = "disabled";
1118                         };
1119                 };
1120
1121                 ocram: sram@f8000000 {
1122                         compatible = "mmio-sram";
1123                         reg = <0xf8000000 0x20000>;
1124                         clocks = <&clks 186>;
1125                 };
1126         };
1127 };