arch/arm/boot/dts/imx6qdl-tx6.dtsi

   1 /*
   2  * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/input/input.h>
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/pwm/pwm.h>
  46
  47 / {
  48         aliases {
  49                 can0 = &can2;
  50                 can1 = &can1;
  51                 ethernet0 = &fec;
  52                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  53                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  54                 pwm0 = &pwm1;
  55                 pwm1 = &pwm2;
  56                 reg_can_xcvr = &reg_can_xcvr;
  57                 stk5led = &user_led;
  58                 usbotg = &usbotg;
  59                 sdhc0 = &usdhc1;
  60                 sdhc1 = &usdhc2;
  61         };
  62
  63         memory {
  64                 reg = <0 0>; /* will be filled by U-Boot */
  65         };
  66
  67         clocks {
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70
  71                 mclk: clock@0 {
  72                         compatible = "fixed-clock";
  73                         reg = <0>;
  74                         #clock-cells = <0>;
  75                         clock-frequency = <26000000>;
  76                 };
  77         };
  78
  79         gpio-keys {
  80                 compatible = "gpio-keys";
  81
  82                 power {
  83                         label = "Power Button";
  84                         gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  85                         linux,code = <KEY_POWER>;
  86                         gpio-key,wakeup;
  87                 };
  88         };
  89
  90         leds {
  91                 compatible = "gpio-leds";
  92
  93                 user_led: user {
  94                         label = "Heartbeat";
  95                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
  96                         linux,default-trigger = "heartbeat";
  97                 };
  98         };
  99
 100         reg_3v3_etn: reg-3v3-etn {
 101                 compatible = "regulator-fixed";
 102                 regulator-name = "3V3_ETN";
 103                 regulator-min-microvolt = <3300000>;
 104                 regulator-max-microvolt = <3300000>;
 105                 pinctrl-names = "default";
 106                 pinctrl-0 = <&pinctrl_etnphy_power>;
 107                 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 108                 enable-active-high;
 109         };
 110
 111         reg_2v5: reg-2v5 {
 112                 compatible = "regulator-fixed";
 113                 regulator-name = "2V5";
 114                 regulator-min-microvolt = <2500000>;
 115                 regulator-max-microvolt = <2500000>;
 116                 regulator-always-on;
 117         };
 118
 119         reg_3v3: reg-3v3 {
 120                 compatible = "regulator-fixed";
 121                 regulator-name = "3V3";
 122                 regulator-min-microvolt = <3300000>;
 123                 regulator-max-microvolt = <3300000>;
 124                 regulator-always-on;
 125         };
 126
 127         reg_can_xcvr: reg-can-xcvr {
 128                 compatible = "regulator-fixed";
 129                 regulator-name = "CAN XCVR";
 130                 regulator-min-microvolt = <3300000>;
 131                 regulator-max-microvolt = <3300000>;
 132                 pinctrl-names = "default";
 133                 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 134                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 135                 enable-active-low;
 136         };
 137
 138         reg_lcd0_pwr: reg-lcd0-pwr {
 139                 compatible = "regulator-fixed";
 140                 regulator-name = "LCD0 POWER";
 141                 regulator-min-microvolt = <3300000>;
 142                 regulator-max-microvolt = <3300000>;
 143                 pinctrl-names = "default";
 144                 pinctrl-0 = <&pinctrl_lcd0_pwr>;
 145                 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 146                 enable-active-high;
 147                 regulator-boot-on;
 148         };
 149
 150         reg_lcd1_pwr: reg-lcd1-pwr {
 151                 compatible = "regulator-fixed";
 152                 regulator-name = "LCD1 POWER";
 153                 regulator-min-microvolt = <3300000>;
 154                 regulator-max-microvolt = <3300000>;
 155                 pinctrl-names = "default";
 156                 pinctrl-0 = <&pinctrl_lcd1_pwr>;
 157                 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
 158                 enable-active-high;
 159                 regulator-boot-on;
 160         };
 161
 162         reg_usbh1_vbus: reg-usbh1-vbus {
 163                 compatible = "regulator-fixed";
 164                 regulator-name = "usbh1_vbus";
 165                 regulator-min-microvolt = <5000000>;
 166                 regulator-max-microvolt = <5000000>;
 167                 pinctrl-names = "default";
 168                 pinctrl-0 = <&pinctrl_usbh1_vbus>;
 169                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 170                 enable-active-high;
 171         };
 172
 173         reg_usbotg_vbus: reg-usbotg-vbus {
 174                 compatible = "regulator-fixed";
 175                 regulator-name = "usbotg_vbus";
 176                 regulator-min-microvolt = <5000000>;
 177                 regulator-max-microvolt = <5000000>;
 178                 pinctrl-names = "default";
 179                 pinctrl-0 = <&pinctrl_usbotg_vbus>;
 180                 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 181                 enable-active-high;
 182         };
 183
 184         sound {
 185                 compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
 186                              "fsl,imx-audio-sgtl5000";
 187                 model = "sgtl5000-audio";
 188                 pinctrl-names = "default";
 189                 pinctrl-0 = <&pinctrl_audmux>;
 190                 ssi-controller = <&ssi1>;
 191                 audio-codec = <&sgtl5000>;
 192                 audio-routing =
 193                         "MIC_IN", "Mic Jack",
 194                         "Mic Jack", "Mic Bias",
 195                         "Headphone Jack", "HP_OUT";
 196                 mux-int-port = <1>;
 197                 mux-ext-port = <5>;
 198         };
 199 };
 200
 201 &audmux {
 202         status = "okay";
 203 };
 204
 205 &can1 {
 206         pinctrl-names = "default";
 207         pinctrl-0 = <&pinctrl_flexcan1>;
 208         xceiver-supply = <&reg_can_xcvr>;
 209         status = "okay";
 210 };
 211
 212 &can2 {
 213         pinctrl-names = "default";
 214         pinctrl-0 = <&pinctrl_flexcan2>;
 215         xceiver-supply = <&reg_can_xcvr>;
 216         status = "okay";
 217 };
 218
 219 &ecspi1 {
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&pinctrl_ecspi1>;
 222         fsl,spi-num-chipselects = <2>;
 223         cs-gpios = <
 224                 &gpio2 30 GPIO_ACTIVE_HIGH
 225                 &gpio3 19 GPIO_ACTIVE_HIGH
 226         >;
 227         status = "disabled";
 228
 229         spidev0: spi@0 {
 230                 compatible = "spidev";
 231                 reg = <0>;
 232                 spi-max-frequency = <54000000>;
 233         };
 234
 235         spidev1: spi@1 {
 236                 compatible = "spidev";
 237                 reg = <1>;
 238                 spi-max-frequency = <54000000>;
 239         };
 240 };
 241
 242 &fec {
 243         pinctrl-names = "default";
 244         pinctrl-0 = <&pinctrl_enet>;
 245         clocks = <&clks IMX6QDL_CLK_ENET>,
 246                  <&clks IMX6QDL_CLK_ENET>,
 247                  <&clks IMX6QDL_CLK_ENET_REF>,
 248                  <&clks IMX6QDL_CLK_ENET_REF>;
 249         clock-names = "ipg", "ahb", "ptp", "enet_out";
 250         phy-mode = "rmii";
 251         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
 252         phy-supply = <&reg_3v3_etn>;
 253         status = "okay";
 254 };
 255
 256 &gpmi {
 257         pinctrl-names = "default";
 258         pinctrl-0 = <&pinctrl_gpmi_nand>;
 259         nand-on-flash-bbt;
 260         fsl,no-blockmark-swap;
 261         status = "okay";
 262 };
 263
 264 &i2c1 {
 265         pinctrl-names = "default";
 266         pinctrl-0 = <&pinctrl_i2c1>;
 267         clock-frequency = <400000>;
 268         status = "okay";
 269
 270         ds1339: rtc@68 {
 271                 compatible = "dallas,ds1339";
 272                 reg = <0x68>;
 273         };
 274 };
 275
 276 &i2c3 {
 277         pinctrl-names = "default";
 278         pinctrl-0 = <&pinctrl_i2c3>;
 279         clock-frequency = <400000>;
 280         status = "okay";
 281
 282         sgtl5000: sgtl5000@0a {
 283                 compatible = "fsl,sgtl5000";
 284                 reg = <0x0a>;
 285                 VDDA-supply = <&reg_2v5>;
 286                 VDDIO-supply = <&reg_3v3>;
 287                 clocks = <&mclk>;
 288         };
 289
 290         polytouch: edt-ft5x06@38 {
 291                 compatible = "edt,edt-ft5x06";
 292                 reg = <0x38>;
 293                 pinctrl-names = "default";
 294                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 295                 interrupt-parent = <&gpio6>;
 296                 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
 297                 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
 298                 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 299                 linux,wakeup;
 300         };
 301
 302         touchscreen: tsc2007@48 {
 303                 compatible = "ti,tsc2007";
 304                 reg = <0x48>;
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&pinctrl_tsc2007>;
 307                 interrupt-parent = <&gpio3>;
 308                 interrupts = <26 0>;
 309                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 310                 ti,x-plate-ohms = <660>;
 311                 linux,wakeup;
 312         };
 313 };
 314
 315 &iomuxc {
 316         pinctrl-names = "default";
 317         pinctrl-0 = <&pinctrl_hog>;
 318
 319         pinctrl_hog: hoggrp {
 320                 fsl,pins = <
 321                         MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x1b0b1 /* LED */
 322                         MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x1b0b1 /* ETN PHY RESET */
 323                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */
 324                         MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* PWR BTN */
 325                 >;
 326         };
 327
 328         pinctrl_audmux: audmuxgrp {
 329                 fsl,pins = <
 330                         MX6QDL_PAD_KEY_ROW1__AUD5_RXD           0x130b0 /* SSI1_RXD */
 331                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x110b0 /* SSI1_TXD */
 332                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0 /* SSI1_CLK */
 333                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0 /* SSI1_FS */
 334                 >;
 335         };
 336
 337         pinctrl_disp0_1: disp0grp-1 {
 338                 fsl,pins = <
 339                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 340                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 341                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 342                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 343                         /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 344                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 345                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 346                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 347                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 348                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 349                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 350                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 351                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 352                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 353                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 354                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 355                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 356                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 357                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 358                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 359                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 360                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 361                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 362                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 363                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 364                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 365                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 366                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 367                 >;
 368         };
 369
 370         pinctrl_disp0_2: disp0grp-2 {
 371                 fsl,pins = <
 372                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 373                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 374                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 375                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 376                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 377                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 378                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 379                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 380                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 381                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 382                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 383                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 384                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 385                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 386                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 387                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 388                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 389                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 390                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 391                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 392                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 393                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 394                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 395                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 396                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 397                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 398                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 399                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 400                 >;
 401         };
 402
 403         pinctrl_ecspi1: ecspi1grp {
 404                 fsl,pins = <
 405                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x0b0b0
 406                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x0b0b0
 407                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x0b0b0
 408                         MX6QDL_PAD_GPIO_19__ECSPI1_RDY          0x0b0b0
 409                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x0b0b0 /* SPI CS0 */
 410                         MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x0b0b0 /* SPI CS1 */
 411                 >;
 412         };
 413
 414         pinctrl_edt_ft5x06: edt-ft5x06grp {
 415                 fsl,pins = <
 416                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x1b0b0 /* Interrupt */
 417                         MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0 /* Reset */
 418                         MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b0 /* Wake */
 419                 >;
 420         };
 421
 422         pinctrl_enet: enetgrp {
 423                 fsl,pins = <
 424                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 425                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 426                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 427                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 428                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 429                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 430                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 431                 >;
 432         };
 433
 434         pinctrl_enet_mdio: enet-mdiogrp {
 435                 fsl,pins = <
 436                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 437                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 438                 >;
 439         };
 440
 441         pinctrl_etnphy_power: etnphy-pwrgrp {
 442                 fsl,pins = <
 443                         MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b1 /* ETN PHY POWER */
 444                 >;
 445         };
 446
 447         pinctrl_flexcan1: flexcan1grp {
 448                 fsl,pins = <
 449                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 450                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 451                 >;
 452         };
 453
 454         pinctrl_flexcan2: flexcan2grp {
 455                 fsl,pins = <
 456                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 457                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 458                 >;
 459         };
 460
 461         pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 462                 fsl,pins = <
 463                         MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21       0x1b0b0 /* Flexcan XCVR enable */
 464                 >;
 465         };
 466
 467         pinctrl_gpmi_nand: gpminandgrp {
 468                 fsl,pins = <
 469                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
 470                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
 471                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
 472                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
 473                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
 474                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
 475                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
 476                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
 477                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
 478                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
 479                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
 480                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
 481                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
 482                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
 483                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
 484                 >;
 485         };
 486
 487         pinctrl_i2c1: i2c1grp {
 488                 fsl,pins = <
 489                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 490                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 491                 >;
 492         };
 493
 494         pinctrl_i2c3: i2c3grp {
 495                 fsl,pins = <
 496                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 497                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 498                 >;
 499         };
 500
 501         pinctrl_kpp: kppgrp {
 502                 fsl,pins = <
 503                         MX6QDL_PAD_GPIO_9__KEY_COL6             0x1b0b1
 504                         MX6QDL_PAD_GPIO_4__KEY_COL7             0x1b0b1
 505                         MX6QDL_PAD_KEY_COL2__KEY_COL2           0x1b0b1
 506                         MX6QDL_PAD_KEY_COL3__KEY_COL3           0x1b0b1
 507                         MX6QDL_PAD_GPIO_2__KEY_ROW6             0x1b0b1
 508                         MX6QDL_PAD_GPIO_5__KEY_ROW7             0x1b0b1
 509                         MX6QDL_PAD_KEY_ROW2__KEY_ROW2           0x1b0b1
 510                         MX6QDL_PAD_KEY_ROW3__KEY_ROW3           0x1b0b1
 511                 >;
 512         };
 513
 514         pinctrl_lcd0_pwr: lcd0-pwrgrp {
 515                 fsl,pins = <
 516                         MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x1b0b1 /* LCD Reset */
 517                 >;
 518         };
 519
 520         pinctrl_lcd1_pwr: lcd-pwrgrp {
 521                 fsl,pins = <
 522                         MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x1b0b1 /* LCD Power Enable */
 523                 >;
 524         };
 525
 526         pinctrl_pwm1: pwm1grp {
 527                 fsl,pins = <
 528                         MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 529                 >;
 530         };
 531
 532         pinctrl_pwm2: pwm2grp {
 533                 fsl,pins = <
 534                         MX6QDL_PAD_GPIO_1__PWM2_OUT             0x1b0b1
 535                 >;
 536         };
 537
 538         pinctrl_tsc2007: tsc2007grp {
 539                 fsl,pins = <
 540                         MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0 /* Interrupt */
 541                 >;
 542         };
 543
 544         pinctrl_uart1: uart1grp {
 545                 fsl,pins = <
 546                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 547                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 548                 >;
 549         };
 550
 551         pinctrl_uart1_rtscts: uart1_rtsctsgrp {
 552                 fsl,pins = <
 553                         MX6QDL_PAD_SD3_DAT1__UART1_RTS_B        0x1b0b1
 554                         MX6QDL_PAD_SD3_DAT0__UART1_CTS_B        0x1b0b1
 555                 >;
 556         };
 557
 558         pinctrl_uart2: uart2grp {
 559                 fsl,pins = <
 560                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 561                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 562                 >;
 563         };
 564
 565         pinctrl_uart2_rtscts: uart2_rtsctsgrp {
 566                 fsl,pins = <
 567                         MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
 568                         MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
 569                 >;
 570         };
 571
 572         pinctrl_uart3: uart3grp {
 573                 fsl,pins = <
 574                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 575                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 576                 >;
 577         };
 578
 579         pinctrl_uart3_rtscts: uart3_rtsctsgrp {
 580                 fsl,pins = <
 581                         MX6QDL_PAD_SD3_DAT3__UART3_CTS_B        0x1b0b1
 582                         MX6QDL_PAD_SD3_RST__UART3_RTS_B         0x1b0b1
 583                 >;
 584         };
 585
 586         pinctrl_usbh1_vbus: usbh1-vbusgrp {
 587                 fsl,pins = <
 588                         MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x1b0b0 /* USBH1_VBUSEN */
 589                 >;
 590         };
 591
 592         pinctrl_usbotg: usbotggrp {
 593                 fsl,pins = <
 594                         MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x17059
 595                 >;
 596         };
 597
 598         pinctrl_usbotg_vbus: usbotg-vbusgrp {
 599                 fsl,pins = <
 600                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0 /* USBOTG_VBUSEN */
 601                 >;
 602         };
 603
 604         pinctrl_usdhc1: usdhc1grp {
 605                 fsl,pins = <
 606                         MX6QDL_PAD_SD1_CMD__SD1_CMD             0x070b1
 607                         MX6QDL_PAD_SD1_CLK__SD1_CLK             0x070b1
 608                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x070b1
 609                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x070b1
 610                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x070b1
 611                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x070b1
 612                         MX6QDL_PAD_SD3_CMD__GPIO7_IO02          0x170b0 /* SD1 CD */
 613                 >;
 614         };
 615
 616         pinctrl_usdhc2: usdhc2grp {
 617                 fsl,pins = <
 618                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x070b1
 619                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x070b1
 620                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x070b1
 621                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x070b1
 622                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x070b1
 623                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x070b1
 624                         MX6QDL_PAD_SD3_CLK__GPIO7_IO03          0x170b0 /* SD2 CD */
 625                 >;
 626         };
 627 };
 628
 629 &kpp {
 630         pinctrl-names = "default";
 631         pinctrl-0 = <&pinctrl_kpp>;
 632         /* sample keymap */
 633         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 634         linux,keymap = <
 635                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
 636                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
 637                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
 638                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
 639                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
 640                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
 641                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
 642                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
 643                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
 644                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
 645                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
 646         >;
 647         status = "okay";
 648 };
 649
 650 &pwm1 {
 651         pinctrl-names = "default";
 652         pinctrl-0 = <&pinctrl_pwm1>;
 653         #pwm-cells = <3>;
 654         status = "disabled";
 655 };
 656
 657 &pwm2 {
 658         pinctrl-names = "default";
 659         pinctrl-0 = <&pinctrl_pwm2>;
 660         #pwm-cells = <3>;
 661         status = "okay";
 662 };
 663
 664 &ssi1 {
 665         status = "okay";
 666 };
 667
 668 &uart1 {
 669         pinctrl-names = "default";
 670         pinctrl-0 = <&pinctrl_uart1>;
 671         status = "okay";
 672 };
 673
 674 &uart2 {
 675         pinctrl-names = "default";
 676         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 677         status = "okay";
 678 };
 679
 680 &uart3 {
 681         pinctrl-names = "default";
 682         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
 683         status = "okay";
 684 };
 685
 686 &usbh1 {
 687         vbus-supply = <&reg_usbh1_vbus>;
 688         dr_mode = "host";
 689         disable-over-current;
 690         status = "okay";
 691 };
 692
 693 &usbotg {
 694         vbus-supply = <&reg_usbotg_vbus>;
 695         pinctrl-names = "default";
 696         pinctrl-0 = <&pinctrl_usbotg>;
 697         dr_mode = "peripheral";
 698         disable-over-current;
 699         status = "okay";
 700 };
 701
 702 &usdhc1 {
 703         pinctrl-names = "default";
 704         pinctrl-0 = <&pinctrl_usdhc1>;
 705         bus-width = <4>;
 706         no-1-8-v;
 707         cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
 708         fsl,wp-controller;
 709         status = "okay";
 710 };
 711
 712 &usdhc2 {
 713         pinctrl-names = "default";
 714         pinctrl-0 = <&pinctrl_usdhc2>;
 715         bus-width = <4>;
 716         no-1-8-v;
 717         cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
 718         fsl,wp-controller;
 719         status = "okay";
 720 };