2 * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/gpio/gpio.h>
21 lcdif_23bit_pins_a = &tx6_pinctrl_disp0_1;
22 lcdif_24bit_pins_a = &tx6_pinctrl_disp0_2;
27 reg_can_xcvr = ®_can_xcvr;
35 reg = <0 0>; /* will be filled by U-Boot */
42 compatible = "fixed-clock";
45 clock-frequency = <27000000>;
49 backlight: backlight@0 {
50 compatible = "pwm-backlight";
51 pwms = <&pwm2 0 500000>;
52 power-supply = <®_3v3>;
54 * a poor man's way to create an inverse 1:1 relationship
55 * between the PWM value and the actual duty cycle
57 brightness-levels = <100
58 99 98 97 96 95 94 93 92 91 90
59 89 88 87 86 85 84 83 82 81 80
60 79 78 77 76 75 74 73 72 71 70
61 69 68 67 66 65 64 63 62 61 60
62 59 58 57 56 55 54 53 52 51 50
63 49 48 47 46 45 44 43 42 41 40
64 39 38 37 36 35 34 33 32 31 30
65 29 28 27 26 25 24 23 22 21 20
66 19 18 17 16 15 14 13 12 11 10
68 default-brightness-level = <50>;
72 compatible = "pwm-backlight";
73 pwms = <&pwm1 0 500000>;
74 power-supply = <®_3v3>;
76 * a poor man's way to create a 1:1 relationship between
77 * the PWM value and the actual duty cycle
79 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
80 10 11 12 13 14 15 16 17 18 19
81 20 21 22 23 24 25 26 27 28 29
82 30 31 32 33 34 35 36 37 38 39
83 40 41 42 43 44 45 46 47 48 49
84 50 51 52 53 54 55 56 57 58 59
85 60 61 62 63 64 65 66 67 68 69
86 70 71 72 73 74 75 76 77 78 79
87 80 81 82 83 84 85 86 87 88 89
88 90 91 92 93 94 95 96 97 98 99
90 default-brightness-level = <50>;
94 display: display@di0 {
95 compatible = "fsl,imx-parallel-display";
97 interface-pix-fmt = "rgb24";
98 pinctrl-names = "default";
99 pinctrl-0 = <&tx6_pinctrl_disp0_1>;
104 clock-frequency = <25200000>;
116 pixelclk-active = <0>;
120 clock-frequency = <25200000>;
132 pixelclk-active = <0>;
136 clock-frequency = <6413760>;
148 pixelclk-active = <0>;
152 clock-frequency = <9009000>;
164 pixelclk-active = <1>;
168 clock-frequency = <33264000>;
180 pixelclk-active = <0>;
183 ET0700 { /* same as ET0500 */
184 clock-frequency = <33264000>;
196 pixelclk-active = <0>;
200 clock-frequency = <6596040>;
212 pixelclk-active = <0>;
218 compatible = "gpio-keys";
221 label = "Power Button";
222 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
223 linux,code = <KEY_POWER>;
229 compatible = "gpio-leds";
233 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
234 linux,default-trigger = "heartbeat";
239 compatible = "simple-bus";
240 #address-cells = <1>;
243 reg_3v3_etn: regulator@0 {
244 compatible = "regulator-fixed";
246 regulator-name = "3V3_ETN";
247 regulator-min-microvolt = <3300000>;
248 regulator-max-microvolt = <3300000>;
249 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
253 reg_2v5: regulator@1 {
254 compatible = "regulator-fixed";
256 regulator-name = "2V5";
257 regulator-min-microvolt = <2500000>;
258 regulator-max-microvolt = <2500000>;
262 reg_3v3: regulator@2 {
263 compatible = "regulator-fixed";
265 regulator-name = "3V3";
266 regulator-min-microvolt = <3300000>;
267 regulator-max-microvolt = <3300000>;
271 reg_can_xcvr: regulator@3 {
272 compatible = "regulator-fixed";
274 regulator-name = "CAN XCVR";
275 regulator-min-microvolt = <3300000>;
276 regulator-max-microvolt = <3300000>;
277 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_tx6qdl_flexcan_xcvr>;
283 reg_lcd_pwr0: regulator@4 {
284 compatible = "regulator-fixed";
286 regulator-name = "LCD0 POWER";
287 regulator-min-microvolt = <3300000>;
288 regulator-max-microvolt = <3300000>;
289 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
293 reg_lcd_pwr1: regulator@5 {
294 compatible = "regulator-fixed";
296 regulator-name = "LCD1 POWER";
297 regulator-min-microvolt = <3300000>;
298 regulator-max-microvolt = <3300000>;
299 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
303 reg_lcd_reset: regulator@6 {
304 compatible = "regulator-fixed";
306 regulator-name = "LCD RESET";
307 regulator-min-microvolt = <3300000>;
308 regulator-max-microvolt = <3300000>;
309 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
310 startup-delay-us = <300000>;
315 reg_usbh1_vbus: regulator@7 {
316 compatible = "regulator-fixed";
318 regulator-name = "usbh1_vbus";
319 regulator-min-microvolt = <5000000>;
320 regulator-max-microvolt = <5000000>;
321 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_tx6_usbh1_vbus>;
327 reg_usbotg_vbus: regulator@8 {
328 compatible = "regulator-fixed";
330 regulator-name = "usbotg_vbus";
331 regulator-min-microvolt = <5000000>;
332 regulator-max-microvolt = <5000000>;
333 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_tx6_usbotg_vbus>;
341 compatible = "fsl,imx6qdl-tx6qdl-sgtl5000",
342 "fsl,imx-audio-sgtl5000";
343 model = "sgtl5000-audio";
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_audmux_5>;
346 ssi-controller = <&ssi1>;
347 audio-codec = <&sgtl5000>;
349 "MIC_IN", "Mic Jack",
350 "Mic Jack", "Mic Bias",
351 "Headphone Jack", "HP_OUT";
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_flexcan1_3>;
364 xceiver-supply = <®_can_xcvr>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_flexcan2_1>;
372 xceiver-supply = <®_can_xcvr>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&pinctrl_enet_4>;
381 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
382 phy-supply = <®_3v3_etn>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_tx6_gpmi_nand>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_i2c1_1>;
396 clock-frequency = <400000>;
400 compatible = "dallas,ds1339";
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_i2c3_2>;
408 clock-frequency = <400000>;
411 touchscreen: tsc2007@48 {
412 compatible = "ti,tsc2007";
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_tsc2007_1>;
416 interrupt-parent = <&gpio3>;
418 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
419 ti,x-plate-ohms = <660>;
423 polytouch: edt-ft5x06@38 {
424 compatible = "edt,edt-ft5x06";
426 pinctrl-names = "default";
427 pinctrl-0 = <&pinctrl_edt_ft5x06_1>;
428 interrupt-parent = <&gpio6>;
430 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
431 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
434 sgtl5000: sgtl5000@0a {
435 compatible = "fsl,sgtl5000";
437 VDDA-supply = <®_2v5>;
438 VDDIO-supply = <®_3v3>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_hog>;
448 tx6_pinctrl_disp0_1: disp0grp-1 {
450 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
451 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
452 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
453 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
454 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
455 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
456 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
457 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
458 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
459 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
460 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
461 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
462 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
463 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
464 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
465 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
466 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
467 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
468 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
469 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
470 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
471 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
472 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
473 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
474 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
475 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
476 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
477 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
481 tx6_pinctrl_disp0_2: disp0grp-2 {
483 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
484 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
485 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
486 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
487 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
488 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
489 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
490 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
491 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
492 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
493 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
494 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
495 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
496 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
497 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
498 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
499 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
500 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
501 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
502 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
503 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
504 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
505 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
506 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
507 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
508 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
509 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
510 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
516 pinctrl_tx6qdl_flexcan_xcvr: flexcan-xcvrgrp-1 {
518 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
524 pinctrl_hog: hoggrp {
526 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
527 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
528 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
529 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT
530 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x1b0b0 /* SD1 CD */
531 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x1b0b0 /* SD2 CD */
532 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
533 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
534 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
540 pinctrl_kpp: kppgrp {
542 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
543 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
544 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
545 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
547 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
548 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
549 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
550 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
556 pinctrl_tx6_gpmi_nand: tx6-gpmi-nand {
558 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
559 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
560 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
561 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
562 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
563 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
564 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
565 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
566 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
567 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
568 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
569 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
570 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
571 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
572 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
578 pinctrl_tsc2007_1: tsc2007grp-1 {
580 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
584 pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 {
586 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
587 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
588 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
594 pinctrl_tx6_usbh1_vbus: tx6-usbh1-vbusgrp {
596 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
602 pinctrl_tx6_usbotg: tx6-usbotggrp {
604 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
608 pinctrl_tx6_usbotg_vbus: tx6-usbotg-vbusgrp {
610 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
617 pinctrl-names = "default";
618 pinctrl-0 = <&pinctrl_kpp>;
620 /* row/col 0,1 are mapped to KPP row/col 6,7 */
622 0x06060074 /* row 6, col 6, KEY_POWER */
623 0x06070052 /* row 6, col 7, KEY_KP0 */
624 0x0602004f /* row 6, col 2, KEY_KP1 */
625 0x06030050 /* row 6, col 3, KEY_KP2 */
626 0x07060051 /* row 7, col 6, KEY_KP3 */
627 0x0707004b /* row 7, col 7, KEY_KP4 */
628 0x0702004c /* row 7, col 2, KEY_KP5 */
629 0x0703004d /* row 7, col 3, KEY_KP6 */
630 0x02060047 /* row 2, col 6, KEY_KP7 */
631 0x02070048 /* row 2, col 7, KEY_KP8 */
632 0x02020049 /* row 2, col 2, KEY_KP9 */
639 lvds0: lvds-channel@0 {
640 fsl,data-mapping = "spwg";
641 fsl,data-width = <18>;
645 native-mode = <&lvds_timing0>;
646 lvds_timing0: hsd100pxn1 {
647 clock-frequency = <65000000>;
660 lvds1: lvds-channel@1 {
661 fsl,data-mapping = "spwg";
662 fsl,data-width = <18>;
666 native-mode = <&lvds_timing1>;
667 lvds_timing1: hsd100pxn1 {
668 clock-frequency = <65000000>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&pinctrl_pwm1_2>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&pinctrl_pwm2_1>;
695 fsl,mode = "i2s-slave";
700 pinctrl-names = "default";
701 pinctrl-0 = <&pinctrl_uart1_2>;
706 pinctrl-names = "default";
707 pinctrl-0 = <&pinctrl_uart2_3 &pinctrl_uart2_rtscts_3>;
712 pinctrl-names = "default";
713 pinctrl-0 = <&pinctrl_uart3_3 &pinctrl_uart3_rtscts_3>;
718 vbus-supply = <®_usbh1_vbus>;
720 disable-over-current;
725 vbus-supply = <®_usbotg_vbus>;
726 pinctrl-names = "default";
727 pinctrl-0 = <&pinctrl_tx6_usbotg>;
728 dr_mode = "peripheral";
729 disable-over-current;
734 pinctrl-names = "default";
735 pinctrl-0 = <&pinctrl_usdhc1_2>;
736 cd-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
741 pinctrl-names = "default";
742 pinctrl-0 = <&pinctrl_usdhc2_2>;
743 cd-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;