2 * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pwm/pwm.h>
22 lcdif_23bit_pins_a = &tx6_pinctrl_disp0_1;
23 lcdif_24bit_pins_a = &tx6_pinctrl_disp0_2;
28 reg_can_xcvr = ®_can_xcvr;
36 reg = <0 0>; /* will be filled by U-Boot */
43 compatible = "fixed-clock";
46 clock-frequency = <27000000>;
50 backlight: backlight@0 {
51 compatible = "pwm-backlight";
52 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
53 power-supply = <®_3v3>;
55 * a poor man's way to create a 1:1 relationship between
56 * the PWM value and the actual duty cycle
58 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
59 10 11 12 13 14 15 16 17 18 19
60 20 21 22 23 24 25 26 27 28 29
61 30 31 32 33 34 35 36 37 38 39
62 40 41 42 43 44 45 46 47 48 49
63 50 51 52 53 54 55 56 57 58 59
64 60 61 62 63 64 65 66 67 68 69
65 70 71 72 73 74 75 76 77 78 79
66 80 81 82 83 84 85 86 87 88 89
67 90 91 92 93 94 95 96 97 98 99
69 default-brightness-level = <50>;
73 compatible = "pwm-backlight";
74 pwms = <&pwm1 0 500000>;
75 power-supply = <®_3v3>;
77 * a poor man's way to create a 1:1 relationship between
78 * the PWM value and the actual duty cycle
80 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
81 10 11 12 13 14 15 16 17 18 19
82 20 21 22 23 24 25 26 27 28 29
83 30 31 32 33 34 35 36 37 38 39
84 40 41 42 43 44 45 46 47 48 49
85 50 51 52 53 54 55 56 57 58 59
86 60 61 62 63 64 65 66 67 68 69
87 70 71 72 73 74 75 76 77 78 79
88 80 81 82 83 84 85 86 87 88 89
89 90 91 92 93 94 95 96 97 98 99
91 default-brightness-level = <50>;
95 display: display@di0 {
96 compatible = "fsl,imx-parallel-display";
98 interface-pix-fmt = "rgb24";
99 pinctrl-names = "default";
100 pinctrl-0 = <&tx6_pinctrl_disp0_1>;
105 clock-frequency = <25200000>;
117 pixelclk-active = <0>;
121 clock-frequency = <25200000>;
133 pixelclk-active = <0>;
137 clock-frequency = <6413760>;
149 pixelclk-active = <0>;
153 clock-frequency = <9009000>;
165 pixelclk-active = <1>;
169 clock-frequency = <33264000>;
181 pixelclk-active = <0>;
184 ET0700 { /* same as ET0500 */
185 clock-frequency = <33264000>;
197 pixelclk-active = <0>;
201 clock-frequency = <6596040>;
213 pixelclk-active = <0>;
219 compatible = "gpio-keys";
222 label = "Power Button";
223 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
224 linux,code = <KEY_POWER>;
230 compatible = "gpio-leds";
234 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
235 linux,default-trigger = "heartbeat";
240 compatible = "simple-bus";
241 #address-cells = <1>;
244 reg_3v3_etn: regulator@0 {
245 compatible = "regulator-fixed";
247 regulator-name = "3V3_ETN";
248 regulator-min-microvolt = <3300000>;
249 regulator-max-microvolt = <3300000>;
250 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
254 reg_2v5: regulator@1 {
255 compatible = "regulator-fixed";
257 regulator-name = "2V5";
258 regulator-min-microvolt = <2500000>;
259 regulator-max-microvolt = <2500000>;
263 reg_3v3: regulator@2 {
264 compatible = "regulator-fixed";
266 regulator-name = "3V3";
267 regulator-min-microvolt = <3300000>;
268 regulator-max-microvolt = <3300000>;
272 reg_can_xcvr: regulator@3 {
273 compatible = "regulator-fixed";
275 regulator-name = "CAN XCVR";
276 regulator-min-microvolt = <3300000>;
277 regulator-max-microvolt = <3300000>;
278 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_tx6qdl_flexcan_xcvr>;
284 reg_lcd_pwr0: regulator@4 {
285 compatible = "regulator-fixed";
287 regulator-name = "LCD0 POWER";
288 regulator-min-microvolt = <3300000>;
289 regulator-max-microvolt = <3300000>;
290 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
294 reg_lcd_pwr1: regulator@5 {
295 compatible = "regulator-fixed";
297 regulator-name = "LCD1 POWER";
298 regulator-min-microvolt = <3300000>;
299 regulator-max-microvolt = <3300000>;
300 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
304 reg_lcd_reset: regulator@6 {
305 compatible = "regulator-fixed";
307 regulator-name = "LCD RESET";
308 regulator-min-microvolt = <3300000>;
309 regulator-max-microvolt = <3300000>;
310 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
311 startup-delay-us = <300000>;
316 reg_usbh1_vbus: regulator@7 {
317 compatible = "regulator-fixed";
319 regulator-name = "usbh1_vbus";
320 regulator-min-microvolt = <5000000>;
321 regulator-max-microvolt = <5000000>;
322 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_tx6_usbh1_vbus>;
328 reg_usbotg_vbus: regulator@8 {
329 compatible = "regulator-fixed";
331 regulator-name = "usbotg_vbus";
332 regulator-min-microvolt = <5000000>;
333 regulator-max-microvolt = <5000000>;
334 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_tx6_usbotg_vbus>;
342 compatible = "fsl,imx6qdl-tx6qdl-sgtl5000",
343 "fsl,imx-audio-sgtl5000";
344 model = "sgtl5000-audio";
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_audmux_5>;
347 ssi-controller = <&ssi1>;
348 audio-codec = <&sgtl5000>;
350 "MIC_IN", "Mic Jack",
351 "Mic Jack", "Mic Bias",
352 "Headphone Jack", "HP_OUT";
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_flexcan1_3>;
365 xceiver-supply = <®_can_xcvr>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_flexcan2_1>;
373 xceiver-supply = <®_can_xcvr>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_enet_4>;
382 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
383 phy-supply = <®_3v3_etn>;
388 pinctrl-names = "default";
389 pinctrl-0 = <&pinctrl_tx6_gpmi_nand>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_i2c1_1>;
397 clock-frequency = <400000>;
401 compatible = "dallas,ds1339";
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_i2c3_2>;
409 clock-frequency = <400000>;
412 touchscreen: tsc2007@48 {
413 compatible = "ti,tsc2007";
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_tsc2007_1>;
417 interrupt-parent = <&gpio3>;
419 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
420 ti,x-plate-ohms = <660>;
424 polytouch: edt-ft5x06@38 {
425 compatible = "edt,edt-ft5x06";
427 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_edt_ft5x06_1>;
429 interrupt-parent = <&gpio6>;
431 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
432 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
435 sgtl5000: sgtl5000@0a {
436 compatible = "fsl,sgtl5000";
438 VDDA-supply = <®_2v5>;
439 VDDIO-supply = <®_3v3>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_hog>;
449 tx6_pinctrl_disp0_1: disp0grp-1 {
451 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
452 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
453 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
454 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
455 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
456 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
457 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
458 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
459 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
460 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
461 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
462 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
463 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
464 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
465 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
466 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
467 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
468 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
469 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
470 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
471 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
472 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
473 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
474 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
475 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
476 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
477 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
478 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
482 tx6_pinctrl_disp0_2: disp0grp-2 {
484 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
485 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
486 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
487 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
488 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
489 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
490 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
491 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
492 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
493 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
494 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
495 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
496 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
497 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
498 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
499 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
500 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
501 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
502 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
503 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
504 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
505 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
506 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
507 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
508 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
509 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
510 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
511 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
517 pinctrl_tx6qdl_flexcan_xcvr: flexcan-xcvrgrp-1 {
519 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
525 pinctrl_hog: hoggrp {
527 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
528 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
529 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
530 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT
531 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x1b0b0 /* SD1 CD */
532 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x1b0b0 /* SD2 CD */
533 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
534 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
535 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
541 pinctrl_kpp: kppgrp {
543 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
544 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
545 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
546 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
548 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
549 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
550 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
551 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
557 pinctrl_tx6_gpmi_nand: tx6-gpmi-nand {
559 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
560 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
561 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
562 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
563 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
564 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
565 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
566 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
567 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
568 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
569 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
570 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
571 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
572 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
573 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
579 pinctrl_tsc2007_1: tsc2007grp-1 {
581 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
585 pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 {
587 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
588 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
589 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
595 pinctrl_tx6_usbh1_vbus: tx6-usbh1-vbusgrp {
597 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
603 pinctrl_tx6_usbotg: tx6-usbotggrp {
605 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
609 pinctrl_tx6_usbotg_vbus: tx6-usbotg-vbusgrp {
611 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
618 pinctrl-names = "default";
619 pinctrl-0 = <&pinctrl_kpp>;
621 /* row/col 0,1 are mapped to KPP row/col 6,7 */
623 0x06060074 /* row 6, col 6, KEY_POWER */
624 0x06070052 /* row 6, col 7, KEY_KP0 */
625 0x0602004f /* row 6, col 2, KEY_KP1 */
626 0x06030050 /* row 6, col 3, KEY_KP2 */
627 0x07060051 /* row 7, col 6, KEY_KP3 */
628 0x0707004b /* row 7, col 7, KEY_KP4 */
629 0x0702004c /* row 7, col 2, KEY_KP5 */
630 0x0703004d /* row 7, col 3, KEY_KP6 */
631 0x02060047 /* row 2, col 6, KEY_KP7 */
632 0x02070048 /* row 2, col 7, KEY_KP8 */
633 0x02020049 /* row 2, col 2, KEY_KP9 */
640 lvds0: lvds-channel@0 {
641 fsl,data-mapping = "spwg";
642 fsl,data-width = <18>;
646 native-mode = <&lvds_timing0>;
647 lvds_timing0: hsd100pxn1 {
648 clock-frequency = <65000000>;
661 lvds1: lvds-channel@1 {
662 fsl,data-mapping = "spwg";
663 fsl,data-width = <18>;
667 native-mode = <&lvds_timing1>;
668 lvds_timing1: hsd100pxn1 {
669 clock-frequency = <65000000>;
684 pinctrl-names = "default";
685 pinctrl-0 = <&pinctrl_pwm1_2>;
690 pinctrl-names = "default";
691 pinctrl-0 = <&pinctrl_pwm2_1>;
696 fsl,mode = "i2s-slave";
701 pinctrl-names = "default";
702 pinctrl-0 = <&pinctrl_uart1_2>;
707 pinctrl-names = "default";
708 pinctrl-0 = <&pinctrl_uart2_3 &pinctrl_uart2_rtscts_3>;
713 pinctrl-names = "default";
714 pinctrl-0 = <&pinctrl_uart3_3 &pinctrl_uart3_rtscts_3>;
719 vbus-supply = <®_usbh1_vbus>;
721 disable-over-current;
726 vbus-supply = <®_usbotg_vbus>;
727 pinctrl-names = "default";
728 pinctrl-0 = <&pinctrl_tx6_usbotg>;
729 dr_mode = "peripheral";
730 disable-over-current;
735 pinctrl-names = "default";
736 pinctrl-0 = <&pinctrl_usdhc1_2>;
737 cd-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
742 pinctrl-names = "default";
743 pinctrl-0 = <&pinctrl_usdhc2_2>;
744 cd-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;