2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
31 intc: interrupt-controller@00a01000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
37 reg = <0x00a01000 0x1000>,
46 compatible = "fsl,imx-ckil", "fixed-clock";
47 clock-frequency = <32768>;
51 compatible = "fsl,imx-ckih1", "fixed-clock";
52 clock-frequency = <0>;
56 compatible = "fsl,imx-osc", "fixed-clock";
57 clock-frequency = <24000000>;
64 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
68 dma_apbh: dma-apbh@00110000 {
69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70 reg = <0x00110000 0x2000>;
71 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
72 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
78 gpmi: gpmi-nand@00112000 {
79 compatible = "fsl,imx6q-gpmi-nand";
82 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
83 reg-names = "gpmi-nand", "bch";
84 interrupts = <0 13 0x04>, <0 15 0x04>;
85 interrupt-names = "gpmi-dma", "bch";
86 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
87 <&clks 150>, <&clks 149>;
88 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
89 "gpmi_bch_apb", "per1_bch";
92 fsl,gpmi-dma-channel = <0>;
97 compatible = "arm,cortex-a9-twd-timer";
98 reg = <0x00a00600 0x20>;
99 interrupts = <1 13 0xf01>;
103 L2: l2-cache@00a02000 {
104 compatible = "arm,pl310-cache";
105 reg = <0x00a02000 0x1000>;
106 interrupts = <0 92 0x04>;
111 aips-bus@02000000 { /* AIPS1 */
112 compatible = "fsl,aips-bus", "simple-bus";
113 #address-cells = <1>;
115 reg = <0x02000000 0x100000>;
119 compatible = "fsl,spba-bus", "simple-bus";
120 #address-cells = <1>;
122 reg = <0x02000000 0x40000>;
125 spdif: spdif@02004000 {
126 reg = <0x02004000 0x4000>;
127 interrupts = <0 52 0x04>;
130 ecspi1: ecspi@02008000 {
131 #address-cells = <1>;
133 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
134 reg = <0x02008000 0x4000>;
135 interrupts = <0 31 0x04>;
136 clocks = <&clks 112>, <&clks 112>;
137 clock-names = "ipg", "per";
141 ecspi2: ecspi@0200c000 {
142 #address-cells = <1>;
144 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
145 reg = <0x0200c000 0x4000>;
146 interrupts = <0 32 0x04>;
147 clocks = <&clks 113>, <&clks 113>;
148 clock-names = "ipg", "per";
152 ecspi3: ecspi@02010000 {
153 #address-cells = <1>;
155 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
156 reg = <0x02010000 0x4000>;
157 interrupts = <0 33 0x04>;
158 clocks = <&clks 114>, <&clks 114>;
159 clock-names = "ipg", "per";
163 ecspi4: ecspi@02014000 {
164 #address-cells = <1>;
166 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
167 reg = <0x02014000 0x4000>;
168 interrupts = <0 34 0x04>;
169 clocks = <&clks 115>, <&clks 115>;
170 clock-names = "ipg", "per";
174 uart1: serial@02020000 {
175 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
176 reg = <0x02020000 0x4000>;
177 interrupts = <0 26 0x04>;
178 clocks = <&clks 160>, <&clks 161>;
179 clock-names = "ipg", "per";
183 esai: esai@02024000 {
184 reg = <0x02024000 0x4000>;
185 interrupts = <0 51 0x04>;
189 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
190 reg = <0x02028000 0x4000>;
191 interrupts = <0 46 0x04>;
192 clocks = <&clks 178>;
193 fsl,fifo-depth = <15>;
194 fsl,ssi-dma-events = <38 37>;
199 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
200 reg = <0x0202c000 0x4000>;
201 interrupts = <0 47 0x04>;
202 clocks = <&clks 179>;
203 fsl,fifo-depth = <15>;
204 fsl,ssi-dma-events = <42 41>;
209 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
210 reg = <0x02030000 0x4000>;
211 interrupts = <0 48 0x04>;
212 clocks = <&clks 180>;
213 fsl,fifo-depth = <15>;
214 fsl,ssi-dma-events = <46 45>;
218 asrc: asrc@02034000 {
219 reg = <0x02034000 0x4000>;
220 interrupts = <0 50 0x04>;
224 reg = <0x0203c000 0x4000>;
229 reg = <0x02040000 0x3c000>;
230 interrupts = <0 3 0x04 0 12 0x04>;
233 aipstz@0207c000 { /* AIPSTZ1 */
234 reg = <0x0207c000 0x4000>;
239 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
240 reg = <0x02080000 0x4000>;
241 interrupts = <0 83 0x04>;
242 clocks = <&clks 62>, <&clks 145>;
243 clock-names = "ipg", "per";
248 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
249 reg = <0x02084000 0x4000>;
250 interrupts = <0 84 0x04>;
251 clocks = <&clks 62>, <&clks 146>;
252 clock-names = "ipg", "per";
257 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
258 reg = <0x02088000 0x4000>;
259 interrupts = <0 85 0x04>;
260 clocks = <&clks 62>, <&clks 147>;
261 clock-names = "ipg", "per";
266 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
267 reg = <0x0208c000 0x4000>;
268 interrupts = <0 86 0x04>;
269 clocks = <&clks 62>, <&clks 148>;
270 clock-names = "ipg", "per";
273 can1: flexcan@02090000 {
274 reg = <0x02090000 0x4000>;
275 interrupts = <0 110 0x04>;
278 can2: flexcan@02094000 {
279 reg = <0x02094000 0x4000>;
280 interrupts = <0 111 0x04>;
284 compatible = "fsl,imx6q-gpt";
285 reg = <0x02098000 0x4000>;
286 interrupts = <0 55 0x04>;
289 gpio1: gpio@0209c000 {
290 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
291 reg = <0x0209c000 0x4000>;
292 interrupts = <0 66 0x04 0 67 0x04>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
299 gpio2: gpio@020a0000 {
300 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
301 reg = <0x020a0000 0x4000>;
302 interrupts = <0 68 0x04 0 69 0x04>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
309 gpio3: gpio@020a4000 {
310 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
311 reg = <0x020a4000 0x4000>;
312 interrupts = <0 70 0x04 0 71 0x04>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
319 gpio4: gpio@020a8000 {
320 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
321 reg = <0x020a8000 0x4000>;
322 interrupts = <0 72 0x04 0 73 0x04>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
329 gpio5: gpio@020ac000 {
330 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
331 reg = <0x020ac000 0x4000>;
332 interrupts = <0 74 0x04 0 75 0x04>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
339 gpio6: gpio@020b0000 {
340 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
341 reg = <0x020b0000 0x4000>;
342 interrupts = <0 76 0x04 0 77 0x04>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
349 gpio7: gpio@020b4000 {
350 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
351 reg = <0x020b4000 0x4000>;
352 interrupts = <0 78 0x04 0 79 0x04>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
360 reg = <0x020b8000 0x4000>;
361 interrupts = <0 82 0x04>;
364 wdog1: wdog@020bc000 {
365 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
366 reg = <0x020bc000 0x4000>;
367 interrupts = <0 80 0x04>;
371 wdog2: wdog@020c0000 {
372 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
373 reg = <0x020c0000 0x4000>;
374 interrupts = <0 81 0x04>;
380 compatible = "fsl,imx6q-ccm";
381 reg = <0x020c4000 0x4000>;
382 interrupts = <0 87 0x04 0 88 0x04>;
386 anatop: anatop@020c8000 {
387 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
388 reg = <0x020c8000 0x1000>;
389 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
392 compatible = "fsl,anatop-regulator";
393 regulator-name = "vdd1p1";
394 regulator-min-microvolt = <800000>;
395 regulator-max-microvolt = <1375000>;
397 anatop-reg-offset = <0x110>;
398 anatop-vol-bit-shift = <8>;
399 anatop-vol-bit-width = <5>;
400 anatop-min-bit-val = <4>;
401 anatop-min-voltage = <800000>;
402 anatop-max-voltage = <1375000>;
406 compatible = "fsl,anatop-regulator";
407 regulator-name = "vdd3p0";
408 regulator-min-microvolt = <2800000>;
409 regulator-max-microvolt = <3150000>;
411 anatop-reg-offset = <0x120>;
412 anatop-vol-bit-shift = <8>;
413 anatop-vol-bit-width = <5>;
414 anatop-min-bit-val = <0>;
415 anatop-min-voltage = <2625000>;
416 anatop-max-voltage = <3400000>;
420 compatible = "fsl,anatop-regulator";
421 regulator-name = "vdd2p5";
422 regulator-min-microvolt = <2000000>;
423 regulator-max-microvolt = <2750000>;
425 anatop-reg-offset = <0x130>;
426 anatop-vol-bit-shift = <8>;
427 anatop-vol-bit-width = <5>;
428 anatop-min-bit-val = <0>;
429 anatop-min-voltage = <2000000>;
430 anatop-max-voltage = <2750000>;
433 reg_arm: regulator-vddcore@140 {
434 compatible = "fsl,anatop-regulator";
435 regulator-name = "cpu";
436 regulator-min-microvolt = <725000>;
437 regulator-max-microvolt = <1450000>;
439 anatop-reg-offset = <0x140>;
440 anatop-vol-bit-shift = <0>;
441 anatop-vol-bit-width = <5>;
442 anatop-delay-reg-offset = <0x170>;
443 anatop-delay-bit-shift = <24>;
444 anatop-delay-bit-width = <2>;
445 anatop-min-bit-val = <1>;
446 anatop-min-voltage = <725000>;
447 anatop-max-voltage = <1450000>;
450 reg_pu: regulator-vddpu@140 {
451 compatible = "fsl,anatop-regulator";
452 regulator-name = "vddpu";
453 regulator-min-microvolt = <725000>;
454 regulator-max-microvolt = <1450000>;
456 anatop-reg-offset = <0x140>;
457 anatop-vol-bit-shift = <9>;
458 anatop-vol-bit-width = <5>;
459 anatop-delay-reg-offset = <0x170>;
460 anatop-delay-bit-shift = <26>;
461 anatop-delay-bit-width = <2>;
462 anatop-min-bit-val = <1>;
463 anatop-min-voltage = <725000>;
464 anatop-max-voltage = <1450000>;
467 reg_soc: regulator-vddsoc@140 {
468 compatible = "fsl,anatop-regulator";
469 regulator-name = "vddsoc";
470 regulator-min-microvolt = <725000>;
471 regulator-max-microvolt = <1450000>;
473 anatop-reg-offset = <0x140>;
474 anatop-vol-bit-shift = <18>;
475 anatop-vol-bit-width = <5>;
476 anatop-delay-reg-offset = <0x170>;
477 anatop-delay-bit-shift = <28>;
478 anatop-delay-bit-width = <2>;
479 anatop-min-bit-val = <1>;
480 anatop-min-voltage = <725000>;
481 anatop-max-voltage = <1450000>;
485 usbphy1: usbphy@020c9000 {
486 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
487 reg = <0x020c9000 0x1000>;
488 interrupts = <0 44 0x04>;
489 clocks = <&clks 182>;
492 usbphy2: usbphy@020ca000 {
493 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
494 reg = <0x020ca000 0x1000>;
495 interrupts = <0 45 0x04>;
496 clocks = <&clks 183>;
500 compatible = "fsl,sec-v4.0-mon", "simple-bus";
501 #address-cells = <1>;
503 ranges = <0 0x020cc000 0x4000>;
506 compatible = "fsl,sec-v4.0-mon-rtc-lp";
508 interrupts = <0 19 0x04 0 20 0x04>;
512 epit1: epit@020d0000 { /* EPIT1 */
513 reg = <0x020d0000 0x4000>;
514 interrupts = <0 56 0x04>;
517 epit2: epit@020d4000 { /* EPIT2 */
518 reg = <0x020d4000 0x4000>;
519 interrupts = <0 57 0x04>;
523 compatible = "fsl,imx6q-src";
524 reg = <0x020d8000 0x4000>;
525 interrupts = <0 91 0x04 0 96 0x04>;
529 compatible = "fsl,imx6q-gpc";
530 reg = <0x020dc000 0x4000>;
531 interrupts = <0 89 0x04 0 90 0x04>;
534 gpr: iomuxc-gpr@020e0000 {
535 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
536 reg = <0x020e0000 0x38>;
539 dcic1: dcic@020e4000 {
540 reg = <0x020e4000 0x4000>;
541 interrupts = <0 124 0x04>;
544 dcic2: dcic@020e8000 {
545 reg = <0x020e8000 0x4000>;
546 interrupts = <0 125 0x04>;
549 sdma: sdma@020ec000 {
550 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
551 reg = <0x020ec000 0x4000>;
552 interrupts = <0 2 0x04>;
553 clocks = <&clks 155>, <&clks 155>;
554 clock-names = "ipg", "ahb";
555 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
559 aips-bus@02100000 { /* AIPS2 */
560 compatible = "fsl,aips-bus", "simple-bus";
561 #address-cells = <1>;
563 reg = <0x02100000 0x100000>;
567 reg = <0x02100000 0x40000>;
568 interrupts = <0 105 0x04 0 106 0x04>;
571 aipstz@0217c000 { /* AIPSTZ2 */
572 reg = <0x0217c000 0x4000>;
575 usbotg: usb@02184000 {
576 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
577 reg = <0x02184000 0x200>;
578 interrupts = <0 43 0x04>;
579 clocks = <&clks 162>;
580 fsl,usbphy = <&usbphy1>;
581 fsl,usbmisc = <&usbmisc 0>;
585 usbh1: usb@02184200 {
586 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
587 reg = <0x02184200 0x200>;
588 interrupts = <0 40 0x04>;
589 clocks = <&clks 162>;
590 fsl,usbphy = <&usbphy2>;
591 fsl,usbmisc = <&usbmisc 1>;
595 usbh2: usb@02184400 {
596 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
597 reg = <0x02184400 0x200>;
598 interrupts = <0 41 0x04>;
599 clocks = <&clks 162>;
600 fsl,usbmisc = <&usbmisc 2>;
604 usbh3: usb@02184600 {
605 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
606 reg = <0x02184600 0x200>;
607 interrupts = <0 42 0x04>;
608 clocks = <&clks 162>;
609 fsl,usbmisc = <&usbmisc 3>;
613 usbmisc: usbmisc: usbmisc@02184800 {
615 compatible = "fsl,imx6q-usbmisc";
616 reg = <0x02184800 0x200>;
617 clocks = <&clks 162>;
620 fec: ethernet@02188000 {
621 compatible = "fsl,imx6q-fec";
622 reg = <0x02188000 0x4000>;
623 interrupts = <0 118 0x04 0 119 0x04>;
624 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
625 clock-names = "ipg", "ahb", "ptp";
630 reg = <0x0218c000 0x4000>;
631 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
634 usdhc1: usdhc@02190000 {
635 compatible = "fsl,imx6q-usdhc";
636 reg = <0x02190000 0x4000>;
637 interrupts = <0 22 0x04>;
638 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
639 clock-names = "ipg", "ahb", "per";
644 usdhc2: usdhc@02194000 {
645 compatible = "fsl,imx6q-usdhc";
646 reg = <0x02194000 0x4000>;
647 interrupts = <0 23 0x04>;
648 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
649 clock-names = "ipg", "ahb", "per";
654 usdhc3: usdhc@02198000 {
655 compatible = "fsl,imx6q-usdhc";
656 reg = <0x02198000 0x4000>;
657 interrupts = <0 24 0x04>;
658 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
659 clock-names = "ipg", "ahb", "per";
664 usdhc4: usdhc@0219c000 {
665 compatible = "fsl,imx6q-usdhc";
666 reg = <0x0219c000 0x4000>;
667 interrupts = <0 25 0x04>;
668 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
669 clock-names = "ipg", "ahb", "per";
675 #address-cells = <1>;
677 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
678 reg = <0x021a0000 0x4000>;
679 interrupts = <0 36 0x04>;
680 clocks = <&clks 125>;
685 #address-cells = <1>;
687 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
688 reg = <0x021a4000 0x4000>;
689 interrupts = <0 37 0x04>;
690 clocks = <&clks 126>;
695 #address-cells = <1>;
697 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
698 reg = <0x021a8000 0x4000>;
699 interrupts = <0 38 0x04>;
700 clocks = <&clks 127>;
705 reg = <0x021ac000 0x4000>;
708 mmdc0: mmdc@021b0000 { /* MMDC0 */
709 compatible = "fsl,imx6q-mmdc";
710 reg = <0x021b0000 0x4000>;
713 mmdc1: mmdc@021b4000 { /* MMDC1 */
714 reg = <0x021b4000 0x4000>;
718 reg = <0x021b8000 0x4000>;
719 interrupts = <0 14 0x04>;
723 compatible = "fsl,imx6q-ocotp";
724 reg = <0x021bc000 0x4000>;
728 reg = <0x021c0000 0x4000>;
729 interrupts = <0 21 0x04>;
732 tzasc@021d0000 { /* TZASC1 */
733 reg = <0x021d0000 0x4000>;
734 interrupts = <0 108 0x04>;
737 tzasc@021d4000 { /* TZASC2 */
738 reg = <0x021d4000 0x4000>;
739 interrupts = <0 109 0x04>;
742 audmux: audmux@021d8000 {
743 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
744 reg = <0x021d8000 0x4000>;
748 mipi@021dc000 { /* MIPI-CSI */
749 reg = <0x021dc000 0x4000>;
752 mipi@021e0000 { /* MIPI-DSI */
753 reg = <0x021e0000 0x4000>;
757 reg = <0x021e4000 0x4000>;
758 interrupts = <0 18 0x04>;
761 uart2: serial@021e8000 {
762 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
763 reg = <0x021e8000 0x4000>;
764 interrupts = <0 27 0x04>;
765 clocks = <&clks 160>, <&clks 161>;
766 clock-names = "ipg", "per";
770 uart3: serial@021ec000 {
771 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
772 reg = <0x021ec000 0x4000>;
773 interrupts = <0 28 0x04>;
774 clocks = <&clks 160>, <&clks 161>;
775 clock-names = "ipg", "per";
779 uart4: serial@021f0000 {
780 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
781 reg = <0x021f0000 0x4000>;
782 interrupts = <0 29 0x04>;
783 clocks = <&clks 160>, <&clks 161>;
784 clock-names = "ipg", "per";
788 uart5: serial@021f4000 {
789 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
790 reg = <0x021f4000 0x4000>;
791 interrupts = <0 30 0x04>;
792 clocks = <&clks 160>, <&clks 161>;
793 clock-names = "ipg", "per";
800 compatible = "fsl,imx6q-ipu";
801 reg = <0x02400000 0x400000>;
802 interrupts = <0 6 0x4 0 5 0x4>;
803 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
804 clock-names = "bus", "di0", "di1";