arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         aliases {
  19                 ethernet0 = &fec;
  20                 can0 = &can1;
  21                 can1 = &can2;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29                 i2c0 = &i2c1;
  30                 i2c1 = &i2c2;
  31                 i2c2 = &i2c3;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 mmc3 = &usdhc4;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 serial4 = &uart5;
  41                 spi0 = &ecspi1;
  42                 spi1 = &ecspi2;
  43                 spi2 = &ecspi3;
  44                 spi3 = &ecspi4;
  45                 usbphy0 = &usbphy1;
  46                 usbphy1 = &usbphy2;
  47         };
  48
  49         intc: interrupt-controller@00a01000 {
  50                 compatible = "arm,cortex-a9-gic";
  51                 #interrupt-cells = <3>;
  52                 interrupt-controller;
  53                 reg = <0x00a01000 0x1000>,
  54                       <0x00a00100 0x100>;
  55         };
  56
  57         clocks {
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 ckil {
  62                         compatible = "fsl,imx-ckil", "fixed-clock";
  63                         #clock-cells = <0>;
  64                         clock-frequency = <32768>;
  65                 };
  66
  67                 ckih1 {
  68                         compatible = "fsl,imx-ckih1", "fixed-clock";
  69                         #clock-cells = <0>;
  70                         clock-frequency = <0>;
  71                 };
  72
  73                 osc {
  74                         compatible = "fsl,imx-osc", "fixed-clock";
  75                         #clock-cells = <0>;
  76                         clock-frequency = <24000000>;
  77                 };
  78         };
  79
  80         soc {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 compatible = "simple-bus";
  84                 interrupt-parent = <&intc>;
  85                 ranges;
  86
  87                 dma_apbh: dma-apbh@00110000 {
  88                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  89                         reg = <0x00110000 0x2000>;
  90                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  91                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  94                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  95                         #dma-cells = <1>;
  96                         dma-channels = <4>;
  97                         clocks = <&clks 106>;
  98                 };
  99
 100                 gpmi: gpmi-nand@00112000 {
 101                         compatible = "fsl,imx6q-gpmi-nand";
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 105                         reg-names = "gpmi-nand", "bch";
 106                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 107                         interrupt-names = "bch";
 108                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
 109                                  <&clks 150>, <&clks 149>;
 110                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 111                                       "gpmi_bch_apb", "per1_bch";
 112                         dmas = <&dma_apbh 0>;
 113                         dma-names = "rx-tx";
 114                         status = "disabled";
 115                 };
 116
 117                 timer@00a00600 {
 118                         compatible = "arm,cortex-a9-twd-timer";
 119                         reg = <0x00a00600 0x20>;
 120                         interrupts = <1 13 0xf01>;
 121                         clocks = <&clks 15>;
 122                 };
 123
 124                 L2: l2-cache@00a02000 {
 125                         compatible = "arm,pl310-cache";
 126                         reg = <0x00a02000 0x1000>;
 127                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 128                         cache-unified;
 129                         cache-level = <2>;
 130                         arm,tag-latency = <4 2 3>;
 131                         arm,data-latency = <4 2 3>;
 132                 };
 133
 134                 pcie: pcie@0x01000000 {
 135                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 136                         reg = <0x01ffc000 0x4000>; /* DBI */
 137                         #address-cells = <3>;
 138                         #size-cells = <2>;
 139                         device_type = "pci";
 140                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 141                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 142                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 143                         num-lanes = <1>;
 144                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 145                         interrupt-names = "msi";
 146                         #interrupt-cells = <1>;
 147                         interrupt-map-mask = <0 0 0 0x7>;
 148                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 149                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 150                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 151                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 152                         clocks = <&clks 144>, <&clks 206>, <&clks 189>;
 153                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 154                         status = "disabled";
 155                 };
 156
 157                 pmu {
 158                         compatible = "arm,cortex-a9-pmu";
 159                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 160                 };
 161
 162                 aips-bus@02000000 { /* AIPS1 */
 163                         compatible = "fsl,aips-bus", "simple-bus";
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                         reg = <0x02000000 0x100000>;
 167                         ranges;
 168
 169                         spba-bus@02000000 {
 170                                 compatible = "fsl,spba-bus", "simple-bus";
 171                                 #address-cells = <1>;
 172                                 #size-cells = <1>;
 173                                 reg = <0x02000000 0x40000>;
 174                                 ranges;
 175
 176                                 spdif: spdif@02004000 {
 177                                         compatible = "fsl,imx35-spdif";
 178                                         reg = <0x02004000 0x4000>;
 179                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 180                                         dmas = <&sdma 14 18 0>,
 181                                                <&sdma 15 18 0>;
 182                                         dma-names = "rx", "tx";
 183                                         clocks = <&clks 197>, <&clks 3>,
 184                                                  <&clks 197>, <&clks 107>,
 185                                                  <&clks 0>,   <&clks 118>,
 186                                                  <&clks 0>,  <&clks 139>,
 187                                                  <&clks 0>;
 188                                         clock-names = "core",  "rxtx0",
 189                                                       "rxtx1", "rxtx2",
 190                                                       "rxtx3", "rxtx4",
 191                                                       "rxtx5", "rxtx6",
 192                                                       "rxtx7";
 193                                         status = "disabled";
 194                                 };
 195
 196                                 ecspi1: ecspi@02008000 {
 197                                         #address-cells = <1>;
 198                                         #size-cells = <0>;
 199                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 200                                         reg = <0x02008000 0x4000>;
 201                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 202                                         clocks = <&clks 112>, <&clks 112>;
 203                                         clock-names = "ipg", "per";
 204                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 205                                         dma-names = "rx", "tx";
 206                                         status = "disabled";
 207                                 };
 208
 209                                 ecspi2: ecspi@0200c000 {
 210                                         #address-cells = <1>;
 211                                         #size-cells = <0>;
 212                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 213                                         reg = <0x0200c000 0x4000>;
 214                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 215                                         clocks = <&clks 113>, <&clks 113>;
 216                                         clock-names = "ipg", "per";
 217                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 218                                         dma-names = "rx", "tx";
 219                                         status = "disabled";
 220                                 };
 221
 222                                 ecspi3: ecspi@02010000 {
 223                                         #address-cells = <1>;
 224                                         #size-cells = <0>;
 225                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 226                                         reg = <0x02010000 0x4000>;
 227                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 228                                         clocks = <&clks 114>, <&clks 114>;
 229                                         clock-names = "ipg", "per";
 230                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 231                                         dma-names = "rx", "tx";
 232                                         status = "disabled";
 233                                 };
 234
 235                                 ecspi4: ecspi@02014000 {
 236                                         #address-cells = <1>;
 237                                         #size-cells = <0>;
 238                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 239                                         reg = <0x02014000 0x4000>;
 240                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 241                                         clocks = <&clks 115>, <&clks 115>;
 242                                         clock-names = "ipg", "per";
 243                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 244                                         dma-names = "rx", "tx";
 245                                         status = "disabled";
 246                                 };
 247
 248                                 uart1: serial@02020000 {
 249                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 250                                         reg = <0x02020000 0x4000>;
 251                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 252                                         clocks = <&clks 160>, <&clks 161>;
 253                                         clock-names = "ipg", "per";
 254                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 255                                         dma-names = "rx", "tx";
 256                                         status = "disabled";
 257                                 };
 258
 259                                 esai: esai@02024000 {
 260                                         reg = <0x02024000 0x4000>;
 261                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 262                                 };
 263
 264                                 ssi1: ssi@02028000 {
 265                                         compatible = "fsl,imx6q-ssi",
 266                                                         "fsl,imx51-ssi",
 267                                                         "fsl,imx21-ssi";
 268                                         reg = <0x02028000 0x4000>;
 269                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 270                                         clocks = <&clks 178>;
 271                                         dmas = <&sdma 37 1 0>,
 272                                                <&sdma 38 1 0>;
 273                                         dma-names = "rx", "tx";
 274                                         fsl,fifo-depth = <15>;
 275                                         fsl,ssi-dma-events = <38 37>;
 276                                         status = "disabled";
 277                                 };
 278
 279                                 ssi2: ssi@0202c000 {
 280                                         compatible = "fsl,imx6q-ssi",
 281                                                         "fsl,imx51-ssi",
 282                                                         "fsl,imx21-ssi";
 283                                         reg = <0x0202c000 0x4000>;
 284                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 285                                         clocks = <&clks 179>;
 286                                         dmas = <&sdma 41 1 0>,
 287                                                <&sdma 42 1 0>;
 288                                         dma-names = "rx", "tx";
 289                                         fsl,fifo-depth = <15>;
 290                                         fsl,ssi-dma-events = <42 41>;
 291                                         status = "disabled";
 292                                 };
 293
 294                                 ssi3: ssi@02030000 {
 295                                         compatible = "fsl,imx6q-ssi",
 296                                                         "fsl,imx51-ssi",
 297                                                         "fsl,imx21-ssi";
 298                                         reg = <0x02030000 0x4000>;
 299                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 300                                         clocks = <&clks 180>;
 301                                         dmas = <&sdma 45 1 0>,
 302                                                <&sdma 46 1 0>;
 303                                         dma-names = "rx", "tx";
 304                                         fsl,fifo-depth = <15>;
 305                                         fsl,ssi-dma-events = <46 45>;
 306                                         status = "disabled";
 307                                 };
 308
 309                                 asrc: asrc@02034000 {
 310                                         compatible = "fsl,imx6q-asrc";
 311                                         reg = <0x02034000 0x4000>;
 312                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 313                                         clocks = <&clks 107>;
 314                                         clock-names = "core";
 315                                         dmas = <&sdma 17 20 0>, <&sdma 18 20 0>, <&sdma 19 20 0>,
 316                                              <&sdma 20 20 0>, <&sdma 21 20 0>, <&sdma 22 20 0>;
 317                                         dma-names = "rxa", "rxb", "rxc",
 318                                                 "txa", "txb", "txc";
 319                                         fsl,clk-map-version = <2>;
 320                                         fsl,clk-channel-bits = <4>;
 321                                         status = "okay";
 322                                 };
 323
 324                                 spba@0203c000 {
 325                                         reg = <0x0203c000 0x4000>;
 326                                 };
 327                         };
 328
 329                         vpu: vpu@02040000 {
 330                                 compatible = "fsl,imx6-vpu";
 331                                 reg = <0x02040000 0x3c000>;
 332                                 reg-names = "vpu_regs";
 333                                 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
 334                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 335                                 clocks = <&clks 168>, <&clks 140>, <&clks 142>;
 336                                 clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
 337                                 iramsize = <0x21000>;
 338                                 iram = <&ocram>;
 339                                 resets = <&src 1>;
 340                                 pu-supply = <&reg_pu>;
 341                                 status = "disabled";
 342                         };
 343
 344                         aipstz@0207c000 { /* AIPSTZ1 */
 345                                 reg = <0x0207c000 0x4000>;
 346                         };
 347
 348                         pwm1: pwm@02080000 {
 349                                 #pwm-cells = <2>;
 350                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 351                                 reg = <0x02080000 0x4000>;
 352                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 353                                 clocks = <&clks 62>, <&clks 145>;
 354                                 clock-names = "ipg", "per";
 355                         };
 356
 357                         pwm2: pwm@02084000 {
 358                                 #pwm-cells = <2>;
 359                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 360                                 reg = <0x02084000 0x4000>;
 361                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 362                                 clocks = <&clks 62>, <&clks 146>;
 363                                 clock-names = "ipg", "per";
 364                         };
 365
 366                         pwm3: pwm@02088000 {
 367                                 #pwm-cells = <2>;
 368                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 369                                 reg = <0x02088000 0x4000>;
 370                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 371                                 clocks = <&clks 62>, <&clks 147>;
 372                                 clock-names = "ipg", "per";
 373                         };
 374
 375                         pwm4: pwm@0208c000 {
 376                                 #pwm-cells = <2>;
 377                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 378                                 reg = <0x0208c000 0x4000>;
 379                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 380                                 clocks = <&clks 62>, <&clks 148>;
 381                                 clock-names = "ipg", "per";
 382                         };
 383
 384                         can1: flexcan@02090000 {
 385                                 compatible = "fsl,imx6q-flexcan";
 386                                 reg = <0x02090000 0x4000>;
 387                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 388                                 clocks = <&clks 108>, <&clks 109>;
 389                                 clock-names = "ipg", "per";
 390                                 status = "disabled";
 391                         };
 392
 393                         can2: flexcan@02094000 {
 394                                 compatible = "fsl,imx6q-flexcan";
 395                                 reg = <0x02094000 0x4000>;
 396                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 397                                 clocks = <&clks 110>, <&clks 111>;
 398                                 clock-names = "ipg", "per";
 399                                 status = "disabled";
 400                         };
 401
 402                         gpt: gpt@02098000 {
 403                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 404                                 reg = <0x02098000 0x4000>;
 405                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 406                                 clocks = <&clks 119>, <&clks 120>;
 407                                 clock-names = "ipg", "per";
 408                         };
 409
 410                         gpio1: gpio@0209c000 {
 411                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 412                                 reg = <0x0209c000 0x4000>;
 413                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 414                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 415                                 gpio-controller;
 416                                 #gpio-cells = <2>;
 417                                 interrupt-controller;
 418                                 #interrupt-cells = <2>;
 419                         };
 420
 421                         gpio2: gpio@020a0000 {
 422                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 423                                 reg = <0x020a0000 0x4000>;
 424                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 425                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 426                                 gpio-controller;
 427                                 #gpio-cells = <2>;
 428                                 interrupt-controller;
 429                                 #interrupt-cells = <2>;
 430                         };
 431
 432                         gpio3: gpio@020a4000 {
 433                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 434                                 reg = <0x020a4000 0x4000>;
 435                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 436                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 437                                 gpio-controller;
 438                                 #gpio-cells = <2>;
 439                                 interrupt-controller;
 440                                 #interrupt-cells = <2>;
 441                         };
 442
 443                         gpio4: gpio@020a8000 {
 444                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 445                                 reg = <0x020a8000 0x4000>;
 446                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 447                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 448                                 gpio-controller;
 449                                 #gpio-cells = <2>;
 450                                 interrupt-controller;
 451                                 #interrupt-cells = <2>;
 452                         };
 453
 454                         gpio5: gpio@020ac000 {
 455                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 456                                 reg = <0x020ac000 0x4000>;
 457                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 458                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 459                                 gpio-controller;
 460                                 #gpio-cells = <2>;
 461                                 interrupt-controller;
 462                                 #interrupt-cells = <2>;
 463                         };
 464
 465                         gpio6: gpio@020b0000 {
 466                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 467                                 reg = <0x020b0000 0x4000>;
 468                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 469                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 470                                 gpio-controller;
 471                                 #gpio-cells = <2>;
 472                                 interrupt-controller;
 473                                 #interrupt-cells = <2>;
 474                         };
 475
 476                         gpio7: gpio@020b4000 {
 477                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 478                                 reg = <0x020b4000 0x4000>;
 479                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 480                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 481                                 gpio-controller;
 482                                 #gpio-cells = <2>;
 483                                 interrupt-controller;
 484                                 #interrupt-cells = <2>;
 485                         };
 486
 487                         kpp: kpp@020b8000 {
 488                                 reg = <0x020b8000 0x4000>;
 489                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 490                         };
 491
 492                         wdog1: wdog@020bc000 {
 493                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 494                                 reg = <0x020bc000 0x4000>;
 495                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 496                                 clocks = <&clks 0>;
 497                         };
 498
 499                         wdog2: wdog@020c0000 {
 500                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 501                                 reg = <0x020c0000 0x4000>;
 502                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 503                                 clocks = <&clks 0>;
 504                                 status = "disabled";
 505                         };
 506
 507                         clks: ccm@020c4000 {
 508                                 compatible = "fsl,imx6q-ccm";
 509                                 reg = <0x020c4000 0x4000>;
 510                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 511                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 512                                 #clock-cells = <1>;
 513                         };
 514
 515                         anatop: anatop@020c8000 {
 516                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 517                                 reg = <0x020c8000 0x1000>;
 518                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 519                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 520                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 521
 522                                 regulator-1p1@110 {
 523                                         compatible = "fsl,anatop-regulator";
 524                                         regulator-name = "vdd1p1";
 525                                         regulator-min-microvolt = <800000>;
 526                                         regulator-max-microvolt = <1375000>;
 527                                         regulator-always-on;
 528                                         anatop-reg-offset = <0x110>;
 529                                         anatop-vol-bit-shift = <8>;
 530                                         anatop-vol-bit-width = <5>;
 531                                         anatop-min-bit-val = <4>;
 532                                         anatop-min-voltage = <800000>;
 533                                         anatop-max-voltage = <1375000>;
 534                                 };
 535
 536                                 regulator-3p0@120 {
 537                                         compatible = "fsl,anatop-regulator";
 538                                         regulator-name = "vdd3p0";
 539                                         regulator-min-microvolt = <2800000>;
 540                                         regulator-max-microvolt = <3150000>;
 541                                         regulator-always-on;
 542                                         anatop-reg-offset = <0x120>;
 543                                         anatop-vol-bit-shift = <8>;
 544                                         anatop-vol-bit-width = <5>;
 545                                         anatop-min-bit-val = <0>;
 546                                         anatop-min-voltage = <2625000>;
 547                                         anatop-max-voltage = <3400000>;
 548                                 };
 549
 550                                 regulator-2p5@130 {
 551                                         compatible = "fsl,anatop-regulator";
 552                                         regulator-name = "vdd2p5";
 553                                         regulator-min-microvolt = <2000000>;
 554                                         regulator-max-microvolt = <2750000>;
 555                                         regulator-always-on;
 556                                         anatop-reg-offset = <0x130>;
 557                                         anatop-vol-bit-shift = <8>;
 558                                         anatop-vol-bit-width = <5>;
 559                                         anatop-min-bit-val = <0>;
 560                                         anatop-min-voltage = <2000000>;
 561                                         anatop-max-voltage = <2750000>;
 562                                 };
 563
 564                                 reg_arm: regulator-vddcore@140 {
 565                                         compatible = "fsl,anatop-regulator";
 566                                         regulator-name = "vddarm";
 567                                         regulator-min-microvolt = <725000>;
 568                                         regulator-max-microvolt = <1450000>;
 569                                         regulator-always-on;
 570                                         anatop-reg-offset = <0x140>;
 571                                         anatop-vol-bit-shift = <0>;
 572                                         anatop-vol-bit-width = <5>;
 573                                         anatop-delay-reg-offset = <0x170>;
 574                                         anatop-delay-bit-shift = <24>;
 575                                         anatop-delay-bit-width = <2>;
 576                                         anatop-min-bit-val = <1>;
 577                                         anatop-min-voltage = <725000>;
 578                                         anatop-max-voltage = <1450000>;
 579                                 };
 580
 581                                 reg_pu: regulator-vddpu@140 {
 582                                         compatible = "fsl,anatop-regulator";
 583                                         regulator-name = "vddpu";
 584                                         regulator-min-microvolt = <725000>;
 585                                         regulator-max-microvolt = <1450000>;
 586                                         anatop-reg-offset = <0x140>;
 587                                         anatop-vol-bit-shift = <9>;
 588                                         anatop-vol-bit-width = <5>;
 589                                         anatop-delay-reg-offset = <0x170>;
 590                                         anatop-delay-bit-shift = <26>;
 591                                         anatop-delay-bit-width = <2>;
 592                                         anatop-min-bit-val = <1>;
 593                                         anatop-min-voltage = <725000>;
 594                                         anatop-max-voltage = <1450000>;
 595                                 };
 596
 597                                 reg_soc: regulator-vddsoc@140 {
 598                                         compatible = "fsl,anatop-regulator";
 599                                         regulator-name = "vddsoc";
 600                                         regulator-min-microvolt = <725000>;
 601                                         regulator-max-microvolt = <1450000>;
 602                                         regulator-always-on;
 603                                         anatop-reg-offset = <0x140>;
 604                                         anatop-vol-bit-shift = <18>;
 605                                         anatop-vol-bit-width = <5>;
 606                                         anatop-delay-reg-offset = <0x170>;
 607                                         anatop-delay-bit-shift = <28>;
 608                                         anatop-delay-bit-width = <2>;
 609                                         anatop-min-bit-val = <1>;
 610                                         anatop-min-voltage = <725000>;
 611                                         anatop-max-voltage = <1450000>;
 612                                 };
 613                         };
 614
 615                         tempmon: tempmon {
 616                                 compatible = "fsl,imx6q-tempmon";
 617                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 618                                 fsl,tempmon = <&anatop>;
 619                                 fsl,tempmon-data = <&ocotp>;
 620                                 clocks = <&clks 172>;
 621                         };
 622
 623                         usbphy1: usbphy@020c9000 {
 624                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 625                                 reg = <0x020c9000 0x1000>;
 626                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 627                                 clocks = <&clks 182>;
 628                                 fsl,anatop = <&anatop>;
 629                         };
 630
 631                         usbphy2: usbphy@020ca000 {
 632                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 633                                 reg = <0x020ca000 0x1000>;
 634                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 635                                 clocks = <&clks 183>;
 636                                 fsl,anatop = <&anatop>;
 637                         };
 638
 639                         snvs@020cc000 {
 640                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 641                                 #address-cells = <1>;
 642                                 #size-cells = <1>;
 643                                 ranges = <0 0x020cc000 0x4000>;
 644
 645                                 snvs-rtc-lp@34 {
 646                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 647                                         reg = <0x34 0x58>;
 648                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 649                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 650                                 };
 651                         };
 652
 653                         epit1: epit@020d0000 { /* EPIT1 */
 654                                 reg = <0x020d0000 0x4000>;
 655                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 656                         };
 657
 658                         epit2: epit@020d4000 { /* EPIT2 */
 659                                 reg = <0x020d4000 0x4000>;
 660                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 661                         };
 662
 663                         src: src@020d8000 {
 664                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 665                                 reg = <0x020d8000 0x4000>;
 666                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 667                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 668                                 #reset-cells = <1>;
 669                         };
 670
 671                         gpc: gpc@020dc000 {
 672                                 compatible = "fsl,imx6q-gpc";
 673                                 reg = <0x020dc000 0x4000>;
 674                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 675                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 676                         };
 677
 678                         gpr: iomuxc-gpr@020e0000 {
 679                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 680                                 reg = <0x020e0000 0x38>;
 681                         };
 682
 683                         iomuxc: iomuxc@020e0000 {
 684                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 685                                 reg = <0x020e0000 0x4000>;
 686                         };
 687
 688                         ldb: ldb@020e0008 {
 689                                 #address-cells = <1>;
 690                                 #size-cells = <0>;
 691                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 692                                 gpr = <&gpr>;
 693                                 status = "disabled";
 694
 695                                 lvds-channel@0 {
 696                                         #address-cells = <1>;
 697                                         #size-cells = <0>;
 698                                         reg = <0>;
 699                                         status = "disabled";
 700
 701                                         port@0 {
 702                                                 reg = <0>;
 703
 704                                                 lvds0_mux_0: endpoint {
 705                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 706                                                 };
 707                                         };
 708
 709                                         port@1 {
 710                                                 reg = <1>;
 711
 712                                                 lvds0_mux_1: endpoint {
 713                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 714                                                 };
 715                                         };
 716                                 };
 717
 718                                 lvds-channel@1 {
 719                                         #address-cells = <1>;
 720                                         #size-cells = <0>;
 721                                         reg = <1>;
 722                                         status = "disabled";
 723
 724                                         port@0 {
 725                                                 reg = <0>;
 726
 727                                                 lvds1_mux_0: endpoint {
 728                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 729                                                 };
 730                                         };
 731
 732                                         port@1 {
 733                                                 reg = <1>;
 734
 735                                                 lvds1_mux_1: endpoint {
 736                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 737                                                 };
 738                                         };
 739                                 };
 740                         };
 741
 742                         hdmi: hdmi@0120000 {
 743                                 #address-cells = <1>;
 744                                 #size-cells = <0>;
 745                                 reg = <0x00120000 0x9000>;
 746                                 interrupts = <0 115 0x04>;
 747                                 gpr = <&gpr>;
 748                                 clocks = <&clks 123>, <&clks 124>;
 749                                 clock-names = "iahb", "isfr";
 750                                 status = "disabled";
 751
 752                                 port@0 {
 753                                         reg = <0>;
 754
 755                                         hdmi_mux_0: endpoint {
 756                                                 remote-endpoint = <&ipu1_di0_hdmi>;
 757                                         };
 758                                 };
 759
 760                                 port@1 {
 761                                         reg = <1>;
 762
 763                                         hdmi_mux_1: endpoint {
 764                                                 remote-endpoint = <&ipu1_di1_hdmi>;
 765                                         };
 766                                 };
 767                         };
 768
 769                         dcic1: dcic@020e4000 {
 770                                 reg = <0x020e4000 0x4000>;
 771                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 772                         };
 773
 774                         dcic2: dcic@020e8000 {
 775                                 reg = <0x020e8000 0x4000>;
 776                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 777                         };
 778
 779                         sdma: sdma@020ec000 {
 780                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 781                                 reg = <0x020ec000 0x4000>;
 782                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 783                                 clocks = <&clks 155>, <&clks 155>;
 784                                 clock-names = "ipg", "ahb";
 785                                 #dma-cells = <3>;
 786                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 787                         };
 788                 };
 789
 790                 aips-bus@02100000 { /* AIPS2 */
 791                         compatible = "fsl,aips-bus", "simple-bus";
 792                         #address-cells = <1>;
 793                         #size-cells = <1>;
 794                         reg = <0x02100000 0x100000>;
 795                         ranges;
 796
 797                         caam@02100000 {
 798                                 reg = <0x02100000 0x40000>;
 799                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 800                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 801                         };
 802
 803                         aipstz@0217c000 { /* AIPSTZ2 */
 804                                 reg = <0x0217c000 0x4000>;
 805                         };
 806
 807                         usbotg: usb@02184000 {
 808                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 809                                 reg = <0x02184000 0x200>;
 810                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 811                                 clocks = <&clks 162>;
 812                                 fsl,usbphy = <&usbphy1>;
 813                                 fsl,usbmisc = <&usbmisc 0>;
 814                                 status = "disabled";
 815                         };
 816
 817                         usbh1: usb@02184200 {
 818                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 819                                 reg = <0x02184200 0x200>;
 820                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 821                                 clocks = <&clks 162>;
 822                                 fsl,usbphy = <&usbphy2>;
 823                                 fsl,usbmisc = <&usbmisc 1>;
 824                                 status = "disabled";
 825                         };
 826
 827                         usbh2: usb@02184400 {
 828                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 829                                 reg = <0x02184400 0x200>;
 830                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 831                                 clocks = <&clks 162>;
 832                                 fsl,usbmisc = <&usbmisc 2>;
 833                                 status = "disabled";
 834                         };
 835
 836                         usbh3: usb@02184600 {
 837                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 838                                 reg = <0x02184600 0x200>;
 839                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 840                                 clocks = <&clks 162>;
 841                                 fsl,usbmisc = <&usbmisc 3>;
 842                                 status = "disabled";
 843                         };
 844
 845                         usbmisc: usbmisc@02184800 {
 846                                 #index-cells = <1>;
 847                                 compatible = "fsl,imx6q-usbmisc";
 848                                 reg = <0x02184800 0x200>;
 849                                 clocks = <&clks 162>;
 850                         };
 851
 852                         fec: ethernet@02188000 {
 853                                 compatible = "fsl,imx6q-fec";
 854                                 reg = <0x02188000 0x4000>;
 855                                 interrupts-extended =
 856                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 857                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 858                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 859                                 clock-names = "ipg", "ahb", "ptp";
 860                                 status = "disabled";
 861                         };
 862
 863                         mlb@0218c000 {
 864                                 reg = <0x0218c000 0x4000>;
 865                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 866                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 867                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 868                         };
 869
 870                         usdhc1: usdhc@02190000 {
 871                                 compatible = "fsl,imx6q-usdhc";
 872                                 reg = <0x02190000 0x4000>;
 873                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 874                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
 875                                 clock-names = "ipg", "ahb", "per";
 876                                 bus-width = <4>;
 877                                 status = "disabled";
 878                         };
 879
 880                         usdhc2: usdhc@02194000 {
 881                                 compatible = "fsl,imx6q-usdhc";
 882                                 reg = <0x02194000 0x4000>;
 883                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 884                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
 885                                 clock-names = "ipg", "ahb", "per";
 886                                 bus-width = <4>;
 887                                 status = "disabled";
 888                         };
 889
 890                         usdhc3: usdhc@02198000 {
 891                                 compatible = "fsl,imx6q-usdhc";
 892                                 reg = <0x02198000 0x4000>;
 893                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 894                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
 895                                 clock-names = "ipg", "ahb", "per";
 896                                 bus-width = <4>;
 897                                 status = "disabled";
 898                         };
 899
 900                         usdhc4: usdhc@0219c000 {
 901                                 compatible = "fsl,imx6q-usdhc";
 902                                 reg = <0x0219c000 0x4000>;
 903                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 904                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
 905                                 clock-names = "ipg", "ahb", "per";
 906                                 bus-width = <4>;
 907                                 status = "disabled";
 908                         };
 909
 910                         i2c1: i2c@021a0000 {
 911                                 #address-cells = <1>;
 912                                 #size-cells = <0>;
 913                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 914                                 reg = <0x021a0000 0x4000>;
 915                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 916                                 clocks = <&clks 125>;
 917                                 status = "disabled";
 918                         };
 919
 920                         i2c2: i2c@021a4000 {
 921                                 #address-cells = <1>;
 922                                 #size-cells = <0>;
 923                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 924                                 reg = <0x021a4000 0x4000>;
 925                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 926                                 clocks = <&clks 126>;
 927                                 status = "disabled";
 928                         };
 929
 930                         i2c3: i2c@021a8000 {
 931                                 #address-cells = <1>;
 932                                 #size-cells = <0>;
 933                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 934                                 reg = <0x021a8000 0x4000>;
 935                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 936                                 clocks = <&clks 127>;
 937                                 status = "disabled";
 938                         };
 939
 940                         romcp@021ac000 {
 941                                 reg = <0x021ac000 0x4000>;
 942                         };
 943
 944                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 945                                 compatible = "fsl,imx6q-mmdc";
 946                                 reg = <0x021b0000 0x4000>;
 947                         };
 948
 949                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 950                                 reg = <0x021b4000 0x4000>;
 951                         };
 952
 953                         weim: weim@021b8000 {
 954                                 compatible = "fsl,imx6q-weim";
 955                                 reg = <0x021b8000 0x4000>;
 956                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 957                                 clocks = <&clks 196>;
 958                         };
 959
 960                         ocotp: ocotp@021bc000 {
 961                                 compatible = "fsl,imx6q-ocotp", "syscon";
 962                                 reg = <0x021bc000 0x4000>;
 963                         };
 964
 965                         tzasc@021d0000 { /* TZASC1 */
 966                                 reg = <0x021d0000 0x4000>;
 967                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 968                         };
 969
 970                         tzasc@021d4000 { /* TZASC2 */
 971                                 reg = <0x021d4000 0x4000>;
 972                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 973                         };
 974
 975                         audmux: audmux@021d8000 {
 976                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 977                                 reg = <0x021d8000 0x4000>;
 978                                 status = "disabled";
 979                         };
 980
 981                         mipi_csi: mipi@021dc000 {
 982                                 reg = <0x021dc000 0x4000>;
 983                         };
 984
 985                         mipi_dsi: mipi@021e0000 {
 986                                 #address-cells = <1>;
 987                                 #size-cells = <0>;
 988                                 reg = <0x021e0000 0x4000>;
 989                                 status = "disabled";
 990
 991                                 port@0 {
 992                                         reg = <0>;
 993
 994                                         mipi_mux_0: endpoint {
 995                                                 remote-endpoint = <&ipu1_di0_mipi>;
 996                                         };
 997                                 };
 998
 999                                 port@1 {
1000                                         reg = <1>;
1001
1002                                         mipi_mux_1: endpoint {
1003                                                 remote-endpoint = <&ipu1_di1_mipi>;
1004                                         };
1005                                 };
1006                         };
1007
1008                         vdoa@021e4000 {
1009                                 reg = <0x021e4000 0x4000>;
1010                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1011                         };
1012
1013                         uart2: serial@021e8000 {
1014                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1015                                 reg = <0x021e8000 0x4000>;
1016                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1017                                 clocks = <&clks 160>, <&clks 161>;
1018                                 clock-names = "ipg", "per";
1019                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1020                                 dma-names = "rx", "tx";
1021                                 status = "disabled";
1022                         };
1023
1024                         uart3: serial@021ec000 {
1025                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1026                                 reg = <0x021ec000 0x4000>;
1027                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1028                                 clocks = <&clks 160>, <&clks 161>;
1029                                 clock-names = "ipg", "per";
1030                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1031                                 dma-names = "rx", "tx";
1032                                 status = "disabled";
1033                         };
1034
1035                         uart4: serial@021f0000 {
1036                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1037                                 reg = <0x021f0000 0x4000>;
1038                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1039                                 clocks = <&clks 160>, <&clks 161>;
1040                                 clock-names = "ipg", "per";
1041                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1042                                 dma-names = "rx", "tx";
1043                                 status = "disabled";
1044                         };
1045
1046                         uart5: serial@021f4000 {
1047                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1048                                 reg = <0x021f4000 0x4000>;
1049                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1050                                 clocks = <&clks 160>, <&clks 161>;
1051                                 clock-names = "ipg", "per";
1052                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1053                                 dma-names = "rx", "tx";
1054                                 status = "disabled";
1055                         };
1056                 };
1057
1058                 ipu1: ipu@02400000 {
1059                         #address-cells = <1>;
1060                         #size-cells = <0>;
1061                         compatible = "fsl,imx6q-ipu";
1062                         reg = <0x02400000 0x400000>;
1063                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1064                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1065                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1066                         clock-names = "bus", "di0", "di1";
1067                         resets = <&src 2>;
1068
1069                         ipu1_di0: port@2 {
1070                                 #address-cells = <1>;
1071                                 #size-cells = <0>;
1072                                 reg = <2>;
1073
1074                                 ipu1_di0_disp0: endpoint@0 {
1075                                 };
1076
1077                                 ipu1_di0_hdmi: endpoint@1 {
1078                                         remote-endpoint = <&hdmi_mux_0>;
1079                                 };
1080
1081                                 ipu1_di0_mipi: endpoint@2 {
1082                                         remote-endpoint = <&mipi_mux_0>;
1083                                 };
1084
1085                                 ipu1_di0_lvds0: endpoint@3 {
1086                                         remote-endpoint = <&lvds0_mux_0>;
1087                                 };
1088
1089                                 ipu1_di0_lvds1: endpoint@4 {
1090                                         remote-endpoint = <&lvds1_mux_0>;
1091                                 };
1092                         };
1093
1094                         ipu1_di1: port@3 {
1095                                 #address-cells = <1>;
1096                                 #size-cells = <0>;
1097                                 reg = <3>;
1098
1099                                 ipu1_di0_disp1: endpoint@0 {
1100                                 };
1101
1102                                 ipu1_di1_hdmi: endpoint@1 {
1103                                         remote-endpoint = <&hdmi_mux_1>;
1104                                 };
1105
1106                                 ipu1_di1_mipi: endpoint@2 {
1107                                         remote-endpoint = <&mipi_mux_1>;
1108                                 };
1109
1110                                 ipu1_di1_lvds0: endpoint@3 {
1111                                         remote-endpoint = <&lvds0_mux_1>;
1112                                 };
1113
1114                                 ipu1_di1_lvds1: endpoint@4 {
1115                                         remote-endpoint = <&lvds1_mux_1>;
1116                                 };
1117                         };
1118                 };
1119         };
1120 };
1121
1122
1123 &iomuxc {
1124         audmux {
1125                 pinctrl_audmux_1: audmux-1 {
1126                         fsl,pins = <
1127                                 MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x130b0
1128                                 MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x130b0
1129                                 MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x110b0
1130                                 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
1131                         >;
1132                 };
1133
1134                 pinctrl_audmux_2: audmux-2 {
1135                         fsl,pins = <
1136                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x130b0
1137                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x130b0
1138                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x110b0
1139                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
1140                         >;
1141                 };
1142
1143                 pinctrl_audmux_3: audmux-3 {
1144                         fsl,pins = <
1145                                 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC  0x130b0
1146                                 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
1147                                 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x130b0
1148                         >;
1149                 };
1150         };
1151
1152         ecspi1 {
1153                 pinctrl_ecspi1_1: ecspi1grp-1 {
1154                         fsl,pins = <
1155                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
1156                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
1157                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
1158                         >;
1159                 };
1160
1161                 pinctrl_ecspi1_2: ecspi1grp-2 {
1162                         fsl,pins = <
1163                                 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
1164                                 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
1165                                 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
1166                         >;
1167                 };
1168         };
1169
1170         ecspi3 {
1171                 pinctrl_ecspi3_1: ecspi3grp-1 {
1172                         fsl,pins = <
1173                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
1174                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
1175                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
1176                         >;
1177                 };
1178         };
1179
1180         enet {
1181                 pinctrl_enet_1: enetgrp-1 {
1182                         fsl,pins = <
1183                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
1184                                 MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
1185                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
1186                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
1187                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
1188                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
1189                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
1190                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
1191                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
1192                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
1193                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
1194                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
1195                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
1196                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
1197                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
1198                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
1199                         >;
1200                 };
1201
1202                 pinctrl_enet_2: enetgrp-2 {
1203                         fsl,pins = <
1204                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
1205                                 MX6QDL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
1206                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
1207                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
1208                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
1209                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
1210                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
1211                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
1212                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
1213                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
1214                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
1215                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
1216                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
1217                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
1218                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
1219                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
1220                         >;
1221                 };
1222
1223                 pinctrl_enet_3: enetgrp-3 {
1224                         fsl,pins = <
1225                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
1226                                 MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
1227                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
1228                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
1229                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
1230                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
1231                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
1232                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
1233                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
1234                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
1235                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
1236                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
1237                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
1238                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
1239                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
1240                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
1241                         >;
1242                 };
1243         };
1244
1245         esai {
1246                 pinctrl_esai_1: esaigrp-1 {
1247                         fsl,pins = <
1248                                 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
1249                                 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK  0x1b030
1250                                 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS     0x1b030
1251                                 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2  0x1b030
1252                                 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3   0x1b030
1253                                 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1   0x1b030
1254                                 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0    0x1b030
1255                                 MX6QDL_PAD_NANDF_CS2__ESAI_TX0       0x1b030
1256                                 MX6QDL_PAD_NANDF_CS3__ESAI_TX1       0x1b030
1257                         >;
1258                 };
1259
1260                 pinctrl_esai_2: esaigrp-2 {
1261                         fsl,pins = <
1262                                 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
1263                                 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
1264                                 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
1265                                 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
1266                                 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
1267                                 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
1268                                 MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
1269                                 MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
1270                                 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
1271                                 MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
1272                         >;
1273                 };
1274         };
1275
1276         flexcan1 {
1277                 pinctrl_flexcan1_1: flexcan1grp-1 {
1278                         fsl,pins = <
1279                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
1280                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
1281                         >;
1282                 };
1283
1284                 pinctrl_flexcan1_2: flexcan1grp-2 {
1285                         fsl,pins = <
1286                                 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
1287                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
1288                         >;
1289                 };
1290         };
1291
1292         flexcan2 {
1293                 pinctrl_flexcan2_1: flexcan2grp-1 {
1294                         fsl,pins = <
1295                                 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
1296                                 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
1297                         >;
1298                 };
1299         };
1300
1301         gpmi-nand {
1302                 pinctrl_gpmi_nand_1: gpmi-nand-1 {
1303                         fsl,pins = <
1304                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
1305                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
1306                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
1307                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
1308                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
1309                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
1310                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
1311                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
1312                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
1313                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
1314                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
1315                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
1316                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
1317                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
1318                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
1319                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
1320                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
1321                         >;
1322                 };
1323         };
1324
1325         hdmi_hdcp {
1326                 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
1327                         fsl,pins = <
1328                                 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
1329                                 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
1330                         >;
1331                 };
1332
1333                 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
1334                         fsl,pins = <
1335                                 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
1336                                 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
1337                         >;
1338                 };
1339
1340                 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
1341                         fsl,pins = <
1342                                 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL  0x4001b8b1
1343                                 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
1344                         >;
1345                 };
1346         };
1347
1348         hdmi_cec {
1349                 pinctrl_hdmi_cec_1: hdmicecgrp-1 {
1350                         fsl,pins = <
1351                                 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
1352                         >;
1353                 };
1354
1355                 pinctrl_hdmi_cec_2: hdmicecgrp-2 {
1356                         fsl,pins = <
1357                                 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
1358                         >;
1359                 };
1360         };
1361
1362         i2c1 {
1363                 pinctrl_i2c1_1: i2c1grp-1 {
1364                         fsl,pins = <
1365                                 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
1366                                 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
1367                         >;
1368                 };
1369
1370                 pinctrl_i2c1_2: i2c1grp-2 {
1371                         fsl,pins = <
1372                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
1373                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
1374                         >;
1375                 };
1376         };
1377
1378         i2c2 {
1379                 pinctrl_i2c2_1: i2c2grp-1 {
1380                         fsl,pins = <
1381                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
1382                                 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
1383                         >;
1384                 };
1385
1386                 pinctrl_i2c2_2: i2c2grp-2 {
1387                         fsl,pins = <
1388                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
1389                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
1390                         >;
1391                 };
1392
1393                 pinctrl_i2c2_3: i2c2grp-3 {
1394                         fsl,pins = <
1395                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL  0x4001b8b1
1396                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
1397                         >;
1398                 };
1399         };
1400
1401         i2c3 {
1402                 pinctrl_i2c3_1: i2c3grp-1 {
1403                         fsl,pins = <
1404                                 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
1405                                 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
1406                         >;
1407                 };
1408
1409                 pinctrl_i2c3_2: i2c3grp-2 {
1410                         fsl,pins = <
1411                                 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
1412                                 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
1413                         >;
1414                 };
1415
1416                 pinctrl_i2c3_3: i2c3grp-3 {
1417                         fsl,pins = <
1418                                 MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
1419                                 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
1420                         >;
1421                 };
1422
1423                 pinctrl_i2c3_4: i2c3grp-4 {
1424                         fsl,pins = <
1425                                 MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
1426                                 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
1427                         >;
1428                 };
1429         };
1430
1431         ipu1 {
1432                 pinctrl_ipu1_1: ipu1grp-1 {
1433                         fsl,pins = <
1434                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
1435                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
1436                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
1437                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
1438                                 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
1439                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
1440                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
1441                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
1442                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
1443                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
1444                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
1445                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
1446                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
1447                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
1448                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
1449                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
1450                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
1451                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
1452                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
1453                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
1454                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
1455                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
1456                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
1457                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
1458                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
1459                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
1460                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
1461                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
1462                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
1463                         >;
1464                 };
1465
1466                 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
1467                         fsl,pins = <
1468                                 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x80000000
1469                                 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x80000000
1470                                 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x80000000
1471                                 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x80000000
1472                                 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x80000000
1473                                 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x80000000
1474                                 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x80000000
1475                                 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x80000000
1476                                 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
1477                                 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x80000000
1478                                 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x80000000
1479                                 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x80000000
1480                         >;
1481                 };
1482
1483                 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
1484                         fsl,pins = <
1485                                 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04   0x80000000
1486                                 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05   0x80000000
1487                                 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06   0x80000000
1488                                 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07   0x80000000
1489                                 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08   0x80000000
1490                                 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09   0x80000000
1491                                 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10  0x80000000
1492                                 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11  0x80000000
1493                                 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x80000000
1494                                 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x80000000
1495                                 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x80000000
1496                                 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x80000000
1497                                 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x80000000
1498                                 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x80000000
1499                                 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x80000000
1500                                 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x80000000
1501                                 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
1502                                 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x80000000
1503                                 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x80000000
1504                         >;
1505                 };
1506         };
1507
1508         mlb {
1509                 pinctrl_mlb_1: mlbgrp-1 {
1510                         fsl,pins = <
1511                                 MX6QDL_PAD_GPIO_3__MLB_CLK  0x71
1512                                 MX6QDL_PAD_GPIO_6__MLB_SIG  0x71
1513                                 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
1514                         >;
1515                 };
1516
1517                 pinctrl_mlb_2: mlbgrp-2 {
1518                         fsl,pins = <
1519                                 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
1520                                 MX6QDL_PAD_GPIO_6__MLB_SIG    0x71
1521                                 MX6QDL_PAD_GPIO_2__MLB_DATA   0x71
1522                         >;
1523                 };
1524         };
1525
1526         pwm1 {
1527                 pinctrl_pwm1_1: pwm1grp-1 {
1528                         fsl,pins = <
1529                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
1530                         >;
1531                 };
1532         };
1533
1534         pwm3 {
1535                 pinctrl_pwm3_1: pwm3grp-1 {
1536                         fsl,pins = <
1537                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
1538                         >;
1539                 };
1540         };
1541
1542         spdif {
1543                 pinctrl_spdif_1: spdifgrp-1 {
1544                         fsl,pins = <
1545                                 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
1546                         >;
1547                 };
1548
1549                 pinctrl_spdif_2: spdifgrp-2 {
1550                         fsl,pins = <
1551                                 MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
1552                                 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1553                         >;
1554                 };
1555         };
1556
1557         uart1 {
1558                 pinctrl_uart1_1: uart1grp-1 {
1559                         fsl,pins = <
1560                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1561                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1562                         >;
1563                 };
1564         };
1565
1566         uart2 {
1567                 pinctrl_uart2_1: uart2grp-1 {
1568                         fsl,pins = <
1569                                 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1570                                 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1571                         >;
1572                 };
1573
1574                 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1575                         fsl,pins = <
1576                                 MX6QDL_PAD_EIM_D26__UART2_RX_DATA   0x1b0b1
1577                                 MX6QDL_PAD_EIM_D27__UART2_TX_DATA   0x1b0b1
1578                                 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1579                                 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1580                         >;
1581                 };
1582         };
1583
1584         uart3 {
1585                 pinctrl_uart3_1: uart3grp-1 {
1586                         fsl,pins = <
1587                                 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1588                                 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1589                                 MX6QDL_PAD_EIM_D30__UART3_CTS_B   0x1b0b1
1590                                 MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
1591                         >;
1592                 };
1593         };
1594
1595         uart4 {
1596                 pinctrl_uart4_1: uart4grp-1 {
1597                         fsl,pins = <
1598                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1599                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1600                         >;
1601                 };
1602         };
1603
1604         usbotg {
1605                 pinctrl_usbotg_1: usbotggrp-1 {
1606                         fsl,pins = <
1607                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1608                         >;
1609                 };
1610
1611                 pinctrl_usbotg_2: usbotggrp-2 {
1612                         fsl,pins = <
1613                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1614                         >;
1615                 };
1616         };
1617
1618         usbh2 {
1619                 pinctrl_usbh2_1: usbh2grp-1 {
1620                         fsl,pins = <
1621                                 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA      0x40013030
1622                                 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1623                         >;
1624                 };
1625
1626                 pinctrl_usbh2_2: usbh2grp-2 {
1627                         fsl,pins = <
1628                                 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1629                         >;
1630                 };
1631         };
1632
1633         usbh3 {
1634                 pinctrl_usbh3_1: usbh3grp-1 {
1635                         fsl,pins = <
1636                                 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1637                                 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE  0x40013030
1638                         >;
1639                 };
1640
1641                 pinctrl_usbh3_2: usbh3grp-2 {
1642                         fsl,pins = <
1643                                 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1644                         >;
1645                 };
1646         };
1647
1648         usdhc2 {
1649                 pinctrl_usdhc2_1: usdhc2grp-1 {
1650                         fsl,pins = <
1651                                 MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
1652                                 MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
1653                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1654                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1655                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1656                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1657                                 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1658                                 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1659                                 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1660                                 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1661                         >;
1662                 };
1663
1664                 pinctrl_usdhc2_2: usdhc2grp-2 {
1665                         fsl,pins = <
1666                                 MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
1667                                 MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
1668                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1669                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1670                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1671                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1672                         >;
1673                 };
1674         };
1675
1676         usdhc3 {
1677                 pinctrl_usdhc3_1: usdhc3grp-1 {
1678                         fsl,pins = <
1679                                 MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
1680                                 MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
1681                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1682                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1683                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1684                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1685                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1686                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1687                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1688                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1689                         >;
1690                 };
1691
1692                 pinctrl_usdhc3_2: usdhc3grp-2 {
1693                         fsl,pins = <
1694                                 MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
1695                                 MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
1696                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1697                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1698                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1699                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1700                         >;
1701                 };
1702         };
1703
1704         usdhc4 {
1705                 pinctrl_usdhc4_1: usdhc4grp-1 {
1706                         fsl,pins = <
1707                                 MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
1708                                 MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
1709                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1710                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1711                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1712                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1713                                 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1714                                 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1715                                 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1716                                 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1717                         >;
1718                 };
1719
1720                 pinctrl_usdhc4_2: usdhc4grp-2 {
1721                         fsl,pins = <
1722                                 MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
1723                                 MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
1724                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1725                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1726                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1727                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1728                         >;
1729                 };
1730         };
1731
1732         weim {
1733                 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1734                         fsl,pins = <
1735                                 MX6QDL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
1736                         >;
1737                 };
1738
1739                 pinctrl_weim_nor_1: weim_norgrp-1 {
1740                         fsl,pins = <
1741                                 MX6QDL_PAD_EIM_OE__EIM_OE_B     0xb0b1
1742                                 MX6QDL_PAD_EIM_RW__EIM_RW       0xb0b1
1743                                 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1744                                 /* data */
1745                                 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1746                                 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1747                                 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1748                                 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1749                                 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1750                                 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1751                                 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1752                                 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1753                                 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1754                                 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1755                                 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1756                                 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1757                                 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1758                                 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1759                                 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1760                                 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1761                                 /* address */
1762                                 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1763                                 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1764                                 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1765                                 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1766                                 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1767                                 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1768                                 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1769                                 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1770                                 MX6QDL_PAD_EIM_DA15__EIM_AD15  0xb0b1
1771                                 MX6QDL_PAD_EIM_DA14__EIM_AD14  0xb0b1
1772                                 MX6QDL_PAD_EIM_DA13__EIM_AD13  0xb0b1
1773                                 MX6QDL_PAD_EIM_DA12__EIM_AD12  0xb0b1
1774                                 MX6QDL_PAD_EIM_DA11__EIM_AD11  0xb0b1
1775                                 MX6QDL_PAD_EIM_DA10__EIM_AD10  0xb0b1
1776                                 MX6QDL_PAD_EIM_DA9__EIM_AD09   0xb0b1
1777                                 MX6QDL_PAD_EIM_DA8__EIM_AD08   0xb0b1
1778                                 MX6QDL_PAD_EIM_DA7__EIM_AD07   0xb0b1
1779                                 MX6QDL_PAD_EIM_DA6__EIM_AD06   0xb0b1
1780                                 MX6QDL_PAD_EIM_DA5__EIM_AD05   0xb0b1
1781                                 MX6QDL_PAD_EIM_DA4__EIM_AD04   0xb0b1
1782                                 MX6QDL_PAD_EIM_DA3__EIM_AD03   0xb0b1
1783                                 MX6QDL_PAD_EIM_DA2__EIM_AD02   0xb0b1
1784                                 MX6QDL_PAD_EIM_DA1__EIM_AD01   0xb0b1
1785                                 MX6QDL_PAD_EIM_DA0__EIM_AD00   0xb0b1
1786                         >;
1787                 };
1788         };
1789 };