arch/arm/boot/dts/imx6ul-tx6ul.dtsi

   1 /*
   2  * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/interrupt-controller/irq.h>
  44 #include <dt-bindings/pwm/pwm.h>
  45
  46 / {
  47         aliases {
  48                 can0 = &can2;
  49                 can1 = &can1;
  50                 display = &display;
  51                 i2c0 = &i2c2;
  52                 i2c1 = &i2c_gpio;
  53                 i2c2 = &i2c1;
  54                 i2c3 = &i2c3;
  55                 i2c4 = &i2c4;
  56                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  57                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  58                 pwm0 = &pwm5;
  59                 reg_can_xcvr = &reg_can_xcvr;
  60                 serial2 = &uart5;
  61                 serial4 = &uart3;
  62                 spi0 = &ecspi2;
  63                 spi1 = &spi_gpio;
  64                 stk5led = &user_led;
  65                 usbh1 = &usbotg2;
  66                 usbotg = &usbotg1;
  67         };
  68
  69         chosen {
  70                 stdout-path = &uart1;
  71         };
  72
  73         memory {
  74                 reg = <0 0>; /* will be filled by U-Boot */
  75         };
  76
  77         clocks {
  78                 mclk: mclk {
  79                         compatible = "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <26000000>;
  82                 };
  83         };
  84
  85         backlight: backlight {
  86                 compatible = "pwm-backlight";
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pinctrl_lcd_rst>;
  89                 enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
  90                 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
  91                 power-supply = <&reg_lcd_pwr>;
  92                 /*
  93                  * a poor man's way to create a 1:1 relationship between
  94                  * the PWM value and the actual duty cycle
  95                  */
  96                 brightness-levels = < 0  1  2  3  4  5  6  7  8  9
  97                                      10 11 12 13 14 15 16 17 18 19
  98                                      20 21 22 23 24 25 26 27 28 29
  99                                      30 31 32 33 34 35 36 37 38 39
 100                                      40 41 42 43 44 45 46 47 48 49
 101                                      50 51 52 53 54 55 56 57 58 59
 102                                      60 61 62 63 64 65 66 67 68 69
 103                                      70 71 72 73 74 75 76 77 78 79
 104                                      80 81 82 83 84 85 86 87 88 89
 105                                      90 91 92 93 94 95 96 97 98 99
 106                                     100>;
 107                 default-brightness-level = <50>;
 108         };
 109
 110         gpio-keys {
 111                 compatible = "gpio-keys";
 112         };
 113
 114         i2c_gpio: i2c-gpio {
 115                 compatible = "i2c-gpio";
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118                 pinctrl-names = "default";
 119                 pinctrl-0 = <&pinctrl_i2c_gpio>;
 120                 gpios = <
 121                         &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
 122                         &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
 123                 >;
 124                 clock-frequency = <400000>;
 125                 status = "okay";
 126
 127                 ds1339: rtc@68 {
 128                         compatible = "dallas,ds1339";
 129                         reg = <0x68>;
 130                         status = "disabled";
 131                 };
 132         };
 133
 134         leds {
 135                 compatible = "gpio-leds";
 136
 137                 user_led: user {
 138                         label = "Heartbeat";
 139                         pinctrl-names = "default";
 140                         pinctrl-0 = <&pinctrl_led>;
 141                         gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 142                         linux,default-trigger = "heartbeat";
 143                 };
 144         };
 145
 146         reg_3v3_etn: regulator-3v3etn {
 147                 compatible = "regulator-fixed";
 148                 regulator-name = "3V3_ETN";
 149                 regulator-min-microvolt = <3300000>;
 150                 regulator-max-microvolt = <3300000>;
 151                 pinctrl-names = "default";
 152                 pinctrl-0 = <&pinctrl_etnphy_power>;
 153                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
 154                 enable-active-high;
 155         };
 156
 157         reg_2v5: regulator-2v5 {
 158                 compatible = "regulator-fixed";
 159                 regulator-name = "2V5";
 160                 regulator-min-microvolt = <2500000>;
 161                 regulator-max-microvolt = <2500000>;
 162                 regulator-always-on;
 163         };
 164
 165         reg_3v3: regulator-3v3 {
 166                 compatible = "regulator-fixed";
 167                 regulator-name = "3V3";
 168                 regulator-min-microvolt = <3300000>;
 169                 regulator-max-microvolt = <3300000>;
 170                 regulator-always-on;
 171         };
 172
 173         reg_can_xcvr: regulator-canxcvr {
 174                 compatible = "regulator-fixed";
 175                 regulator-name = "CAN XCVR";
 176                 regulator-min-microvolt = <3300000>;
 177                 regulator-max-microvolt = <3300000>;
 178                 pinctrl-names = "default";
 179                 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 180                 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
 181                 enable-active-low;
 182         };
 183
 184         reg_lcd_pwr: regulator-lcdpwr {
 185                 compatible = "regulator-fixed";
 186                 regulator-name = "LCD POWER";
 187                 regulator-min-microvolt = <3300000>;
 188                 regulator-max-microvolt = <3300000>;
 189                 pinctrl-names = "default";
 190                 pinctrl-0 = <&pinctrl_lcd_pwr>;
 191                 gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
 192                 enable-active-high;
 193                 regulator-boot-on;
 194                 regulator-always-on;
 195         };
 196
 197         reg_usbh1_vbus: regulator-usbh1vbus {
 198                 compatible = "regulator-fixed";
 199                 regulator-name = "usbh1_vbus";
 200                 regulator-min-microvolt = <5000000>;
 201                 regulator-max-microvolt = <5000000>;
 202                 pinctrl-names = "default";
 203                 pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
 204                 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 205                 enable-active-high;
 206         };
 207
 208         reg_usbotg_vbus: regulator-usbotgvbus {
 209                 compatible = "regulator-fixed";
 210                 regulator-name = "usbotg_vbus";
 211                 regulator-min-microvolt = <5000000>;
 212                 regulator-max-microvolt = <5000000>;
 213                 pinctrl-names = "default";
 214                 pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
 215                 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 216                 enable-active-high;
 217         };
 218
 219         spi_gpio: spi-gpio {
 220                 #address-cells = <1>;
 221                 #size-cells = <0>;
 222                 compatible = "spi-gpio";
 223                 pinctrl-names = "default";
 224                 pinctrl-0 = <&pinctrl_spi_gpio>;
 225                 gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
 226                 gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
 227                 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 228                 num-chipselects = <2>;
 229                 cs-gpios = <
 230                         &gpio1 29 GPIO_ACTIVE_HIGH
 231                         &gpio1 10 GPIO_ACTIVE_HIGH
 232                 >;
 233                 status = "disabled";
 234
 235                 spi@0 {
 236                         compatible = "spidev";
 237                         reg = <0>;
 238                         spi-max-frequency = <660000>;
 239                 };
 240
 241                 spi@1 {
 242                         compatible = "spidev";
 243                         reg = <1>;
 244                         spi-max-frequency = <660000>;
 245                 };
 246         };
 247
 248         sound {
 249                 compatible = "karo,imx6ul-tx6ul-sgtl5000",
 250                              "simple-audio-card";
 251                 simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
 252                 simple-audio-card,format = "i2s";
 253                 simple-audio-card,bitclock-master = <&codec_dai>;
 254                 simple-audio-card,frame-master = <&codec_dai>;
 255                 simple-audio-card,widgets =
 256                         "Microphone", "Mic Jack",
 257                         "Line", "Line In",
 258                         "Line", "Line Out",
 259                         "Headphone", "Headphone Jack";
 260                 simple-audio-card,routing =
 261                         "MIC_IN", "Mic Jack",
 262                         "Mic Jack", "Mic Bias",
 263                         "Headphone Jack", "HP_OUT";
 264
 265                 cpu_dai: simple-audio-card,cpu {
 266                         sound-dai = <&sai2>;
 267                 };
 268
 269                 codec_dai: simple-audio-card,codec {
 270                         sound-dai = <&sgtl5000>;
 271                 };
 272         };
 273 };
 274
 275 &can1 {
 276         pinctrl-names = "default";
 277         pinctrl-0 = <&pinctrl_flexcan1>;
 278         xceiver-supply = <&reg_can_xcvr>;
 279         status = "okay";
 280 };
 281
 282 &can2 {
 283         pinctrl-names = "default";
 284         pinctrl-0 = <&pinctrl_flexcan2>;
 285         xceiver-supply = <&reg_can_xcvr>;
 286         status = "okay";
 287 };
 288
 289 &ecspi2 {
 290         pinctrl-names = "default";
 291         pinctrl-0 = <&pinctrl_ecspi2>;
 292         fsl,spi-num-chipselects = <2>;
 293         cs-gpios = <
 294                 &gpio1 29 GPIO_ACTIVE_HIGH
 295                 &gpio1 10 GPIO_ACTIVE_HIGH
 296         >;
 297         status = "disabled";
 298
 299         spidev0: spi@0 {
 300                 compatible = "spidev";
 301                 reg = <0>;
 302                 spi-max-frequency = <60000000>;
 303         };
 304
 305         spidev1: spi@1 {
 306                 compatible = "spidev";
 307                 reg = <1>;
 308                 spi-max-frequency = <60000000>;
 309         };
 310 };
 311
 312 &fec1 {
 313         pinctrl-names = "default";
 314         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
 315         phy-mode = "rmii";
 316         phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
 317         phy-supply = <&reg_3v3_etn>;
 318         phy-handle = <&etnphy0>;
 319         status = "okay";
 320
 321         mdio {
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324
 325                 etnphy0: ethernet-phy@0 {
 326                         compatible = "ethernet-phy-ieee802.3-c22";
 327                         reg = <0>;
 328                         pinctrl-names = "default";
 329                         pinctrl-0 = <&pinctrl_etnphy0_int>;
 330                         interrupt-parent = <&gpio5>;
 331                         interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
 332                         status = "okay";
 333                 };
 334
 335                 etnphy1: ethernet-phy@2 {
 336                         compatible = "ethernet-phy-ieee802.3-c22";
 337                         reg = <2>;
 338                         pinctrl-names = "default";
 339                         pinctrl-0 = <&pinctrl_etnphy1_int>;
 340                         interrupt-parent = <&gpio4>;
 341                         interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
 342                         status = "okay";
 343                 };
 344         };
 345 };
 346
 347 &fec2 {
 348         pinctrl-names = "default";
 349         pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
 350         phy-mode = "rmii";
 351         phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
 352         phy-supply = <&reg_3v3_etn>;
 353         phy-handle = <&etnphy1>;
 354         status = "disabled";
 355 };
 356
 357 &gpmi {
 358         pinctrl-names = "default";
 359         pinctrl-0 = <&pinctrl_gpmi_nand>;
 360         nand-on-flash-bbt;
 361         fsl,no-blockmark-swap;
 362         status = "okay";
 363 };
 364
 365 &i2c2 {
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&pinctrl_i2c2>;
 368         clock-frequency = <400000>;
 369         status = "okay";
 370
 371         sgtl5000: codec@0a {
 372                 compatible = "fsl,sgtl5000";
 373                 reg = <0x0a>;
 374                 #sound-dai-cells = <0>;
 375                 VDDA-supply = <&reg_2v5>;
 376                 VDDIO-supply = <&reg_3v3>;
 377                 clocks = <&mclk>;
 378         };
 379
 380         polytouch: polytouch@38 {
 381                 compatible = "edt,edt-ft5x06";
 382                 reg = <0x38>;
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 385                 interrupt-parent = <&gpio5>;
 386                 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
 387                 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
 388                 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
 389                 wakeup-source;
 390         };
 391
 392         touchscreen: touchscreen@48 {
 393                 compatible = "ti,tsc2007";
 394                 reg = <0x48>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&pinctrl_tsc2007>;
 397                 interrupt-parent = <&gpio3>;
 398                 interrupts = <26 IRQ_TYPE_NONE>;
 399                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 400                 ti,x-plate-ohms = <660>;
 401                 wakeup-source;
 402         };
 403 };
 404
 405 &kpp {
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&pinctrl_kpp>;
 408         /* sample keymap */
 409         /* row/col 0..3 are mapped to KPP row/col 4..7 */
 410         linux,keymap = <
 411                 MATRIX_KEY(4, 4, KEY_POWER)
 412                 MATRIX_KEY(4, 5, KEY_KP0)
 413                 MATRIX_KEY(4, 6, KEY_KP1)
 414                 MATRIX_KEY(4, 7, KEY_KP2)
 415                 MATRIX_KEY(5, 4, KEY_KP3)
 416                 MATRIX_KEY(5, 5, KEY_KP4)
 417                 MATRIX_KEY(5, 6, KEY_KP5)
 418                 MATRIX_KEY(5, 7, KEY_KP6)
 419                 MATRIX_KEY(6, 4, KEY_KP7)
 420                 MATRIX_KEY(6, 5, KEY_KP8)
 421                 MATRIX_KEY(6, 6, KEY_KP9)
 422         >;
 423         status = "okay";
 424 };
 425
 426 &lcdif {
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&pinctrl_disp0_1>;
 429         lcd-supply = <&reg_lcd_pwr>;
 430         display = <&display>;
 431         status = "okay";
 432
 433         display: display@di0 {
 434                 bits-per-pixel = <32>;
 435                 bus-width = <24>;
 436                 status = "okay";
 437
 438                 display-timings {
 439                         VGA {
 440                                 clock-frequency = <25200000>;
 441                                 hactive = <640>;
 442                                 vactive = <480>;
 443                                 hback-porch = <48>;
 444                                 hsync-len = <96>;
 445                                 hfront-porch = <16>;
 446                                 vback-porch = <31>;
 447                                 vsync-len = <2>;
 448                                 vfront-porch = <12>;
 449                                 hsync-active = <0>;
 450                                 vsync-active = <0>;
 451                                 de-active = <1>;
 452                                 pixelclk-active = <1>;
 453                         };
 454
 455                         ETV570 {
 456                                 clock-frequency = <25200000>;
 457                                 hactive = <640>;
 458                                 vactive = <480>;
 459                                 hback-porch = <114>;
 460                                 hsync-len = <30>;
 461                                 hfront-porch = <16>;
 462                                 vback-porch = <32>;
 463                                 vsync-len = <3>;
 464                                 vfront-porch = <10>;
 465                                 hsync-active = <0>;
 466                                 vsync-active = <0>;
 467                                 de-active = <1>;
 468                                 pixelclk-active = <1>;
 469                         };
 470
 471                         ET0350 {
 472                                 clock-frequency = <6413760>;
 473                                 hactive = <320>;
 474                                 vactive = <240>;
 475                                 hback-porch = <34>;
 476                                 hsync-len = <34>;
 477                                 hfront-porch = <20>;
 478                                 vback-porch = <15>;
 479                                 vsync-len = <3>;
 480                                 vfront-porch = <4>;
 481                                 hsync-active = <0>;
 482                                 vsync-active = <0>;
 483                                 de-active = <1>;
 484                                 pixelclk-active = <1>;
 485                         };
 486
 487                         ET0430 {
 488                                 clock-frequency = <9009000>;
 489                                 hactive = <480>;
 490                                 vactive = <272>;
 491                                 hback-porch = <2>;
 492                                 hsync-len = <41>;
 493                                 hfront-porch = <2>;
 494                                 vback-porch = <2>;
 495                                 vsync-len = <10>;
 496                                 vfront-porch = <2>;
 497                                 hsync-active = <0>;
 498                                 vsync-active = <0>;
 499                                 de-active = <1>;
 500                                 pixelclk-active = <0>;
 501                         };
 502
 503                         ET0500 {
 504                                 clock-frequency = <33264000>;
 505                                 hactive = <800>;
 506                                 vactive = <480>;
 507                                 hback-porch = <88>;
 508                                 hsync-len = <128>;
 509                                 hfront-porch = <40>;
 510                                 vback-porch = <33>;
 511                                 vsync-len = <2>;
 512                                 vfront-porch = <10>;
 513                                 hsync-active = <0>;
 514                                 vsync-active = <0>;
 515                                 de-active = <1>;
 516                                 pixelclk-active = <1>;
 517                         };
 518
 519                         ET0700 { /* same as ET0500 */
 520                                 clock-frequency = <33264000>;
 521                                 hactive = <800>;
 522                                 vactive = <480>;
 523                                 hback-porch = <88>;
 524                                 hsync-len = <128>;
 525                                 hfront-porch = <40>;
 526                                 vback-porch = <33>;
 527                                 vsync-len = <2>;
 528                                 vfront-porch = <10>;
 529                                 hsync-active = <0>;
 530                                 vsync-active = <0>;
 531                                 de-active = <1>;
 532                                 pixelclk-active = <1>;
 533                         };
 534
 535                         ETQ570 {
 536                                 clock-frequency = <6596040>;
 537                                 hactive = <320>;
 538                                 vactive = <240>;
 539                                 hback-porch = <38>;
 540                                 hsync-len = <30>;
 541                                 hfront-porch = <30>;
 542                                 vback-porch = <16>;
 543                                 vsync-len = <3>;
 544                                 vfront-porch = <4>;
 545                                 hsync-active = <0>;
 546                                 vsync-active = <0>;
 547                                 de-active = <1>;
 548                                 pixelclk-active = <1>;
 549                         };
 550                 };
 551         };
 552 };
 553
 554 &pwm5 {
 555         pinctrl-names = "default";
 556         pinctrl-0 = <&pinctrl_pwm5>;
 557         #pwm-cells = <3>;
 558         status = "okay";
 559 };
 560
 561 &sai2 {
 562         pinctrl-names = "default";
 563         pinctrl-0 = <&pinctrl_sai2>;
 564         status = "okay";
 565 };
 566
 567 &uart1 {
 568         pinctrl-names = "default";
 569         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
 570         fsl,uart-has-rtscts;
 571         status = "okay";
 572 };
 573
 574 &uart2 {
 575         pinctrl-names = "default";
 576         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 577         fsl,uart-has-rtscts;
 578         status = "okay";
 579 };
 580
 581 &uart5 {
 582         pinctrl-names = "default";
 583         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
 584         fsl,uart-has-rtscts;
 585         status = "okay";
 586 };
 587
 588 &usbotg1 {
 589         vbus-supply = <&reg_usbotg_vbus>;
 590         dr_mode = "peripheral";
 591         disable-over-current;
 592         status = "okay";
 593 };
 594
 595 &usbotg2 {
 596         vbus-supply = <&reg_usbh1_vbus>;
 597         dr_mode = "host";
 598         disable-over-current;
 599         status = "okay";
 600 };
 601
 602 &usdhc1 {
 603         pinctrl-names = "default";
 604         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
 605         bus-width = <4>;
 606         no-1-8-v;
 607         cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
 608         fsl,wp-controller;
 609         status = "okay";
 610 };
 611
 612 &iomuxc {
 613         pinctrl-names = "default";
 614         pinctrl-0 = <&pinctrl_hog>;
 615
 616         pinctrl_hog: hoggrp {
 617         };
 618
 619         pinctrl_led: ledgrp {
 620                 fsl,pins = <
 621                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
 622                 >;
 623         };
 624
 625         pinctrl_disp0_1: disp0grp-1 {
 626                 fsl,pins = <
 627                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 628                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 629                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 630                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 631                         /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
 632                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 633                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 634                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 635                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 636                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 637                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 638                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 639                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 640                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 641                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 642                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 643                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 644                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 645                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 646                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 647                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 648                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 649                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 650                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 651                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 652                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 653                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 654                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 655                 >;
 656         };
 657
 658         pinctrl_disp0_2: disp0grp-2 {
 659                 fsl,pins = <
 660                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 661                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 662                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 663                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 664                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
 665                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
 666                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 667                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 668                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 669                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 670                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 671                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 672                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
 673                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
 674                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 675                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 676                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 677                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 678                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 679                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 680                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
 681                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
 682                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 683                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 684                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 685                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 686                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 687                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 688                 >;
 689         };
 690
 691         pinctrl_ecspi2: ecspi2grp {
 692                 fsl,pins = <
 693                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 694                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 695                         MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
 696                         MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
 697                         MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
 698                 >;
 699         };
 700
 701         pinctrl_edt_ft5x06: edt-ft5x06grp {
 702                 fsl,pins = <
 703                         MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
 704                         MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
 705                         MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
 706                 >;
 707         };
 708
 709         pinctrl_enet1: enet1grp {
 710                 fsl,pins = <
 711                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
 712                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
 713                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x000b0
 714                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x000b0
 715                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x000b0
 716                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
 717                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
 718                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x400000b1
 719                 >;
 720         };
 721
 722         pinctrl_enet2: enet2grp {
 723                 fsl,pins = <
 724                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
 725                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
 726                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x000b0
 727                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x000b0
 728                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x000b0
 729                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
 730                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
 731                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x400000b1
 732                 >;
 733         };
 734
 735         pinctrl_enet1_mdio: enet1-mdiogrp {
 736                 fsl,pins = <
 737                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
 738                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 739                 >;
 740         };
 741
 742         pinctrl_etnphy_power: etnphy-pwrgrp {
 743                 fsl,pins = <
 744                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
 745                 >;
 746         };
 747
 748         pinctrl_etnphy0_int: etnphy-intgrp-0 {
 749                 fsl,pins = <
 750                         MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
 751                 >;
 752         };
 753
 754         pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
 755                 fsl,pins = <
 756                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
 757                 >;
 758         };
 759
 760         pinctrl_etnphy1_int: etnphy-intgrp-1 {
 761                 fsl,pins = <
 762                         MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x0b0b0 /* ETN PHY INT */
 763                 >;
 764         };
 765
 766         pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
 767                 fsl,pins = <
 768                         MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x0b0b0 /* ETN PHY RESET */
 769                 >;
 770         };
 771
 772         pinctrl_flexcan1: flexcan1grp {
 773                 fsl,pins = <
 774                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x0b0b0
 775                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x0b0b0
 776                 >;
 777         };
 778
 779         pinctrl_flexcan2: flexcan2grp {
 780                 fsl,pins = <
 781                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x0b0b0
 782                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x0b0b0
 783                 >;
 784         };
 785
 786         pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 787                 fsl,pins = <
 788                         MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
 789                 >;
 790         };
 791
 792         pinctrl_gpmi_nand: gpminandgrp {
 793                 fsl,pins = <
 794                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 795                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 796                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 797                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 798                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 799                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 800                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 801                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 802                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 803                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 804                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 805                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 806                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 807                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 808                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 809                 >;
 810         };
 811
 812         pinctrl_i2c_gpio: i2c-gpiogrp {
 813                 fsl,pins = <
 814                         MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
 815                         MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
 816                 >;
 817         };
 818
 819         pinctrl_i2c2: i2c2grp {
 820                 fsl,pins = <
 821                         MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
 822                         MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
 823                 >;
 824         };
 825
 826         pinctrl_kpp: kppgrp {
 827                 fsl,pins = <
 828                         MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
 829                         MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
 830                         MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
 831                         MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
 832                         MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
 833                         MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
 834                         MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
 835                         MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
 836                 >;
 837         };
 838
 839         pinctrl_lcd_pwr: lcd-pwrgrp {
 840                 fsl,pins = <
 841                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
 842                 >;
 843         };
 844
 845         pinctrl_lcd_rst: lcd-rstgrp {
 846                 fsl,pins = <
 847                         MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
 848                 >;
 849         };
 850
 851         pinctrl_pwm5: pwm5grp {
 852                 fsl,pins = <
 853                         MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
 854                 >;
 855         };
 856
 857         pinctrl_sai2: sai2grp {
 858                 fsl,pins = <
 859                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
 860                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
 861                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
 862                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
 863                 >;
 864         };
 865
 866         pinctrl_spi_gpio: spi-gpiogrp {
 867                 fsl,pins = <
 868                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
 869                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
 870                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
 871                         MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
 872                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
 873                 >;
 874         };
 875
 876         pinctrl_tsc2007: tsc2007grp {
 877                 fsl,pins = <
 878                         MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
 879                 >;
 880         };
 881
 882         pinctrl_uart1: uart1grp {
 883                 fsl,pins = <
 884                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
 885                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
 886                 >;
 887         };
 888
 889         pinctrl_uart1_rtscts: uart1-rtsctsgrp {
 890                 fsl,pins = <
 891                         MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
 892                         MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
 893                 >;
 894         };
 895
 896         pinctrl_uart2: uart2grp {
 897                 fsl,pins = <
 898                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
 899                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
 900                 >;
 901         };
 902
 903         pinctrl_uart2_rtscts: uart2-rtsctsgrp {
 904                 fsl,pins = <
 905                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
 906                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
 907                 >;
 908         };
 909
 910         pinctrl_uart5: uart5grp {
 911                 fsl,pins = <
 912                         MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
 913                         MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
 914                 >;
 915         };
 916
 917         pinctrl_uart5_rtscts: uart5-rtsctsgrp {
 918                 fsl,pins = <
 919                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
 920                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
 921                 >;
 922         };
 923
 924         pinctrl_usbh1_oc: usbh1-ocgrp {
 925                 fsl,pins = <
 926                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
 927                 >;
 928         };
 929
 930         pinctrl_usbh1_vbus: usbh1-vbusgrp {
 931                 fsl,pins = <
 932                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
 933                 >;
 934         };
 935
 936         pinctrl_usbotg_oc: usbotg-ocgrp {
 937                 fsl,pins = <
 938                         MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
 939                 >;
 940         };
 941
 942         pinctrl_usbotg_vbus: usbotg-vbusgrp {
 943                 fsl,pins = <
 944                         MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
 945                 >;
 946         };
 947
 948         pinctrl_usdhc1: usdhc1grp {
 949                 fsl,pins = <
 950                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
 951                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
 952                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
 953                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
 954                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
 955                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
 956                 >;
 957         };
 958
 959         pinctrl_usdhc1_cd: usdhc1cdgrp {
 960                 fsl,pins = <
 961                         MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
 962                 >;
 963         };
 964
 965         pinctrl_usdhc2: usdhc2grp {
 966                 fsl,pins = <
 967                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
 968                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
 969                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
 970                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
 971                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
 972                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
 973                         /* eMMC RESET */
 974                         MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
 975                 >;
 976         };
 977 };