arch/arm/boot/dts/imx6ul.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6ul-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include "imx6ul-pinfunc.h"
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         aliases {
  18                 ethernet0 = &fec1;
  19                 ethernet1 = &fec2;
  20                 gpio0 = &gpio1;
  21                 gpio1 = &gpio2;
  22                 gpio2 = &gpio3;
  23                 gpio3 = &gpio4;
  24                 gpio4 = &gpio5;
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 mmc0 = &usdhc1;
  30                 mmc1 = &usdhc2;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 serial5 = &uart6;
  37                 serial6 = &uart7;
  38                 serial7 = &uart8;
  39                 spi0 = &ecspi1;
  40                 spi1 = &ecspi2;
  41                 spi2 = &ecspi3;
  42                 spi3 = &ecspi4;
  43                 usbphy0 = &usbphy1;
  44                 usbphy1 = &usbphy2;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 cpu0: cpu@0 {
  52                         compatible = "arm,cortex-a7";
  53                         device_type = "cpu";
  54                         reg = <0>;
  55                         clock-latency = <61036>; /* two CLK32 periods */
  56                         operating-points = <
  57                                 /* kHz  uV */
  58                                 528000  1250000
  59                                 396000  1150000
  60                                 198000  1150000
  61                         >;
  62                         fsl,soc-operating-points = <
  63                                 /* KHz  uV */
  64                                 528000  1250000
  65                                 396000  1150000
  66                                 198000  1150000
  67                         >;
  68                         clocks = <&clks IMX6UL_CLK_ARM>,
  69                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  70                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  71                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  72                                  <&clks IMX6UL_CLK_STEP>,
  73                                  <&clks IMX6UL_CLK_PLL1_SW>,
  74                                  <&clks IMX6UL_CLK_PLL1_SYS>,
  75                                  <&clks IMX6UL_PLL1_BYPASS>,
  76                                  <&clks IMX6UL_CLK_PLL1>,
  77                                  <&clks IMX6UL_PLL1_BYPASS_SRC>,
  78                                  <&clks IMX6UL_CLK_OSC>;
  79                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  80                                       "secondary_sel", "step", "pll1_sw",
  81                                       "pll1_sys", "pll1_bypass", "pll1",
  82                                       "pll1_bypass_src", "osc";
  83                         arm-supply = <&reg_arm>;
  84                         soc-supply = <&reg_soc>;
  85                 };
  86         };
  87
  88         intc: interrupt-controller@00a01000 {
  89                 compatible = "arm,cortex-a7-gic";
  90                 #interrupt-cells = <3>;
  91                 interrupt-controller;
  92                 reg = <0x00a01000 0x1000>,
  93                       <0x00a02000 0x1000>,
  94                       <0x00a04000 0x2000>,
  95                       <0x00a06000 0x2000>;
  96         };
  97
  98         ckil: clock-cli {
  99                 compatible = "fixed-clock";
 100                 #clock-cells = <0>;
 101                 clock-frequency = <32768>;
 102                 clock-output-names = "ckil";
 103         };
 104
 105         osc: clock-osc {
 106                 compatible = "fixed-clock";
 107                 #clock-cells = <0>;
 108                 clock-frequency = <24000000>;
 109                 clock-output-names = "osc";
 110         };
 111
 112         ipp_di0: clock-di0 {
 113                 compatible = "fixed-clock";
 114                 #clock-cells = <0>;
 115                 clock-frequency = <0>;
 116                 clock-output-names = "ipp_di0";
 117         };
 118
 119         ipp_di1: clock-di1 {
 120                 compatible = "fixed-clock";
 121                 #clock-cells = <0>;
 122                 clock-frequency = <0>;
 123                 clock-output-names = "ipp_di1";
 124         };
 125
 126         soc {
 127                 #address-cells = <1>;
 128                 #size-cells = <1>;
 129                 compatible = "simple-bus";
 130                 interrupt-parent = <&gpc>;
 131                 ranges;
 132
 133                 pmu {
 134                         compatible = "arm,cortex-a7-pmu";
 135                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 136                         status = "disabled";
 137                 };
 138
 139                 ocram: sram@00900000 {
 140                         compatible = "mmio-sram";
 141                         reg = <0x00900000 0x20000>;
 142                 };
 143
 144                 dma_apbh: dma-apbh@01804000 {
 145                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 146                         reg = <0x01804000 0x2000>;
 147                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 148                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 149                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 150                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 151                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 152                         #dma-cells = <1>;
 153                         dma-channels = <4>;
 154                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 155                 };
 156
 157                 gpmi: gpmi-nand@01806000         {
 158                         compatible = "fsl,imx6q-gpmi-nand";
 159                         #address-cells = <1>;
 160                         #size-cells = <1>;
 161                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 162                         reg-names = "gpmi-nand", "bch";
 163                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 164                         interrupt-names = "bch";
 165                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 166                                  <&clks IMX6UL_CLK_GPMI_APB>,
 167                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 168                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 169                                  <&clks IMX6UL_CLK_PER_BCH>;
 170                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 171                                       "gpmi_bch_apb", "per1_bch";
 172                         dmas = <&dma_apbh 0>;
 173                         dma-names = "rx-tx";
 174                         status = "disabled";
 175                 };
 176
 177                 aips1: aips-bus@02000000 {
 178                         compatible = "fsl,aips-bus", "simple-bus";
 179                         #address-cells = <1>;
 180                         #size-cells = <1>;
 181                         reg = <0x02000000 0x100000>;
 182                         ranges;
 183
 184                         spba-bus@02000000 {
 185                                 compatible = "fsl,spba-bus", "simple-bus";
 186                                 #address-cells = <1>;
 187                                 #size-cells = <1>;
 188                                 reg = <0x02000000 0x40000>;
 189                                 ranges;
 190
 191                                 ecspi1: ecspi@02008000 {
 192                                         #address-cells = <1>;
 193                                         #size-cells = <0>;
 194                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 195                                         reg = <0x02008000 0x4000>;
 196                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 197                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 198                                                  <&clks IMX6UL_CLK_ECSPI1>;
 199                                         clock-names = "ipg", "per";
 200                                         status = "disabled";
 201                                 };
 202
 203                                 ecspi2: ecspi@0200c000 {
 204                                         #address-cells = <1>;
 205                                         #size-cells = <0>;
 206                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 207                                         reg = <0x0200c000 0x4000>;
 208                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 209                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 210                                                  <&clks IMX6UL_CLK_ECSPI2>;
 211                                         clock-names = "ipg", "per";
 212                                         status = "disabled";
 213                                 };
 214
 215                                 ecspi3: ecspi@02010000 {
 216                                         #address-cells = <1>;
 217                                         #size-cells = <0>;
 218                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 219                                         reg = <0x02010000 0x4000>;
 220                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 221                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 222                                                  <&clks IMX6UL_CLK_ECSPI3>;
 223                                         clock-names = "ipg", "per";
 224                                         status = "disabled";
 225                                 };
 226
 227                                 ecspi4: ecspi@02014000 {
 228                                         #address-cells = <1>;
 229                                         #size-cells = <0>;
 230                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 231                                         reg = <0x02014000 0x4000>;
 232                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 233                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 234                                                  <&clks IMX6UL_CLK_ECSPI4>;
 235                                         clock-names = "ipg", "per";
 236                                         status = "disabled";
 237                                 };
 238
 239                                 uart7: serial@02018000 {
 240                                         compatible = "fsl,imx6ul-uart",
 241                                                      "fsl,imx6q-uart";
 242                                         reg = <0x02018000 0x4000>;
 243                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 244                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 245                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 246                                         clock-names = "ipg", "per";
 247                                         status = "disabled";
 248                                 };
 249
 250                                 uart1: serial@02020000 {
 251                                         compatible = "fsl,imx6ul-uart",
 252                                                      "fsl,imx6q-uart";
 253                                         reg = <0x02020000 0x4000>;
 254                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 255                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 256                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 257                                         clock-names = "ipg", "per";
 258                                         status = "disabled";
 259                                 };
 260
 261                                 uart8: serial@02024000 {
 262                                         compatible = "fsl,imx6ul-uart",
 263                                                      "fsl,imx6q-uart";
 264                                         reg = <0x02024000 0x4000>;
 265                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 266                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 267                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 268                                         clock-names = "ipg", "per";
 269                                         status = "disabled";
 270                                 };
 271
 272                                 sai1: sai@02028000 {
 273                                         #sound-dai-cells = <0>;
 274                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 275                                         reg = <0x02028000 0x4000>;
 276                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 277                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 278                                                  <&clks IMX6UL_CLK_SAI1>,
 279                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 280                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 281                                         dmas = <&sdma 35 24 0>,
 282                                                <&sdma 36 24 0>;
 283                                         dma-names = "rx", "tx";
 284                                         status = "disabled";
 285                                 };
 286
 287                                 sai2: sai@0202c000 {
 288                                         #sound-dai-cells = <0>;
 289                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 290                                         reg = <0x0202c000 0x4000>;
 291                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 292                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 293                                                  <&clks IMX6UL_CLK_SAI2>,
 294                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 295                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 296                                         dmas = <&sdma 37 24 0>,
 297                                                <&sdma 38 24 0>;
 298                                         dma-names = "rx", "tx";
 299                                         status = "disabled";
 300                                 };
 301
 302                                 sai3: sai@02030000 {
 303                                         #sound-dai-cells = <0>;
 304                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 305                                         reg = <0x02030000 0x4000>;
 306                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 307                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 308                                                  <&clks IMX6UL_CLK_SAI3>,
 309                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 310                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 311                                         dmas = <&sdma 39 24 0>,
 312                                                <&sdma 40 24 0>;
 313                                         dma-names = "rx", "tx";
 314                                         status = "disabled";
 315                                 };
 316                         };
 317
 318                         tsc: tsc@02040000 {
 319                                 compatible = "fsl,imx6ul-tsc";
 320                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 321                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 322                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 323                                 clocks = <&clks IMX6UL_CLK_IPG>,
 324                                          <&clks IMX6UL_CLK_ADC2>;
 325                                 clock-names = "tsc", "adc";
 326                                 status = "disabled";
 327                         };
 328
 329                         pwm1: pwm@02080000 {
 330                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 331                                 reg = <0x02080000 0x4000>;
 332                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 333                                 clocks = <&clks IMX6UL_CLK_PWM1>,
 334                                          <&clks IMX6UL_CLK_PWM1>;
 335                                 clock-names = "ipg", "per";
 336                                 #pwm-cells = <2>;
 337                                 status = "disabled";
 338                         };
 339
 340                         pwm2: pwm@02084000 {
 341                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 342                                 reg = <0x02084000 0x4000>;
 343                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 344                                 clocks = <&clks IMX6UL_CLK_PWM2>,
 345                                          <&clks IMX6UL_CLK_PWM2>;
 346                                 clock-names = "ipg", "per";
 347                                 #pwm-cells = <2>;
 348                                 status = "disabled";
 349                         };
 350
 351                         pwm3: pwm@02088000 {
 352                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 353                                 reg = <0x02088000 0x4000>;
 354                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 355                                 clocks = <&clks IMX6UL_CLK_PWM3>,
 356                                          <&clks IMX6UL_CLK_PWM3>;
 357                                 clock-names = "ipg", "per";
 358                                 #pwm-cells = <2>;
 359                                 status = "disabled";
 360                         };
 361
 362                         pwm4: pwm@0208c000 {
 363                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 364                                 reg = <0x0208c000 0x4000>;
 365                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 366                                 clocks = <&clks IMX6UL_CLK_PWM4>,
 367                                          <&clks IMX6UL_CLK_PWM4>;
 368                                 clock-names = "ipg", "per";
 369                                 #pwm-cells = <2>;
 370                                 status = "disabled";
 371                         };
 372
 373                         can1: flexcan@02090000 {
 374                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 375                                 reg = <0x02090000 0x4000>;
 376                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 377                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 378                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 379                                 clock-names = "ipg", "per";
 380                                 status = "disabled";
 381                         };
 382
 383                         can2: flexcan@02094000 {
 384                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 385                                 reg = <0x02094000 0x4000>;
 386                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 387                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 388                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 389                                 clock-names = "ipg", "per";
 390                                 status = "disabled";
 391                         };
 392
 393                         gpt1: gpt@02098000 {
 394                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 395                                 reg = <0x02098000 0x4000>;
 396                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 397                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 398                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 399                                 clock-names = "ipg", "per";
 400                         };
 401
 402                         gpio1: gpio@0209c000 {
 403                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 404                                 reg = <0x0209c000 0x4000>;
 405                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 406                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 407                                 gpio-controller;
 408                                 #gpio-cells = <2>;
 409                                 interrupt-controller;
 410                                 #interrupt-cells = <2>;
 411                         };
 412
 413                         gpio2: gpio@020a0000 {
 414                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 415                                 reg = <0x020a0000 0x4000>;
 416                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 417                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 418                                 gpio-controller;
 419                                 #gpio-cells = <2>;
 420                                 interrupt-controller;
 421                                 #interrupt-cells = <2>;
 422                         };
 423
 424                         gpio3: gpio@020a4000 {
 425                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 426                                 reg = <0x020a4000 0x4000>;
 427                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 428                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 429                                 gpio-controller;
 430                                 #gpio-cells = <2>;
 431                                 interrupt-controller;
 432                                 #interrupt-cells = <2>;
 433                         };
 434
 435                         gpio4: gpio@020a8000 {
 436                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 437                                 reg = <0x020a8000 0x4000>;
 438                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 439                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 440                                 gpio-controller;
 441                                 #gpio-cells = <2>;
 442                                 interrupt-controller;
 443                                 #interrupt-cells = <2>;
 444                         };
 445
 446                         gpio5: gpio@020ac000 {
 447                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 448                                 reg = <0x020ac000 0x4000>;
 449                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 450                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 451                                 gpio-controller;
 452                                 #gpio-cells = <2>;
 453                                 interrupt-controller;
 454                                 #interrupt-cells = <2>;
 455                         };
 456
 457                         fec2: ethernet@020b4000 {
 458                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 459                                 reg = <0x020b4000 0x4000>;
 460                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 461                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 462                                 clocks = <&clks IMX6UL_CLK_ENET>,
 463                                          <&clks IMX6UL_CLK_ENET_AHB>,
 464                                          <&clks IMX6UL_CLK_ENET_PTP>,
 465                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 466                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 467                                 clock-names = "ipg", "ahb", "ptp",
 468                                               "enet_clk_ref", "enet_out";
 469                                 fsl,num-tx-queues=<1>;
 470                                 fsl,num-rx-queues=<1>;
 471                                 status = "disabled";
 472                         };
 473
 474                         wdog1: wdog@020bc000 {
 475                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 476                                 reg = <0x020bc000 0x4000>;
 477                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 478                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 479                         };
 480
 481                         wdog2: wdog@020c0000 {
 482                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 483                                 reg = <0x020c0000 0x4000>;
 484                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 485                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 486                                 status = "disabled";
 487                         };
 488
 489                         clks: ccm@020c4000 {
 490                                 compatible = "fsl,imx6ul-ccm";
 491                                 reg = <0x020c4000 0x4000>;
 492                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 493                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 494                                 #clock-cells = <1>;
 495                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 496                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 497                         };
 498
 499                         anatop: anatop@020c8000 {
 500                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 501                                              "syscon", "simple-bus";
 502                                 reg = <0x020c8000 0x1000>;
 503                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 504                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 505                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 506
 507                                 reg_3p0: regulator-3p0@120 {
 508                                         compatible = "fsl,anatop-regulator";
 509                                         regulator-name = "vdd3p0";
 510                                         regulator-min-microvolt = <2625000>;
 511                                         regulator-max-microvolt = <3400000>;
 512                                         anatop-reg-offset = <0x120>;
 513                                         anatop-vol-bit-shift = <8>;
 514                                         anatop-vol-bit-width = <5>;
 515                                         anatop-min-bit-val = <0>;
 516                                         anatop-min-voltage = <2625000>;
 517                                         anatop-max-voltage = <3400000>;
 518                                         anatop-enable-bit = <0>;
 519                                 };
 520
 521                                 reg_arm: regulator-vddcore@140 {
 522                                         compatible = "fsl,anatop-regulator";
 523                                         regulator-name = "cpu";
 524                                         regulator-min-microvolt = <725000>;
 525                                         regulator-max-microvolt = <1450000>;
 526                                         regulator-always-on;
 527                                         anatop-reg-offset = <0x140>;
 528                                         anatop-vol-bit-shift = <0>;
 529                                         anatop-vol-bit-width = <5>;
 530                                         anatop-delay-reg-offset = <0x170>;
 531                                         anatop-delay-bit-shift = <24>;
 532                                         anatop-delay-bit-width = <2>;
 533                                         anatop-min-bit-val = <1>;
 534                                         anatop-min-voltage = <725000>;
 535                                         anatop-max-voltage = <1450000>;
 536                                 };
 537
 538                                 reg_soc: regulator-vddsoc@140 {
 539                                         compatible = "fsl,anatop-regulator";
 540                                         regulator-name = "vddsoc";
 541                                         regulator-min-microvolt = <725000>;
 542                                         regulator-max-microvolt = <1450000>;
 543                                         regulator-always-on;
 544                                         anatop-reg-offset = <0x140>;
 545                                         anatop-vol-bit-shift = <18>;
 546                                         anatop-vol-bit-width = <5>;
 547                                         anatop-delay-reg-offset = <0x170>;
 548                                         anatop-delay-bit-shift = <28>;
 549                                         anatop-delay-bit-width = <2>;
 550                                         anatop-min-bit-val = <1>;
 551                                         anatop-min-voltage = <725000>;
 552                                         anatop-max-voltage = <1450000>;
 553                                 };
 554                         };
 555
 556                         usbphy1: usbphy@020c9000 {
 557                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 558                                 reg = <0x020c9000 0x1000>;
 559                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 560                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 561                                 phy-3p0-supply = <&reg_3p0>;
 562                                 fsl,anatop = <&anatop>;
 563                         };
 564
 565                         usbphy2: usbphy@020ca000 {
 566                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 567                                 reg = <0x020ca000 0x1000>;
 568                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 569                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 570                                 phy-3p0-supply = <&reg_3p0>;
 571                                 fsl,anatop = <&anatop>;
 572                         };
 573
 574                         snvs: snvs@020cc000 {
 575                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 576                                 reg = <0x020cc000 0x4000>;
 577
 578                                 snvs_rtc: snvs-rtc-lp {
 579                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 580                                         regmap = <&snvs>;
 581                                         offset = <0x34>;
 582                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 583                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 584                                 };
 585
 586                                 snvs_poweroff: snvs-poweroff {
 587                                         compatible = "syscon-poweroff";
 588                                         regmap = <&snvs>;
 589                                         offset = <0x38>;
 590                                         mask = <0x60>;
 591                                         status = "disabled";
 592                                 };
 593
 594                                 snvs_pwrkey: snvs-powerkey {
 595                                         compatible = "fsl,sec-v4.0-pwrkey";
 596                                         regmap = <&snvs>;
 597                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 598                                         linux,keycode = <KEY_POWER>;
 599                                         wakeup-source;
 600                                 };
 601                         };
 602
 603                         epit1: epit@020d0000 {
 604                                 reg = <0x020d0000 0x4000>;
 605                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 606                         };
 607
 608                         epit2: epit@020d4000 {
 609                                 reg = <0x020d4000 0x4000>;
 610                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 611                         };
 612
 613                         src: src@020d8000 {
 614                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 615                                 reg = <0x020d8000 0x4000>;
 616                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 617                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 618                                 #reset-cells = <1>;
 619                         };
 620
 621                         gpc: gpc@020dc000 {
 622                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 623                                 reg = <0x020dc000 0x4000>;
 624                                 interrupt-controller;
 625                                 #interrupt-cells = <3>;
 626                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 627                                 interrupt-parent = <&intc>;
 628                         };
 629
 630                         iomuxc: iomuxc@020e0000 {
 631                                 compatible = "fsl,imx6ul-iomuxc";
 632                                 reg = <0x020e0000 0x4000>;
 633                         };
 634
 635                         gpr: iomuxc-gpr@020e4000 {
 636                                 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
 637                                 reg = <0x020e4000 0x4000>;
 638                         };
 639
 640                         gpt2: gpt@020e8000 {
 641                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 642                                 reg = <0x020e8000 0x4000>;
 643                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 644                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 645                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 646                                 clock-names = "ipg", "per";
 647                         };
 648
 649                         sdma: sdma@020ec000 {
 650                                 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
 651                                              "fsl,imx35-sdma";
 652                                 reg = <0x020ec000 0x4000>;
 653                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 654                                 clocks = <&clks IMX6UL_CLK_SDMA>,
 655                                          <&clks IMX6UL_CLK_SDMA>;
 656                                 clock-names = "ipg", "ahb";
 657                                 #dma-cells = <3>;
 658                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 659                         };
 660
 661                         pwm5: pwm@020f0000 {
 662                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 663                                 reg = <0x020f0000 0x4000>;
 664                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 665                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 666                                          <&clks IMX6UL_CLK_PWM5>;
 667                                 clock-names = "ipg", "per";
 668                                 #pwm-cells = <2>;
 669                                 status = "disabled";
 670                         };
 671
 672                         pwm6: pwm@020f4000 {
 673                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 674                                 reg = <0x020f4000 0x4000>;
 675                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 676                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 677                                          <&clks IMX6UL_CLK_PWM6>;
 678                                 clock-names = "ipg", "per";
 679                                 #pwm-cells = <2>;
 680                                 status = "disabled";
 681                         };
 682
 683                         pwm7: pwm@020f8000 {
 684                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 685                                 reg = <0x020f8000 0x4000>;
 686                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 687                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 688                                          <&clks IMX6UL_CLK_PWM7>;
 689                                 clock-names = "ipg", "per";
 690                                 #pwm-cells = <2>;
 691                                 status = "disabled";
 692                         };
 693
 694                         pwm8: pwm@020fc000 {
 695                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 696                                 reg = <0x020fc000 0x4000>;
 697                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 698                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 699                                          <&clks IMX6UL_CLK_PWM8>;
 700                                 clock-names = "ipg", "per";
 701                                 #pwm-cells = <2>;
 702                                 status = "disabled";
 703                         };
 704                 };
 705
 706                 aips2: aips-bus@02100000 {
 707                         compatible = "fsl,aips-bus", "simple-bus";
 708                         #address-cells = <1>;
 709                         #size-cells = <1>;
 710                         reg = <0x02100000 0x100000>;
 711                         ranges;
 712
 713                         usbotg1: usb@02184000 {
 714                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 715                                 reg = <0x02184000 0x200>;
 716                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 717                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 718                                 fsl,usbphy = <&usbphy1>;
 719                                 fsl,usbmisc = <&usbmisc 0>;
 720                                 fsl,anatop = <&anatop>;
 721                                 ahb-burst-config = <0x0>;
 722                                 tx-burst-size-dword = <0x10>;
 723                                 rx-burst-size-dword = <0x10>;
 724                                 status = "disabled";
 725                         };
 726
 727                         usbotg2: usb@02184200 {
 728                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 729                                 reg = <0x02184200 0x200>;
 730                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 731                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 732                                 fsl,usbphy = <&usbphy2>;
 733                                 fsl,usbmisc = <&usbmisc 1>;
 734                                 ahb-burst-config = <0x0>;
 735                                 tx-burst-size-dword = <0x10>;
 736                                 rx-burst-size-dword = <0x10>;
 737                                 status = "disabled";
 738                         };
 739
 740                         usbmisc: usbmisc@02184800 {
 741                                 #index-cells = <1>;
 742                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 743                                 reg = <0x02184800 0x200>;
 744                         };
 745
 746                         fec1: ethernet@02188000 {
 747                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 748                                 reg = <0x02188000 0x4000>;
 749                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 750                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 751                                 clocks = <&clks IMX6UL_CLK_ENET>,
 752                                          <&clks IMX6UL_CLK_ENET_AHB>,
 753                                          <&clks IMX6UL_CLK_ENET_PTP>,
 754                                          <&clks IMX6UL_CLK_ENET_REF>,
 755                                          <&clks IMX6UL_CLK_ENET_REF>;
 756                                 clock-names = "ipg", "ahb", "ptp",
 757                                               "enet_clk_ref", "enet_out";
 758                                 fsl,num-tx-queues=<1>;
 759                                 fsl,num-rx-queues=<1>;
 760                                 status = "disabled";
 761                         };
 762
 763                         usdhc1: usdhc@02190000 {
 764                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 765                                 reg = <0x02190000 0x4000>;
 766                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 767                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 768                                          <&clks IMX6UL_CLK_USDHC1>,
 769                                          <&clks IMX6UL_CLK_USDHC1>;
 770                                 clock-names = "ipg", "ahb", "per";
 771                                 bus-width = <4>;
 772                                 status = "disabled";
 773                         };
 774
 775                         usdhc2: usdhc@02194000 {
 776                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 777                                 reg = <0x02194000 0x4000>;
 778                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 779                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 780                                          <&clks IMX6UL_CLK_USDHC2>,
 781                                          <&clks IMX6UL_CLK_USDHC2>;
 782                                 clock-names = "ipg", "ahb", "per";
 783                                 bus-width = <4>;
 784                                 status = "disabled";
 785                         };
 786
 787                         adc1: adc@02198000 {
 788                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
 789                                 reg = <0x02198000 0x4000>;
 790                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 791                                 clocks = <&clks IMX6UL_CLK_ADC1>;
 792                                 num-channels = <2>;
 793                                 clock-names = "adc";
 794                                 fsl,adck-max-frequency = <30000000>, <40000000>,
 795                                                          <20000000>;
 796                                 status = "disabled";
 797                         };
 798
 799                         i2c1: i2c@021a0000 {
 800                                 #address-cells = <1>;
 801                                 #size-cells = <0>;
 802                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 803                                 reg = <0x021a0000 0x4000>;
 804                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 805                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 806                                 status = "disabled";
 807                         };
 808
 809                         i2c2: i2c@021a4000 {
 810                                 #address-cells = <1>;
 811                                 #size-cells = <0>;
 812                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 813                                 reg = <0x021a4000 0x4000>;
 814                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 815                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 816                                 status = "disabled";
 817                         };
 818
 819                         i2c3: i2c@021a8000 {
 820                                 #address-cells = <1>;
 821                                 #size-cells = <0>;
 822                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 823                                 reg = <0x021a8000 0x4000>;
 824                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 825                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 826                                 status = "disabled";
 827                         };
 828
 829                         mmdc: mmdc@021b0000 {
 830                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 831                                 reg = <0x021b0000 0x4000>;
 832                         };
 833
 834                         lcdif: lcdif@021c8000 {
 835                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 836                                 reg = <0x021c8000 0x4000>;
 837                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 838                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
 839                                          <&clks IMX6UL_CLK_LCDIF_APB>,
 840                                          <&clks IMX6UL_CLK_DUMMY>;
 841                                 clock-names = "pix", "axi", "disp_axi";
 842                                 status = "disabled";
 843                         };
 844
 845                         qspi: qspi@021e0000 {
 846                                 #address-cells = <1>;
 847                                 #size-cells = <0>;
 848                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 849                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 850                                 reg-names = "QuadSPI", "QuadSPI-memory";
 851                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 852                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 853                                          <&clks IMX6UL_CLK_QSPI>;
 854                                 clock-names = "qspi_en", "qspi";
 855                                 status = "disabled";
 856                         };
 857
 858                         uart2: serial@021e8000 {
 859                                 compatible = "fsl,imx6ul-uart",
 860                                              "fsl,imx6q-uart";
 861                                 reg = <0x021e8000 0x4000>;
 862                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 863                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 864                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 865                                 clock-names = "ipg", "per";
 866                                 status = "disabled";
 867                         };
 868
 869                         uart3: serial@021ec000 {
 870                                 compatible = "fsl,imx6ul-uart",
 871                                              "fsl,imx6q-uart";
 872                                 reg = <0x021ec000 0x4000>;
 873                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 874                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
 875                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
 876                                 clock-names = "ipg", "per";
 877                                 status = "disabled";
 878                         };
 879
 880                         uart4: serial@021f0000 {
 881                                 compatible = "fsl,imx6ul-uart",
 882                                              "fsl,imx6q-uart";
 883                                 reg = <0x021f0000 0x4000>;
 884                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 885                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
 886                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
 887                                 clock-names = "ipg", "per";
 888                                 status = "disabled";
 889                         };
 890
 891                         uart5: serial@021f4000 {
 892                                 compatible = "fsl,imx6ul-uart",
 893                                              "fsl,imx6q-uart";
 894                                 reg = <0x021f4000 0x4000>;
 895                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 896                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
 897                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
 898                                 clock-names = "ipg", "per";
 899                                 status = "disabled";
 900                         };
 901
 902                         i2c4: i2c@021f8000 {
 903                                 #address-cells = <1>;
 904                                 #size-cells = <0>;
 905                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 906                                 reg = <0x021f8000 0x4000>;
 907                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 908                                 clocks = <&clks IMX6UL_CLK_I2C4>;
 909                                 status = "disabled";
 910                         };
 911
 912                         uart6: serial@021fc000 {
 913                                 compatible = "fsl,imx6ul-uart",
 914                                              "fsl,imx6q-uart";
 915                                 reg = <0x021fc000 0x4000>;
 916                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 917                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
 918                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
 919                                 clock-names = "ipg", "per";
 920                                 status = "disabled";
 921                         };
 922                 };
 923         };
 924 };