2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "skeleton.dtsi"
47 #include <dt-bindings/clock/at91.h>
48 #include <dt-bindings/dma/at91.h>
49 #include <dt-bindings/pinctrl/at91.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/gpio/gpio.h>
54 model = "Atmel SAMA5D4 family SoC";
55 compatible = "atmel,sama5d4";
56 interrupt-parent = <&aic>;
82 compatible = "arm,cortex-a5";
84 next-level-cache = <&L2>;
89 reg = <0x20000000 0x20000000>;
93 slow_xtal: slow_xtal {
94 compatible = "fixed-clock";
96 clock-frequency = <0>;
99 main_xtal: main_xtal {
100 compatible = "fixed-clock";
102 clock-frequency = <0>;
105 adc_op_clk: adc_op_clk{
106 compatible = "fixed-clock";
108 clock-frequency = <1000000>;
112 ns_sram: sram@00210000 {
113 compatible = "mmio-sram";
114 reg = <0x00210000 0x10000>;
118 compatible = "simple-bus";
119 #address-cells = <1>;
123 usb0: gadget@00400000 {
124 #address-cells = <1>;
126 compatible = "atmel,at91sam9rl-udc";
127 reg = <0x00400000 0x100000
129 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
130 clocks = <&udphs_clk>, <&utmi>;
131 clock-names = "pclk", "hclk";
136 atmel,fifo-size = <64>;
137 atmel,nb-banks = <1>;
142 atmel,fifo-size = <1024>;
143 atmel,nb-banks = <3>;
150 atmel,fifo-size = <1024>;
151 atmel,nb-banks = <3>;
158 atmel,fifo-size = <1024>;
159 atmel,nb-banks = <2>;
166 atmel,fifo-size = <1024>;
167 atmel,nb-banks = <2>;
174 atmel,fifo-size = <1024>;
175 atmel,nb-banks = <2>;
182 atmel,fifo-size = <1024>;
183 atmel,nb-banks = <2>;
190 atmel,fifo-size = <1024>;
191 atmel,nb-banks = <2>;
198 atmel,fifo-size = <1024>;
199 atmel,nb-banks = <2>;
205 atmel,fifo-size = <1024>;
206 atmel,nb-banks = <2>;
212 atmel,fifo-size = <1024>;
213 atmel,nb-banks = <2>;
219 atmel,fifo-size = <1024>;
220 atmel,nb-banks = <2>;
226 atmel,fifo-size = <1024>;
227 atmel,nb-banks = <2>;
233 atmel,fifo-size = <1024>;
234 atmel,nb-banks = <2>;
240 atmel,fifo-size = <1024>;
241 atmel,nb-banks = <2>;
247 atmel,fifo-size = <1024>;
248 atmel,nb-banks = <2>;
253 usb1: ohci@00500000 {
254 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
255 reg = <0x00500000 0x100000>;
256 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
257 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
259 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
263 usb2: ehci@00600000 {
264 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
265 reg = <0x00600000 0x100000>;
266 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
267 clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
268 clock-names = "usb_clk", "ehci_clk", "uhpck";
272 L2: cache-controller@00a00000 {
273 compatible = "arm,pl310-cache";
274 reg = <0x00a00000 0x1000>;
275 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
280 nand0: nand@80000000 {
281 compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
282 #address-cells = <1>;
285 reg = < 0x80000000 0x08000000 /* EBI CS3 */
286 0xfc05c070 0x00000490 /* SMC PMECC regs */
287 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
289 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
290 atmel,nand-addr-offset = <21>;
291 atmel,nand-cmd-offset = <22>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_nand>;
298 compatible = "atmel,sama5d3-nfc";
299 #address-cells = <1>;
302 0x90000000 0x10000000 /* NFC Command Registers */
303 0xfc05c000 0x00000070 /* NFC HSMC regs */
304 0x00100000 0x00100000 /* NFC SRAM banks */
306 clocks = <&hsmc_clk>;
312 compatible = "simple-bus";
313 #address-cells = <1>;
317 hlcdc: hlcdc@f0000000 {
318 compatible = "atmel,sama5d4-hlcdc";
319 reg = <0xf0000000 0x4000>;
320 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
321 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
322 clock-names = "periph_clk","sys_clk", "slow_clk";
325 hlcdc-display-controller {
326 compatible = "atmel,hlcdc-display-controller";
327 #address-cells = <1>;
331 #address-cells = <1>;
337 hlcdc_pwm: hlcdc-pwm {
338 compatible = "atmel,hlcdc-pwm";
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_lcd_pwm>;
345 dma1: dma-controller@f0004000 {
346 compatible = "atmel,sama5d4-dma";
347 reg = <0xf0004000 0x200>;
348 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
350 clocks = <&dma1_clk>;
351 clock-names = "dma_clk";
355 compatible = "atmel,at91sam9g45-isi";
356 reg = <0xf0008000 0x4000>;
357 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_isi_data_0_7>;
361 clock-names = "isi_clk";
364 #address-cells = <1>;
369 ramc0: ramc@f0010000 {
370 compatible = "atmel,sama5d3-ddramc";
371 reg = <0xf0010000 0x200>;
372 clocks = <&ddrck>, <&mpddr_clk>;
373 clock-names = "ddrck", "mpddr";
376 dma0: dma-controller@f0014000 {
377 compatible = "atmel,sama5d4-dma";
378 reg = <0xf0014000 0x200>;
379 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
381 clocks = <&dma0_clk>;
382 clock-names = "dma_clk";
386 compatible = "atmel,sama5d3-pmc";
387 reg = <0xf0018000 0x120>;
388 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
389 interrupt-controller;
390 #address-cells = <1>;
392 #interrupt-cells = <1>;
394 main_rc_osc: main_rc_osc {
395 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
397 interrupt-parent = <&pmc>;
398 interrupts = <AT91_PMC_MOSCRCS>;
399 clock-frequency = <12000000>;
400 clock-accuracy = <100000000>;
404 compatible = "atmel,at91rm9200-clk-main-osc";
406 interrupt-parent = <&pmc>;
407 interrupts = <AT91_PMC_MOSCS>;
408 clocks = <&main_xtal>;
412 compatible = "atmel,at91sam9x5-clk-main";
414 interrupt-parent = <&pmc>;
415 interrupts = <AT91_PMC_MOSCSELS>;
416 clocks = <&main_rc_osc &main_osc>;
420 compatible = "atmel,sama5d3-clk-pll";
422 interrupt-parent = <&pmc>;
423 interrupts = <AT91_PMC_LOCKA>;
426 atmel,clk-input-range = <12000000 12000000>;
427 #atmel,pll-clk-output-range-cells = <4>;
428 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
432 compatible = "atmel,at91sam9x5-clk-plldiv";
438 compatible = "atmel,at91sam9x5-clk-utmi";
440 interrupt-parent = <&pmc>;
441 interrupts = <AT91_PMC_LOCKU>;
446 compatible = "atmel,at91sam9x5-clk-master";
448 interrupt-parent = <&pmc>;
449 interrupts = <AT91_PMC_MCKRDY>;
450 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
451 atmel,clk-output-range = <125000000 177000000>;
452 atmel,clk-divisors = <1 2 4 3>;
457 compatible = "atmel,sama5d4-clk-h32mx";
462 compatible = "atmel,at91sam9x5-clk-usb";
464 clocks = <&plladiv>, <&utmi>;
468 compatible = "atmel,at91sam9x5-clk-programmable";
469 #address-cells = <1>;
471 interrupt-parent = <&pmc>;
472 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
477 interrupts = <AT91_PMC_PCKRDY(0)>;
483 interrupts = <AT91_PMC_PCKRDY(1)>;
489 interrupts = <AT91_PMC_PCKRDY(2)>;
494 compatible = "atmel,at91sam9x5-clk-smd";
496 clocks = <&plladiv>, <&utmi>;
500 compatible = "atmel,at91rm9200-clk-system";
501 #address-cells = <1>;
554 compatible = "atmel,at91sam9x5-clk-peripheral";
555 #address-cells = <1>;
564 usart0_clk: usart0_clk {
569 usart1_clk: usart1_clk {
594 matrix1_clk: matrix1_clk {
624 uart0_clk: uart0_clk {
629 uart1_clk: uart1_clk {
634 usart2_clk: usart2_clk {
639 usart3_clk: usart3_clk {
644 usart4_clk: usart4_clk {
719 uhphs_clk: uhphs_clk {
724 udphs_clk: udphs_clk {
744 macb0_clk: macb0_clk {
749 macb1_clk: macb1_clk {
759 securam_clk: securam_clk {
781 compatible = "atmel,at91sam9x5-clk-peripheral";
782 #address-cells = <1>;
791 cpkcc_clk: cpkcc_clk {
801 mpddr_clk: mpddr_clk {
806 matrix0_clk: matrix0_clk {
834 compatible = "atmel,hsmci";
835 reg = <0xf8000000 0x600>;
836 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
838 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
839 | AT91_XDMAC_DT_PERID(0))>;
841 pinctrl-names = "default";
842 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
844 #address-cells = <1>;
846 clocks = <&mci0_clk>;
847 clock-names = "mci_clk";
851 compatible = "atmel,at91sam9g45-ssc";
852 reg = <0xf8008000 0x4000>;
853 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
854 pinctrl-names = "default";
855 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
857 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
858 | AT91_XDMAC_DT_PERID(26))>,
860 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
861 | AT91_XDMAC_DT_PERID(27))>;
862 dma-names = "tx", "rx";
863 clocks = <&ssc0_clk>;
864 clock-names = "pclk";
869 compatible = "atmel,sama5d3-pwm";
870 reg = <0xf800c000 0x300>;
871 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
878 #address-cells = <1>;
880 compatible = "atmel,at91rm9200-spi";
881 reg = <0xf8010000 0x100>;
882 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
884 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
885 | AT91_XDMAC_DT_PERID(10))>,
887 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
888 | AT91_XDMAC_DT_PERID(11))>;
889 dma-names = "tx", "rx";
890 pinctrl-names = "default";
891 pinctrl-0 = <&pinctrl_spi0>;
892 clocks = <&spi0_clk>;
893 clock-names = "spi_clk";
898 compatible = "atmel,at91sam9x5-i2c";
899 reg = <0xf8014000 0x4000>;
900 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
902 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
903 | AT91_XDMAC_DT_PERID(2))>,
905 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
906 | AT91_XDMAC_DT_PERID(3))>;
907 dma-names = "tx", "rx";
908 pinctrl-names = "default";
909 pinctrl-0 = <&pinctrl_i2c0>;
910 #address-cells = <1>;
912 clocks = <&twi0_clk>;
917 compatible = "atmel,at91sam9x5-i2c";
918 reg = <0xf8018000 0x4000>;
919 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
921 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
922 AT91_XDMAC_DT_PERID(4)>,
924 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
925 AT91_XDMAC_DT_PERID(5)>;
926 dma-names = "tx", "rx";
927 pinctrl-names = "default";
928 pinctrl-0 = <&pinctrl_i2c1>;
929 #address-cells = <1>;
931 clocks = <&twi1_clk>;
935 tcb0: timer@f801c000 {
936 compatible = "atmel,at91sam9x5-tcb";
937 reg = <0xf801c000 0x100>;
938 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
939 clocks = <&tcb0_clk>;
940 clock-names = "t0_clk";
943 macb0: ethernet@f8020000 {
944 compatible = "atmel,sama5d4-gem";
945 reg = <0xf8020000 0x100>;
946 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
947 pinctrl-names = "default";
948 pinctrl-0 = <&pinctrl_macb0_rmii>;
949 #address-cells = <1>;
951 clocks = <&macb0_clk>, <&macb0_clk>;
952 clock-names = "hclk", "pclk";
957 compatible = "atmel,at91sam9x5-i2c";
958 reg = <0xf8024000 0x4000>;
959 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
961 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
962 | AT91_XDMAC_DT_PERID(6))>,
964 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
965 | AT91_XDMAC_DT_PERID(7))>;
966 dma-names = "tx", "rx";
967 pinctrl-names = "default";
968 pinctrl-0 = <&pinctrl_i2c2>;
969 #address-cells = <1>;
971 clocks = <&twi2_clk>;
976 compatible = "atmel,sama5d4-sfr", "syscon";
977 reg = <0xf8028000 0x60>;
980 usart0: serial@f802c000 {
981 compatible = "atmel,at91sam9260-usart";
982 reg = <0xf802c000 0x100>;
983 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
985 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
986 AT91_XDMAC_DT_PERID(36))>,
988 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
989 AT91_XDMAC_DT_PERID(37))>;
990 dma-names = "tx", "rx";
991 pinctrl-names = "default";
992 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
993 clocks = <&usart0_clk>;
994 clock-names = "usart";
998 usart1: serial@f8030000 {
999 compatible = "atmel,at91sam9260-usart";
1000 reg = <0xf8030000 0x100>;
1001 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
1002 dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1003 AT91_XDMAC_DT_PERID(38))>,
1004 <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1005 AT91_XDMAC_DT_PERID(39))>;
1006 dma-names = "tx", "rx";
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
1009 clocks = <&usart1_clk>;
1010 clock-names = "usart";
1011 status = "disabled";
1014 mmc1: mmc@fc000000 {
1015 compatible = "atmel,hsmci";
1016 reg = <0xfc000000 0x600>;
1017 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1019 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1020 | AT91_XDMAC_DT_PERID(1))>;
1022 pinctrl-names = "default";
1023 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
1024 status = "disabled";
1025 #address-cells = <1>;
1027 clocks = <&mci1_clk>;
1028 clock-names = "mci_clk";
1031 usart2: serial@fc008000 {
1032 compatible = "atmel,at91sam9260-usart";
1033 reg = <0xfc008000 0x100>;
1034 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
1036 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1037 | AT91_XDMAC_DT_PERID(16))>,
1039 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1040 | AT91_XDMAC_DT_PERID(17))>;
1041 dma-names = "tx", "rx";
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
1044 clocks = <&usart2_clk>;
1045 clock-names = "usart";
1046 status = "disabled";
1049 usart3: serial@fc00c000 {
1050 compatible = "atmel,at91sam9260-usart";
1051 reg = <0xfc00c000 0x100>;
1052 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
1054 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1055 | AT91_XDMAC_DT_PERID(18))>,
1057 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1058 | AT91_XDMAC_DT_PERID(19))>;
1059 dma-names = "tx", "rx";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&pinctrl_usart3>;
1062 clocks = <&usart3_clk>;
1063 clock-names = "usart";
1064 status = "disabled";
1067 usart4: serial@fc010000 {
1068 compatible = "atmel,at91sam9260-usart";
1069 reg = <0xfc010000 0x100>;
1070 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
1072 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1073 | AT91_XDMAC_DT_PERID(20))>,
1075 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1076 | AT91_XDMAC_DT_PERID(21))>;
1077 dma-names = "tx", "rx";
1078 pinctrl-names = "default";
1079 pinctrl-0 = <&pinctrl_usart4>;
1080 clocks = <&usart4_clk>;
1081 clock-names = "usart";
1082 status = "disabled";
1085 ssc1: ssc@fc014000 {
1086 compatible = "atmel,at91sam9g45-ssc";
1087 reg = <0xfc014000 0x4000>;
1088 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1092 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1093 | AT91_XDMAC_DT_PERID(28))>,
1095 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1096 | AT91_XDMAC_DT_PERID(29))>;
1097 dma-names = "tx", "rx";
1098 clocks = <&ssc1_clk>;
1099 clock-names = "pclk";
1100 status = "disabled";
1103 tcb1: timer@fc020000 {
1104 compatible = "atmel,at91sam9x5-tcb";
1105 reg = <0xfc020000 0x100>;
1106 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
1107 clocks = <&tcb1_clk>;
1108 clock-names = "t0_clk";
1111 adc0: adc@fc034000 {
1112 compatible = "atmel,at91sam9x5-adc";
1113 reg = <0xfc034000 0x100>;
1114 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
1115 pinctrl-names = "default";
1117 /* external trigger is conflict with USBA_VBUS */
1124 clocks = <&adc_clk>,
1126 clock-names = "adc_clk", "adc_op_clk";
1127 atmel,adc-channels-used = <0x01f>;
1128 atmel,adc-startup-time = <40>;
1129 atmel,adc-use-external;
1130 atmel,adc-vref = <3000>;
1131 atmel,adc-res = <8 10>;
1132 atmel,adc-sample-hold-time = <11>;
1133 atmel,adc-res-names = "lowres", "highres";
1134 atmel,adc-ts-pressure-threshold = <10000>;
1135 status = "disabled";
1138 trigger-name = "external-rising";
1139 trigger-value = <0x1>;
1143 trigger-name = "external-falling";
1144 trigger-value = <0x2>;
1148 trigger-name = "external-any";
1149 trigger-value = <0x3>;
1153 trigger-name = "continuous";
1154 trigger-value = <0x6>;
1159 compatible = "atmel,at91sam9g46-aes";
1160 reg = <0xfc044000 0x100>;
1161 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1162 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1163 AT91_XDMAC_DT_PERID(41)>,
1164 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1165 AT91_XDMAC_DT_PERID(40)>;
1166 dma-names = "tx", "rx";
1167 clocks = <&aes_clk>;
1168 clock-names = "aes_clk";
1169 status = "disabled";
1173 compatible = "atmel,at91sam9g46-tdes";
1174 reg = <0xfc04c000 0x100>;
1175 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
1176 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1177 AT91_XDMAC_DT_PERID(42)>,
1178 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1179 AT91_XDMAC_DT_PERID(43)>;
1180 dma-names = "tx", "rx";
1181 clocks = <&tdes_clk>;
1182 clock-names = "tdes_clk";
1183 status = "disabled";
1187 compatible = "atmel,at91sam9g46-sha";
1188 reg = <0xfc050000 0x100>;
1189 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
1190 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1191 AT91_XDMAC_DT_PERID(44)>;
1193 clocks = <&sha_clk>;
1194 clock-names = "sha_clk";
1195 status = "disabled";
1199 compatible = "atmel,at91sam9g45-rstc";
1200 reg = <0xfc068600 0x10>;
1204 compatible = "atmel,at91sam9x5-shdwc";
1205 reg = <0xfc068610 0x10>;
1208 pit: timer@fc068630 {
1209 compatible = "atmel,at91sam9260-pit";
1210 reg = <0xfc068630 0x10>;
1211 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1216 compatible = "atmel,at91sam9260-wdt";
1217 reg = <0xfc068640 0x10>;
1218 status = "disabled";
1222 compatible = "atmel,at91sam9x5-sckc";
1223 reg = <0xfc068650 0x4>;
1225 slow_rc_osc: slow_rc_osc {
1226 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1228 clock-frequency = <32768>;
1229 clock-accuracy = <250000000>;
1230 atmel,startup-time-usec = <75>;
1233 slow_osc: slow_osc {
1234 compatible = "atmel,at91sam9x5-clk-slow-osc";
1236 clocks = <&slow_xtal>;
1237 atmel,startup-time-usec = <1200000>;
1241 compatible = "atmel,at91sam9x5-clk-slow";
1243 clocks = <&slow_rc_osc &slow_osc>;
1248 compatible = "atmel,at91rm9200-rtc";
1249 reg = <0xfc0686b0 0x30>;
1250 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1253 dbgu: serial@fc069000 {
1254 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1255 reg = <0xfc069000 0x200>;
1256 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
1257 pinctrl-names = "default";
1258 pinctrl-0 = <&pinctrl_dbgu>;
1259 clocks = <&dbgu_clk>;
1260 clock-names = "usart";
1261 status = "disabled";
1266 #address-cells = <1>;
1268 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1269 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1270 /* WARNING: revisit as pin spec has changed */
1273 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1274 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1275 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1276 0x00000000 0x00000000 0x00000000 /* pioD */
1277 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1280 pioA: gpio@fc06a000 {
1281 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1282 reg = <0xfc06a000 0x100>;
1283 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1286 interrupt-controller;
1287 #interrupt-cells = <2>;
1288 clocks = <&pioA_clk>;
1291 pioB: gpio@fc06b000 {
1292 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1293 reg = <0xfc06b000 0x100>;
1294 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1297 interrupt-controller;
1298 #interrupt-cells = <2>;
1299 clocks = <&pioB_clk>;
1302 pioC: gpio@fc06c000 {
1303 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1304 reg = <0xfc06c000 0x100>;
1305 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1308 interrupt-controller;
1309 #interrupt-cells = <2>;
1310 clocks = <&pioC_clk>;
1313 pioD: gpio@fc068000 {
1314 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1315 reg = <0xfc068000 0x100>;
1316 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1319 interrupt-controller;
1320 #interrupt-cells = <2>;
1321 clocks = <&pioD_clk>;
1322 status = "disabled";
1325 pioE: gpio@fc06d000 {
1326 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1327 reg = <0xfc06d000 0x100>;
1328 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1331 interrupt-controller;
1332 #interrupt-cells = <2>;
1333 clocks = <&pioE_clk>;
1336 /* pinctrl pin settings */
1338 pinctrl_adc0_adtrg: adc0_adtrg {
1340 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1343 pinctrl_adc0_ad0: adc0_ad0 {
1345 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1348 pinctrl_adc0_ad1: adc0_ad1 {
1350 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1353 pinctrl_adc0_ad2: adc0_ad2 {
1355 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1358 pinctrl_adc0_ad3: adc0_ad3 {
1360 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1363 pinctrl_adc0_ad4: adc0_ad4 {
1365 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1370 pinctrl_dbgu: dbgu-0 {
1372 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1373 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1378 pinctrl_i2c0: i2c0-0 {
1380 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1381 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1386 pinctrl_i2c1: i2c1-0 {
1388 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
1389 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1394 pinctrl_i2c2: i2c2-0 {
1396 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1397 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1402 pinctrl_isi_data_0_7: isi-0-data-0-7 {
1404 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */
1405 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */
1406 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */
1407 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */
1408 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */
1409 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */
1410 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */
1411 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */
1412 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */
1413 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */
1414 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1417 pinctrl_isi_data_8_9: isi-0-data-8-9 {
1419 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1420 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1423 pinctrl_isi_data_10_11: isi-0-data-10-11 {
1425 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1426 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1431 pinctrl_lcd_base: lcd-base-0 {
1433 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
1434 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
1435 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
1436 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1439 pinctrl_lcd_pwm: lcd-pwm-0 {
1440 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
1443 pinctrl_lcd_rgb444: lcd-rgb-0 {
1445 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1446 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1447 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1448 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1449 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1450 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1451 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1452 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1453 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1454 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1455 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1456 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1459 pinctrl_lcd_rgb565: lcd-rgb-1 {
1461 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1462 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1463 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1464 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1465 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1466 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1467 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1468 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1469 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1470 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1471 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1472 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1473 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1474 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1475 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1476 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1479 pinctrl_lcd_rgb666: lcd-rgb-2 {
1481 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1482 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1483 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1484 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1485 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1486 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1487 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1488 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1489 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1490 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1491 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1492 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1493 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1494 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1495 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1496 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1497 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1498 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1501 pinctrl_lcd_rgb777: lcd-rgb-3 {
1503 /* LCDDAT0 conflicts with TMS */
1504 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1505 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1506 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1507 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1508 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1509 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1510 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1511 /* LCDDAT8 conflicts with TCK */
1512 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1513 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1514 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1515 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1516 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1517 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1518 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1519 /* LCDDAT16 conflicts with NTRST */
1520 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1521 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1522 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1523 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1524 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1525 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1526 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1529 pinctrl_lcd_rgb888: lcd-rgb-4 {
1531 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1532 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1533 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1534 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1535 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1536 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1537 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1538 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1539 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1540 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1541 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1542 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1543 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1544 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1545 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1546 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1547 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
1548 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1549 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1550 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1551 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1552 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1553 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1554 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1559 pinctrl_macb0_rmii: macb0_rmii-0 {
1561 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1562 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1563 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1564 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1565 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1566 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1567 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1568 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1569 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1570 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1576 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1578 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1579 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1580 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1584 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1586 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1587 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1588 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1594 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1596 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1597 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1598 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1602 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1604 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1605 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1606 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1612 pinctrl_nand: nand-0 {
1614 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1615 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1617 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1618 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1620 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1621 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1622 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1623 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1624 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1625 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1626 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1627 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1628 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1629 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1634 pinctrl_spi0: spi0-0 {
1636 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1637 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1638 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1644 pinctrl_ssc0_tx: ssc0_tx {
1646 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
1647 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
1648 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1651 pinctrl_ssc0_rx: ssc0_rx {
1653 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
1654 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
1655 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1660 pinctrl_ssc1_tx: ssc1_tx {
1662 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
1663 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
1664 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1667 pinctrl_ssc1_rx: ssc1_rx {
1669 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
1670 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
1671 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1676 pinctrl_usart2: usart2-0 {
1678 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1679 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1683 pinctrl_usart2_rts: usart2_rts-0 {
1684 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1687 pinctrl_usart2_cts: usart2_cts-0 {
1688 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1693 pinctrl_usart0: usart0-0 {
1695 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
1696 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
1700 pinctrl_usart0_rts: usart0_rts-0 {
1701 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1704 pinctrl_usart0_cts: usart0_cts-0 {
1705 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1710 pinctrl_usart1: usart1-0 {
1712 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
1713 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
1717 pinctrl_usart1_rts: usart1_rts-0 {
1718 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1721 pinctrl_usart1_cts: usart1_cts-0 {
1722 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1727 pinctrl_usart3: usart3-0 {
1729 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1730 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1736 pinctrl_usart4: usart4-0 {
1738 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1739 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1743 pinctrl_usart4_rts: usart4_rts-0 {
1744 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1747 pinctrl_usart4_cts: usart4_cts-0 {
1748 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1753 aic: interrupt-controller@fc06e000 {
1754 #interrupt-cells = <3>;
1755 compatible = "atmel,sama5d4-aic";
1756 interrupt-controller;
1757 reg = <0xfc06e000 0x200>;
1758 atmel,external-irqs = <56>;