arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/bitops.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqchip.h>
  17 #include <linux/io.h>
  18 #include <linux/device.h>
  19 #include <linux/gpio.h>
  20 #include <clocksource/samsung_pwm.h>
  21 #include <linux/sched.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/of.h>
  24 #include <linux/of_fdt.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/export.h>
  27 #include <linux/irqdomain.h>
  28 #include <linux/of_address.h>
  29 #include <linux/irqchip/arm-gic.h>
  30 #include <linux/irqchip/chained_irq.h>
  31
  32 #include <asm/proc-fns.h>
  33 #include <asm/exception.h>
  34 #include <asm/hardware/cache-l2x0.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/cacheflush.h>
  38
  39 #include <mach/regs-irq.h>
  40 #include <mach/regs-pmu.h>
  41
  42 #include <plat/cpu.h>
  43 #include <plat/pm.h>
  44 #include <plat/regs-serial.h>
  45
  46 #include "common.h"
  47 #define L2_AUX_VAL 0x7C470001
  48 #define L2_AUX_MASK 0xC200ffff
  49
  50 static const char name_exynos4210[] = "EXYNOS4210";
  51 static const char name_exynos4212[] = "EXYNOS4212";
  52 static const char name_exynos4412[] = "EXYNOS4412";
  53 static const char name_exynos5250[] = "EXYNOS5250";
  54 static const char name_exynos5420[] = "EXYNOS5420";
  55 static const char name_exynos5440[] = "EXYNOS5440";
  56
  57 static void exynos4_map_io(void);
  58 static void exynos5_map_io(void);
  59 static int exynos_init(void);
  60
  61 static struct cpu_table cpu_ids[] __initdata = {
  62         {
  63                 .idcode         = EXYNOS4210_CPU_ID,
  64                 .idmask         = EXYNOS4_CPU_MASK,
  65                 .map_io         = exynos4_map_io,
  66                 .init           = exynos_init,
  67                 .name           = name_exynos4210,
  68         }, {
  69                 .idcode         = EXYNOS4212_CPU_ID,
  70                 .idmask         = EXYNOS4_CPU_MASK,
  71                 .map_io         = exynos4_map_io,
  72                 .init           = exynos_init,
  73                 .name           = name_exynos4212,
  74         }, {
  75                 .idcode         = EXYNOS4412_CPU_ID,
  76                 .idmask         = EXYNOS4_CPU_MASK,
  77                 .map_io         = exynos4_map_io,
  78                 .init           = exynos_init,
  79                 .name           = name_exynos4412,
  80         }, {
  81                 .idcode         = EXYNOS5250_SOC_ID,
  82                 .idmask         = EXYNOS5_SOC_MASK,
  83                 .map_io         = exynos5_map_io,
  84                 .init           = exynos_init,
  85                 .name           = name_exynos5250,
  86         }, {
  87                 .idcode         = EXYNOS5420_SOC_ID,
  88                 .idmask         = EXYNOS5_SOC_MASK,
  89                 .map_io         = exynos5_map_io,
  90                 .init           = exynos_init,
  91                 .name           = name_exynos5420,
  92         }, {
  93                 .idcode         = EXYNOS5440_SOC_ID,
  94                 .idmask         = EXYNOS5_SOC_MASK,
  95                 .init           = exynos_init,
  96                 .name           = name_exynos5440,
  97         },
  98 };
  99
 100 /* Initial IO mappings */
 101
 102 static struct map_desc exynos4_iodesc[] __initdata = {
 103         {
 104                 .virtual        = (unsigned long)S3C_VA_SYS,
 105                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 106                 .length         = SZ_64K,
 107                 .type           = MT_DEVICE,
 108         }, {
 109                 .virtual        = (unsigned long)S3C_VA_TIMER,
 110                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 111                 .length         = SZ_16K,
 112                 .type           = MT_DEVICE,
 113         }, {
 114                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 115                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 116                 .length         = SZ_4K,
 117                 .type           = MT_DEVICE,
 118         }, {
 119                 .virtual        = (unsigned long)S5P_VA_SROMC,
 120                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 121                 .length         = SZ_4K,
 122                 .type           = MT_DEVICE,
 123         }, {
 124                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 125                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 126                 .length         = SZ_4K,
 127                 .type           = MT_DEVICE,
 128         }, {
 129                 .virtual        = (unsigned long)S5P_VA_PMU,
 130                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 131                 .length         = SZ_64K,
 132                 .type           = MT_DEVICE,
 133         }, {
 134                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 135                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 136                 .length         = SZ_4K,
 137                 .type           = MT_DEVICE,
 138         }, {
 139                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 140                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 141                 .length         = SZ_64K,
 142                 .type           = MT_DEVICE,
 143         }, {
 144                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 145                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 146                 .length         = SZ_64K,
 147                 .type           = MT_DEVICE,
 148         }, {
 149                 .virtual        = (unsigned long)S5P_VA_CMU,
 150                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 151                 .length         = SZ_128K,
 152                 .type           = MT_DEVICE,
 153         }, {
 154                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 155                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 156                 .length         = SZ_8K,
 157                 .type           = MT_DEVICE,
 158         }, {
 159                 .virtual        = (unsigned long)S5P_VA_L2CC,
 160                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 161                 .length         = SZ_4K,
 162                 .type           = MT_DEVICE,
 163         }, {
 164                 .virtual        = (unsigned long)S5P_VA_DMC0,
 165                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 166                 .length         = SZ_64K,
 167                 .type           = MT_DEVICE,
 168         }, {
 169                 .virtual        = (unsigned long)S5P_VA_DMC1,
 170                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 171                 .length         = SZ_64K,
 172                 .type           = MT_DEVICE,
 173         }, {
 174                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 175                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 176                 .length         = SZ_4K,
 177                 .type           = MT_DEVICE,
 178         },
 179 };
 180
 181 static struct map_desc exynos4_iodesc0[] __initdata = {
 182         {
 183                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 184                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 185                 .length         = SZ_4K,
 186                 .type           = MT_DEVICE,
 187         },
 188 };
 189
 190 static struct map_desc exynos4_iodesc1[] __initdata = {
 191         {
 192                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 193                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 194                 .length         = SZ_4K,
 195                 .type           = MT_DEVICE,
 196         },
 197 };
 198
 199 static struct map_desc exynos4210_iodesc[] __initdata = {
 200         {
 201                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 202                 .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
 203                 .length         = SZ_4K,
 204                 .type           = MT_DEVICE,
 205         },
 206 };
 207
 208 static struct map_desc exynos4x12_iodesc[] __initdata = {
 209         {
 210                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 211                 .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
 212                 .length         = SZ_4K,
 213                 .type           = MT_DEVICE,
 214         },
 215 };
 216
 217 static struct map_desc exynos5250_iodesc[] __initdata = {
 218         {
 219                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 220                 .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
 221                 .length         = SZ_4K,
 222                 .type           = MT_DEVICE,
 223         },
 224 };
 225
 226 static struct map_desc exynos5_iodesc[] __initdata = {
 227         {
 228                 .virtual        = (unsigned long)S3C_VA_SYS,
 229                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 230                 .length         = SZ_64K,
 231                 .type           = MT_DEVICE,
 232         }, {
 233                 .virtual        = (unsigned long)S3C_VA_TIMER,
 234                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 235                 .length         = SZ_16K,
 236                 .type           = MT_DEVICE,
 237         }, {
 238                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 239                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 240                 .length         = SZ_4K,
 241                 .type           = MT_DEVICE,
 242         }, {
 243                 .virtual        = (unsigned long)S5P_VA_SROMC,
 244                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 245                 .length         = SZ_4K,
 246                 .type           = MT_DEVICE,
 247         }, {
 248                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 249                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 250                 .length         = SZ_4K,
 251                 .type           = MT_DEVICE,
 252         }, {
 253                 .virtual        = (unsigned long)S5P_VA_CMU,
 254                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 255                 .length         = 144 * SZ_1K,
 256                 .type           = MT_DEVICE,
 257         }, {
 258                 .virtual        = (unsigned long)S5P_VA_PMU,
 259                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 260                 .length         = SZ_64K,
 261                 .type           = MT_DEVICE,
 262         },
 263 };
 264
 265 void exynos4_restart(enum reboot_mode mode, const char *cmd)
 266 {
 267         __raw_writel(0x1, S5P_SWRESET);
 268 }
 269
 270 void exynos5_restart(enum reboot_mode mode, const char *cmd)
 271 {
 272         struct device_node *np;
 273         u32 val;
 274         void __iomem *addr;
 275
 276         val = 0x1;
 277         addr = EXYNOS_SWRESET;
 278
 279         if (of_machine_is_compatible("samsung,exynos5440")) {
 280                 u32 status;
 281                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 282
 283                 addr = of_iomap(np, 0) + 0xbc;
 284                 status = __raw_readl(addr);
 285
 286                 addr = of_iomap(np, 0) + 0xcc;
 287                 val = __raw_readl(addr);
 288
 289                 val = (val & 0xffff0000) | (status & 0xffff);
 290         }
 291
 292         __raw_writel(val, addr);
 293 }
 294
 295 void __init exynos_init_late(void)
 296 {
 297         if (of_machine_is_compatible("samsung,exynos5440"))
 298                 /* to be supported later */
 299                 return;
 300
 301         exynos_pm_late_initcall();
 302 }
 303
 304 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 305                                         int depth, void *data)
 306 {
 307         struct map_desc iodesc;
 308         __be32 *reg;
 309         unsigned long len;
 310
 311         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 312                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 313                 return 0;
 314
 315         reg = of_get_flat_dt_prop(node, "reg", &len);
 316         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 317                 return 0;
 318
 319         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 320         iodesc.length = be32_to_cpu(reg[1]) - 1;
 321         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 322         iodesc.type = MT_DEVICE;
 323         iotable_init(&iodesc, 1);
 324         return 1;
 325 }
 326
 327 /*
 328  * exynos_map_io
 329  *
 330  * register the standard cpu IO areas
 331  */
 332
 333 void __init exynos_init_io(void)
 334 {
 335         debug_ll_io_init();
 336
 337         of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 338
 339         /* detect cpu id and rev. */
 340         s5p_init_cpu(S5P_VA_CHIPID);
 341
 342         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 343 }
 344
 345 static void __init exynos4_map_io(void)
 346 {
 347         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 348
 349         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 350                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 351         else
 352                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 353
 354         if (soc_is_exynos4210())
 355                 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
 356         if (soc_is_exynos4212() || soc_is_exynos4412())
 357                 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
 358 }
 359
 360 static void __init exynos5_map_io(void)
 361 {
 362         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 363
 364         if (soc_is_exynos5250())
 365                 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 366 }
 367
 368 struct bus_type exynos_subsys = {
 369         .name           = "exynos-core",
 370         .dev_name       = "exynos-core",
 371 };
 372
 373 static struct device exynos4_dev = {
 374         .bus    = &exynos_subsys,
 375 };
 376
 377 static int __init exynos_core_init(void)
 378 {
 379         return subsys_system_register(&exynos_subsys, NULL);
 380 }
 381 core_initcall(exynos_core_init);
 382
 383 static int __init exynos4_l2x0_cache_init(void)
 384 {
 385         int ret;
 386
 387         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 388         if (ret)
 389                 return ret;
 390
 391         l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 392         clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 393         return 0;
 394 }
 395 early_initcall(exynos4_l2x0_cache_init);
 396
 397 static int __init exynos_init(void)
 398 {
 399         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 400
 401         return device_register(&exynos4_dev);
 402 }