arch/arm/mach-imx/mach-imx6q.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/cpu.h>
  17 #include <linux/delay.h>
  18 #include <linux/export.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21 #include <linux/irq.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/opp.h>
  28 #include <linux/phy.h>
  29 #include <linux/regmap.h>
  30 #include <linux/micrel_phy.h>
  31 #include <linux/mfd/syscon.h>
  32 #include <asm/hardware/cache-l2x0.h>
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/map.h>
  35 #include <asm/system_misc.h>
  36
  37 #include "common.h"
  38 #include "cpuidle.h"
  39 #include "hardware.h"
  40
  41 #define IMX6Q_ANALOG_DIGPROG    0x260
  42
  43 static int imx6q_revision(void)
  44 {
  45         struct device_node *np;
  46         void __iomem *base;
  47         static u32 rev;
  48
  49         if (!rev) {
  50                 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
  51                 if (!np)
  52                         return IMX_CHIP_REVISION_UNKNOWN;
  53                 base = of_iomap(np, 0);
  54                 if (!base) {
  55                         of_node_put(np);
  56                         return IMX_CHIP_REVISION_UNKNOWN;
  57                 }
  58                 rev =  readl_relaxed(base + IMX6Q_ANALOG_DIGPROG);
  59                 iounmap(base);
  60                 of_node_put(np);
  61         }
  62
  63         switch (rev & 0xff) {
  64         case 0:
  65                 return IMX_CHIP_REVISION_1_0;
  66         case 1:
  67                 return IMX_CHIP_REVISION_1_1;
  68         case 2:
  69                 return IMX_CHIP_REVISION_1_2;
  70         default:
  71                 return IMX_CHIP_REVISION_UNKNOWN;
  72         }
  73 }
  74
  75 void imx6q_restart(char mode, const char *cmd)
  76 {
  77         struct device_node *np;
  78         void __iomem *wdog_base;
  79
  80         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
  81         wdog_base = of_iomap(np, 0);
  82         if (!wdog_base)
  83                 goto soft;
  84
  85         imx_src_prepare_restart();
  86
  87         /* enable wdog */
  88         writew_relaxed(1 << 2, wdog_base);
  89         /* write twice to ensure the request will not get ignored */
  90         writew_relaxed(1 << 2, wdog_base);
  91
  92         /* wait for reset to assert ... */
  93         mdelay(500);
  94
  95         pr_err("Watchdog reset failed to assert reset\n");
  96
  97         /* delay to allow the serial port to show the message */
  98         mdelay(50);
  99
 100 soft:
 101         /* we'll take a jump through zero as a poor second */
 102         soft_restart(0);
 103 }
 104
 105 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
 106 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 107 {
 108         if (IS_BUILTIN(CONFIG_PHYLIB)) {
 109                 /* min rx data delay */
 110                 phy_write(phydev, 0x0b, 0x8105);
 111                 phy_write(phydev, 0x0c, 0x0000);
 112
 113                 /* max rx/tx clock delay, min rx/tx control delay */
 114                 phy_write(phydev, 0x0b, 0x8104);
 115                 phy_write(phydev, 0x0c, 0xf0f0);
 116                 phy_write(phydev, 0x0b, 0x104);
 117         }
 118
 119         return 0;
 120 }
 121
 122 static void __init imx6q_sabrelite_cko1_setup(void)
 123 {
 124         struct clk *cko1_sel, *ahb, *cko1;
 125         unsigned long rate;
 126
 127         cko1_sel = clk_get_sys(NULL, "cko1_sel");
 128         ahb = clk_get_sys(NULL, "ahb");
 129         cko1 = clk_get_sys(NULL, "cko1");
 130         if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
 131                 pr_err("cko1 setup failed!\n");
 132                 goto put_clk;
 133         }
 134         clk_set_parent(cko1_sel, ahb);
 135         rate = clk_round_rate(cko1, 16000000);
 136         clk_set_rate(cko1, rate);
 137 put_clk:
 138         if (!IS_ERR(cko1_sel))
 139                 clk_put(cko1_sel);
 140         if (!IS_ERR(ahb))
 141                 clk_put(ahb);
 142         if (!IS_ERR(cko1))
 143                 clk_put(cko1);
 144 }
 145
 146 static void __init imx6q_sabrelite_init(void)
 147 {
 148         if (IS_BUILTIN(CONFIG_PHYLIB))
 149                 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
 150                                 ksz9021rn_phy_fixup);
 151         imx6q_sabrelite_cko1_setup();
 152 }
 153
 154 static void __init imx6q_1588_init(void)
 155 {
 156         struct regmap *gpr;
 157
 158         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 159         if (!IS_ERR(gpr))
 160                 regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
 161         else
 162                 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
 163
 164 }
 165 static void __init imx6q_usb_init(void)
 166 {
 167         struct regmap *anatop;
 168
 169 #define HW_ANADIG_USB1_CHRG_DETECT              0x000001b0
 170 #define HW_ANADIG_USB2_CHRG_DETECT              0x00000210
 171
 172 #define BM_ANADIG_USB_CHRG_DETECT_EN_B          0x00100000
 173 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B    0x00080000
 174
 175         anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
 176         if (!IS_ERR(anatop)) {
 177                 /*
 178                  * The external charger detector needs to be disabled,
 179                  * or the signal at DP will be poor
 180                  */
 181                 regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
 182                                 BM_ANADIG_USB_CHRG_DETECT_EN_B
 183                                 | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
 184                 regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
 185                                 BM_ANADIG_USB_CHRG_DETECT_EN_B |
 186                                 BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
 187         } else {
 188                 pr_warn("failed to find fsl,imx6q-anatop regmap\n");
 189         }
 190 }
 191
 192 static void __init imx6q_init_machine(void)
 193 {
 194         if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
 195                 imx6q_sabrelite_init();
 196
 197         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 198
 199         imx6q_pm_init();
 200         imx6q_usb_init();
 201         imx6q_1588_init();
 202 }
 203
 204 #define OCOTP_CFG3                      0x440
 205 #define OCOTP_CFG3_SPEED_SHIFT          16
 206 #define OCOTP_CFG3_SPEED_1P2GHZ         0x3
 207
 208 static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
 209 {
 210         struct device_node *np;
 211         void __iomem *base;
 212         u32 val;
 213
 214         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
 215         if (!np) {
 216                 pr_warn("failed to find ocotp node\n");
 217                 return;
 218         }
 219
 220         base = of_iomap(np, 0);
 221         if (!base) {
 222                 pr_warn("failed to map ocotp\n");
 223                 goto put_node;
 224         }
 225
 226         val = readl_relaxed(base + OCOTP_CFG3);
 227         val >>= OCOTP_CFG3_SPEED_SHIFT;
 228         if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
 229                 if (opp_disable(cpu_dev, 1200000000))
 230                         pr_warn("failed to disable 1.2 GHz OPP\n");
 231
 232 put_node:
 233         of_node_put(np);
 234 }
 235
 236 static void __init imx6q_opp_init(struct device *cpu_dev)
 237 {
 238         struct device_node *np;
 239
 240         np = of_find_node_by_path("/cpus/cpu@0");
 241         if (!np) {
 242                 pr_warn("failed to find cpu0 node\n");
 243                 return;
 244         }
 245
 246         cpu_dev->of_node = np;
 247         if (of_init_opp_table(cpu_dev)) {
 248                 pr_warn("failed to init OPP table\n");
 249                 goto put_node;
 250         }
 251
 252         imx6q_opp_check_1p2ghz(cpu_dev);
 253
 254 put_node:
 255         of_node_put(np);
 256 }
 257
 258 struct platform_device imx6q_cpufreq_pdev = {
 259         .name = "imx6q-cpufreq",
 260 };
 261
 262 static void __init imx6q_init_late(void)
 263 {
 264         /*
 265          * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
 266          * to run cpuidle on them.
 267          */
 268         if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
 269                 imx6q_cpuidle_init();
 270
 271         if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
 272                 imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
 273                 platform_device_register(&imx6q_cpufreq_pdev);
 274         }
 275 }
 276
 277 static void __init imx6q_map_io(void)
 278 {
 279         debug_ll_io_init();
 280         imx_scu_map_io();
 281 }
 282
 283 static void __init imx6q_init_irq(void)
 284 {
 285         l2x0_of_init(0, ~0UL);
 286         imx_src_init();
 287         imx_gpc_init();
 288         irqchip_init();
 289 }
 290
 291 static void __init imx6q_timer_init(void)
 292 {
 293         mx6q_clocks_init();
 294         clocksource_of_init();
 295         imx_print_silicon_rev("i.MX6Q", imx6q_revision());
 296 }
 297
 298 static const char *imx6q_dt_compat[] __initdata = {
 299         "fsl,imx6q",
 300         NULL,
 301 };
 302
 303 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
 304         .smp            = smp_ops(imx_smp_ops),
 305         .map_io         = imx6q_map_io,
 306         .init_irq       = imx6q_init_irq,
 307         .init_time      = imx6q_timer_init,
 308         .init_machine   = imx6q_init_machine,
 309         .init_late      = imx6q_init_late,
 310         .dt_compat      = imx6q_dt_compat,
 311         .restart        = imx6q_restart,
 312 MACHINE_END