arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17 #include <dt-bindings/clock/qcom,rpmcc.h>
  18 #include <dt-bindings/thermal/thermal.h>
  19 #include <dt-bindings/arm/qcom-ids.h>
  20
  21 / {
  22         model = "Qualcomm Technologies, Inc. MSM8916";
  23         compatible = "qcom,msm8916";
  24         qcom,msm-id =   <QCOM_ID_MSM8916 0>,
  25                         <QCOM_ID_MSM8216 0>,
  26                         <QCOM_ID_MSM8116 0>,
  27                         <QCOM_ID_MSM8616 0>,
  28                         <QCOM_ID_APQ8016 0>;
  29
  30
  31         interrupt-parent = <&intc>;
  32
  33         #address-cells = <2>;
  34         #size-cells = <2>;
  35
  36         aliases {
  37                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  38                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  39         };
  40
  41         chosen { };
  42
  43         memory {
  44                 device_type = "memory";
  45                 /* We expect the bootloader to fill in the reg */
  46                 reg = <0 0 0 0>;
  47         };
  48
  49         reserved-memory {
  50                 #address-cells = <2>;
  51                 #size-cells = <2>;
  52                 ranges;
  53
  54                 tz-apps@86000000 {
  55                         reg = <0x0 0x86000000 0x0 0x300000>;
  56                         no-map;
  57                 };
  58
  59                 smem_mem: smem_region@86300000 {
  60                         reg = <0x0 0x86300000 0x0 0x100000>;
  61                         no-map;
  62                 };
  63
  64                 hypervisor@86400000 {
  65                         reg = <0x0 0x86400000 0x0 0x100000>;
  66                         no-map;
  67                 };
  68
  69                 tz@86500000 {
  70                         reg = <0x0 0x86500000 0x0 0x180000>;
  71                         no-map;
  72                 };
  73
  74                 reserved@86680000 {
  75                         reg = <0x0 0x86680000 0x0 0x80000>;
  76                         no-map;
  77                 };
  78
  79                 rmtfs@86700000 {
  80                         reg = <0x0 0x86700000 0x0 0xe0000>;
  81                         no-map;
  82                 };
  83
  84                 rfsa@867e00000 {
  85                         reg = <0x0 0x867e0000 0x0 0x20000>;
  86                         no-map;
  87                 };
  88
  89                 modem_adsp_mem: modem_adsp_region@86800000 {
  90                         reg = <0x0 0x86800000 0x0 0x2b00000>;
  91                         no-map;
  92                 };
  93
  94                 wcnss_mem: wcnss@89300000 {
  95                         reg = <0x0 0x89300000 0x0 0x600000>;
  96                         no-map;
  97                 };
  98
  99                 vidc_mem: vidc_region@8f800000 {
 100                         reg = <0 0x8f800000 0 0x800000>;
 101                         no-map;
 102                 };
 103
 104                 mba_mem: mba@8ea00000 {
 105                         reg = <0 0x8ea00000 0 0x100000>;
 106                         no-map;
 107                 };
 108         };
 109
 110         cpus {
 111                 #address-cells = <1>;
 112                 #size-cells = <0>;
 113
 114                 CPU0: cpu@0 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a53", "arm,armv8";
 117                         reg = <0x0>;
 118                         enable-method = "qcom,arm-cortex-acc";
 119                         qcom,acc = <&acc0>;
 120                         next-level-cache = <&L2_0>;
 121                         clocks = <&a53cc 1>;
 122                         clock-latency = <200000>;
 123                         cpu-supply = <&pm8916_spmi_s2>;
 124                         /* cooling options */
 125                         cooling-min-level = <0>;
 126                         cooling-max-level = <7>;
 127                         #cooling-cells = <2>;
 128                         L2_0: l2-cache {
 129                               compatible = "arm,arch-cache";
 130                               cache-level = <2>;
 131                               power-domain = <&l2ccc_0>;
 132                         };
 133                 };
 134
 135                 CPU1: cpu@1 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x1>;
 139                         enable-method = "qcom,arm-cortex-acc";
 140                         qcom,acc = <&acc1>;
 141                         next-level-cache = <&L2_0>;
 142                         clocks = <&a53cc 1>;
 143                         clock-latency = <200000>;
 144                         cpu-supply = <&pm8916_spmi_s2>;
 145                         /* cooling options */
 146                         cooling-min-level = <0>;
 147                         cooling-max-level = <7>;
 148                         #cooling-cells = <2>;
 149                 };
 150
 151                 CPU2: cpu@2 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a53", "arm,armv8";
 154                         reg = <0x2>;
 155                         enable-method = "qcom,arm-cortex-acc";
 156                         qcom,acc = <&acc2>;
 157                         next-level-cache = <&L2_0>;
 158                         clocks = <&a53cc 1>;
 159                         clock-latency = <200000>;
 160                         cpu-supply = <&pm8916_spmi_s2>;
 161                         /* cooling options */
 162                         cooling-min-level = <0>;
 163                         cooling-max-level = <7>;
 164                         #cooling-cells = <2>;
 165                 };
 166
 167                 CPU3: cpu@3 {
 168                         device_type = "cpu";
 169                         compatible = "arm,cortex-a53", "arm,armv8";
 170                         reg = <0x3>;
 171                         enable-method = "qcom,arm-cortex-acc";
 172                         qcom,acc = <&acc3>;
 173                         next-level-cache = <&L2_0>;
 174                         clocks = <&a53cc 1>;
 175                         clock-latency = <200000>;
 176                         cpu-supply = <&pm8916_spmi_s2>;
 177                         /* cooling options */
 178                         cooling-min-level = <0>;
 179                         cooling-max-level = <7>;
 180                         #cooling-cells = <2>;
 181                 };
 182         };
 183
 184         psci {
 185                 compatible = "arm,psci-1.0";
 186                 method = "smc";
 187         };
 188
 189         cpu-pmu {
 190                 compatible = "arm,armv8-pmuv3";
 191                 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
 192         };
 193
 194         thermal-zones {
 195                 cpu-thermal0 {
 196                         polling-delay-passive = <250>;
 197                         polling-delay = <1000>;
 198
 199                         thermal-sensors = <&tsens 4>;
 200
 201                         trips {
 202                                 cpu_alert0: trip@0 {
 203                                         temperature = <75000>;
 204                                         hysteresis = <2000>;
 205                                         type = "passive";
 206                                 };
 207                                 cpu_crit0: trip@1 {
 208                                         temperature = <100000>;
 209                                         hysteresis = <2000>;
 210                                         type = "critical";
 211                                 };
 212                         };
 213
 214                         cooling-maps {
 215                                 map0 {
 216                                         trip = <&cpu_alert0>;
 217                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 218                                 };
 219                         };
 220                 };
 221
 222                 cpu-thermal1 {
 223                         polling-delay-passive = <250>;
 224                         polling-delay = <1000>;
 225
 226                         thermal-sensors = <&tsens 3>;
 227
 228                         trips {
 229                                 cpu_alert1: trip@0 {
 230                                         temperature = <75000>;
 231                                         hysteresis = <2000>;
 232                                         type = "passive";
 233                                 };
 234                                 cpu_crit1: trip@1 {
 235                                         temperature = <100000>;
 236                                         hysteresis = <2000>;
 237                                         type = "critical";
 238                                 };
 239                         };
 240
 241                         cooling-maps {
 242                                 map0 {
 243                                         trip = <&cpu_alert1>;
 244                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 245                                 };
 246                         };
 247                 };
 248         };
 249
 250         timer {
 251                 compatible = "arm,armv8-timer";
 252                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 253                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 254                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 255                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 256         };
 257
 258         clocks {
 259                 xo_board: xo_board {
 260                         compatible = "fixed-clock";
 261                         #clock-cells = <0>;
 262                         clock-frequency = <19200000>;
 263                         clock-output-names = "xo_board";
 264                 };
 265
 266                 sleep_clk: sleep_clk {
 267                         compatible = "fixed-clock";
 268                         #clock-cells = <0>;
 269                         clock-frequency = <32768>;
 270                 };
 271         };
 272
 273         firmware {
 274                 compatible = "simple-bus";
 275
 276                 scm: scm {
 277                         compatible = "qcom,scm";
 278                         clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
 279                         clock-names = "core", "bus", "iface";
 280                         #reset-cells = <1>;
 281                 };
 282         };
 283
 284         soc: soc {
 285                 #address-cells = <1>;
 286                 #size-cells = <1>;
 287                 ranges = <0 0 0 0xffffffff>;
 288                 compatible = "simple-bus";
 289
 290                 restart@4ab000 {
 291                         compatible = "qcom,pshold";
 292                         reg = <0x4ab000 0x4>;
 293                 };
 294
 295                 camss@0 {
 296                         compatible = "qcom,msm-camss";
 297
 298                         reg = <0x1b0ac00 0x200>,
 299                                 <0x1b00030 0x4>,
 300                                 <0x1b0b000 0x200>,
 301                                 <0x1b00038 0x4>,
 302                                 <0x1b08000 0x100>,
 303                                 <0x1b08400 0x100>,
 304                                 <0x1b0a000 0x500>,
 305                                 <0x1b00020 0x10>,
 306                                 <0x1b10000 0x1000>,
 307                                 <0x1b40000 0x200>;
 308                         reg-names = "csiphy0",
 309                                 "csiphy0_clk_mux",
 310                                 "csiphy1",
 311                                 "csiphy1_clk_mux",
 312                                 "csid0",
 313                                 "csid1",
 314                                 "ispif",
 315                                 "csi_clk_mux",
 316                                 "vfe0",
 317                                 "vfe0_vbif";
 318                         interrupts = <GIC_SPI 78 0>,
 319                                 <GIC_SPI 79 0>,
 320                                 <GIC_SPI 51 0>,
 321                                 <GIC_SPI 52 0>,
 322                                 <GIC_SPI 55 0>,
 323                                 <GIC_SPI 57 0>;
 324                         interrupt-names = "csiphy0",
 325                                 "csiphy1",
 326                                 "csid0",
 327                                 "csid1",
 328                                 "ispif",
 329                                 "vfe0";
 330                         power-domains = <&gcc VFE_GDSC>;
 331                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
 332                                 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
 333                                 <&gcc CSI0PHYTIMER_CLK_SRC>,
 334                                 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
 335                                 <&gcc CSI1PHYTIMER_CLK_SRC>,
 336                                 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
 337                                 <&gcc CAMSS_AHB_CLK_SRC>,
 338                                 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
 339                                 <&gcc CSI0_CLK_SRC>,
 340                                 <&gcc GCC_CAMSS_CSI0_CLK>,
 341                                 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
 342                                 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
 343                                 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
 344                                 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
 345                                 <&gcc CSI1_CLK_SRC>,
 346                                 <&gcc GCC_CAMSS_CSI1_CLK>,
 347                                 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
 348                                 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
 349                                 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
 350                                 <&gcc GCC_CAMSS_AHB_CLK>,
 351                                 <&gcc VFE0_CLK_SRC>,
 352                                 <&gcc GCC_CAMSS_VFE0_CLK>,
 353                                 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
 354                                 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
 355                                 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
 356                         clock-names = "camss_top_ahb_clk",
 357                                 "ispif_ahb_clk",
 358                                 "csiphy0_timer_src_clk",
 359                                 "csiphy0_timer_clk",
 360                                 "csiphy1_timer_src_clk",
 361                                 "csiphy1_timer_clk",
 362                                 "camss_ahb_src",
 363                                 "csi0_ahb_clk",
 364                                 "csi0_src_clk",
 365                                 "csi0_clk",
 366                                 "csi0_phy_clk",
 367                                 "csi0_pix_clk",
 368                                 "csi0_rdi_clk",
 369                                 "csi1_ahb_clk",
 370                                 "csi1_src_clk",
 371                                 "csi1_clk",
 372                                 "csi1_phy_clk",
 373                                 "csi1_pix_clk",
 374                                 "csi1_rdi_clk",
 375                                 "camss_ahb_clk",
 376                                 "vfe_clk_src",
 377                                 "camss_vfe_vfe_clk",
 378                                 "camss_csi_vfe_clk",
 379                                 "iface_clk",
 380                                 "bus_clk";
 381                         vdda-supply = <&pm8916_l2>;
 382
 383                         qcom,msm-bus,name = "msm_camera_isp";
 384                         qcom,msm-bus,num-cases = <3>;
 385                         qcom,msm-bus,num-paths = <1>;
 386                         qcom,msm-bus,vectors-KBps =
 387                                         <29 512 0 0>,
 388                                         <29 512 450000 900000>,
 389                                         <29 512 11000 11000>;
 390
 391                         ports {
 392                                 #address-cells = <1>;
 393                                 #size-cells = <0>;
 394                                 port@0 {
 395                                         reg = <0>;
 396                                         csiphy0_ep: endpoint {
 397                                                 clock-lanes = <1>;
 398                                                 data-lanes = <0 2>;
 399                                                 qcom,settle-cnt = <0xe>;
 400                                                 remote-endpoint = <&ov5645_ep>;
 401                                         };
 402                                 };
 403                         };
 404                 };
 405
 406                 cci: qcom,cci@1b0c000 {
 407                         cell-index = <0>;
 408                         compatible = "qcom,cci";
 409                         reg = <0x1b0c000 0x1000>;
 410                         #address-cells = <1>;
 411                         #size-cells = <0>;
 412                         reg-names = "cci";
 413                         interrupts = <GIC_SPI 50 0>;
 414                         interrupt-names = "cci";
 415                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
 416                                 <&gcc CCI_CLK_SRC>,
 417                                 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
 418                                 <&gcc GCC_CAMSS_CCI_CLK>,
 419                                 <&gcc GCC_CAMSS_AHB_CLK>;
 420                         clock-names = "camss_top_ahb_clk",
 421                                 "cci_src_clk",
 422                                 "cci_ahb_clk",
 423                                 "cci_clk",
 424                                 "camss_ahb_clk";
 425                         qcom,clock-rates = <0 19200000 80000000 0 0>;
 426                         pinctrl-names = "default", "sleep";
 427                         pinctrl-0 = <&cci0_default>;
 428                         pinctrl-1 = <&cci0_sleep>;
 429                         i2c_freq_100Khz: qcom,i2c_standard_mode {
 430                                 status = "disabled";
 431                         };
 432                         i2c_freq_400Khz: qcom,i2c_fast_mode {
 433                                 status = "disabled";
 434                         };
 435                         i2c_freq_custom: qcom,i2c_custom_mode {
 436                                 status = "disabled";
 437                         };
 438                 };
 439
 440                 msmgpio: pinctrl@1000000 {
 441                         compatible = "qcom,msm8916-pinctrl";
 442                         reg = <0x1000000 0x300000>;
 443                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 444                         gpio-controller;
 445                         #gpio-cells = <2>;
 446                         interrupt-controller;
 447                         #interrupt-cells = <2>;
 448                 };
 449
 450                 gcc: qcom,gcc@1800000 {
 451                         compatible = "qcom,gcc-msm8916";
 452                         #clock-cells = <1>;
 453                         #reset-cells = <1>;
 454                         #power-domain-cells = <1>;
 455                         reg = <0x1800000 0x80000>;
 456                 };
 457
 458                 tcsr_mutex_regs: syscon@1905000 {
 459                         compatible = "syscon";
 460                         reg = <0x1905000 0x20000>;
 461                 };
 462
 463                 tcsr_mutex: hwlock {
 464                         compatible = "qcom,tcsr-mutex";
 465                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 466                         #hwlock-cells = <1>;
 467                 };
 468
 469                 rpm_msg_ram: memory@60000 {
 470                         compatible = "qcom,rpm-msg-ram";
 471                         reg = <0x60000 0x8000>;
 472                 };
 473
 474                 blsp1_uart1: serial@78af000 {
 475                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 476                         reg = <0x78af000 0x200>;
 477                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 478                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 479                         clock-names = "core", "iface";
 480                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 481                         dma-names = "rx", "tx";
 482                         status = "disabled";
 483                 };
 484
 485                 apcs: syscon@b011000 {
 486                         compatible = "syscon";
 487                         reg = <0x0b011000 0x1000>;
 488                 };
 489
 490                 a53cc: qcom,a53cc@0b016000 {
 491                         compatible = "qcom,clock-a53-msm8916";
 492                         reg = <0x0b016000 0x40>;
 493                         #clock-cells = <1>;
 494                         qcom,apcs = <&apcs>;
 495                 };
 496
 497                 blsp1_uart2: serial@78b0000 {
 498                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 499                         reg = <0x78b0000 0x200>;
 500                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 501                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 502                         clock-names = "core", "iface";
 503                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 504                         dma-names = "rx", "tx";
 505                         status = "disabled";
 506                 };
 507
 508                 blsp_dma: dma@7884000 {
 509                         compatible = "qcom,bam-v1.7.0";
 510                         reg = <0x07884000 0x23000>;
 511                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 512                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 513                         clock-names = "bam_clk";
 514                         #dma-cells = <1>;
 515                         qcom,ee = <0>;
 516                         status = "disabled";
 517                 };
 518
 519                 blsp_spi1: spi@78b5000 {
 520                         compatible = "qcom,spi-qup-v2.2.1";
 521                         reg = <0x078b5000 0x600>;
 522                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 523                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 524                                  <&gcc GCC_BLSP1_AHB_CLK>;
 525                         clock-names = "core", "iface";
 526                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 527                         dma-names = "rx", "tx";
 528                         pinctrl-names = "default", "sleep";
 529                         pinctrl-0 = <&spi1_default>;
 530                         pinctrl-1 = <&spi1_sleep>;
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         status = "disabled";
 534                 };
 535
 536                 blsp_spi2: spi@78b6000 {
 537                         compatible = "qcom,spi-qup-v2.2.1";
 538                         reg = <0x078b6000 0x600>;
 539                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 540                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 541                                  <&gcc GCC_BLSP1_AHB_CLK>;
 542                         clock-names = "core", "iface";
 543                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 544                         dma-names = "rx", "tx";
 545                         pinctrl-names = "default", "sleep";
 546                         pinctrl-0 = <&spi2_default>;
 547                         pinctrl-1 = <&spi2_sleep>;
 548                         #address-cells = <1>;
 549                         #size-cells = <0>;
 550                         status = "disabled";
 551                 };
 552
 553                 blsp_spi3: spi@78b7000 {
 554                         compatible = "qcom,spi-qup-v2.2.1";
 555                         reg = <0x078b7000 0x600>;
 556                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 557                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 558                                  <&gcc GCC_BLSP1_AHB_CLK>;
 559                         clock-names = "core", "iface";
 560                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 561                         dma-names = "rx", "tx";
 562                         pinctrl-names = "default", "sleep";
 563                         pinctrl-0 = <&spi3_default>;
 564                         pinctrl-1 = <&spi3_sleep>;
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567                         status = "disabled";
 568                 };
 569
 570                 blsp_spi4: spi@78b8000 {
 571                         compatible = "qcom,spi-qup-v2.2.1";
 572                         reg = <0x078b8000 0x600>;
 573                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 574                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 575                                  <&gcc GCC_BLSP1_AHB_CLK>;
 576                         clock-names = "core", "iface";
 577                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 578                         dma-names = "rx", "tx";
 579                         pinctrl-names = "default", "sleep";
 580                         pinctrl-0 = <&spi4_default>;
 581                         pinctrl-1 = <&spi4_sleep>;
 582                         #address-cells = <1>;
 583                         #size-cells = <0>;
 584                         status = "disabled";
 585                 };
 586
 587                 blsp_spi5: spi@78b9000 {
 588                         compatible = "qcom,spi-qup-v2.2.1";
 589                         reg = <0x078b9000 0x600>;
 590                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 591                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 592                                  <&gcc GCC_BLSP1_AHB_CLK>;
 593                         clock-names = "core", "iface";
 594                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 595                         dma-names = "rx", "tx";
 596                         pinctrl-names = "default", "sleep";
 597                         pinctrl-0 = <&spi5_default>;
 598                         pinctrl-1 = <&spi5_sleep>;
 599                         #address-cells = <1>;
 600                         #size-cells = <0>;
 601                         status = "disabled";
 602                 };
 603
 604                 blsp_spi6: spi@78ba000 {
 605                         compatible = "qcom,spi-qup-v2.2.1";
 606                         reg = <0x078ba000 0x600>;
 607                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 608                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 609                                  <&gcc GCC_BLSP1_AHB_CLK>;
 610                         clock-names = "core", "iface";
 611                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 612                         dma-names = "rx", "tx";
 613                         pinctrl-names = "default", "sleep";
 614                         pinctrl-0 = <&spi6_default>;
 615                         pinctrl-1 = <&spi6_sleep>;
 616                         #address-cells = <1>;
 617                         #size-cells = <0>;
 618                         status = "disabled";
 619                 };
 620
 621                 blsp_i2c2: i2c@78b6000 {
 622                         compatible = "qcom,i2c-qup-v2.2.1";
 623                         reg = <0x78b6000 0x1000>;
 624                         interrupts = <GIC_SPI 96 0>;
 625                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 626                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 627                         clock-names = "iface", "core";
 628                         pinctrl-names = "default", "sleep";
 629                         pinctrl-0 = <&i2c2_default>;
 630                         pinctrl-1 = <&i2c2_sleep>;
 631                         #address-cells = <1>;
 632                         #size-cells = <0>;
 633                         status = "disabled";
 634                 };
 635
 636                 blsp_i2c4: i2c@78b8000 {
 637                         compatible = "qcom,i2c-qup-v2.2.1";
 638                         reg = <0x78b8000 0x1000>;
 639                         interrupts = <GIC_SPI 98 0>;
 640                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 641                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 642                         clock-names = "iface", "core";
 643                         pinctrl-names = "default", "sleep";
 644                         pinctrl-0 = <&i2c4_default>;
 645                         pinctrl-1 = <&i2c4_sleep>;
 646                         #address-cells = <1>;
 647                         #size-cells = <0>;
 648                         status = "disabled";
 649                 };
 650
 651                 camera_vdddo_1v8: fixedregulator@0 {
 652                         compatible = "regulator-fixed";
 653                         regulator-name = "camera_vdddo";
 654                         regulator-min-microvolt = <1800000>;
 655                         regulator-max-microvolt = <1800000>;
 656                         regulator-always-on;
 657                 };
 658
 659                 camera_vdda_2v8: fixedregulator@1 {
 660                         compatible = "regulator-fixed";
 661                         regulator-name = "camera_vdda";
 662                         regulator-min-microvolt = <2800000>;
 663                         regulator-max-microvolt = <2800000>;
 664                         regulator-always-on;
 665                 };
 666
 667                 camera_vddd_1v5: fixedregulator@2 {
 668                         compatible = "regulator-fixed";
 669                         regulator-name = "camera_vddd";
 670                         regulator-min-microvolt = <1500000>;
 671                         regulator-max-microvolt = <1500000>;
 672                         regulator-always-on;
 673                 };
 674
 675                 blsp_i2c6: i2c@78ba000 {
 676                         compatible = "qcom,i2c-qup-v2.2.1";
 677                         reg = <0x78ba000 0x1000>;
 678                         interrupts = <GIC_SPI 100 0>;
 679                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 680                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 681                         clock-names = "iface", "core";
 682                         pinctrl-names = "default", "sleep";
 683                         pinctrl-0 = <&i2c6_default>;
 684                         pinctrl-1 = <&i2c6_sleep>;
 685                         #address-cells = <1>;
 686                         #size-cells = <0>;
 687                         status = "disabled";
 688                         camera@78 {
 689                                 compatible = "ovti,ov5645";
 690                                 reg = <0x78>;
 691
 692                                 enable-gpios = <&msmgpio 34 0>;
 693                                 reset-gpios = <&msmgpio 35 1>;
 694                                 pinctrl-names = "default";
 695                                 pinctrl-0 = <&camera_rear_default>;
 696
 697                                 clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
 698                                 clock-names = "xclk";
 699
 700                                 vdddo-supply = <&camera_vdddo_1v8>;
 701                                 vdda-supply = <&camera_vdda_2v8>;
 702                                 vddd-supply = <&camera_vddd_1v5>;
 703
 704                                 port {
 705                                         ov5645_ep: endpoint {
 706                                                 clock-lanes = <1>;
 707                                                 data-lanes = <0 2>;
 708                                                 remote-endpoint = <&csiphy0_ep>;
 709                                         };
 710                                 };
 711                         };
 712                 };
 713
 714                 sdhc_1: sdhci@07824000 {
 715                         compatible = "qcom,sdhci-msm-v4";
 716                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 717                         reg-names = "hc_mem", "core_mem";
 718
 719                         interrupts = <0 123 0>, <0 138 0>;
 720                         interrupt-names = "hc_irq", "pwr_irq";
 721                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 722                                  <&gcc GCC_SDCC1_AHB_CLK>;
 723                         clock-names = "core", "iface";
 724                         bus-width = <8>;
 725                         non-removable;
 726                         status = "disabled";
 727                 };
 728
 729                 sdhc_2: sdhci@07864000 {
 730                         compatible = "qcom,sdhci-msm-v4";
 731                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 732                         reg-names = "hc_mem", "core_mem";
 733
 734                         interrupts = <0 125 0>, <0 221 0>;
 735                         interrupt-names = "hc_irq", "pwr_irq";
 736                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 737                                  <&gcc GCC_SDCC2_AHB_CLK>;
 738                         clock-names = "core", "iface";
 739                         bus-width = <4>;
 740                         status = "disabled";
 741                 };
 742
 743                 usb_dev: usb@78d9000 {
 744                         compatible = "qcom,ci-hdrc";
 745                         reg = <0x78d9000 0x400>;
 746                         dr_mode = "peripheral";
 747                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 748                         usb-phy = <&usb_otg>;
 749                         status = "disabled";
 750                 };
 751
 752                 usb_host: ehci@78d9000 {
 753                         compatible = "qcom,ehci-host";
 754                         reg = <0x78d9000 0x400>;
 755                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 756                         usb-phy = <&usb_otg>;
 757                         status = "disabled";
 758                 };
 759
 760                 usb_otg: phy@78d9000 {
 761                         compatible = "qcom,usb-otg-snps";
 762                         reg = <0x78d9000 0x400>;
 763                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
 764                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 765
 766                         v1p8-supply = <&pm8916_l7>;
 767                         v3p3-supply = <&pm8916_l13>;
 768                         qcom,vdd-levels = <1000000 5000000 7000000>;
 769                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 770                         dr_mode = "peripheral";
 771                         qcom,otg-control = <2>; // PMIC
 772                         qcom,manual-pullup;
 773
 774                         qcom,msm-bus,name = "usb2";
 775                         qcom,msm-bus,num-cases = <3>;
 776                         qcom,msm-bus,num-paths = <1>;
 777                         qcom,msm-bus,vectors-KBps =
 778                                         <87 512 0 0>,
 779                                         <87 512 80000 0>,
 780                                         <87 512 6000  6000>;
 781
 782                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 783                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 784                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 785                         clock-names = "iface", "core", "sleep";
 786
 787                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 788                                  <&gcc GCC_USB_HS_BCR>;
 789                         reset-names = "phy", "link";
 790                         status = "disabled";
 791                 };
 792
 793                 intc: interrupt-controller@b000000 {
 794                         compatible = "qcom,msm-qgic2";
 795                         interrupt-controller;
 796                         #interrupt-cells = <3>;
 797                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 798                 };
 799
 800                 l2ccc_0: clock-controller@b011000 {
 801                         compatible = "qcom,8916-l2ccc";
 802                         reg = <0x0b011000 0x1000>;
 803                 };
 804
 805                 timer@b020000 {
 806                         #address-cells = <1>;
 807                         #size-cells = <1>;
 808                         ranges;
 809                         compatible = "arm,armv7-timer-mem";
 810                         reg = <0xb020000 0x1000>;
 811                         clock-frequency = <19200000>;
 812
 813                         frame@b021000 {
 814                                 frame-number = <0>;
 815                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 816                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 817                                 reg = <0xb021000 0x1000>,
 818                                       <0xb022000 0x1000>;
 819                         };
 820
 821                         frame@b023000 {
 822                                 frame-number = <1>;
 823                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 824                                 reg = <0xb023000 0x1000>;
 825                                 status = "disabled";
 826                         };
 827
 828                         frame@b024000 {
 829                                 frame-number = <2>;
 830                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 831                                 reg = <0xb024000 0x1000>;
 832                                 status = "disabled";
 833                         };
 834
 835                         frame@b025000 {
 836                                 frame-number = <3>;
 837                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 838                                 reg = <0xb025000 0x1000>;
 839                                 status = "disabled";
 840                         };
 841
 842                         frame@b026000 {
 843                                 frame-number = <4>;
 844                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 845                                 reg = <0xb026000 0x1000>;
 846                                 status = "disabled";
 847                         };
 848
 849                         frame@b027000 {
 850                                 frame-number = <5>;
 851                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 852                                 reg = <0xb027000 0x1000>;
 853                                 status = "disabled";
 854                         };
 855
 856                         frame@b028000 {
 857                                 frame-number = <6>;
 858                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 859                                 reg = <0xb028000 0x1000>;
 860                                 status = "disabled";
 861                         };
 862                 };
 863
 864                 spmi_bus: spmi@200f000 {
 865                         compatible = "qcom,spmi-pmic-arb";
 866                         reg = <0x200f000 0x001000>,
 867                               <0x2400000 0x400000>,
 868                               <0x2c00000 0x400000>,
 869                               <0x3800000 0x200000>,
 870                               <0x200a000 0x002100>;
 871                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 872                         interrupt-names = "periph_irq";
 873                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 874                         qcom,ee = <0>;
 875                         qcom,channel = <0>;
 876                         #address-cells = <2>;
 877                         #size-cells = <0>;
 878                         interrupt-controller;
 879                         #interrupt-cells = <4>;
 880                 };
 881
 882                 rng@22000 {
 883                         compatible = "qcom,prng";
 884                         reg = <0x00022000 0x200>;
 885                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 886                         clock-names = "core";
 887                 };
 888                 acc0: clock-controller@b088000 {
 889                         compatible = "qcom,arm-cortex-acc";
 890                         reg = <0x0b088000 0x1000>,
 891                               <0x0b008000 0x1000>;
 892                 };
 893
 894                 acc1: clock-controller@b098000 {
 895                         compatible = "qcom,arm-cortex-acc";
 896                         reg = <0x0b098000 0x1000>,
 897                               <0x0b008000 0x1000>;
 898                 };
 899
 900                 acc2: clock-controller@b0a8000 {
 901                         compatible = "qcom,arm-cortex-acc";
 902                         reg = <0x0b0a8000 0x1000>,
 903                               <0x0b008000 0x1000>;
 904                 };
 905
 906                 acc3: clock-controller@b0b8000 {
 907                         compatible = "qcom,arm-cortex-acc";
 908                         reg = <0x0b0b8000 0x1000>,
 909                               <0x0b008000 0x1000>;
 910                 };
 911
 912                 /* Audio */
 913
 914                 lpass_codec_core: lpass-codec{
 915                         compatible = "syscon", "qcom,msm8916-lpass-codec";
 916                         reg = <0x0771c000 0x400>;
 917                 };
 918
 919                 lpass: lpass-cpu@07700000 {
 920                         status = "disabled";
 921                         compatible = "qcom,lpass-cpu-apq8016";
 922                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 923                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 924                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 925                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 926                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 927                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 928                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 929
 930                         clock-names = "ahbix-clk",
 931                                         "pcnoc-mport-clk",
 932                                         "pcnoc-sway-clk",
 933                                         "mi2s-bit-clk0",
 934                                         "mi2s-bit-clk1",
 935                                         "mi2s-bit-clk2",
 936                                         "mi2s-bit-clk3";
 937                         #sound-dai-cells = <1>;
 938
 939                         interrupts = <0 160 0>;
 940                         interrupt-names = "lpass-irq-lpaif";
 941                         reg = <0x07708000 0x10000>, <0x07702000 0x4>, <0x07702004 0x4>;
 942                         reg-names = "lpass-lpaif", "mic-iomux", "spkr-iomux";
 943                 };
 944
 945                 sound: sound {
 946                         status = "disabled";
 947                         compatible = "qcom,apq8016-sbc-sndcard";
 948                         reg = <0x07702000 0x4>, <0x07702004 0x4>;
 949                         reg-names = "mic-iomux", "spkr-iomux";
 950                 };
 951
 952                 tcsr: syscon@1937000 {
 953                         compatible = "qcom,tcsr-msm8916", "syscon";
 954                         reg = <0x1937000 0x30000>;
 955                 };
 956
 957                 uqfprom: eeprom@58000 {
 958                         compatible = "qcom,qfprom-msm8916";
 959                         reg = <0x58000 0x7000>;
 960                 };
 961
 962                 cpr@b018000 {
 963                         compatible = "qcom,cpr";
 964                         reg = <0xb018000 0x1000>;
 965                         interrupts = <0 15 1>, <0 16 1>, <0 17 1>;
 966                         vdd-mx-supply = <&pm8916_l3>;
 967                         acc-syscon = <&tcsr>;
 968                         eeprom = <&uqfprom>;
 969
 970                         qcom,cpr-ref-clk = <19200>;
 971                         qcom,cpr-timer-delay-us = <5000>;
 972                         qcom,cpr-timer-cons-up = <0>;
 973                         qcom,cpr-timer-cons-down = <2>;
 974                         qcom,cpr-up-threshold = <0>;
 975                         qcom,cpr-down-threshold = <2>;
 976                         qcom,cpr-idle-clocks = <15>;
 977                         qcom,cpr-gcnt-us = <1>;
 978                         qcom,vdd-apc-step-up-limit = <1>;
 979                         qcom,vdd-apc-step-down-limit = <1>;
 980                         qcom,cpr-cpus = <&CPU0 &CPU1 &CPU2 &CPU3>;
 981                 };
 982
 983                 qfprom: qfprom@5c000 {
 984                         compatible = "qcom,qfprom";
 985                         reg = <0x5c000 0x1000>;
 986                         #address-cells = <1>;
 987                         #size-cells = <1>;
 988                         tsens_caldata: caldata@d0 {
 989                                 reg = <0xd0 0x8>;
 990                         };
 991                         tsens_calsel: calsel@ec {
 992                                 reg = <0xec 0x4>;
 993                         };
 994                 };
 995
 996                 tsens: thermal-sensor@4a8000 {
 997                         compatible = "qcom,msm8916-tsens";
 998                         reg = <0x4a8000 0x2000>;
 999                         nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
1000                         nvmem-cell-names = "calib", "calib_sel";
1001                         qcom,tsens-slopes = <3200 3200 3200 3200 3200>;
1002                         qcom,sensor-id = <0 1 2 4 5>;
1003                         #thermal-sensor-cells = <1>;
1004                 };
1005
1006                 hexagon@4080000 {
1007                         compatible = "qcom,pil-q6v56-mss", "qcom,q6v5-pil";
1008                         reg = <0x04080000 0x100>,
1009                               <0x04020000 0x040>;
1010
1011                         reg-names = "qdsp6", "rmb";
1012
1013                         interrupts-extended = <&intc 0 24 1>,
1014                                               <&hexagon_smp2p_in 0 0>,
1015                                               <&hexagon_smp2p_in 1 0>,
1016                                               <&hexagon_smp2p_in 2 0>,
1017                                               <&hexagon_smp2p_in 3 0>;
1018                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1019
1020                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, <&gcc GCC_BOOT_ROM_AHB_CLK>;
1021                         clock-names = "iface", "bus", "mem";
1022
1023                         qcom,state = <&hexagon_smp2p_out 0>;
1024                         qcom,state-names = "stop";
1025
1026                         resets = <&scm 0>;
1027                         reset-names = "mss_restart";
1028
1029                         mx-supply = <&pm8916_l3>;
1030                         pll-supply = <&pm8916_l7>;
1031
1032                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1033
1034                         mba {
1035                                 memory-region = <&mba_mem>;
1036                         };
1037
1038                         mpss {
1039                                 memory-region = <&modem_adsp_mem>;
1040                         };
1041                 };
1042
1043                 pronto: wcnss@a21b000 {
1044                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1045                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1046                         reg-names = "ccu", "dxe", "pmu";
1047
1048                         memory-region = <&wcnss_mem>;
1049
1050                         interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
1051                                 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1052                                 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1053                                 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1054                                 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1055                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1056
1057                         vddmx-supply = <&pm8916_l3>;
1058                         vddpx-supply = <&pm8916_l7>;
1059
1060                         qcom,state = <&wcnss_smp2p_out 0>;
1061                         qcom,state-names = "stop";
1062
1063                         pinctrl-names = "default";
1064                         pinctrl-0 = <&wcnss_default>;
1065
1066                         iris {
1067                                 compatible = "qcom,wcn3620";
1068
1069                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1070                                 clock-names = "xo";
1071
1072                                 vddxo-supply = <&pm8916_l7>;
1073                                 vddrfa-supply = <&pm8916_s3>;
1074                                 vddpa-supply = <&pm8916_l9>;
1075                                 vdddig-supply = <&pm8916_l5>;
1076                         };
1077                 };
1078
1079                 qcom,rpm-log@29dc00 {
1080                         compatible = "qcom,rpm-log";
1081                         reg = <0x29dc00 0x4000>;
1082                         qcom,rpm-addr-phys = <0x200000>;
1083                         qcom,offset-version = <4>;
1084                         qcom,offset-page-buffer-addr = <36>;
1085                         qcom,offset-log-len = <40>;
1086                         qcom,offset-log-len-mask = <44>;
1087                         qcom,offset-page-indices = <56>;
1088                 };
1089
1090                 vidc_rproc: vidc_tzpil@0 {
1091                         compatible = "qcom,tz-pil";
1092                         clocks = <&gcc GCC_CRYPTO_CLK>,
1093                                  <&gcc GCC_CRYPTO_AHB_CLK>,
1094                                  <&gcc GCC_CRYPTO_AXI_CLK>,
1095                                  <&gcc CRYPTO_CLK_SRC>;
1096                         clock-names = "scm_core_clk", "scm_iface_clk",
1097                                       "scm_bus_clk", "scm_src_clk";
1098                         qcom,firmware-name = "venus";
1099                         qcom,pas-id = <9>;
1100                         memory-region = <&vidc_mem>;
1101                         status = "disabled";
1102                 };
1103
1104                 vidc: qcom,vidc@1d00000 {
1105                         compatible = "qcom,msm-vidc";
1106                         reg = <0x01d00000 0xff000>;
1107                         interrupts = <GIC_SPI 44 0>;
1108                         power-domains = <&gcc VENUS_GDSC>;
1109                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1110                                  <&gcc GCC_VENUS0_AHB_CLK>,
1111                                  <&gcc GCC_VENUS0_AXI_CLK>;
1112                         clock-names = "core_clk", "iface_clk", "bus_clk";
1113                         qcom,hfi = "venus";
1114                         qcom,max-hw-load = <352800>; /* 720p @ 30 + 1080p @ 30 */
1115                         qcom,enable-idle-indicator;
1116                         rproc = <&vidc_rproc>;
1117                         qcom,iommu-cb = <&venus_ns>,
1118                                         <&venus_sec_bitstream>,
1119                                         <&venus_sec_pixel>,
1120                                         <&venus_sec_non_pixel>;
1121                         status = "disabled";
1122                 };
1123         };
1124
1125         smem {
1126                 compatible = "qcom,smem";
1127
1128                 memory-region = <&smem_mem>;
1129                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
1130
1131                 hwlocks = <&tcsr_mutex 3>;
1132         };
1133         smd {
1134                 compatible = "qcom,smd";
1135
1136                 rpm {
1137                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1138                         qcom,ipc = <&apcs 8 0>;
1139                         qcom,smd-edge = <15>;
1140                         qcom,remote-pid = <0xffffffff>;
1141
1142                         rpm_requests {
1143                                 compatible = "qcom,rpm-msm8916";
1144                                 qcom,smd-channels = "rpm_requests";
1145                                 rpmcc: qcom,rpmcc {
1146                                         compatible = "qcom,rpmcc-msm8916";
1147                                         #clock-cells = <1>;
1148                                 };
1149
1150                                 msm-bus {
1151                                         compatible = "qcom,rpm-msm-bus";
1152                                 };
1153
1154                                 smd_rpm_regulators: pm8916-regulators {
1155                                         compatible = "qcom,rpm-pm8916-regulators";
1156
1157                                         pm8916_s1: s1 {};
1158                                         pm8916_s2: s2 {};
1159                                         pm8916_s3: s3 {};
1160                                         pm8916_s4: s4 {};
1161
1162                                         pm8916_l1: l1 {};
1163                                         pm8916_l2: l2 {};
1164                                         pm8916_l3: l3 {};
1165                                         pm8916_l4: l4 {};
1166                                         pm8916_l5: l5 {};
1167                                         pm8916_l6: l6 {};
1168                                         pm8916_l7: l7 {};
1169                                         pm8916_l8: l8 {};
1170                                         pm8916_l9: l9 {};
1171                                         pm8916_l10: l10 {};
1172                                         pm8916_l11: l11 {};
1173                                         pm8916_l12: l12 {};
1174                                         pm8916_l13: l13 {};
1175                                         pm8916_l14: l14 {};
1176                                         pm8916_l15: l15 {};
1177                                         pm8916_l16: l16 {};
1178                                         pm8916_l17: l17 {};
1179                                         pm8916_l18: l18 {};
1180                                 };
1181                         };
1182                 };
1183
1184                 qcom,smd-modem {
1185                         interrupts = <0 25 1>;
1186                         qcom,smd-edge = <0>;
1187                         qcom,ipc = <&apcs 8 12>;
1188                         qcom,remote-pid = <1>;
1189                         ipcrtr_requests {
1190                                 compatible = "qcom,ipcrtr";
1191                                 qcom,smd-channels = "IPCRTR";
1192                         };
1193                 };
1194
1195                 pronto {
1196                         interrupts = <0 142 1>;
1197
1198                         qcom,ipc = <&apcs 8 17>;
1199                         qcom,smd-edge = <6>;
1200                         qcom,remote-pid = <4>;
1201
1202                         wcnss {
1203                                 compatible = "qcom,wcnss";
1204                                 qcom,smd-channels = "WCNSS_CTRL";
1205
1206                                 qcom,mmio = <&pronto>;
1207
1208                                 bt {
1209                                         compatible = "qcom,wcnss-bt";
1210                                 };
1211
1212                                 wifi {
1213                                         compatible = "qcom,wcnss-wlan";
1214
1215                                         interrupts = <0 145 0>, <0 146 0>;
1216                                         interrupt-names = "tx", "rx";
1217
1218                                         qcom,state = <&apps_smsm 10>, <&apps_smsm 9>;
1219                                         qcom,state-names = "tx-enable", "tx-rings-empty";
1220                                 };
1221                         };
1222                 };
1223         };
1224
1225         hexagon-smp2p {
1226                 compatible = "qcom,smp2p";
1227                 qcom,smem = <435>, <428>;
1228
1229                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1230
1231                 qcom,ipc = <&apcs 8 14>;
1232
1233                 qcom,local-pid = <0>;
1234                 qcom,remote-pid = <1>;
1235
1236                 hexagon_smp2p_out: master-kernel {
1237                         qcom,entry-name = "master-kernel";
1238
1239                         #qcom,state-cells = <1>;
1240                 };
1241
1242                 hexagon_smp2p_in: slave-kernel {
1243                         qcom,entry-name = "slave-kernel";
1244
1245                         interrupt-controller;
1246                         #interrupt-cells = <2>;
1247                 };
1248         };
1249
1250         wcnss-smp2p {
1251                 compatible = "qcom,smp2p";
1252                 qcom,smem = <451>, <431>;
1253
1254                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1255
1256                 qcom,ipc = <&apcs 8 18>;
1257
1258                 qcom,local-pid = <0>;
1259                 qcom,remote-pid = <4>;
1260
1261                 wcnss_smp2p_out: master-kernel {
1262                         qcom,entry-name = "master-kernel";
1263
1264                         #qcom,state-cells = <1>;
1265                 };
1266
1267                 wcnss_smp2p_in: slave-kernel {
1268                         qcom,entry-name = "slave-kernel";
1269
1270                         interrupt-controller;
1271                         #interrupt-cells = <2>;
1272                 };
1273         };
1274
1275         smsm {
1276                 compatible = "qcom,smsm";
1277
1278                 #address-cells = <1>;
1279                 #size-cells = <0>;
1280
1281                 qcom,ipc-1 = <&apcs 0 13>;
1282                 qcom,ipc-6 = <&apcs 0 19>;
1283
1284                 apps_smsm: apps@0 {
1285                         reg = <0>;
1286
1287                         #qcom,state-cells = <1>;
1288                 };
1289
1290                 hexagon_smsm: hexagon@1 {
1291                         reg = <1>;
1292                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1293
1294                         interrupt-controller;
1295                         #interrupt-cells = <2>;
1296                 };
1297
1298                 wcnss_smsm: wcnss@6 {
1299                         reg = <6>;
1300                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1301
1302                         interrupt-controller;
1303                         #interrupt-cells = <2>;
1304                 };
1305         };
1306 };
1307
1308 &i2c_freq_100Khz {
1309         qcom,hw-thigh = <78>;
1310         qcom,hw-tlow = <114>;
1311         qcom,hw-tsu-sto = <28>;
1312         qcom,hw-tsu-sta = <28>;
1313         qcom,hw-thd-dat = <10>;
1314         qcom,hw-thd-sta = <77>;
1315         qcom,hw-tbuf = <118>;
1316         qcom,hw-scl-stretch-en = <0>;
1317         qcom,hw-trdhld = <6>;
1318         qcom,hw-tsp = <1>;
1319         status = "ok";
1320 };
1321
1322 &i2c_freq_400Khz {
1323         qcom,hw-thigh = <20>;
1324         qcom,hw-tlow = <28>;
1325         qcom,hw-tsu-sto = <21>;
1326         qcom,hw-tsu-sta = <21>;
1327         qcom,hw-thd-dat = <13>;
1328         qcom,hw-thd-sta = <18>;
1329         qcom,hw-tbuf = <32>;
1330         qcom,hw-scl-stretch-en = <0>;
1331         qcom,hw-trdhld = <6>;
1332         qcom,hw-tsp = <3>;
1333         status = "ok";
1334 };
1335
1336 &i2c_freq_custom {
1337         qcom,hw-thigh = <15>;
1338         qcom,hw-tlow = <28>;
1339         qcom,hw-tsu-sto = <21>;
1340         qcom,hw-tsu-sta = <21>;
1341         qcom,hw-thd-dat = <13>;
1342         qcom,hw-thd-sta = <18>;
1343         qcom,hw-tbuf = <25>;
1344         qcom,hw-scl-stretch-en = <1>;
1345         qcom,hw-trdhld = <6>;
1346         qcom,hw-tsp = <3>;
1347         status = "ok";
1348 };
1349
1350
1351 #include "msm8916-pins.dtsi"
1352 #include "msm8916-iommu.dtsi"
1353 #include "msm8916-coresight.dtsi"
1354 #include "msm8916-bus.dtsi"