arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17 #include <dt-bindings/clock/qcom,rpmcc.h>
  18 #include <dt-bindings/thermal/thermal.h>
  19 #include <dt-bindings/arm/qcom-ids.h>
  20
  21 / {
  22         model = "Qualcomm Technologies, Inc. MSM8916";
  23         compatible = "qcom,msm8916";
  24         qcom,msm-id =   <QCOM_ID_MSM8916 0>,
  25                         <QCOM_ID_MSM8216 0>,
  26                         <QCOM_ID_MSM8116 0>,
  27                         <QCOM_ID_MSM8616 0>,
  28                         <QCOM_ID_APQ8016 0>;
  29
  30
  31         interrupt-parent = <&intc>;
  32
  33         #address-cells = <2>;
  34         #size-cells = <2>;
  35
  36         aliases {
  37                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  38                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  39         };
  40
  41         chosen { };
  42
  43         memory {
  44                 device_type = "memory";
  45                 /* We expect the bootloader to fill in the reg */
  46                 reg = <0 0 0 0>;
  47         };
  48
  49         reserved-memory {
  50                 #address-cells = <2>;
  51                 #size-cells = <2>;
  52                 ranges;
  53
  54                 reserve_aligned@86000000 {
  55                         reg = <0x0 0x86000000 0x0 0x0300000>;
  56                         no-map;
  57                 };
  58
  59                 smem_mem: smem_region@86300000 {
  60                         reg = <0x0 0x86300000 0x0 0x0100000>;
  61                         no-map;
  62                 };
  63
  64                 hypervisor_mem: hypervisor_region@86400000 {
  65                         no-map;
  66                         reg = <0x0 0x86400000 0x0 0x0400000>;
  67                 };
  68
  69                 modem_adsp_mem: modem_adsp_region@86800000 {
  70                         no-map;
  71                         reg = <0x0 0x86800000 0x0 0x04800000>;
  72                 };
  73
  74                 rmtfs@86700000 {
  75                         reg = <0x0 0x86700000 0x0 0xe0000>;
  76                         no-map;
  77                 };
  78
  79                 peripheral_mem: peripheral_region@8b600000 {
  80                         no-map;
  81                         reg = <0x0 0x8b600000 0x0 0x0600000>;
  82                 };
  83
  84                 wcnss_mem: wcnss@89300000 {
  85                         reg = <0x0 0x89300000 0x0 0x600000>;
  86                         no-map;
  87                 };
  88
  89                 vidc_mem: vidc_region@8f800000 {
  90                         no-map;
  91                         reg = <0 0x8f800000 0 0x800000>;
  92                 };
  93         };
  94
  95         cpus {
  96                 #address-cells = <1>;
  97                 #size-cells = <0>;
  98
  99                 CPU0: cpu@0 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a53", "arm,armv8";
 102                         reg = <0x0>;
 103                         enable-method = "qcom,arm-cortex-acc";
 104                         qcom,acc = <&acc0>;
 105                         next-level-cache = <&L2_0>;
 106                         clocks = <&a53cc 1>;
 107                         clock-latency = <200000>;
 108                         cpu-supply = <&pm8916_spmi_s2>;
 109                         /* cooling options */
 110                         cooling-min-level = <0>;
 111                         cooling-max-level = <7>;
 112                         #cooling-cells = <2>;
 113                         L2_0: l2-cache {
 114                               compatible = "arm,arch-cache";
 115                               cache-level = <2>;
 116                               power-domain = <&l2ccc_0>;
 117                         };
 118                 };
 119
 120                 CPU1: cpu@1 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53", "arm,armv8";
 123                         reg = <0x1>;
 124                         enable-method = "qcom,arm-cortex-acc";
 125                         qcom,acc = <&acc1>;
 126                         next-level-cache = <&L2_0>;
 127                         clocks = <&a53cc 1>;
 128                         clock-latency = <200000>;
 129                         cpu-supply = <&pm8916_spmi_s2>;
 130                         /* cooling options */
 131                         cooling-min-level = <0>;
 132                         cooling-max-level = <7>;
 133                         #cooling-cells = <2>;
 134                 };
 135
 136                 CPU2: cpu@2 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53", "arm,armv8";
 139                         reg = <0x2>;
 140                         enable-method = "qcom,arm-cortex-acc";
 141                         qcom,acc = <&acc2>;
 142                         next-level-cache = <&L2_0>;
 143                         clocks = <&a53cc 1>;
 144                         clock-latency = <200000>;
 145                         cpu-supply = <&pm8916_spmi_s2>;
 146                         /* cooling options */
 147                         cooling-min-level = <0>;
 148                         cooling-max-level = <7>;
 149                         #cooling-cells = <2>;
 150                 };
 151
 152                 CPU3: cpu@3 {
 153                         device_type = "cpu";
 154                         compatible = "arm,cortex-a53", "arm,armv8";
 155                         reg = <0x3>;
 156                         enable-method = "qcom,arm-cortex-acc";
 157                         qcom,acc = <&acc3>;
 158                         next-level-cache = <&L2_0>;
 159                         clocks = <&a53cc 1>;
 160                         clock-latency = <200000>;
 161                         cpu-supply = <&pm8916_spmi_s2>;
 162                         /* cooling options */
 163                         cooling-min-level = <0>;
 164                         cooling-max-level = <7>;
 165                         #cooling-cells = <2>;
 166                 };
 167         };
 168
 169         cpu-pmu {
 170                 compatible = "arm,armv8-pmuv3";
 171                 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
 172         };
 173
 174         thermal-zones {
 175                 cpu-thermal0 {
 176                         polling-delay-passive = <250>;
 177                         polling-delay = <1000>;
 178
 179                         thermal-sensors = <&tsens 4>;
 180
 181                         trips {
 182                                 cpu_alert0: trip@0 {
 183                                         temperature = <75000>;
 184                                         hysteresis = <2000>;
 185                                         type = "passive";
 186                                 };
 187                                 cpu_crit0: trip@1 {
 188                                         temperature = <100000>;
 189                                         hysteresis = <2000>;
 190                                         type = "critical";
 191                                 };
 192                         };
 193
 194                         cooling-maps {
 195                                 map0 {
 196                                         trip = <&cpu_alert0>;
 197                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 198                                 };
 199                         };
 200                 };
 201
 202                 cpu-thermal1 {
 203                         polling-delay-passive = <250>;
 204                         polling-delay = <1000>;
 205
 206                         thermal-sensors = <&tsens 3>;
 207
 208                         trips {
 209                                 cpu_alert1: trip@0 {
 210                                         temperature = <75000>;
 211                                         hysteresis = <2000>;
 212                                         type = "passive";
 213                                 };
 214                                 cpu_crit1: trip@1 {
 215                                         temperature = <100000>;
 216                                         hysteresis = <2000>;
 217                                         type = "critical";
 218                                 };
 219                         };
 220
 221                         cooling-maps {
 222                                 map0 {
 223                                         trip = <&cpu_alert1>;
 224                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 225                                 };
 226                         };
 227                 };
 228         };
 229
 230         timer {
 231                 compatible = "arm,armv8-timer";
 232                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 233                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 234                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 235                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 236         };
 237
 238         clocks {
 239                 xo_board: xo_board {
 240                         compatible = "fixed-clock";
 241                         #clock-cells = <0>;
 242                         clock-frequency = <19200000>;
 243                         clock-output-names = "xo_board";
 244                 };
 245
 246                 sleep_clk: sleep_clk {
 247                         compatible = "fixed-clock";
 248                         #clock-cells = <0>;
 249                         clock-frequency = <32768>;
 250                 };
 251         };
 252
 253         firmware {
 254                 compatible = "simple-bus";
 255
 256                 scm {
 257                         compatible = "qcom,scm";
 258                         clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
 259                         clock-names = "core", "bus", "iface";
 260                 };
 261         };
 262
 263         soc: soc {
 264                 #address-cells = <1>;
 265                 #size-cells = <1>;
 266                 ranges = <0 0 0 0xffffffff>;
 267                 compatible = "simple-bus";
 268
 269                 restart@4ab000 {
 270                         compatible = "qcom,pshold";
 271                         reg = <0x4ab000 0x4>;
 272                 };
 273
 274                 msmgpio: pinctrl@1000000 {
 275                         compatible = "qcom,msm8916-pinctrl";
 276                         reg = <0x1000000 0x300000>;
 277                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 278                         gpio-controller;
 279                         #gpio-cells = <2>;
 280                         interrupt-controller;
 281                         #interrupt-cells = <2>;
 282                 };
 283
 284                 gcc: qcom,gcc@1800000 {
 285                         compatible = "qcom,gcc-msm8916";
 286                         #clock-cells = <1>;
 287                         #reset-cells = <1>;
 288                         #power-domain-cells = <1>;
 289                         reg = <0x1800000 0x80000>;
 290                 };
 291
 292                 tcsr_mutex_regs: syscon@1905000 {
 293                         compatible = "syscon";
 294                         reg = <0x1905000 0x20000>;
 295                 };
 296
 297                 tcsr_mutex: hwlock {
 298                         compatible = "qcom,tcsr-mutex";
 299                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 300                         #hwlock-cells = <1>;
 301                 };
 302
 303                 rpm_msg_ram: memory@60000 {
 304                         compatible = "qcom,rpm-msg-ram";
 305                         reg = <0x60000 0x8000>;
 306                 };
 307
 308                 blsp1_uart1: serial@78af000 {
 309                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 310                         reg = <0x78af000 0x200>;
 311                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 312                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 313                         clock-names = "core", "iface";
 314                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 315                         dma-names = "rx", "tx";
 316                         status = "disabled";
 317                 };
 318
 319                 apcs: syscon@b011000 {
 320                         compatible = "syscon";
 321                         reg = <0x0b011000 0x1000>;
 322                 };
 323
 324                 a53cc: qcom,a53cc@0b016000 {
 325                         compatible = "qcom,clock-a53-msm8916";
 326                         reg = <0x0b016000 0x40>;
 327                         #clock-cells = <1>;
 328                         qcom,apcs = <&apcs>;
 329                 };
 330
 331                 blsp1_uart2: serial@78b0000 {
 332                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 333                         reg = <0x78b0000 0x200>;
 334                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 335                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 336                         clock-names = "core", "iface";
 337                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 338                         dma-names = "rx", "tx";
 339                         status = "disabled";
 340                 };
 341
 342                 blsp_dma: dma@7884000 {
 343                         compatible = "qcom,bam-v1.7.0";
 344                         reg = <0x07884000 0x23000>;
 345                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 347                         clock-names = "bam_clk";
 348                         #dma-cells = <1>;
 349                         qcom,ee = <0>;
 350                         status = "disabled";
 351                 };
 352
 353                 blsp_spi1: spi@78b5000 {
 354                         compatible = "qcom,spi-qup-v2.2.1";
 355                         reg = <0x078b5000 0x600>;
 356                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 357                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 358                                  <&gcc GCC_BLSP1_AHB_CLK>;
 359                         clock-names = "core", "iface";
 360                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 361                         dma-names = "rx", "tx";
 362                         pinctrl-names = "default", "sleep";
 363                         pinctrl-0 = <&spi1_default>;
 364                         pinctrl-1 = <&spi1_sleep>;
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                         status = "disabled";
 368                 };
 369
 370                 blsp_spi2: spi@78b6000 {
 371                         compatible = "qcom,spi-qup-v2.2.1";
 372                         reg = <0x078b6000 0x600>;
 373                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 374                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 375                                  <&gcc GCC_BLSP1_AHB_CLK>;
 376                         clock-names = "core", "iface";
 377                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 378                         dma-names = "rx", "tx";
 379                         pinctrl-names = "default", "sleep";
 380                         pinctrl-0 = <&spi2_default>;
 381                         pinctrl-1 = <&spi2_sleep>;
 382                         #address-cells = <1>;
 383                         #size-cells = <0>;
 384                         status = "disabled";
 385                 };
 386
 387                 blsp_spi3: spi@78b7000 {
 388                         compatible = "qcom,spi-qup-v2.2.1";
 389                         reg = <0x078b7000 0x600>;
 390                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 391                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 392                                  <&gcc GCC_BLSP1_AHB_CLK>;
 393                         clock-names = "core", "iface";
 394                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 395                         dma-names = "rx", "tx";
 396                         pinctrl-names = "default", "sleep";
 397                         pinctrl-0 = <&spi3_default>;
 398                         pinctrl-1 = <&spi3_sleep>;
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         status = "disabled";
 402                 };
 403
 404                 blsp_spi4: spi@78b8000 {
 405                         compatible = "qcom,spi-qup-v2.2.1";
 406                         reg = <0x078b8000 0x600>;
 407                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 408                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 409                                  <&gcc GCC_BLSP1_AHB_CLK>;
 410                         clock-names = "core", "iface";
 411                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 412                         dma-names = "rx", "tx";
 413                         pinctrl-names = "default", "sleep";
 414                         pinctrl-0 = <&spi4_default>;
 415                         pinctrl-1 = <&spi4_sleep>;
 416                         #address-cells = <1>;
 417                         #size-cells = <0>;
 418                         status = "disabled";
 419                 };
 420
 421                 blsp_spi5: spi@78b9000 {
 422                         compatible = "qcom,spi-qup-v2.2.1";
 423                         reg = <0x078b9000 0x600>;
 424                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 425                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 426                                  <&gcc GCC_BLSP1_AHB_CLK>;
 427                         clock-names = "core", "iface";
 428                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 429                         dma-names = "rx", "tx";
 430                         pinctrl-names = "default", "sleep";
 431                         pinctrl-0 = <&spi5_default>;
 432                         pinctrl-1 = <&spi5_sleep>;
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         status = "disabled";
 436                 };
 437
 438                 blsp_spi6: spi@78ba000 {
 439                         compatible = "qcom,spi-qup-v2.2.1";
 440                         reg = <0x078ba000 0x600>;
 441                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 442                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 443                                  <&gcc GCC_BLSP1_AHB_CLK>;
 444                         clock-names = "core", "iface";
 445                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 446                         dma-names = "rx", "tx";
 447                         pinctrl-names = "default", "sleep";
 448                         pinctrl-0 = <&spi6_default>;
 449                         pinctrl-1 = <&spi6_sleep>;
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452                         status = "disabled";
 453                 };
 454
 455                 blsp_i2c2: i2c@78b6000 {
 456                         compatible = "qcom,i2c-qup-v2.2.1";
 457                         reg = <0x78b6000 0x1000>;
 458                         interrupts = <GIC_SPI 96 0>;
 459                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 460                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 461                         clock-names = "iface", "core";
 462                         pinctrl-names = "default", "sleep";
 463                         pinctrl-0 = <&i2c2_default>;
 464                         pinctrl-1 = <&i2c2_sleep>;
 465                         #address-cells = <1>;
 466                         #size-cells = <0>;
 467                         status = "disabled";
 468                 };
 469
 470                 blsp_i2c4: i2c@78b8000 {
 471                         compatible = "qcom,i2c-qup-v2.2.1";
 472                         reg = <0x78b8000 0x1000>;
 473                         interrupts = <GIC_SPI 98 0>;
 474                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 475                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 476                         clock-names = "iface", "core";
 477                         pinctrl-names = "default", "sleep";
 478                         pinctrl-0 = <&i2c4_default>;
 479                         pinctrl-1 = <&i2c4_sleep>;
 480                         #address-cells = <1>;
 481                         #size-cells = <0>;
 482                         status = "disabled";
 483                 };
 484
 485                 blsp_i2c6: i2c@78ba000 {
 486                         compatible = "qcom,i2c-qup-v2.2.1";
 487                         reg = <0x78ba000 0x1000>;
 488                         interrupts = <GIC_SPI 100 0>;
 489                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 490                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 491                         clock-names = "iface", "core";
 492                         pinctrl-names = "default", "sleep";
 493                         pinctrl-0 = <&i2c6_default>;
 494                         pinctrl-1 = <&i2c6_sleep>;
 495                         #address-cells = <1>;
 496                         #size-cells = <0>;
 497                         status = "disabled";
 498                 };
 499
 500                 sdhc_1: sdhci@07824000 {
 501                         compatible = "qcom,sdhci-msm-v4";
 502                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 503                         reg-names = "hc_mem", "core_mem";
 504
 505                         interrupts = <0 123 0>, <0 138 0>;
 506                         interrupt-names = "hc_irq", "pwr_irq";
 507                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 508                                  <&gcc GCC_SDCC1_AHB_CLK>;
 509                         clock-names = "core", "iface";
 510                         bus-width = <8>;
 511                         non-removable;
 512                         status = "disabled";
 513                 };
 514
 515                 sdhc_2: sdhci@07864000 {
 516                         compatible = "qcom,sdhci-msm-v4";
 517                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 518                         reg-names = "hc_mem", "core_mem";
 519
 520                         interrupts = <0 125 0>, <0 221 0>;
 521                         interrupt-names = "hc_irq", "pwr_irq";
 522                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 523                                  <&gcc GCC_SDCC2_AHB_CLK>;
 524                         clock-names = "core", "iface";
 525                         bus-width = <4>;
 526                         status = "disabled";
 527                 };
 528
 529                 usb_dev: usb@78d9000 {
 530                         compatible = "qcom,ci-hdrc";
 531                         reg = <0x78d9000 0x400>;
 532                         dr_mode = "peripheral";
 533                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 534                         usb-phy = <&usb_otg>;
 535                         status = "disabled";
 536                 };
 537
 538                 usb_host: ehci@78d9000 {
 539                         compatible = "qcom,ehci-host";
 540                         reg = <0x78d9000 0x400>;
 541                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 542                         usb-phy = <&usb_otg>;
 543                         status = "disabled";
 544                 };
 545
 546                 usb_otg: phy@78d9000 {
 547                         compatible = "qcom,usb-otg-snps";
 548                         reg = <0x78d9000 0x400>;
 549                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
 550                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 551
 552                         v1p8-supply = <&pm8916_l7>;
 553                         v3p3-supply = <&pm8916_l13>;
 554                         qcom,vdd-levels = <1 5 7>;
 555                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 556                         dr_mode = "peripheral";
 557                         qcom,otg-control = <2>; // PMIC
 558                         qcom,manual-pullup;
 559
 560                         qcom,msm-bus,name = "usb2";
 561                         qcom,msm-bus,num-cases = <3>;
 562                         qcom,msm-bus,num-paths = <1>;
 563                         qcom,msm-bus,vectors-KBps =
 564                                         <87 512 0 0>,
 565                                         <87 512 80000 0>,
 566                                         <87 512 6000  6000>;
 567
 568                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 569                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 570                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 571                         clock-names = "iface", "core", "sleep";
 572
 573                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 574                                  <&gcc GCC_USB_HS_BCR>;
 575                         reset-names = "phy", "link";
 576                         status = "disabled";
 577                 };
 578
 579                 intc: interrupt-controller@b000000 {
 580                         compatible = "qcom,msm-qgic2";
 581                         interrupt-controller;
 582                         #interrupt-cells = <3>;
 583                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 584                 };
 585
 586                 l2ccc_0: clock-controller@b011000 {
 587                         compatible = "qcom,8916-l2ccc";
 588                         reg = <0x0b011000 0x1000>;
 589                 };
 590
 591                 timer@b020000 {
 592                         #address-cells = <1>;
 593                         #size-cells = <1>;
 594                         ranges;
 595                         compatible = "arm,armv7-timer-mem";
 596                         reg = <0xb020000 0x1000>;
 597                         clock-frequency = <19200000>;
 598
 599                         frame@b021000 {
 600                                 frame-number = <0>;
 601                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 602                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 603                                 reg = <0xb021000 0x1000>,
 604                                       <0xb022000 0x1000>;
 605                         };
 606
 607                         frame@b023000 {
 608                                 frame-number = <1>;
 609                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 610                                 reg = <0xb023000 0x1000>;
 611                                 status = "disabled";
 612                         };
 613
 614                         frame@b024000 {
 615                                 frame-number = <2>;
 616                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 617                                 reg = <0xb024000 0x1000>;
 618                                 status = "disabled";
 619                         };
 620
 621                         frame@b025000 {
 622                                 frame-number = <3>;
 623                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 624                                 reg = <0xb025000 0x1000>;
 625                                 status = "disabled";
 626                         };
 627
 628                         frame@b026000 {
 629                                 frame-number = <4>;
 630                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 631                                 reg = <0xb026000 0x1000>;
 632                                 status = "disabled";
 633                         };
 634
 635                         frame@b027000 {
 636                                 frame-number = <5>;
 637                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 638                                 reg = <0xb027000 0x1000>;
 639                                 status = "disabled";
 640                         };
 641
 642                         frame@b028000 {
 643                                 frame-number = <6>;
 644                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 645                                 reg = <0xb028000 0x1000>;
 646                                 status = "disabled";
 647                         };
 648                 };
 649
 650                 spmi_bus: spmi@200f000 {
 651                         compatible = "qcom,spmi-pmic-arb";
 652                         reg = <0x200f000 0x001000>,
 653                               <0x2400000 0x400000>,
 654                               <0x2c00000 0x400000>,
 655                               <0x3800000 0x200000>,
 656                               <0x200a000 0x002100>;
 657                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 658                         interrupt-names = "periph_irq";
 659                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 660                         qcom,ee = <0>;
 661                         qcom,channel = <0>;
 662                         #address-cells = <2>;
 663                         #size-cells = <0>;
 664                         interrupt-controller;
 665                         #interrupt-cells = <4>;
 666                 };
 667
 668                 rng@22000 {
 669                         compatible = "qcom,prng";
 670                         reg = <0x00022000 0x200>;
 671                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 672                         clock-names = "core";
 673                 };
 674                 acc0: clock-controller@b088000 {
 675                         compatible = "qcom,arm-cortex-acc";
 676                         reg = <0x0b088000 0x1000>,
 677                               <0x0b008000 0x1000>;
 678                 };
 679
 680                 acc1: clock-controller@b098000 {
 681                         compatible = "qcom,arm-cortex-acc";
 682                         reg = <0x0b098000 0x1000>,
 683                               <0x0b008000 0x1000>;
 684                 };
 685
 686                 acc2: clock-controller@b0a8000 {
 687                         compatible = "qcom,arm-cortex-acc";
 688                         reg = <0x0b0a8000 0x1000>,
 689                               <0x0b008000 0x1000>;
 690                 };
 691
 692                 acc3: clock-controller@b0b8000 {
 693                         compatible = "qcom,arm-cortex-acc";
 694                         reg = <0x0b0b8000 0x1000>,
 695                               <0x0b008000 0x1000>;
 696                 };
 697
 698                 /* Audio */
 699
 700                 wcd_digital: codec-digital{
 701                         compatible = "syscon", "qcom,apq8016-wcd-digital-codec";
 702                         reg = <0x0771c000 0x400>;
 703                 };
 704
 705                 lpass: lpass-cpu@07700000 {
 706                         status = "disabled";
 707                         compatible = "qcom,lpass-cpu-apq8016";
 708                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 709                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 710                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 711                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 712                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 713                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 714                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 715
 716                         clock-names = "ahbix-clk",
 717                                         "pcnoc-mport-clk",
 718                                         "pcnoc-sway-clk",
 719                                         "mi2s-bit-clk0",
 720                                         "mi2s-bit-clk1",
 721                                         "mi2s-bit-clk2",
 722                                         "mi2s-bit-clk3";
 723                         #sound-dai-cells = <1>;
 724
 725                         interrupts = <0 160 0>;
 726                         interrupt-names = "lpass-irq-lpaif";
 727                         reg = <0x07708000 0x10000>, <0x07702000 0x4>, <0x07702004 0x4>;
 728                         reg-names = "lpass-lpaif", "mic-iomux", "spkr-iomux";
 729                 };
 730
 731                 sound: sound {
 732                         status = "disabled";
 733                         compatible = "qcom,apq8016-sbc-sndcard";
 734                         reg = <0x07702000 0x4>, <0x07702004 0x4>;
 735                         reg-names = "mic-iomux", "spkr-iomux";
 736                 };
 737
 738                 tcsr: syscon@1937000 {
 739                         compatible = "qcom,tcsr-msm8916", "syscon";
 740                         reg = <0x1937000 0x30000>;
 741                 };
 742
 743                 uqfprom: eeprom@58000 {
 744                         compatible = "qcom,qfprom-msm8916";
 745                         reg = <0x58000 0x7000>;
 746                 };
 747
 748                 cpr@b018000 {
 749                         compatible = "qcom,cpr";
 750                         reg = <0xb018000 0x1000>;
 751                         interrupts = <0 15 1>, <0 16 1>, <0 17 1>;
 752                         vdd-mx-supply = <&pm8916_l3>;
 753                         acc-syscon = <&tcsr>;
 754                         eeprom = <&uqfprom>;
 755
 756                         qcom,cpr-ref-clk = <19200>;
 757                         qcom,cpr-timer-delay-us = <5000>;
 758                         qcom,cpr-timer-cons-up = <0>;
 759                         qcom,cpr-timer-cons-down = <2>;
 760                         qcom,cpr-up-threshold = <0>;
 761                         qcom,cpr-down-threshold = <2>;
 762                         qcom,cpr-idle-clocks = <15>;
 763                         qcom,cpr-gcnt-us = <1>;
 764                         qcom,vdd-apc-step-up-limit = <1>;
 765                         qcom,vdd-apc-step-down-limit = <1>;
 766                         qcom,cpr-cpus = <&CPU0 &CPU1 &CPU2 &CPU3>;
 767                 };
 768
 769                 qfprom: qfprom@5c000 {
 770                         compatible = "qcom,qfprom";
 771                         reg = <0x5c000 0x1000>;
 772                         #address-cells = <1>;
 773                         #size-cells = <1>;
 774                         tsens_caldata: caldata@d0 {
 775                                 reg = <0xd0 0x8>;
 776                         };
 777                         tsens_calsel: calsel@ec {
 778                                 reg = <0xec 0x4>;
 779                         };
 780                 };
 781
 782                 tsens: thermal-sensor@4a8000 {
 783                         compatible = "qcom,msm8916-tsens";
 784                         reg = <0x4a8000 0x2000>;
 785                         nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
 786                         nvmem-cell-names = "calib", "calib_sel";
 787                         qcom,tsens-slopes = <3200 3200 3200 3200 3200>;
 788                         qcom,sensor-id = <0 1 2 4 5>;
 789                         #thermal-sensor-cells = <1>;
 790                 };
 791
 792                 q6-smp2p {
 793                         compatible = "qcom,smp2p";
 794                         qcom,smem = <435>, <428>;
 795                         interrupts = <0 27 1>;
 796                         qcom,ipc = <&apcs 8 14>;
 797
 798                         qcom,local-pid = <0>;
 799                         qcom,remote-pid = <1>;
 800
 801                         q6_smp2p_out: master-kernel {
 802                                 qcom,entry-name = "master-kernel";
 803                                 qcom,outbound;
 804
 805                                 gpio-controller;
 806                                 #gpio-cells = <2>;
 807                         };
 808
 809                         q6_smp2p_in: slave-kernel {
 810                                 qcom,entry-name = "slave-kernel";
 811                                 qcom,inbound;
 812
 813                                 interrupt-controller;
 814                                 #interrupt-cells = <2>;
 815                         };
 816                 };
 817
 818                 wcnss-smp2p {
 819                         compatible = "qcom,smp2p";
 820                         qcom,smem = <451>, <431>;
 821
 822                         interrupts = <0 143 1>;
 823
 824                         qcom,ipc = <&apcs 8 18>;
 825
 826                         qcom,local-pid = <0>;
 827                         qcom,remote-pid = <4>;
 828
 829                         wcnss_smp2p_out: master-kernel {
 830                                 qcom,entry-name = "master-kernel";
 831                                 qcom,outbound;
 832
 833                                 gpio-controller;
 834                                 #gpio-cells = <2>;
 835                         };
 836
 837                         wcnss_smp2p_in: slave-kernel {
 838                                 qcom,entry-name = "slave-kernel";
 839                                 qcom,inbound;
 840
 841                                 interrupt-controller;
 842                                 #interrupt-cells = <2>;
 843                         };
 844                 };
 845
 846                 qcom,mss@4080000 {
 847                         compatible = "qcom,pil-q6v56-mss", "qcom,q6v5-pil";
 848                         reg = <0x04080000 0x100>,
 849                               <0x04020000 0x040>,
 850                               <0x01810000 0x004>,
 851                               <0x01810000 0x004>,
 852                               <0x0194f000 0x010>,
 853                               <0x01950000 0x008>,
 854                               <0x01951000 0x008>;
 855
 856                         reg-names = "qdsp6_base", "rmb_base", "restart_reg_sec",
 857                                         "halt_q6", "halt_modem", "halt_nc";
 858
 859                         interrupts-extended = <&intc 0 24 1>,
 860                                               <&q6_smp2p_in 0 0>,
 861                                               <&q6_smp2p_in 1 0>,
 862                                               <&q6_smp2p_in 2 0>,
 863                                               <&q6_smp2p_in 3 0>;
 864                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 865
 866                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, <&gcc GCC_BOOT_ROM_AHB_CLK>;
 867
 868                         clock-names = "iface", "bus", "mem";
 869
 870                         qcom,mx-supply = <&pm8916_l3>;
 871                         qcom,mx-uV = <1050000>;
 872                         qcom,pll-supply = <&pm8916_l7>;
 873                         qcom,pll-uV = <1800000>;
 874                         qcom,proxy-clock-names = "xo";
 875                         qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";
 876                         qcom,is-loadable;
 877                         qcom,firmware-name = "modem";
 878                         qcom,pil-self-auth;
 879
 880
 881                         /* GPIO inputs from mss */
 882                         qcom,gpio-err-fatal = <&q6_smp2p_in 0 0>;
 883                         qcom,gpio-err-ready = <&q6_smp2p_in 1 0>;
 884                         qcom,gpio-proxy-unvote = <&q6_smp2p_in 2 0>;
 885                         qcom,gpio-stop-ack = <&q6_smp2p_in 3 0>;
 886                         qcom,gpio-ramdump-disable = <&q6_smp2p_in 15 0>;
 887                         /* GPIO output to mss */
 888                         qcom,gpio-force-stop = <&q6_smp2p_out 0 0>;
 889                         qcom,stop-gpio = <&q6_smp2p_out 0 0>;
 890                         memory-region = <&modem_adsp_mem>;
 891                 };
 892
 893                 wcnss@a21b000 {
 894                         compatible = "qcom,pronto-v2-pil";
 895                         reg = <0x0a21b000 0x3000>;
 896                         reg-names = "pmu";
 897
 898                         memory-region = <&wcnss_mem>;
 899
 900                         interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
 901                                 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 902                                 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 903                                 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 904                                 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 905                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 906
 907                         vddmx-supply = <&pm8916_l3>;
 908                         vddpx-supply = <&pm8916_l7>;
 909
 910                         qcom,state = <&wcnss_smp2p_out 0>;
 911                         qcom,state-names = "stop";
 912
 913                         pinctrl-names = "default";
 914                         pinctrl-0 = <&wcnss_default>;
 915
 916                         iris {
 917                                 compatible = "qcom,wcn3620";
 918
 919                                 clocks = <&rpmcc RPM_RF_CLK2>;
 920                                 clock-names = "xo";
 921
 922                                 vddxo-supply = <&pm8916_l7>;
 923                                 vddrfa-supply = <&pm8916_s3>;
 924                                 vddpa-supply = <&pm8916_l9>;
 925                                 vdddig-supply = <&pm8916_l5>;
 926                         };
 927                 };
 928
 929                 qcom,rpm-log@29dc00 {
 930                         compatible = "qcom,rpm-log";
 931                         reg = <0x29dc00 0x4000>;
 932                         qcom,rpm-addr-phys = <0x200000>;
 933                         qcom,offset-version = <4>;
 934                         qcom,offset-page-buffer-addr = <36>;
 935                         qcom,offset-log-len = <40>;
 936                         qcom,offset-log-len-mask = <44>;
 937                         qcom,offset-page-indices = <56>;
 938                 };
 939
 940                 vidc_rproc: vidc_tzpil@0 {
 941                         compatible = "qcom,tz-pil";
 942                         clocks = <&gcc GCC_CRYPTO_CLK>,
 943                                  <&gcc GCC_CRYPTO_AHB_CLK>,
 944                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 945                                  <&gcc CRYPTO_CLK_SRC>;
 946                         clock-names = "scm_core_clk", "scm_iface_clk",
 947                                       "scm_bus_clk", "scm_src_clk";
 948                         qcom,firmware-name = "venus";
 949                         qcom,pas-id = <9>;
 950                         memory-region = <&vidc_mem>;
 951                         status = "disabled";
 952                 };
 953
 954                 vidc: qcom,vidc@1d00000 {
 955                         compatible = "qcom,msm-vidc";
 956                         reg = <0x01d00000 0xff000>;
 957                         interrupts = <GIC_SPI 44 0>;
 958                         power-domains = <&gcc VENUS_GDSC>;
 959                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
 960                                  <&gcc GCC_VENUS0_AHB_CLK>,
 961                                  <&gcc GCC_VENUS0_AXI_CLK>;
 962                         clock-names = "core_clk", "iface_clk", "bus_clk";
 963                         qcom,hfi = "venus";
 964                         qcom,max-hw-load = <352800>; /* 720p @ 30 + 1080p @ 30 */
 965                         qcom,enable-idle-indicator;
 966                         rproc = <&vidc_rproc>;
 967                         qcom,iommu-cb = <&venus_ns>,
 968                                         <&venus_sec_bitstream>,
 969                                         <&venus_sec_pixel>,
 970                                         <&venus_sec_non_pixel>;
 971                         status = "disabled";
 972                 };
 973         };
 974
 975         smem {
 976                 compatible = "qcom,smem";
 977
 978                 memory-region = <&smem_mem>;
 979                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 980
 981                 hwlocks = <&tcsr_mutex 3>;
 982         };
 983         smd {
 984                 compatible = "qcom,smd";
 985
 986                 rpm {
 987                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 988                         qcom,ipc = <&apcs 8 0>;
 989                         qcom,smd-edge = <15>;
 990                         qcom,remote-pid = <0xffffffff>;
 991
 992                         rpm_requests {
 993                                 compatible = "qcom,rpm-msm8916";
 994                                 qcom,smd-channels = "rpm_requests";
 995                                 rpmcc: qcom,rpmcc {
 996                                         compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
 997                                         #clock-cells = <1>;
 998                                 };
 999
1000                                 msm-bus {
1001                                                 compatible = "qcom,rpm-msm-bus";
1002                                 };
1003                                 pm8916-regulators {
1004                                         compatible = "qcom,rpm-pm8916-regulators";
1005
1006                                         pm8916_s1: s1 {};
1007                                         pm8916_s2: s2 {};
1008                                         pm8916_s3: s3 {};
1009                                         pm8916_s4: s4 {};
1010
1011                                         pm8916_l1: l1 {};
1012                                         pm8916_l2: l2 {};
1013                                         pm8916_l3: l3 {};
1014                                         pm8916_l4: l4 {};
1015                                         pm8916_l5: l5 {};
1016                                         pm8916_l6: l6 {};
1017                                         pm8916_l7: l7 {};
1018                                         pm8916_l8: l8 {};
1019                                         pm8916_l9: l9 {};
1020                                         pm8916_l10: l10 {};
1021                                         pm8916_l11: l11 {};
1022                                         pm8916_l12: l12 {};
1023                                         pm8916_l13: l13 {};
1024                                         pm8916_l14: l14 {};
1025                                         pm8916_l15: l15 {};
1026                                         pm8916_l16: l16 {};
1027                                         pm8916_l17: l17 {};
1028                                         pm8916_l18: l18 {};
1029                                 };
1030                         };
1031                 };
1032
1033                 qcom,smd-modem {
1034                         interrupts = <0 25 1>;
1035                         qcom,smd-edge = <0>;
1036                         qcom,ipc = <&apcs 8 12>;
1037                         qcom,remote-pid = <1>;
1038                         ipcrtr_requests {
1039                                 compatible = "qcom,ipcrtr";
1040                                 qcom,smd-channels = "IPCRTR";
1041                         };
1042                 };
1043
1044                 pronto_smd_edge: pronto {
1045                         interrupts = <0 142 1>;
1046
1047                         qcom,ipc = <&apcs 8 17>;
1048                         qcom,smd-edge = <6>;
1049                         qcom,remote-pid = <4>;
1050
1051                                bt {
1052                                 compatible = "qcom,hci-smd";
1053                                 qcom,smd-channels = "APPS_RIVA_BT_CMD", "APPS_RIVA_BT_ACL";
1054                                 qcom,smd-channel-names = "event", "data";
1055                         };
1056
1057                         ipcrtr {
1058                                 compatible = "qcom,ipcrtr";
1059                                 qcom,smd-channels = "IPCRTR";
1060                         };
1061
1062                         wifi {
1063                                 compatible = "qcom,wcn3620-wlan";
1064                                 qcom,smd-channels = "WLAN_CTRL";
1065
1066                                 interrupts = <0 145 0>, <0 146 0>;
1067                                 interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
1068
1069                                 qcom,wcnss-mmio = <0x0a000000 0x21b000>;
1070
1071                                 // qcom,tx-enable-gpios = <&apps_smsm 10 0>;
1072                                 // qcom,tx-rings-empty-gpios = <&apps_smsm 9 0>;
1073                         };
1074
1075                         wcnss_ctrl {
1076                                 compatible = "qcom,wcnss";
1077                                 qcom,smd-channels = "WCNSS_CTRL";
1078                         };
1079                 };
1080         };
1081
1082         hexagon-smp2p {
1083                 compatible = "qcom,smp2p";
1084                 qcom,smem = <435>, <428>;
1085
1086                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1087
1088                 qcom,ipc = <&apcs 8 14>;
1089
1090                 qcom,local-pid = <0>;
1091                 qcom,remote-pid = <1>;
1092
1093                 hexagon_smp2p_out: master-kernel {
1094                         qcom,entry-name = "master-kernel";
1095
1096                         #qcom,state-cells = <1>;
1097                 };
1098
1099                 hexagon_smp2p_in: slave-kernel {
1100                         qcom,entry-name = "slave-kernel";
1101
1102                         interrupt-controller;
1103                         #interrupt-cells = <2>;
1104                 };
1105         };
1106
1107         wcnss-smp2p {
1108                 compatible = "qcom,smp2p";
1109                 qcom,smem = <451>, <431>;
1110
1111                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1112
1113                 qcom,ipc = <&apcs 8 18>;
1114
1115                 qcom,local-pid = <0>;
1116                 qcom,remote-pid = <4>;
1117
1118                 wcnss_smp2p_out: master-kernel {
1119                         qcom,entry-name = "master-kernel";
1120
1121                         #qcom,state-cells = <1>;
1122                 };
1123
1124                 wcnss_smp2p_in: slave-kernel {
1125                         qcom,entry-name = "slave-kernel";
1126
1127                         interrupt-controller;
1128                         #interrupt-cells = <2>;
1129                 };
1130         };
1131
1132         smsm {
1133                 compatible = "qcom,smsm";
1134
1135                 #address-cells = <1>;
1136                 #size-cells = <0>;
1137
1138                 qcom,ipc-1 = <&apcs 0 13>;
1139                 qcom,ipc-6 = <&apcs 0 19>;
1140
1141                 apps_smsm: apps@0 {
1142                         reg = <0>;
1143
1144                         #qcom,state-cells = <1>;
1145                 };
1146
1147                 hexagon_smsm: hexagon@1 {
1148                         reg = <1>;
1149                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1150
1151                         interrupt-controller;
1152                         #interrupt-cells = <2>;
1153                 };
1154
1155                 wcnss_smsm: wcnss@6 {
1156                         reg = <6>;
1157                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1158
1159                         interrupt-controller;
1160                         #interrupt-cells = <2>;
1161                 };
1162         };
1163 };
1164
1165 #include "msm8916-pins.dtsi"
1166 #include "msm8916-iommu.dtsi"
1167 #include "msm8916-coresight.dtsi"
1168 #include "msm8916-bus.dtsi"