2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_PGTABLE_H
17 #define __ASM_PGTABLE_H
20 #include <asm/proc-fns.h>
22 #include <asm/memory.h>
23 #include <asm/pgtable-hwdef.h>
26 * Software defined PTE bits definition.
28 #define PTE_VALID (_AT(pteval_t, 1) << 0)
29 #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */
30 #define PTE_DIRTY (_AT(pteval_t, 1) << 55)
31 #define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
32 #define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
35 * VMALLOC and SPARSEMEM_VMEMMAP ranges.
37 * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array
38 * (rounded up to PUD_SIZE).
39 * VMALLOC_START: beginning of the kernel VA space
40 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space,
41 * fixed mappings and modules
43 #define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE)
44 #define VMALLOC_START (UL(0xffffffffffffffff) << VA_BITS)
45 #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
47 #define vmemmap ((struct page *)(VMALLOC_END + SZ_64K))
49 #define FIRST_USER_ADDRESS 0UL
53 #include <linux/mmdebug.h>
55 extern void __pte_error(const char *file, int line, unsigned long val);
56 extern void __pmd_error(const char *file, int line, unsigned long val);
57 extern void __pud_error(const char *file, int line, unsigned long val);
58 extern void __pgd_error(const char *file, int line, unsigned long val);
60 #define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
61 #define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
63 #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
64 #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC))
65 #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL))
67 #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
68 #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
69 #define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
71 #define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
73 #define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
74 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE)
76 #define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP)
77 #define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
79 #define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
80 #define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
82 #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
83 #define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
84 #define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
85 #define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
86 #define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
87 #define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
88 #define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
90 #define __P000 PAGE_NONE
91 #define __P001 PAGE_READONLY
92 #define __P010 PAGE_COPY
93 #define __P011 PAGE_COPY
94 #define __P100 PAGE_READONLY_EXEC
95 #define __P101 PAGE_READONLY_EXEC
96 #define __P110 PAGE_COPY_EXEC
97 #define __P111 PAGE_COPY_EXEC
99 #define __S000 PAGE_NONE
100 #define __S001 PAGE_READONLY
101 #define __S010 PAGE_SHARED
102 #define __S011 PAGE_SHARED
103 #define __S100 PAGE_READONLY_EXEC
104 #define __S101 PAGE_READONLY_EXEC
105 #define __S110 PAGE_SHARED_EXEC
106 #define __S111 PAGE_SHARED_EXEC
109 * ZERO_PAGE is a global shared page that is always zero: used
110 * for zero-mapped memory areas etc..
112 extern struct page *empty_zero_page;
113 #define ZERO_PAGE(vaddr) (empty_zero_page)
115 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
117 #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
119 #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
121 #define pte_none(pte) (!pte_val(pte))
122 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
123 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
125 /* Find an entry in the third-level page table. */
126 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
128 #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr))
130 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
131 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
132 #define pte_unmap(pte) do { } while (0)
133 #define pte_unmap_nested(pte) do { } while (0)
136 * The following only work if pte_present(). Undefined behaviour otherwise.
138 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
139 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
140 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
141 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
142 #define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
144 #ifdef CONFIG_ARM64_HW_AFDBM
145 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
147 #define pte_hw_dirty(pte) (0)
149 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
150 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
152 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
153 #define pte_valid_user(pte) \
154 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
155 #define pte_valid_not_user(pte) \
156 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
158 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
160 pte_val(pte) &= ~pgprot_val(prot);
164 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
166 pte_val(pte) |= pgprot_val(prot);
170 static inline pte_t pte_wrprotect(pte_t pte)
172 return clear_pte_bit(pte, __pgprot(PTE_WRITE));
175 static inline pte_t pte_mkwrite(pte_t pte)
177 return set_pte_bit(pte, __pgprot(PTE_WRITE));
180 static inline pte_t pte_mkclean(pte_t pte)
182 return clear_pte_bit(pte, __pgprot(PTE_DIRTY));
185 static inline pte_t pte_mkdirty(pte_t pte)
187 return set_pte_bit(pte, __pgprot(PTE_DIRTY));
190 static inline pte_t pte_mkold(pte_t pte)
192 return clear_pte_bit(pte, __pgprot(PTE_AF));
195 static inline pte_t pte_mkyoung(pte_t pte)
197 return set_pte_bit(pte, __pgprot(PTE_AF));
200 static inline pte_t pte_mkspecial(pte_t pte)
202 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
205 static inline void set_pte(pte_t *ptep, pte_t pte)
210 * Only if the new pte is valid and kernel, otherwise TLB maintenance
211 * or update_mmu_cache() have the necessary barriers.
213 if (pte_valid_not_user(pte)) {
220 struct vm_area_struct;
222 extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
225 * PTE bits configuration in the presence of hardware Dirty Bit Management
226 * (PTE_WRITE == PTE_DBM):
228 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
234 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
235 * the page fault mechanism. Checking the dirty status of a pte becomes:
237 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
239 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
240 pte_t *ptep, pte_t pte)
242 if (pte_valid_user(pte)) {
243 if (!pte_special(pte) && pte_exec(pte))
244 __sync_icache_dcache(pte, addr);
245 if (pte_sw_dirty(pte) && pte_write(pte))
246 pte_val(pte) &= ~PTE_RDONLY;
248 pte_val(pte) |= PTE_RDONLY;
252 * If the existing pte is valid, check for potential race with
253 * hardware updates of the pte (ptep_set_access_flags safely changes
254 * valid ptes without going through an invalid entry).
256 if (IS_ENABLED(CONFIG_DEBUG_VM) && IS_ENABLED(CONFIG_ARM64_HW_AFDBM) &&
258 BUG_ON(!pte_young(pte));
259 BUG_ON(pte_write(*ptep) && !pte_dirty(pte));
266 * Huge pte definitions.
268 #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT))
269 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
272 * Hugetlb definitions.
274 #define HUGE_MAX_HSTATE 2
275 #define HPAGE_SHIFT PMD_SHIFT
276 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
277 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
278 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
280 #define __HAVE_ARCH_PTE_SPECIAL
282 static inline pte_t pud_pte(pud_t pud)
284 return __pte(pud_val(pud));
287 static inline pmd_t pud_pmd(pud_t pud)
289 return __pmd(pud_val(pud));
292 static inline pte_t pmd_pte(pmd_t pmd)
294 return __pte(pmd_val(pmd));
297 static inline pmd_t pte_pmd(pte_t pte)
299 return __pmd(pte_val(pte));
302 static inline pgprot_t mk_sect_prot(pgprot_t prot)
304 return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT);
311 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
312 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
313 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
315 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
316 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
317 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
318 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
319 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
320 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
321 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
322 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
323 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
324 #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK))
326 #define __HAVE_ARCH_PMD_WRITE
327 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
329 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
331 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
332 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
333 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
335 #define pud_write(pud) pte_write(pud_pte(pud))
336 #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
338 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
340 static inline int has_transparent_hugepage(void)
345 #define __pgprot_modify(prot,mask,bits) \
346 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
349 * Mark the prot value as uncacheable and unbufferable.
351 #define pgprot_noncached(prot) \
352 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
353 #define pgprot_writecombine(prot) \
354 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
355 #define pgprot_device(prot) \
356 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
357 #define __HAVE_PHYS_MEM_ACCESS_PROT
359 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
360 unsigned long size, pgprot_t vma_prot);
362 #define pmd_none(pmd) (!pmd_val(pmd))
363 #define pmd_present(pmd) (pmd_val(pmd))
365 #define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
367 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
369 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
372 #ifdef CONFIG_ARM64_64K_PAGES
373 #define pud_sect(pud) (0)
374 #define pud_table(pud) (1)
376 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
378 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
382 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
389 static inline void pmd_clear(pmd_t *pmdp)
391 set_pmd(pmdp, __pmd(0));
394 static inline pte_t *pmd_page_vaddr(pmd_t pmd)
396 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
399 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
402 * Conversion functions: convert a page and protection to a page entry,
403 * and a page entry and page directory to the page they refer to.
405 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
407 #if CONFIG_PGTABLE_LEVELS > 2
409 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
411 #define pud_none(pud) (!pud_val(pud))
412 #define pud_bad(pud) (!(pud_val(pud) & 2))
413 #define pud_present(pud) (pud_val(pud))
415 static inline void set_pud(pud_t *pudp, pud_t pud)
422 static inline void pud_clear(pud_t *pudp)
424 set_pud(pudp, __pud(0));
427 static inline pmd_t *pud_page_vaddr(pud_t pud)
429 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
432 /* Find an entry in the second-level page table. */
433 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
435 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
437 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
440 #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK))
442 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
444 #if CONFIG_PGTABLE_LEVELS > 3
446 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
448 #define pgd_none(pgd) (!pgd_val(pgd))
449 #define pgd_bad(pgd) (!(pgd_val(pgd) & 2))
450 #define pgd_present(pgd) (pgd_val(pgd))
452 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
458 static inline void pgd_clear(pgd_t *pgdp)
460 set_pgd(pgdp, __pgd(0));
463 static inline pud_t *pgd_page_vaddr(pgd_t pgd)
465 return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK);
468 /* Find an entry in the frst-level page table. */
469 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
471 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
473 return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr);
476 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK))
478 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
480 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
482 /* to find an entry in a page-table-directory */
483 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
485 #define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
487 /* to find an entry in a kernel page-table-directory */
488 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
490 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
492 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
493 PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
494 /* preserve the hardware dirty information */
495 if (pte_hw_dirty(pte))
496 pte = pte_mkdirty(pte);
497 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
501 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
503 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
506 #ifdef CONFIG_ARM64_HW_AFDBM
508 * Atomic pte/pmd modifications.
510 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
511 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
512 unsigned long address,
516 unsigned int tmp, res;
518 asm volatile("// ptep_test_and_clear_young\n"
519 " prfm pstl1strm, %2\n"
521 " ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n"
522 " and %0, %0, %4 // clear PTE_AF\n"
523 " stxr %w1, %0, %2\n"
525 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res)
526 : "L" (~PTE_AF), "I" (ilog2(PTE_AF)));
531 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
532 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
533 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
534 unsigned long address,
537 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
539 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
541 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
542 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
543 unsigned long address, pte_t *ptep)
548 asm volatile("// ptep_get_and_clear\n"
549 " prfm pstl1strm, %2\n"
551 " stxr %w1, xzr, %2\n"
553 : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)));
555 return __pte(old_pteval);
558 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
559 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR
560 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
561 unsigned long address, pmd_t *pmdp)
563 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
565 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
568 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
569 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
571 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
572 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
577 asm volatile("// ptep_set_wrprotect\n"
578 " prfm pstl1strm, %2\n"
580 " tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n"
581 " csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n"
582 " orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n"
583 " and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n"
584 " stxr %w1, %0, %2\n"
586 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))
587 : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE)
591 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
592 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
593 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
594 unsigned long address, pmd_t *pmdp)
596 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
599 #endif /* CONFIG_ARM64_HW_AFDBM */
601 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
602 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
605 * Encode and decode a swap entry:
606 * bits 0-1: present (must be zero)
607 * bits 2-7: swap type
608 * bits 8-57: swap offset
610 #define __SWP_TYPE_SHIFT 2
611 #define __SWP_TYPE_BITS 6
612 #define __SWP_OFFSET_BITS 50
613 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
614 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
615 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
617 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
618 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
619 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
621 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
622 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
625 * Ensure that there are not more swap files than can be encoded in the kernel
628 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
630 extern int kern_addr_valid(unsigned long addr);
632 #include <asm-generic/pgtable.h>
634 #define pgtable_cache_init() do { } while (0)
637 * On AArch64, the cache coherency is handled via the set_pte_at() function.
639 static inline void update_mmu_cache(struct vm_area_struct *vma,
640 unsigned long addr, pte_t *ptep)
643 * set_pte() does not have a DSB for user mappings, so make sure that
644 * the page table write is visible.
649 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
651 #endif /* !__ASSEMBLY__ */
653 #endif /* __ASM_PGTABLE_H */