arch/sh/kernel/cpu/sh4a/setup-sh7786.c

   1 /*
   2  * SH7786 Setup
   3  *
   4  * Copyright (C) 2009  Renesas Solutions Corp.
   5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  * Paul Mundt <paul.mundt@renesas.com>
   7  *
   8  * Based on SH7785 Setup
   9  *
  10  *  Copyright (C) 2007  Paul Mundt
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file "COPYING" in the main directory of this archive
  14  * for more details.
  15  */
  16 #include <linux/platform_device.h>
  17 #include <linux/init.h>
  18 #include <linux/serial.h>
  19 #include <linux/serial_sci.h>
  20 #include <linux/io.h>
  21 #include <linux/mm.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/sh_timer.h>
  24 #include <asm/mmzone.h>
  25
  26 static struct plat_sci_port sci_platform_data[] = {
  27         {
  28                 .mapbase        = 0xffea0000,
  29                 .flags          = UPF_BOOT_AUTOCONF,
  30                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  31                 .scbrr_algo_id  = SCBRR_ALGO_1,
  32                 .type           = PORT_SCIF,
  33                 .irqs           = { 40, 41, 43, 42 },
  34         },
  35         /*
  36          * The rest of these all have multiplexed IRQs
  37          */
  38         {
  39                 .mapbase        = 0xffeb0000,
  40                 .flags          = UPF_BOOT_AUTOCONF,
  41                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  42                 .scbrr_algo_id  = SCBRR_ALGO_1,
  43                 .type           = PORT_SCIF,
  44                 .irqs           = { 44, 44, 44, 44 },
  45         }, {
  46                 .mapbase        = 0xffec0000,
  47                 .flags          = UPF_BOOT_AUTOCONF,
  48                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  49                 .scbrr_algo_id  = SCBRR_ALGO_1,
  50                 .type           = PORT_SCIF,
  51                 .irqs           = { 50, 50, 50, 50 },
  52         }, {
  53                 .mapbase        = 0xffed0000,
  54                 .flags          = UPF_BOOT_AUTOCONF,
  55                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  56                 .scbrr_algo_id  = SCBRR_ALGO_1,
  57                 .type           = PORT_SCIF,
  58                 .irqs           = { 51, 51, 51, 51 },
  59         }, {
  60                 .mapbase        = 0xffee0000,
  61                 .flags          = UPF_BOOT_AUTOCONF,
  62                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  63                 .scbrr_algo_id  = SCBRR_ALGO_1,
  64                 .type           = PORT_SCIF,
  65                 .irqs           = { 52, 52, 52, 52 },
  66         }, {
  67                 .mapbase        = 0xffef0000,
  68                 .flags          = UPF_BOOT_AUTOCONF,
  69                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  70                 .scbrr_algo_id  = SCBRR_ALGO_1,
  71                 .type           = PORT_SCIF,
  72                 .irqs           = { 53, 53, 53, 53 },
  73         }, {
  74                 .flags = 0,
  75         }
  76 };
  77
  78 static struct platform_device sci_device = {
  79         .name           = "sh-sci",
  80         .id             = -1,
  81         .dev            = {
  82                 .platform_data  = sci_platform_data,
  83         },
  84 };
  85
  86 static struct sh_timer_config tmu0_platform_data = {
  87         .name = "TMU0",
  88         .channel_offset = 0x04,
  89         .timer_bit = 0,
  90         .clk = "peripheral_clk",
  91         .clockevent_rating = 200,
  92 };
  93
  94 static struct resource tmu0_resources[] = {
  95         [0] = {
  96                 .name   = "TMU0",
  97                 .start  = 0xffd80008,
  98                 .end    = 0xffd80013,
  99                 .flags  = IORESOURCE_MEM,
 100         },
 101         [1] = {
 102                 .start  = 16,
 103                 .flags  = IORESOURCE_IRQ,
 104         },
 105 };
 106
 107 static struct platform_device tmu0_device = {
 108         .name           = "sh_tmu",
 109         .id             = 0,
 110         .dev = {
 111                 .platform_data  = &tmu0_platform_data,
 112         },
 113         .resource       = tmu0_resources,
 114         .num_resources  = ARRAY_SIZE(tmu0_resources),
 115 };
 116
 117 static struct sh_timer_config tmu1_platform_data = {
 118         .name = "TMU1",
 119         .channel_offset = 0x10,
 120         .timer_bit = 1,
 121         .clk = "peripheral_clk",
 122         .clocksource_rating = 200,
 123 };
 124
 125 static struct resource tmu1_resources[] = {
 126         [0] = {
 127                 .name   = "TMU1",
 128                 .start  = 0xffd80014,
 129                 .end    = 0xffd8001f,
 130                 .flags  = IORESOURCE_MEM,
 131         },
 132         [1] = {
 133                 .start  = 17,
 134                 .flags  = IORESOURCE_IRQ,
 135         },
 136 };
 137
 138 static struct platform_device tmu1_device = {
 139         .name           = "sh_tmu",
 140         .id             = 1,
 141         .dev = {
 142                 .platform_data  = &tmu1_platform_data,
 143         },
 144         .resource       = tmu1_resources,
 145         .num_resources  = ARRAY_SIZE(tmu1_resources),
 146 };
 147
 148 static struct sh_timer_config tmu2_platform_data = {
 149         .name = "TMU2",
 150         .channel_offset = 0x1c,
 151         .timer_bit = 2,
 152         .clk = "peripheral_clk",
 153 };
 154
 155 static struct resource tmu2_resources[] = {
 156         [0] = {
 157                 .name   = "TMU2",
 158                 .start  = 0xffd80020,
 159                 .end    = 0xffd8002f,
 160                 .flags  = IORESOURCE_MEM,
 161         },
 162         [1] = {
 163                 .start  = 18,
 164                 .flags  = IORESOURCE_IRQ,
 165         },
 166 };
 167
 168 static struct platform_device tmu2_device = {
 169         .name           = "sh_tmu",
 170         .id             = 2,
 171         .dev = {
 172                 .platform_data  = &tmu2_platform_data,
 173         },
 174         .resource       = tmu2_resources,
 175         .num_resources  = ARRAY_SIZE(tmu2_resources),
 176 };
 177
 178 static struct sh_timer_config tmu3_platform_data = {
 179         .name = "TMU3",
 180         .channel_offset = 0x04,
 181         .timer_bit = 0,
 182         .clk = "peripheral_clk",
 183 };
 184
 185 static struct resource tmu3_resources[] = {
 186         [0] = {
 187                 .name   = "TMU3",
 188                 .start  = 0xffda0008,
 189                 .end    = 0xffda0013,
 190                 .flags  = IORESOURCE_MEM,
 191         },
 192         [1] = {
 193                 .start  = 20,
 194                 .flags  = IORESOURCE_IRQ,
 195         },
 196 };
 197
 198 static struct platform_device tmu3_device = {
 199         .name           = "sh_tmu",
 200         .id             = 3,
 201         .dev = {
 202                 .platform_data  = &tmu3_platform_data,
 203         },
 204         .resource       = tmu3_resources,
 205         .num_resources  = ARRAY_SIZE(tmu3_resources),
 206 };
 207
 208 static struct sh_timer_config tmu4_platform_data = {
 209         .name = "TMU4",
 210         .channel_offset = 0x10,
 211         .timer_bit = 1,
 212         .clk = "peripheral_clk",
 213 };
 214
 215 static struct resource tmu4_resources[] = {
 216         [0] = {
 217                 .name   = "TMU4",
 218                 .start  = 0xffda0014,
 219                 .end    = 0xffda001f,
 220                 .flags  = IORESOURCE_MEM,
 221         },
 222         [1] = {
 223                 .start  = 21,
 224                 .flags  = IORESOURCE_IRQ,
 225         },
 226 };
 227
 228 static struct platform_device tmu4_device = {
 229         .name           = "sh_tmu",
 230         .id             = 4,
 231         .dev = {
 232                 .platform_data  = &tmu4_platform_data,
 233         },
 234         .resource       = tmu4_resources,
 235         .num_resources  = ARRAY_SIZE(tmu4_resources),
 236 };
 237
 238 static struct sh_timer_config tmu5_platform_data = {
 239         .name = "TMU5",
 240         .channel_offset = 0x1c,
 241         .timer_bit = 2,
 242         .clk = "peripheral_clk",
 243 };
 244
 245 static struct resource tmu5_resources[] = {
 246         [0] = {
 247                 .name   = "TMU5",
 248                 .start  = 0xffda0020,
 249                 .end    = 0xffda002b,
 250                 .flags  = IORESOURCE_MEM,
 251         },
 252         [1] = {
 253                 .start  = 22,
 254                 .flags  = IORESOURCE_IRQ,
 255         },
 256 };
 257
 258 static struct platform_device tmu5_device = {
 259         .name           = "sh_tmu",
 260         .id             = 5,
 261         .dev = {
 262                 .platform_data  = &tmu5_platform_data,
 263         },
 264         .resource       = tmu5_resources,
 265         .num_resources  = ARRAY_SIZE(tmu5_resources),
 266 };
 267
 268 static struct sh_timer_config tmu6_platform_data = {
 269         .name = "TMU6",
 270         .channel_offset = 0x04,
 271         .timer_bit = 0,
 272         .clk = "peripheral_clk",
 273 };
 274
 275 static struct resource tmu6_resources[] = {
 276         [0] = {
 277                 .name   = "TMU6",
 278                 .start  = 0xffdc0008,
 279                 .end    = 0xffdc0013,
 280                 .flags  = IORESOURCE_MEM,
 281         },
 282         [1] = {
 283                 .start  = 45,
 284                 .flags  = IORESOURCE_IRQ,
 285         },
 286 };
 287
 288 static struct platform_device tmu6_device = {
 289         .name           = "sh_tmu",
 290         .id             = 6,
 291         .dev = {
 292                 .platform_data  = &tmu6_platform_data,
 293         },
 294         .resource       = tmu6_resources,
 295         .num_resources  = ARRAY_SIZE(tmu6_resources),
 296 };
 297
 298 static struct sh_timer_config tmu7_platform_data = {
 299         .name = "TMU7",
 300         .channel_offset = 0x10,
 301         .timer_bit = 1,
 302         .clk = "peripheral_clk",
 303 };
 304
 305 static struct resource tmu7_resources[] = {
 306         [0] = {
 307                 .name   = "TMU7",
 308                 .start  = 0xffdc0014,
 309                 .end    = 0xffdc001f,
 310                 .flags  = IORESOURCE_MEM,
 311         },
 312         [1] = {
 313                 .start  = 45,
 314                 .flags  = IORESOURCE_IRQ,
 315         },
 316 };
 317
 318 static struct platform_device tmu7_device = {
 319         .name           = "sh_tmu",
 320         .id             = 7,
 321         .dev = {
 322                 .platform_data  = &tmu7_platform_data,
 323         },
 324         .resource       = tmu7_resources,
 325         .num_resources  = ARRAY_SIZE(tmu7_resources),
 326 };
 327
 328 static struct sh_timer_config tmu8_platform_data = {
 329         .name = "TMU8",
 330         .channel_offset = 0x1c,
 331         .timer_bit = 2,
 332         .clk = "peripheral_clk",
 333 };
 334
 335 static struct resource tmu8_resources[] = {
 336         [0] = {
 337                 .name   = "TMU8",
 338                 .start  = 0xffdc0020,
 339                 .end    = 0xffdc002b,
 340                 .flags  = IORESOURCE_MEM,
 341         },
 342         [1] = {
 343                 .start  = 45,
 344                 .flags  = IORESOURCE_IRQ,
 345         },
 346 };
 347
 348 static struct platform_device tmu8_device = {
 349         .name           = "sh_tmu",
 350         .id             = 8,
 351         .dev = {
 352                 .platform_data  = &tmu8_platform_data,
 353         },
 354         .resource       = tmu8_resources,
 355         .num_resources  = ARRAY_SIZE(tmu8_resources),
 356 };
 357
 358 static struct sh_timer_config tmu9_platform_data = {
 359         .name = "TMU9",
 360         .channel_offset = 0x04,
 361         .timer_bit = 0,
 362         .clk = "peripheral_clk",
 363 };
 364
 365 static struct resource tmu9_resources[] = {
 366         [0] = {
 367                 .name   = "TMU9",
 368                 .start  = 0xffde0008,
 369                 .end    = 0xffde0013,
 370                 .flags  = IORESOURCE_MEM,
 371         },
 372         [1] = {
 373                 .start  = 46,
 374                 .flags  = IORESOURCE_IRQ,
 375         },
 376 };
 377
 378 static struct platform_device tmu9_device = {
 379         .name           = "sh_tmu",
 380         .id             = 9,
 381         .dev = {
 382                 .platform_data  = &tmu9_platform_data,
 383         },
 384         .resource       = tmu9_resources,
 385         .num_resources  = ARRAY_SIZE(tmu9_resources),
 386 };
 387
 388 static struct sh_timer_config tmu10_platform_data = {
 389         .name = "TMU10",
 390         .channel_offset = 0x10,
 391         .timer_bit = 1,
 392         .clk = "peripheral_clk",
 393 };
 394
 395 static struct resource tmu10_resources[] = {
 396         [0] = {
 397                 .name   = "TMU10",
 398                 .start  = 0xffde0014,
 399                 .end    = 0xffde001f,
 400                 .flags  = IORESOURCE_MEM,
 401         },
 402         [1] = {
 403                 .start  = 46,
 404                 .flags  = IORESOURCE_IRQ,
 405         },
 406 };
 407
 408 static struct platform_device tmu10_device = {
 409         .name           = "sh_tmu",
 410         .id             = 10,
 411         .dev = {
 412                 .platform_data  = &tmu10_platform_data,
 413         },
 414         .resource       = tmu10_resources,
 415         .num_resources  = ARRAY_SIZE(tmu10_resources),
 416 };
 417
 418 static struct sh_timer_config tmu11_platform_data = {
 419         .name = "TMU11",
 420         .channel_offset = 0x1c,
 421         .timer_bit = 2,
 422         .clk = "peripheral_clk",
 423 };
 424
 425 static struct resource tmu11_resources[] = {
 426         [0] = {
 427                 .name   = "TMU11",
 428                 .start  = 0xffde0020,
 429                 .end    = 0xffde002b,
 430                 .flags  = IORESOURCE_MEM,
 431         },
 432         [1] = {
 433                 .start  = 46,
 434                 .flags  = IORESOURCE_IRQ,
 435         },
 436 };
 437
 438 static struct platform_device tmu11_device = {
 439         .name           = "sh_tmu",
 440         .id             = 11,
 441         .dev = {
 442                 .platform_data  = &tmu11_platform_data,
 443         },
 444         .resource       = tmu11_resources,
 445         .num_resources  = ARRAY_SIZE(tmu11_resources),
 446 };
 447
 448 static struct resource usb_ohci_resources[] = {
 449         [0] = {
 450                 .start  = 0xffe70400,
 451                 .end    = 0xffe704ff,
 452                 .flags  = IORESOURCE_MEM,
 453         },
 454         [1] = {
 455                 .start  = 77,
 456                 .end    = 77,
 457                 .flags  = IORESOURCE_IRQ,
 458         },
 459 };
 460
 461 static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
 462 static struct platform_device usb_ohci_device = {
 463         .name           = "sh_ohci",
 464         .id             = -1,
 465         .dev = {
 466                 .dma_mask               = &usb_ohci_dma_mask,
 467                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 468         },
 469         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 470         .resource       = usb_ohci_resources,
 471 };
 472
 473 static struct platform_device *sh7786_early_devices[] __initdata = {
 474         &tmu0_device,
 475         &tmu1_device,
 476         &tmu2_device,
 477         &tmu3_device,
 478         &tmu4_device,
 479         &tmu5_device,
 480         &tmu6_device,
 481         &tmu7_device,
 482         &tmu8_device,
 483         &tmu9_device,
 484         &tmu10_device,
 485         &tmu11_device,
 486 };
 487
 488 static struct platform_device *sh7786_devices[] __initdata = {
 489         &sci_device,
 490         &usb_ohci_device,
 491 };
 492
 493
 494 /*
 495  * Please call this function if your platform board
 496  * use external clock for USB
 497  * */
 498 #define USBCTL0         0xffe70858
 499 #define CLOCK_MODE_MASK 0xffffff7f
 500 #define EXT_CLOCK_MODE  0x00000080
 501 void __init sh7786_usb_use_exclock(void)
 502 {
 503         u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
 504         __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
 505 }
 506
 507 #define USBINITREG1     0xffe70094
 508 #define USBINITREG2     0xffe7009c
 509 #define USBINITVAL1     0x00ff0040
 510 #define USBINITVAL2     0x00000001
 511
 512 #define USBPCTL1        0xffe70804
 513 #define USBST           0xffe70808
 514 #define PHY_ENB         0x00000001
 515 #define PLL_ENB         0x00000002
 516 #define PHY_RST         0x00000004
 517 #define ACT_PLL_STATUS  0xc0000000
 518 static void __init sh7786_usb_setup(void)
 519 {
 520         int i = 1000000;
 521
 522         /*
 523          * USB initial settings
 524          *
 525          * The following settings are necessary
 526          * for using the USB modules.
 527          *
 528          * see "USB Inital Settings" for detail
 529          */
 530         __raw_writel(USBINITVAL1, USBINITREG1);
 531         __raw_writel(USBINITVAL2, USBINITREG2);
 532
 533         /*
 534          * Set the PHY and PLL enable bit
 535          */
 536         __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
 537         while (i--) {
 538                 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
 539                         /* Set the PHY RST bit */
 540                         __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
 541                         printk(KERN_INFO "sh7786 usb setup done\n");
 542                         break;
 543                 }
 544                 cpu_relax();
 545         }
 546 }
 547
 548 static int __init sh7786_devices_setup(void)
 549 {
 550         int ret;
 551
 552         sh7786_usb_setup();
 553
 554         ret = platform_add_devices(sh7786_early_devices,
 555                                    ARRAY_SIZE(sh7786_early_devices));
 556         if (unlikely(ret != 0))
 557                 return ret;
 558
 559         return platform_add_devices(sh7786_devices,
 560                                     ARRAY_SIZE(sh7786_devices));
 561 }
 562 device_initcall(sh7786_devices_setup);
 563
 564 void __init plat_early_device_setup(void)
 565 {
 566         early_platform_add_devices(sh7786_early_devices,
 567                                    ARRAY_SIZE(sh7786_early_devices));
 568 }
 569
 570 enum {
 571         UNUSED = 0,
 572
 573         /* interrupt sources */
 574
 575         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 576         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 577         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 578         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 579
 580         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 581         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 582         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 583         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 584
 585         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 586         WDT,
 587         TMU0_0, TMU0_1, TMU0_2, TMU0_3,
 588         TMU1_0, TMU1_1, TMU1_2,
 589         DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 590         HUDI1, HUDI0,
 591         DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 592         HPB_0, HPB_1, HPB_2,
 593         SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 594         SCIF1,
 595         TMU2, TMU3,
 596         SCIF2, SCIF3, SCIF4, SCIF5,
 597         Eth_0, Eth_1,
 598         PCIeC0_0, PCIeC0_1, PCIeC0_2,
 599         PCIeC1_0, PCIeC1_1, PCIeC1_2,
 600         USB,
 601         I2C0, I2C1,
 602         DU,
 603         SSI0, SSI1, SSI2, SSI3,
 604         PCIeC2_0, PCIeC2_1, PCIeC2_2,
 605         HAC0, HAC1,
 606         FLCTL,
 607         HSPI,
 608         GPIO0, GPIO1,
 609         Thermal,
 610         INTICI0, INTICI1, INTICI2, INTICI3,
 611         INTICI4, INTICI5, INTICI6, INTICI7,
 612 };
 613
 614 static struct intc_vect vectors[] __initdata = {
 615         INTC_VECT(WDT, 0x3e0),
 616         INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
 617         INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
 618         INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
 619         INTC_VECT(TMU1_2, 0x4c0),
 620         INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
 621         INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
 622         INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
 623         INTC_VECT(DMAC0_6, 0x5c0),
 624         INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
 625         INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
 626         INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
 627         INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
 628         INTC_VECT(HPB_2, 0x6e0),
 629         INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
 630         INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
 631         INTC_VECT(SCIF1, 0x780),
 632         INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
 633         INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
 634         INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
 635         INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
 636         INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
 637         INTC_VECT(PCIeC0_2, 0xb20),
 638         INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
 639         INTC_VECT(PCIeC1_2, 0xb80),
 640         INTC_VECT(USB, 0xba0),
 641         INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
 642         INTC_VECT(DU, 0xd00),
 643         INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
 644         INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
 645         INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
 646         INTC_VECT(PCIeC2_2, 0xde0),
 647         INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
 648         INTC_VECT(FLCTL, 0xe40),
 649         INTC_VECT(HSPI, 0xe80),
 650         INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
 651         INTC_VECT(Thermal, 0xee0),
 652         INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
 653         INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
 654         INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
 655         INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
 656 };
 657
 658 #define CnINTMSK0       0xfe410030
 659 #define CnINTMSK1       0xfe410040
 660 #define CnINTMSKCLR0    0xfe410050
 661 #define CnINTMSKCLR1    0xfe410060
 662 #define CnINT2MSKR0     0xfe410a20
 663 #define CnINT2MSKR1     0xfe410a24
 664 #define CnINT2MSKR2     0xfe410a28
 665 #define CnINT2MSKR3     0xfe410a2c
 666 #define CnINT2MSKCR0    0xfe410a30
 667 #define CnINT2MSKCR1    0xfe410a34
 668 #define CnINT2MSKCR2    0xfe410a38
 669 #define CnINT2MSKCR3    0xfe410a3c
 670 #define INTMSK2         0xfe410068
 671 #define INTMSKCLR2      0xfe41006c
 672
 673 static struct intc_mask_reg mask_registers[] __initdata = {
 674         { CnINTMSK0, CnINTMSKCLR0, 32,
 675           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 676         { INTMSK2, INTMSKCLR2, 32,
 677           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 678             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 679             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 680             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 681             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 682             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 683             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 684             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 685         { CnINT2MSKR0, CnINT2MSKCR0 , 32,
 686           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 687             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
 688         { CnINT2MSKR1, CnINT2MSKCR1, 32,
 689           { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
 690             DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
 691             HUDI1, HUDI0,
 692             DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
 693             HPB_0, HPB_1, HPB_2,
 694             SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
 695             SCIF1,
 696             TMU2, TMU3, 0, } },
 697         { CnINT2MSKR2, CnINT2MSKCR2, 32,
 698           { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
 699             Eth_0, Eth_1,
 700             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 701             PCIeC0_0, PCIeC0_1, PCIeC0_2,
 702             PCIeC1_0, PCIeC1_1, PCIeC1_2,
 703             USB, 0, 0 } },
 704         { CnINT2MSKR3, CnINT2MSKCR3, 32,
 705           { 0, 0, 0, 0, 0, 0,
 706             I2C0, I2C1,
 707             DU, SSI0, SSI1, SSI2, SSI3,
 708             PCIeC2_0, PCIeC2_1, PCIeC2_2,
 709             HAC0, HAC1,
 710             FLCTL, 0,
 711             HSPI, GPIO0, GPIO1, Thermal,
 712             0, 0, 0, 0, 0, 0, 0, 0 } },
 713 };
 714
 715 static struct intc_prio_reg prio_registers[] __initdata = {
 716         { 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 717                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 718         { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
 719         { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
 720                                                  TMU0_2, TMU0_3 } },
 721         { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
 722                                                  TMU1_2, 0 } },
 723         { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
 724                                                  DMAC0_2, DMAC0_3 } },
 725         { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
 726                                                  DMAC0_6, HUDI1 } },
 727         { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
 728                                                  DMAC1_1, DMAC1_2 } },
 729         { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
 730                                                  HPB_1, HPB_2 } },
 731         { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
 732                                                  SCIF0_2, SCIF0_3 } },
 733         { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
 734         { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
 735         { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
 736                                                   Eth_0, Eth_1 } },
 737         { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
 738         { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
 739         { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
 740         { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
 741         { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
 742                                                   PCIeC1_0, PCIeC1_1 } },
 743         { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
 744         { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
 745         { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
 746         { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
 747         { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
 748                                                   PCIeC2_1, PCIeC2_2 } },
 749         { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
 750         { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
 751                                                   GPIO1, Thermal } },
 752         { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
 753         { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
 754         { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
 755           { INTICI7, INTICI6, INTICI5, INTICI4,
 756             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
 757 };
 758
 759 static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
 760                          mask_registers, prio_registers, NULL);
 761
 762 /* Support for external interrupt pins in IRQ mode */
 763
 764 static struct intc_vect vectors_irq0123[] __initdata = {
 765         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
 766         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
 767 };
 768
 769 static struct intc_vect vectors_irq4567[] __initdata = {
 770         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
 771         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
 772 };
 773
 774 static struct intc_sense_reg sense_registers[] __initdata = {
 775         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 776                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 777 };
 778
 779 static struct intc_mask_reg ack_registers[] __initdata = {
 780         { 0xfe410024, 0, 32, /* INTREQ */
 781           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 782 };
 783
 784 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
 785                              vectors_irq0123, NULL, mask_registers,
 786                              prio_registers, sense_registers, ack_registers);
 787
 788 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
 789                              vectors_irq4567, NULL, mask_registers,
 790                              prio_registers, sense_registers, ack_registers);
 791
 792 /* External interrupt pins in IRL mode */
 793
 794 static struct intc_vect vectors_irl0123[] __initdata = {
 795         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 796         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 797         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 798         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 799         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 800         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 801         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 802         INTC_VECT(IRL0_HHHL, 0x3c0),
 803 };
 804
 805 static struct intc_vect vectors_irl4567[] __initdata = {
 806         INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
 807         INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
 808         INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
 809         INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
 810         INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
 811         INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
 812         INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
 813         INTC_VECT(IRL4_HHHL, 0xac0),
 814 };
 815
 816 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
 817                          NULL, mask_registers, NULL, NULL);
 818
 819 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
 820                          NULL, mask_registers, NULL, NULL);
 821
 822 #define INTC_ICR0       0xfe410000
 823 #define INTC_INTMSK0    CnINTMSK0
 824 #define INTC_INTMSK1    CnINTMSK1
 825 #define INTC_INTMSK2    INTMSK2
 826 #define INTC_INTMSKCLR1 CnINTMSKCLR1
 827 #define INTC_INTMSKCLR2 INTMSKCLR2
 828
 829 void __init plat_irq_setup(void)
 830 {
 831         /* disable IRQ3-0 + IRQ7-4 */
 832         ctrl_outl(0xff000000, INTC_INTMSK0);
 833
 834         /* disable IRL3-0 + IRL7-4 */
 835         ctrl_outl(0xc0000000, INTC_INTMSK1);
 836         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 837
 838         /* select IRL mode for IRL3-0 + IRL7-4 */
 839         ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 840
 841         register_intc_controller(&intc_desc);
 842 }
 843
 844 void __init plat_irq_setup_pins(int mode)
 845 {
 846         switch (mode) {
 847         case IRQ_MODE_IRQ7654:
 848                 /* select IRQ mode for IRL7-4 */
 849                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 850                 register_intc_controller(&intc_desc_irq4567);
 851                 break;
 852         case IRQ_MODE_IRQ3210:
 853                 /* select IRQ mode for IRL3-0 */
 854                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 855                 register_intc_controller(&intc_desc_irq0123);
 856                 break;
 857         case IRQ_MODE_IRL7654:
 858                 /* enable IRL7-4 but don't provide any masking */
 859                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 860                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 861                 break;
 862         case IRQ_MODE_IRL3210:
 863                 /* enable IRL0-3 but don't provide any masking */
 864                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 865                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 866                 break;
 867         case IRQ_MODE_IRL7654_MASK:
 868                 /* enable IRL7-4 and mask using cpu intc controller */
 869                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 870                 register_intc_controller(&intc_desc_irl4567);
 871                 break;
 872         case IRQ_MODE_IRL3210_MASK:
 873                 /* enable IRL0-3 and mask using cpu intc controller */
 874                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 875                 register_intc_controller(&intc_desc_irl0123);
 876                 break;
 877         default:
 878                 BUG();
 879         }
 880 }
 881
 882 void __init plat_mem_setup(void)
 883 {
 884 }