arch/sh/kernel/cpu/sh4a/setup-shx3.c

   1 /*
   2  * SH-X3 Prototype Setup
   3  *
   4  *  Copyright (C) 2007 - 2009  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/io.h>
  15 #include <linux/sh_timer.h>
  16 #include <asm/mmzone.h>
  17
  18 static struct plat_sci_port sci_platform_data[] = {
  19         {
  20                 .mapbase        = 0xffc30000,
  21                 .flags          = UPF_BOOT_AUTOCONF,
  22                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  23                 .scbrr_algo_id  = SCBRR_ALGO_2,
  24                 .type           = PORT_SCIF,
  25                 .irqs           = { 40, 41, 43, 42 },
  26         }, {
  27                 .mapbase        = 0xffc40000,
  28                 .flags          = UPF_BOOT_AUTOCONF,
  29                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  30                 .scbrr_algo_id  = SCBRR_ALGO_2,
  31                 .type           = PORT_SCIF,
  32                 .irqs           = { 44, 45, 47, 46 },
  33         }, {
  34                 .mapbase        = 0xffc50000,
  35                 .flags          = UPF_BOOT_AUTOCONF,
  36                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  37                 .scbrr_algo_id  = SCBRR_ALGO_2,
  38                 .type           = PORT_SCIF,
  39                 .irqs           = { 48, 49, 51, 50 },
  40         }, {
  41                 .mapbase        = 0xffc60000,
  42                 .flags          = UPF_BOOT_AUTOCONF,
  43                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  44                 .scbrr_algo_id  = SCBRR_ALGO_2,
  45                 .type           = PORT_SCIF,
  46                 .irqs           = { 52, 53, 55, 54 },
  47         }, {
  48                 .flags = 0,
  49         }
  50 };
  51
  52 static struct platform_device sci_device = {
  53         .name           = "sh-sci",
  54         .id             = -1,
  55         .dev            = {
  56                 .platform_data  = sci_platform_data,
  57         },
  58 };
  59
  60 static struct sh_timer_config tmu0_platform_data = {
  61         .name = "TMU0",
  62         .channel_offset = 0x04,
  63         .timer_bit = 0,
  64         .clk = "peripheral_clk",
  65         .clockevent_rating = 200,
  66 };
  67
  68 static struct resource tmu0_resources[] = {
  69         [0] = {
  70                 .name   = "TMU0",
  71                 .start  = 0xffc10008,
  72                 .end    = 0xffc10013,
  73                 .flags  = IORESOURCE_MEM,
  74         },
  75         [1] = {
  76                 .start  = 16,
  77                 .flags  = IORESOURCE_IRQ,
  78         },
  79 };
  80
  81 static struct platform_device tmu0_device = {
  82         .name           = "sh_tmu",
  83         .id             = 0,
  84         .dev = {
  85                 .platform_data  = &tmu0_platform_data,
  86         },
  87         .resource       = tmu0_resources,
  88         .num_resources  = ARRAY_SIZE(tmu0_resources),
  89 };
  90
  91 static struct sh_timer_config tmu1_platform_data = {
  92         .name = "TMU1",
  93         .channel_offset = 0x10,
  94         .timer_bit = 1,
  95         .clk = "peripheral_clk",
  96         .clocksource_rating = 200,
  97 };
  98
  99 static struct resource tmu1_resources[] = {
 100         [0] = {
 101                 .name   = "TMU1",
 102                 .start  = 0xffc10014,
 103                 .end    = 0xffc1001f,
 104                 .flags  = IORESOURCE_MEM,
 105         },
 106         [1] = {
 107                 .start  = 17,
 108                 .flags  = IORESOURCE_IRQ,
 109         },
 110 };
 111
 112 static struct platform_device tmu1_device = {
 113         .name           = "sh_tmu",
 114         .id             = 1,
 115         .dev = {
 116                 .platform_data  = &tmu1_platform_data,
 117         },
 118         .resource       = tmu1_resources,
 119         .num_resources  = ARRAY_SIZE(tmu1_resources),
 120 };
 121
 122 static struct sh_timer_config tmu2_platform_data = {
 123         .name = "TMU2",
 124         .channel_offset = 0x1c,
 125         .timer_bit = 2,
 126         .clk = "peripheral_clk",
 127 };
 128
 129 static struct resource tmu2_resources[] = {
 130         [0] = {
 131                 .name   = "TMU2",
 132                 .start  = 0xffc10020,
 133                 .end    = 0xffc1002f,
 134                 .flags  = IORESOURCE_MEM,
 135         },
 136         [1] = {
 137                 .start  = 18,
 138                 .flags  = IORESOURCE_IRQ,
 139         },
 140 };
 141
 142 static struct platform_device tmu2_device = {
 143         .name           = "sh_tmu",
 144         .id             = 2,
 145         .dev = {
 146                 .platform_data  = &tmu2_platform_data,
 147         },
 148         .resource       = tmu2_resources,
 149         .num_resources  = ARRAY_SIZE(tmu2_resources),
 150 };
 151
 152 static struct sh_timer_config tmu3_platform_data = {
 153         .name = "TMU3",
 154         .channel_offset = 0x04,
 155         .timer_bit = 0,
 156         .clk = "peripheral_clk",
 157 };
 158
 159 static struct resource tmu3_resources[] = {
 160         [0] = {
 161                 .name   = "TMU3",
 162                 .start  = 0xffc20008,
 163                 .end    = 0xffc20013,
 164                 .flags  = IORESOURCE_MEM,
 165         },
 166         [1] = {
 167                 .start  = 19,
 168                 .flags  = IORESOURCE_IRQ,
 169         },
 170 };
 171
 172 static struct platform_device tmu3_device = {
 173         .name           = "sh_tmu",
 174         .id             = 3,
 175         .dev = {
 176                 .platform_data  = &tmu3_platform_data,
 177         },
 178         .resource       = tmu3_resources,
 179         .num_resources  = ARRAY_SIZE(tmu3_resources),
 180 };
 181
 182 static struct sh_timer_config tmu4_platform_data = {
 183         .name = "TMU4",
 184         .channel_offset = 0x10,
 185         .timer_bit = 1,
 186         .clk = "peripheral_clk",
 187 };
 188
 189 static struct resource tmu4_resources[] = {
 190         [0] = {
 191                 .name   = "TMU4",
 192                 .start  = 0xffc20014,
 193                 .end    = 0xffc2001f,
 194                 .flags  = IORESOURCE_MEM,
 195         },
 196         [1] = {
 197                 .start  = 20,
 198                 .flags  = IORESOURCE_IRQ,
 199         },
 200 };
 201
 202 static struct platform_device tmu4_device = {
 203         .name           = "sh_tmu",
 204         .id             = 4,
 205         .dev = {
 206                 .platform_data  = &tmu4_platform_data,
 207         },
 208         .resource       = tmu4_resources,
 209         .num_resources  = ARRAY_SIZE(tmu4_resources),
 210 };
 211
 212 static struct sh_timer_config tmu5_platform_data = {
 213         .name = "TMU5",
 214         .channel_offset = 0x1c,
 215         .timer_bit = 2,
 216         .clk = "peripheral_clk",
 217 };
 218
 219 static struct resource tmu5_resources[] = {
 220         [0] = {
 221                 .name   = "TMU5",
 222                 .start  = 0xffc20020,
 223                 .end    = 0xffc2002b,
 224                 .flags  = IORESOURCE_MEM,
 225         },
 226         [1] = {
 227                 .start  = 21,
 228                 .flags  = IORESOURCE_IRQ,
 229         },
 230 };
 231
 232 static struct platform_device tmu5_device = {
 233         .name           = "sh_tmu",
 234         .id             = 5,
 235         .dev = {
 236                 .platform_data  = &tmu5_platform_data,
 237         },
 238         .resource       = tmu5_resources,
 239         .num_resources  = ARRAY_SIZE(tmu5_resources),
 240 };
 241
 242 static struct platform_device *shx3_early_devices[] __initdata = {
 243         &tmu0_device,
 244         &tmu1_device,
 245         &tmu2_device,
 246         &tmu3_device,
 247         &tmu4_device,
 248         &tmu5_device,
 249 };
 250
 251 static struct platform_device *shx3_devices[] __initdata = {
 252         &sci_device,
 253 };
 254
 255 static int __init shx3_devices_setup(void)
 256 {
 257         int ret;
 258
 259         ret = platform_add_devices(shx3_early_devices,
 260                                    ARRAY_SIZE(shx3_early_devices));
 261         if (unlikely(ret != 0))
 262                 return ret;
 263
 264         return platform_add_devices(shx3_devices,
 265                                     ARRAY_SIZE(shx3_devices));
 266 }
 267 __initcall(shx3_devices_setup);
 268
 269 void __init plat_early_device_setup(void)
 270 {
 271         early_platform_add_devices(shx3_early_devices,
 272                                    ARRAY_SIZE(shx3_early_devices));
 273 }
 274
 275 enum {
 276         UNUSED = 0,
 277
 278         /* interrupt sources */
 279         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 280         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 281         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 282         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 283         IRQ0, IRQ1, IRQ2, IRQ3,
 284         HUDII,
 285         TMU0, TMU1, TMU2, TMU3, TMU4, TMU5,
 286         PCII0, PCII1, PCII2, PCII3, PCII4,
 287         PCII5, PCII6, PCII7, PCII8, PCII9,
 288         SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
 289         SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
 290         SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
 291         SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI,
 292         DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
 293         DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
 294         DU,
 295         DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
 296         DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
 297         IIC, VIN0, VIN1, VCORE0, ATAPI,
 298         DTU0_TEND, DTU0_AE, DTU0_TMISS,
 299         DTU1_TEND, DTU1_AE, DTU1_TMISS,
 300         DTU2_TEND, DTU2_AE, DTU2_TMISS,
 301         DTU3_TEND, DTU3_AE, DTU3_TMISS,
 302         FE0, FE1,
 303         GPIO0, GPIO1, GPIO2, GPIO3,
 304         PAM, IRM,
 305         INTICI0, INTICI1, INTICI2, INTICI3,
 306         INTICI4, INTICI5, INTICI6, INTICI7,
 307
 308         /* interrupt groups */
 309         IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
 310         DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
 311 };
 312
 313 static struct intc_vect vectors[] __initdata = {
 314         INTC_VECT(HUDII, 0x3e0),
 315         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 316         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
 317         INTC_VECT(TMU4, 0x480), INTC_VECT(TMU5, 0x4a0),
 318         INTC_VECT(PCII0, 0x500), INTC_VECT(PCII1, 0x520),
 319         INTC_VECT(PCII2, 0x540), INTC_VECT(PCII3, 0x560),
 320         INTC_VECT(PCII4, 0x580), INTC_VECT(PCII5, 0x5a0),
 321         INTC_VECT(PCII6, 0x5c0), INTC_VECT(PCII7, 0x5e0),
 322         INTC_VECT(PCII8, 0x600), INTC_VECT(PCII9, 0x620),
 323         INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
 324         INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
 325         INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
 326         INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
 327         INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820),
 328         INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860),
 329         INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
 330         INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
 331         INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
 332         INTC_VECT(DMAC0_DMINT2, 0x940), INTC_VECT(DMAC0_DMINT3, 0x960),
 333         INTC_VECT(DMAC0_DMINT4, 0x980), INTC_VECT(DMAC0_DMINT5, 0x9a0),
 334         INTC_VECT(DMAC0_DMAE, 0x9c0),
 335         INTC_VECT(DU, 0x9e0),
 336         INTC_VECT(DMAC1_DMINT6, 0xa00), INTC_VECT(DMAC1_DMINT7, 0xa20),
 337         INTC_VECT(DMAC1_DMINT8, 0xa40), INTC_VECT(DMAC1_DMINT9, 0xa60),
 338         INTC_VECT(DMAC1_DMINT10, 0xa80), INTC_VECT(DMAC1_DMINT11, 0xaa0),
 339         INTC_VECT(DMAC1_DMAE, 0xac0),
 340         INTC_VECT(IIC, 0xae0),
 341         INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
 342         INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
 343         INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20),
 344         INTC_VECT(DTU0_TMISS, 0xc40),
 345         INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80),
 346         INTC_VECT(DTU1_TMISS, 0xca0),
 347         INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0),
 348         INTC_VECT(DTU2_TMISS, 0xd00),
 349         INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40),
 350         INTC_VECT(DTU3_TMISS, 0xd60),
 351         INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
 352         INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
 353         INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
 354         INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0),
 355         INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
 356         INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
 357         INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
 358         INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
 359 };
 360
 361 static struct intc_group groups[] __initdata = {
 362         INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 363                    IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 364                    IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 365                    IRL_HHLL, IRL_HHLH, IRL_HHHL),
 366         INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
 367         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
 368         INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
 369         INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
 370         INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
 371         INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
 372                    DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
 373         INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
 374                    DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
 375         INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
 376         INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
 377         INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS),
 378         INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
 379 };
 380
 381 static struct intc_mask_reg mask_registers[] __initdata = {
 382         { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
 383           { IRQ0, IRQ1, IRQ2, IRQ3 } },
 384         { 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
 385           { IRL } },
 386         { 0xfe410820, 0xfe410850, 32, /* CnINT2MSK0 / CnINT2MSKCLR0 */
 387           { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
 388             DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
 389             0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
 390             0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } },
 391         { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
 392           { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
 393             PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
 394             PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
 395             DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
 396             DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
 397             DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } },
 398         { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
 399           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 400             SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
 401             SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
 402             SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
 403             SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
 404 };
 405
 406 static struct intc_prio_reg prio_registers[] __initdata = {
 407         { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
 408
 409         { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
 410                                                  TMU3, TMU2, TMU1, TMU0 } },
 411         { 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
 412                                                  SCIF3, SCIF2,
 413                                                  SCIF1, SCIF0 } },
 414         { 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0,
 415                                                  PCII56789, PCII4,
 416                                                  PCII3, PCII2,
 417                                                  PCII1, PCII0 } },
 418         { 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
 419                                                  VIN1, VIN0, IIC, DU} },
 420         { 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
 421                                                  GPIO2, GPIO1, GPIO0, IRM } },
 422         { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
 423           { INTICI7, INTICI6, INTICI5, INTICI4,
 424             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 4) },
 425 };
 426
 427 static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups,
 428                          mask_registers, prio_registers, NULL);
 429
 430 /* Support for external interrupt pins in IRQ mode */
 431 static struct intc_vect vectors_irq[] __initdata = {
 432         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 433         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 434 };
 435
 436 static struct intc_sense_reg sense_registers[] __initdata = {
 437         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3 } },
 438 };
 439
 440 static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
 441                          mask_registers, prio_registers, sense_registers);
 442
 443 /* External interrupt pins in IRL mode */
 444 static struct intc_vect vectors_irl[] __initdata = {
 445         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 446         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 447         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 448         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 449         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 450         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 451         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 452         INTC_VECT(IRL_HHHL, 0x3c0),
 453 };
 454
 455 static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
 456                          mask_registers, prio_registers, NULL);
 457
 458 void __init plat_irq_setup_pins(int mode)
 459 {
 460         switch (mode) {
 461         case IRQ_MODE_IRQ:
 462                 register_intc_controller(&intc_desc_irq);
 463                 break;
 464         case IRQ_MODE_IRL3210:
 465                 register_intc_controller(&intc_desc_irl);
 466                 break;
 467         default:
 468                 BUG();
 469         }
 470 }
 471
 472 void __init plat_irq_setup(void)
 473 {
 474         register_intc_controller(&intc_desc);
 475 }
 476
 477 void __init plat_mem_setup(void)
 478 {
 479         unsigned int nid = 1;
 480
 481         /* Register CPU#0 URAM space as Node 1 */
 482         setup_bootmem_node(nid++, 0x145f0000, 0x14610000);      /* CPU0 */
 483
 484 #if 0
 485         /* XXX: Not yet.. */
 486         setup_bootmem_node(nid++, 0x14df0000, 0x14e10000);      /* CPU1 */
 487         setup_bootmem_node(nid++, 0x155f0000, 0x15610000);      /* CPU2 */
 488         setup_bootmem_node(nid++, 0x15df0000, 0x15e10000);      /* CPU3 */
 489 #endif
 490
 491         setup_bootmem_node(nid++, 0x16000000, 0x16020000);      /* CSM */
 492 }