2 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
3 * because MTRRs can span up to 40 bits (36bits on most modern x86)
7 #include <linux/module.h>
8 #include <linux/init.h>
12 #include <asm/processor-flags.h>
13 #include <asm/cpufeature.h>
14 #include <asm/tlbflush.h>
21 struct fixed_range_block {
22 int base_msr; /* start address of an MTRR block */
23 int ranges; /* number of MTRRs in this block */
26 static struct fixed_range_block fixed_range_blocks[] = {
27 { MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */
28 { MSR_MTRRfix16K_80000, 2 }, /* two 16k MTRRs */
29 { MSR_MTRRfix4K_C0000, 8 }, /* eight 4k MTRRs */
33 static unsigned long smp_changes_mask;
34 static int mtrr_state_set;
37 struct mtrr_state_type mtrr_state;
38 EXPORT_SYMBOL_GPL(mtrr_state);
41 * BIOS is expected to clear MtrrFixDramModEn bit, see for example
42 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
43 * Opteron Processors" (26094 Rev. 3.30 February 2006), section
44 * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set
45 * to 1 during BIOS initalization of the fixed MTRRs, then cleared to
48 static inline void k8_check_syscfg_dram_mod_en(void)
52 if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
53 (boot_cpu_data.x86 >= 0x0f)))
56 rdmsr(MSR_K8_SYSCFG, lo, hi);
57 if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
58 printk(KERN_ERR FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
59 " not cleared by BIOS, clearing this bit\n",
61 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
62 mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi);
66 /* Get the size of contiguous MTRR range */
67 static u64 get_mtrr_size(u64 mask)
79 * Check and return the effective type for MTRR-MTRR type overlap.
80 * Returns 1 if the effective type is UNCACHEABLE, else returns 0
82 static int check_type_overlap(u8 *prev, u8 *curr)
84 if (*prev == MTRR_TYPE_UNCACHABLE || *curr == MTRR_TYPE_UNCACHABLE) {
85 *prev = MTRR_TYPE_UNCACHABLE;
86 *curr = MTRR_TYPE_UNCACHABLE;
90 if ((*prev == MTRR_TYPE_WRBACK && *curr == MTRR_TYPE_WRTHROUGH) ||
91 (*prev == MTRR_TYPE_WRTHROUGH && *curr == MTRR_TYPE_WRBACK)) {
92 *prev = MTRR_TYPE_WRTHROUGH;
93 *curr = MTRR_TYPE_WRTHROUGH;
97 *prev = MTRR_TYPE_UNCACHABLE;
98 *curr = MTRR_TYPE_UNCACHABLE;
106 * Error/Semi-error returns:
107 * MTRR_TYPE_INVALID - when MTRR is not enabled
108 * *repeat == 1 implies [start:end] spanned across MTRR range and type returned
109 * corresponds only to [start:*partial_end].
110 * Caller has to lookup again for [*partial_end:end].
112 static u8 __mtrr_type_lookup(u64 start, u64 end, u64 *partial_end, int *repeat)
116 u8 prev_match, curr_match;
120 return MTRR_TYPE_INVALID;
122 if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED))
123 return MTRR_TYPE_INVALID;
125 /* Make end inclusive end, instead of exclusive */
128 /* Look in fixed ranges. Just return the type as per start */
129 if ((start < 0x100000) &&
130 (mtrr_state.have_fixed) &&
131 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) {
134 if (start < 0x80000) {
136 idx += (start >> 16);
137 return mtrr_state.fixed_ranges[idx];
138 } else if (start < 0xC0000) {
140 idx += ((start - 0x80000) >> 14);
141 return mtrr_state.fixed_ranges[idx];
144 idx += ((start - 0xC0000) >> 12);
145 return mtrr_state.fixed_ranges[idx];
150 * Look in variable ranges
151 * Look of multiple ranges matching this address and pick type
152 * as per MTRR precedence
154 prev_match = MTRR_TYPE_INVALID;
155 for (i = 0; i < num_var_ranges; ++i) {
156 unsigned short start_state, end_state, inclusive;
158 if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11)))
161 base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) +
162 (mtrr_state.var_ranges[i].base_lo & PAGE_MASK);
163 mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) +
164 (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK);
166 start_state = ((start & mask) == (base & mask));
167 end_state = ((end & mask) == (base & mask));
168 inclusive = ((start < base) && (end > base));
170 if ((start_state != end_state) || inclusive) {
172 * We have start:end spanning across an MTRR.
173 * We split the region into either
175 * (start:mtrr_end) (mtrr_end:end)
176 * - end_state:1 or inclusive:1
177 * (start:mtrr_start) (mtrr_start:end)
178 * depending on kind of overlap.
179 * Return the type for first region and a pointer to
180 * the start of second region so that caller will
181 * lookup again on the second region.
182 * Note: This way we handle multiple overlaps as well.
185 *partial_end = base + get_mtrr_size(mask);
189 if (unlikely(*partial_end <= start)) {
191 *partial_end = start + PAGE_SIZE;
194 end = *partial_end - 1; /* end is inclusive */
201 curr_match = mtrr_state.var_ranges[i].base_lo & 0xff;
202 if (prev_match == MTRR_TYPE_INVALID) {
203 prev_match = curr_match;
207 if (check_type_overlap(&prev_match, &curr_match))
212 if (start >= (1ULL<<32) && (end < mtrr_tom2))
213 return MTRR_TYPE_WRBACK;
216 if (prev_match != MTRR_TYPE_INVALID)
219 return mtrr_state.def_type;
223 * Returns the effective MTRR type for the region
225 * MTRR_TYPE_INVALID - when MTRR is not enabled
227 u8 mtrr_type_lookup(u64 start, u64 end)
233 type = __mtrr_type_lookup(start, end, &partial_end, &repeat);
236 * Common path is with repeat = 0.
237 * However, we can have cases where [start:end] spans across some
238 * MTRR range. Do repeated lookups for that case here.
243 type = __mtrr_type_lookup(start, end, &partial_end, &repeat);
245 if (check_type_overlap(&prev_type, &type))
252 /* Get the MSR pair relating to a var range */
254 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
256 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
257 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
260 /* Fill the MSR pair relating to a var range */
261 void fill_mtrr_var_range(unsigned int index,
262 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)
264 struct mtrr_var_range *vr;
266 vr = mtrr_state.var_ranges;
268 vr[index].base_lo = base_lo;
269 vr[index].base_hi = base_hi;
270 vr[index].mask_lo = mask_lo;
271 vr[index].mask_hi = mask_hi;
274 static void get_fixed_ranges(mtrr_type *frs)
276 unsigned int *p = (unsigned int *)frs;
279 k8_check_syscfg_dram_mod_en();
281 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]);
283 for (i = 0; i < 2; i++)
284 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
285 for (i = 0; i < 8; i++)
286 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
289 void mtrr_save_fixed_ranges(void *info)
292 get_fixed_ranges(mtrr_state.fixed_ranges);
295 static unsigned __initdata last_fixed_start;
296 static unsigned __initdata last_fixed_end;
297 static mtrr_type __initdata last_fixed_type;
299 static void __init print_fixed_last(void)
304 pr_debug(" %05X-%05X %s\n", last_fixed_start,
305 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
310 static void __init update_fixed_last(unsigned base, unsigned end,
313 last_fixed_start = base;
314 last_fixed_end = end;
315 last_fixed_type = type;
319 print_fixed(unsigned base, unsigned step, const mtrr_type *types)
323 for (i = 0; i < 8; ++i, ++types, base += step) {
324 if (last_fixed_end == 0) {
325 update_fixed_last(base, base + step, *types);
328 if (last_fixed_end == base && last_fixed_type == *types) {
329 last_fixed_end = base + step;
332 /* new segments: gap or different type */
334 update_fixed_last(base, base + step, *types);
338 static void prepare_set(void);
339 static void post_set(void);
341 static void __init print_mtrr_state(void)
346 pr_debug("MTRR default type: %s\n",
347 mtrr_attrib_to_str(mtrr_state.def_type));
348 if (mtrr_state.have_fixed) {
349 pr_debug("MTRR fixed ranges %sabled:\n",
350 ((mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) &&
351 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) ?
353 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0);
354 for (i = 0; i < 2; ++i)
355 print_fixed(0x80000 + i * 0x20000, 0x04000,
356 mtrr_state.fixed_ranges + (i + 1) * 8);
357 for (i = 0; i < 8; ++i)
358 print_fixed(0xC0000 + i * 0x08000, 0x01000,
359 mtrr_state.fixed_ranges + (i + 3) * 8);
364 pr_debug("MTRR variable ranges %sabled:\n",
365 mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis");
366 high_width = (__ffs64(size_or_mask) - (32 - PAGE_SHIFT) + 3) / 4;
368 for (i = 0; i < num_var_ranges; ++i) {
369 if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))
370 pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n",
373 mtrr_state.var_ranges[i].base_hi,
374 mtrr_state.var_ranges[i].base_lo >> 12,
376 mtrr_state.var_ranges[i].mask_hi,
377 mtrr_state.var_ranges[i].mask_lo >> 12,
378 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff));
380 pr_debug(" %u disabled\n", i);
383 pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
386 /* Grab all of the MTRR state for this CPU into *state */
387 void __init get_mtrr_state(void)
389 struct mtrr_var_range *vrs;
394 vrs = mtrr_state.var_ranges;
396 rdmsr(MSR_MTRRcap, lo, dummy);
397 mtrr_state.have_fixed = (lo >> 8) & 1;
399 for (i = 0; i < num_var_ranges; i++)
400 get_mtrr_var_range(i, &vrs[i]);
401 if (mtrr_state.have_fixed)
402 get_fixed_ranges(mtrr_state.fixed_ranges);
404 rdmsr(MSR_MTRRdefType, lo, dummy);
405 mtrr_state.def_type = (lo & 0xff);
406 mtrr_state.enabled = (lo & 0xc00) >> 10;
408 if (amd_special_default_mtrr()) {
412 rdmsr(MSR_K8_TOP_MEM2, low, high);
416 mtrr_tom2 &= 0xffffff800000ULL;
423 /* PAT setup for BP. We need to go through sync steps here */
424 local_irq_save(flags);
430 local_irq_restore(flags);
433 /* Some BIOS's are messed up and don't set all MTRRs the same! */
434 void __init mtrr_state_warn(void)
436 unsigned long mask = smp_changes_mask;
440 if (mask & MTRR_CHANGE_MASK_FIXED)
441 pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n");
442 if (mask & MTRR_CHANGE_MASK_VARIABLE)
443 pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n");
444 if (mask & MTRR_CHANGE_MASK_DEFTYPE)
445 pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n");
447 printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");
448 printk(KERN_INFO "mtrr: corrected configuration.\n");
452 * Doesn't attempt to pass an error out to MTRR users
453 * because it's quite complicated in some cases and probably not
454 * worth it because the best error handling is to ignore it.
456 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
458 if (wrmsr_safe(msr, a, b) < 0) {
460 "MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
461 smp_processor_id(), msr, a, b);
466 * set_fixed_range - checks & updates a fixed-range MTRR if it
467 * differs from the value it should have
468 * @msr: MSR address of the MTTR which should be checked and updated
469 * @changed: pointer which indicates whether the MTRR needed to be changed
470 * @msrwords: pointer to the MSR values which the MSR should have
472 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
478 if (lo != msrwords[0] || hi != msrwords[1]) {
479 mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
485 * generic_get_free_region - Get a free MTRR.
486 * @base: The starting (base) address of the region.
487 * @size: The size (in bytes) of the region.
488 * @replace_reg: mtrr index to be replaced; set to invalid value if none.
490 * Returns: The index of the region on success, else negative on error.
493 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
495 unsigned long lbase, lsize;
499 max = num_var_ranges;
500 if (replace_reg >= 0 && replace_reg < max)
503 for (i = 0; i < max; ++i) {
504 mtrr_if->get(i, &lbase, &lsize, <ype);
512 static void generic_get_mtrr(unsigned int reg, unsigned long *base,
513 unsigned long *size, mtrr_type *type)
515 u32 mask_lo, mask_hi, base_lo, base_hi;
520 * get_mtrr doesn't need to update mtrr_state, also it could be called
521 * from any cpu, so try to print it out directly.
525 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
527 if ((mask_lo & 0x800) == 0) {
528 /* Invalid (i.e. free) range */
535 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
537 /* Work out the shifted address mask: */
538 tmp = (u64)mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
539 mask = size_or_mask | tmp;
541 /* Expand tmp with high bits to all 1s: */
544 tmp |= ~((1ULL<<(hi - 1)) - 1);
547 printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n");
548 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
554 * This works correctly if size is a power of two, i.e. a
558 *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
559 *type = base_lo & 0xff;
566 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they
567 * differ from the saved set
568 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
570 static int set_fixed_ranges(mtrr_type *frs)
572 unsigned long long *saved = (unsigned long long *)frs;
573 bool changed = false;
574 int block = -1, range;
576 k8_check_syscfg_dram_mod_en();
578 while (fixed_range_blocks[++block].ranges) {
579 for (range = 0; range < fixed_range_blocks[block].ranges; range++)
580 set_fixed_range(fixed_range_blocks[block].base_msr + range,
581 &changed, (unsigned int *)saved++);
588 * Set the MSR pair relating to a var range.
589 * Returns true if changes are made.
591 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
594 bool changed = false;
596 rdmsr(MTRRphysBase_MSR(index), lo, hi);
597 if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
598 || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
599 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
601 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
605 rdmsr(MTRRphysMask_MSR(index), lo, hi);
607 if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL)
608 || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
609 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
610 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
616 static u32 deftype_lo, deftype_hi;
619 * set_mtrr_state - Set the MTRR state for this CPU.
621 * NOTE: The CPU must already be in a safe state for MTRR changes.
622 * RETURNS: 0 if no changes made, else a mask indicating what was changed.
624 static unsigned long set_mtrr_state(void)
626 unsigned long change_mask = 0;
629 for (i = 0; i < num_var_ranges; i++) {
630 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
631 change_mask |= MTRR_CHANGE_MASK_VARIABLE;
634 if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
635 change_mask |= MTRR_CHANGE_MASK_FIXED;
638 * Set_mtrr_restore restores the old value of MTRRdefType,
639 * so to set it we fiddle with the saved value:
641 if ((deftype_lo & 0xff) != mtrr_state.def_type
642 || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
644 deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type |
645 (mtrr_state.enabled << 10);
646 change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
653 static unsigned long cr4;
654 static DEFINE_RAW_SPINLOCK(set_atomicity_lock);
657 * Since we are disabling the cache don't allow any interrupts,
658 * they would run extremely slow and would only increase the pain.
660 * The caller must ensure that local interrupts are disabled and
661 * are reenabled after post_set() has been called.
663 static void prepare_set(void) __acquires(set_atomicity_lock)
668 * Note that this is not ideal
669 * since the cache is only flushed/disabled for this CPU while the
670 * MTRRs are changed, but changing this requires more invasive
671 * changes to the way the kernel boots
674 raw_spin_lock(&set_atomicity_lock);
676 /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
677 cr0 = read_cr0() | X86_CR0_CD;
681 /* Save value of CR4 and clear Page Global Enable (bit 7) */
684 __write_cr4(cr4 & ~X86_CR4_PGE);
687 /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
688 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
691 /* Save MTRR state */
692 rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
694 /* Disable MTRRs, and set the default type to uncached */
695 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
699 static void post_set(void) __releases(set_atomicity_lock)
701 /* Flush TLBs (no need to flush caches - they are disabled) */
702 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
705 /* Intel (P6) standard MTRRs */
706 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
709 write_cr0(read_cr0() & ~X86_CR0_CD);
711 /* Restore value of CR4 */
714 raw_spin_unlock(&set_atomicity_lock);
717 static void generic_set_all(void)
719 unsigned long mask, count;
722 local_irq_save(flags);
725 /* Actually set the state */
726 mask = set_mtrr_state();
732 local_irq_restore(flags);
734 /* Use the atomic bitops to update the global mask */
735 for (count = 0; count < sizeof mask * 8; ++count) {
737 set_bit(count, &smp_changes_mask);
744 * generic_set_mtrr - set variable MTRR register on the local CPU.
746 * @reg: The register to set.
747 * @base: The base address of the region.
748 * @size: The size of the region. If this is 0 the region is disabled.
749 * @type: The type of the region.
753 static void generic_set_mtrr(unsigned int reg, unsigned long base,
754 unsigned long size, mtrr_type type)
757 struct mtrr_var_range *vr;
759 vr = &mtrr_state.var_ranges[reg];
761 local_irq_save(flags);
766 * The invalid bit is kept in the mask, so we simply
767 * clear the relevant mask register to disable a range.
769 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);
770 memset(vr, 0, sizeof(struct mtrr_var_range));
772 vr->base_lo = base << PAGE_SHIFT | type;
773 vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
774 vr->mask_lo = -size << PAGE_SHIFT | 0x800;
775 vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
777 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi);
778 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi);
782 local_irq_restore(flags);
785 int generic_validate_add_page(unsigned long base, unsigned long size,
788 unsigned long lbase, last;
791 * For Intel PPro stepping <= 7
792 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF
794 if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
795 boot_cpu_data.x86_model == 1 &&
796 boot_cpu_data.x86_mask <= 7) {
797 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
798 pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
801 if (!(base + size < 0x70000 || base > 0x7003F) &&
802 (type == MTRR_TYPE_WRCOMB
803 || type == MTRR_TYPE_WRBACK)) {
804 pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
810 * Check upper bits of base and last are equal and lower bits are 0
811 * for base and 1 for last
813 last = base + size - 1;
814 for (lbase = base; !(lbase & 1) && (last & 1);
815 lbase = lbase >> 1, last = last >> 1)
818 pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size);
824 static int generic_have_wrcomb(void)
826 unsigned long config, dummy;
827 rdmsr(MSR_MTRRcap, config, dummy);
828 return config & (1 << 10);
831 int positive_have_wrcomb(void)
837 * Generic structure...
839 const struct mtrr_ops generic_mtrr_ops = {
841 .set_all = generic_set_all,
842 .get = generic_get_mtrr,
843 .get_free_region = generic_get_free_region,
844 .set = generic_set_mtrr,
845 .validate_add_page = generic_validate_add_page,
846 .have_wrcomb = generic_have_wrcomb,