arch/x86/kernel/cpu/perf_event_intel_ds.c

   1 #include <linux/bitops.h>
   2 #include <linux/types.h>
   3 #include <linux/slab.h>
   4
   5 #include <asm/perf_event.h>
   6 #include <asm/insn.h>
   7
   8 #include "perf_event.h"
   9
  10 /* The size of a BTS record in bytes: */
  11 #define BTS_RECORD_SIZE         24
  12
  13 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
  14 #define PEBS_BUFFER_SIZE        PAGE_SIZE
  15
  16 /*
  17  * pebs_record_32 for p4 and core not supported
  18
  19 struct pebs_record_32 {
  20         u32 flags, ip;
  21         u32 ax, bc, cx, dx;
  22         u32 si, di, bp, sp;
  23 };
  24
  25  */
  26
  27 union intel_x86_pebs_dse {
  28         u64 val;
  29         struct {
  30                 unsigned int ld_dse:4;
  31                 unsigned int ld_stlb_miss:1;
  32                 unsigned int ld_locked:1;
  33                 unsigned int ld_reserved:26;
  34         };
  35         struct {
  36                 unsigned int st_l1d_hit:1;
  37                 unsigned int st_reserved1:3;
  38                 unsigned int st_stlb_miss:1;
  39                 unsigned int st_locked:1;
  40                 unsigned int st_reserved2:26;
  41         };
  42 };
  43
  44
  45 /*
  46  * Map PEBS Load Latency Data Source encodings to generic
  47  * memory data source information
  48  */
  49 #define P(a, b) PERF_MEM_S(a, b)
  50 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  51 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  52
  53 static const u64 pebs_data_source[] = {
  54         P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  55         OP_LH | P(LVL, L1)  | P(SNOOP, NONE),   /* 0x01: L1 local */
  56         OP_LH | P(LVL, LFB) | P(SNOOP, NONE),   /* 0x02: LFB hit */
  57         OP_LH | P(LVL, L2)  | P(SNOOP, NONE),   /* 0x03: L2 hit */
  58         OP_LH | P(LVL, L3)  | P(SNOOP, NONE),   /* 0x04: L3 hit */
  59         OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
  60         OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
  61         OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x07: L3 hit, snoop hitm */
  62         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
  63         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  64         OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
  65         OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
  66         OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
  67         OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
  68         OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
  69         OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
  70 };
  71
  72 static u64 precise_store_data(u64 status)
  73 {
  74         union intel_x86_pebs_dse dse;
  75         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
  76
  77         dse.val = status;
  78
  79         /*
  80          * bit 4: TLB access
  81          * 1 = stored missed 2nd level TLB
  82          *
  83          * so it either hit the walker or the OS
  84          * otherwise hit 2nd level TLB
  85          */
  86         if (dse.st_stlb_miss)
  87                 val |= P(TLB, MISS);
  88         else
  89                 val |= P(TLB, HIT);
  90
  91         /*
  92          * bit 0: hit L1 data cache
  93          * if not set, then all we know is that
  94          * it missed L1D
  95          */
  96         if (dse.st_l1d_hit)
  97                 val |= P(LVL, HIT);
  98         else
  99                 val |= P(LVL, MISS);
 100
 101         /*
 102          * bit 5: Locked prefix
 103          */
 104         if (dse.st_locked)
 105                 val |= P(LOCK, LOCKED);
 106
 107         return val;
 108 }
 109
 110 static u64 precise_store_data_hsw(u64 status)
 111 {
 112         union perf_mem_data_src dse;
 113
 114         dse.val = 0;
 115         dse.mem_op = PERF_MEM_OP_STORE;
 116         dse.mem_lvl = PERF_MEM_LVL_NA;
 117         if (status & 1)
 118                 dse.mem_lvl = PERF_MEM_LVL_L1;
 119         /* Nothing else supported. Sorry. */
 120         return dse.val;
 121 }
 122
 123 static u64 load_latency_data(u64 status)
 124 {
 125         union intel_x86_pebs_dse dse;
 126         u64 val;
 127         int model = boot_cpu_data.x86_model;
 128         int fam = boot_cpu_data.x86;
 129
 130         dse.val = status;
 131
 132         /*
 133          * use the mapping table for bit 0-3
 134          */
 135         val = pebs_data_source[dse.ld_dse];
 136
 137         /*
 138          * Nehalem models do not support TLB, Lock infos
 139          */
 140         if (fam == 0x6 && (model == 26 || model == 30
 141             || model == 31 || model == 46)) {
 142                 val |= P(TLB, NA) | P(LOCK, NA);
 143                 return val;
 144         }
 145         /*
 146          * bit 4: TLB access
 147          * 0 = did not miss 2nd level TLB
 148          * 1 = missed 2nd level TLB
 149          */
 150         if (dse.ld_stlb_miss)
 151                 val |= P(TLB, MISS) | P(TLB, L2);
 152         else
 153                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 154
 155         /*
 156          * bit 5: locked prefix
 157          */
 158         if (dse.ld_locked)
 159                 val |= P(LOCK, LOCKED);
 160
 161         return val;
 162 }
 163
 164 struct pebs_record_core {
 165         u64 flags, ip;
 166         u64 ax, bx, cx, dx;
 167         u64 si, di, bp, sp;
 168         u64 r8,  r9,  r10, r11;
 169         u64 r12, r13, r14, r15;
 170 };
 171
 172 struct pebs_record_nhm {
 173         u64 flags, ip;
 174         u64 ax, bx, cx, dx;
 175         u64 si, di, bp, sp;
 176         u64 r8,  r9,  r10, r11;
 177         u64 r12, r13, r14, r15;
 178         u64 status, dla, dse, lat;
 179 };
 180
 181 /*
 182  * Same as pebs_record_nhm, with two additional fields.
 183  */
 184 struct pebs_record_hsw {
 185         u64 flags, ip;
 186         u64 ax, bx, cx, dx;
 187         u64 si, di, bp, sp;
 188         u64 r8,  r9,  r10, r11;
 189         u64 r12, r13, r14, r15;
 190         u64 status, dla, dse, lat;
 191         u64 real_ip, tsx_tuning;
 192 };
 193
 194 union hsw_tsx_tuning {
 195         struct {
 196                 u32 cycles_last_block     : 32,
 197                     hle_abort             : 1,
 198                     rtm_abort             : 1,
 199                     instruction_abort     : 1,
 200                     non_instruction_abort : 1,
 201                     retry                 : 1,
 202                     data_conflict         : 1,
 203                     capacity_writes       : 1,
 204                     capacity_reads        : 1;
 205         };
 206         u64         value;
 207 };
 208
 209 void init_debug_store_on_cpu(int cpu)
 210 {
 211         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 212
 213         if (!ds)
 214                 return;
 215
 216         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 217                      (u32)((u64)(unsigned long)ds),
 218                      (u32)((u64)(unsigned long)ds >> 32));
 219 }
 220
 221 void fini_debug_store_on_cpu(int cpu)
 222 {
 223         if (!per_cpu(cpu_hw_events, cpu).ds)
 224                 return;
 225
 226         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 227 }
 228
 229 static int alloc_pebs_buffer(int cpu)
 230 {
 231         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 232         int node = cpu_to_node(cpu);
 233         int max, thresh = 1; /* always use a single PEBS record */
 234         void *buffer;
 235
 236         if (!x86_pmu.pebs)
 237                 return 0;
 238
 239         buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
 240         if (unlikely(!buffer))
 241                 return -ENOMEM;
 242
 243         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
 244
 245         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
 246         ds->pebs_index = ds->pebs_buffer_base;
 247         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
 248                 max * x86_pmu.pebs_record_size;
 249
 250         ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
 251                 thresh * x86_pmu.pebs_record_size;
 252
 253         return 0;
 254 }
 255
 256 static void release_pebs_buffer(int cpu)
 257 {
 258         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 259
 260         if (!ds || !x86_pmu.pebs)
 261                 return;
 262
 263         kfree((void *)(unsigned long)ds->pebs_buffer_base);
 264         ds->pebs_buffer_base = 0;
 265 }
 266
 267 static int alloc_bts_buffer(int cpu)
 268 {
 269         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 270         int node = cpu_to_node(cpu);
 271         int max, thresh;
 272         void *buffer;
 273
 274         if (!x86_pmu.bts)
 275                 return 0;
 276
 277         buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL, node);
 278         if (unlikely(!buffer))
 279                 return -ENOMEM;
 280
 281         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 282         thresh = max / 16;
 283
 284         ds->bts_buffer_base = (u64)(unsigned long)buffer;
 285         ds->bts_index = ds->bts_buffer_base;
 286         ds->bts_absolute_maximum = ds->bts_buffer_base +
 287                 max * BTS_RECORD_SIZE;
 288         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 289                 thresh * BTS_RECORD_SIZE;
 290
 291         return 0;
 292 }
 293
 294 static void release_bts_buffer(int cpu)
 295 {
 296         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 297
 298         if (!ds || !x86_pmu.bts)
 299                 return;
 300
 301         kfree((void *)(unsigned long)ds->bts_buffer_base);
 302         ds->bts_buffer_base = 0;
 303 }
 304
 305 static int alloc_ds_buffer(int cpu)
 306 {
 307         int node = cpu_to_node(cpu);
 308         struct debug_store *ds;
 309
 310         ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
 311         if (unlikely(!ds))
 312                 return -ENOMEM;
 313
 314         per_cpu(cpu_hw_events, cpu).ds = ds;
 315
 316         return 0;
 317 }
 318
 319 static void release_ds_buffer(int cpu)
 320 {
 321         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 322
 323         if (!ds)
 324                 return;
 325
 326         per_cpu(cpu_hw_events, cpu).ds = NULL;
 327         kfree(ds);
 328 }
 329
 330 void release_ds_buffers(void)
 331 {
 332         int cpu;
 333
 334         if (!x86_pmu.bts && !x86_pmu.pebs)
 335                 return;
 336
 337         get_online_cpus();
 338         for_each_online_cpu(cpu)
 339                 fini_debug_store_on_cpu(cpu);
 340
 341         for_each_possible_cpu(cpu) {
 342                 release_pebs_buffer(cpu);
 343                 release_bts_buffer(cpu);
 344                 release_ds_buffer(cpu);
 345         }
 346         put_online_cpus();
 347 }
 348
 349 void reserve_ds_buffers(void)
 350 {
 351         int bts_err = 0, pebs_err = 0;
 352         int cpu;
 353
 354         x86_pmu.bts_active = 0;
 355         x86_pmu.pebs_active = 0;
 356
 357         if (!x86_pmu.bts && !x86_pmu.pebs)
 358                 return;
 359
 360         if (!x86_pmu.bts)
 361                 bts_err = 1;
 362
 363         if (!x86_pmu.pebs)
 364                 pebs_err = 1;
 365
 366         get_online_cpus();
 367
 368         for_each_possible_cpu(cpu) {
 369                 if (alloc_ds_buffer(cpu)) {
 370                         bts_err = 1;
 371                         pebs_err = 1;
 372                 }
 373
 374                 if (!bts_err && alloc_bts_buffer(cpu))
 375                         bts_err = 1;
 376
 377                 if (!pebs_err && alloc_pebs_buffer(cpu))
 378                         pebs_err = 1;
 379
 380                 if (bts_err && pebs_err)
 381                         break;
 382         }
 383
 384         if (bts_err) {
 385                 for_each_possible_cpu(cpu)
 386                         release_bts_buffer(cpu);
 387         }
 388
 389         if (pebs_err) {
 390                 for_each_possible_cpu(cpu)
 391                         release_pebs_buffer(cpu);
 392         }
 393
 394         if (bts_err && pebs_err) {
 395                 for_each_possible_cpu(cpu)
 396                         release_ds_buffer(cpu);
 397         } else {
 398                 if (x86_pmu.bts && !bts_err)
 399                         x86_pmu.bts_active = 1;
 400
 401                 if (x86_pmu.pebs && !pebs_err)
 402                         x86_pmu.pebs_active = 1;
 403
 404                 for_each_online_cpu(cpu)
 405                         init_debug_store_on_cpu(cpu);
 406         }
 407
 408         put_online_cpus();
 409 }
 410
 411 /*
 412  * BTS
 413  */
 414
 415 struct event_constraint bts_constraint =
 416         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 417
 418 void intel_pmu_enable_bts(u64 config)
 419 {
 420         unsigned long debugctlmsr;
 421
 422         debugctlmsr = get_debugctlmsr();
 423
 424         debugctlmsr |= DEBUGCTLMSR_TR;
 425         debugctlmsr |= DEBUGCTLMSR_BTS;
 426         debugctlmsr |= DEBUGCTLMSR_BTINT;
 427
 428         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 429                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 430
 431         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 432                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 433
 434         update_debugctlmsr(debugctlmsr);
 435 }
 436
 437 void intel_pmu_disable_bts(void)
 438 {
 439         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 440         unsigned long debugctlmsr;
 441
 442         if (!cpuc->ds)
 443                 return;
 444
 445         debugctlmsr = get_debugctlmsr();
 446
 447         debugctlmsr &=
 448                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 449                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 450
 451         update_debugctlmsr(debugctlmsr);
 452 }
 453
 454 int intel_pmu_drain_bts_buffer(void)
 455 {
 456         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 457         struct debug_store *ds = cpuc->ds;
 458         struct bts_record {
 459                 u64     from;
 460                 u64     to;
 461                 u64     flags;
 462         };
 463         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 464         struct bts_record *at, *top;
 465         struct perf_output_handle handle;
 466         struct perf_event_header header;
 467         struct perf_sample_data data;
 468         struct pt_regs regs;
 469
 470         if (!event)
 471                 return 0;
 472
 473         if (!x86_pmu.bts_active)
 474                 return 0;
 475
 476         at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 477         top = (struct bts_record *)(unsigned long)ds->bts_index;
 478
 479         if (top <= at)
 480                 return 0;
 481
 482         memset(&regs, 0, sizeof(regs));
 483
 484         ds->bts_index = ds->bts_buffer_base;
 485
 486         perf_sample_data_init(&data, 0, event->hw.last_period);
 487
 488         /*
 489          * Prepare a generic sample, i.e. fill in the invariant fields.
 490          * We will overwrite the from and to address before we output
 491          * the sample.
 492          */
 493         perf_prepare_sample(&header, &data, event, &regs);
 494
 495         if (perf_output_begin(&handle, event, header.size * (top - at)))
 496                 return 1;
 497
 498         for (; at < top; at++) {
 499                 data.ip         = at->from;
 500                 data.addr       = at->to;
 501
 502                 perf_output_sample(&handle, &header, &data, event);
 503         }
 504
 505         perf_output_end(&handle);
 506
 507         /* There's new data available. */
 508         event->hw.interrupts++;
 509         event->pending_kill = POLL_IN;
 510         return 1;
 511 }
 512
 513 /*
 514  * PEBS
 515  */
 516 struct event_constraint intel_core2_pebs_event_constraints[] = {
 517         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 518         INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 519         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 520         INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 521         INTEL_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 522         EVENT_CONSTRAINT_END
 523 };
 524
 525 struct event_constraint intel_atom_pebs_event_constraints[] = {
 526         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 527         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
 528         INTEL_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 529         EVENT_CONSTRAINT_END
 530 };
 531
 532 struct event_constraint intel_slm_pebs_event_constraints[] = {
 533         INTEL_UEVENT_CONSTRAINT(0x0103, 0x1), /* REHABQ.LD_BLOCK_ST_FORWARD_PS */
 534         INTEL_UEVENT_CONSTRAINT(0x0803, 0x1), /* REHABQ.LD_SPLITS_PS */
 535         INTEL_UEVENT_CONSTRAINT(0x0204, 0x1), /* MEM_UOPS_RETIRED.L2_HIT_LOADS_PS */
 536         INTEL_UEVENT_CONSTRAINT(0x0404, 0x1), /* MEM_UOPS_RETIRED.L2_MISS_LOADS_PS */
 537         INTEL_UEVENT_CONSTRAINT(0x0804, 0x1), /* MEM_UOPS_RETIRED.DTLB_MISS_LOADS_PS */
 538         INTEL_UEVENT_CONSTRAINT(0x2004, 0x1), /* MEM_UOPS_RETIRED.HITM_PS */
 539         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY_PS */
 540         INTEL_UEVENT_CONSTRAINT(0x00c4, 0x1), /* BR_INST_RETIRED.ALL_BRANCHES_PS */
 541         INTEL_UEVENT_CONSTRAINT(0x7ec4, 0x1), /* BR_INST_RETIRED.JCC_PS */
 542         INTEL_UEVENT_CONSTRAINT(0xbfc4, 0x1), /* BR_INST_RETIRED.FAR_BRANCH_PS */
 543         INTEL_UEVENT_CONSTRAINT(0xebc4, 0x1), /* BR_INST_RETIRED.NON_RETURN_IND_PS */
 544         INTEL_UEVENT_CONSTRAINT(0xf7c4, 0x1), /* BR_INST_RETIRED.RETURN_PS */
 545         INTEL_UEVENT_CONSTRAINT(0xf9c4, 0x1), /* BR_INST_RETIRED.CALL_PS */
 546         INTEL_UEVENT_CONSTRAINT(0xfbc4, 0x1), /* BR_INST_RETIRED.IND_CALL_PS */
 547         INTEL_UEVENT_CONSTRAINT(0xfdc4, 0x1), /* BR_INST_RETIRED.REL_CALL_PS */
 548         INTEL_UEVENT_CONSTRAINT(0xfec4, 0x1), /* BR_INST_RETIRED.TAKEN_JCC_PS */
 549         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_MISP_RETIRED.ALL_BRANCHES_PS */
 550         INTEL_UEVENT_CONSTRAINT(0x7ec5, 0x1), /* BR_INST_MISP_RETIRED.JCC_PS */
 551         INTEL_UEVENT_CONSTRAINT(0xebc5, 0x1), /* BR_INST_MISP_RETIRED.NON_RETURN_IND_PS */
 552         INTEL_UEVENT_CONSTRAINT(0xf7c5, 0x1), /* BR_INST_MISP_RETIRED.RETURN_PS */
 553         INTEL_UEVENT_CONSTRAINT(0xfbc5, 0x1), /* BR_INST_MISP_RETIRED.IND_CALL_PS */
 554         INTEL_UEVENT_CONSTRAINT(0xfec5, 0x1), /* BR_INST_MISP_RETIRED.TAKEN_JCC_PS */
 555         EVENT_CONSTRAINT_END
 556 };
 557
 558 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 559         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 560         INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 561         INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 562         INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
 563         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 564         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 565         INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
 566         INTEL_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 567         INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 568         INTEL_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 569         INTEL_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 570         EVENT_CONSTRAINT_END
 571 };
 572
 573 struct event_constraint intel_westmere_pebs_event_constraints[] = {
 574         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 575         INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 576         INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 577         INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
 578         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 579         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 580         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 581         INTEL_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 582         INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 583         INTEL_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 584         INTEL_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 585         EVENT_CONSTRAINT_END
 586 };
 587
 588 struct event_constraint intel_snb_pebs_event_constraints[] = {
 589         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 590         INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 591         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
 592         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 593         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 594         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 595         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 596         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 597         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 598         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 599         INTEL_EVENT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 600         INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
 601         EVENT_CONSTRAINT_END
 602 };
 603
 604 struct event_constraint intel_ivb_pebs_event_constraints[] = {
 605         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 606         INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 607         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
 608         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 609         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 610         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 611         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 612         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 613         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 614         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 615         INTEL_EVENT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 616         EVENT_CONSTRAINT_END
 617 };
 618
 619 struct event_constraint intel_hsw_pebs_event_constraints[] = {
 620         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 621         INTEL_PST_HSW_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 622         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
 623         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 624         INTEL_UEVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
 625         INTEL_UEVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
 626         INTEL_UEVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
 627         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.* */
 628         /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 629         INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf),
 630         /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 631         INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf),
 632         INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 633         INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 634         /* MEM_UOPS_RETIRED.SPLIT_STORES */
 635         INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf),
 636         INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 637         INTEL_PST_HSW_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 638         INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
 639         INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
 640         INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
 641         /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
 642         INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf),
 643         /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
 644         INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf),
 645         /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
 646         INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf),
 647         /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
 648         INTEL_UEVENT_CONSTRAINT(0x01d3, 0xf),
 649         INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
 650         INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */
 651
 652         EVENT_CONSTRAINT_END
 653 };
 654
 655 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 656 {
 657         struct event_constraint *c;
 658
 659         if (!event->attr.precise_ip)
 660                 return NULL;
 661
 662         if (x86_pmu.pebs_constraints) {
 663                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 664                         if ((event->hw.config & c->cmask) == c->code) {
 665                                 event->hw.flags |= c->flags;
 666                                 return c;
 667                         }
 668                 }
 669         }
 670
 671         return &emptyconstraint;
 672 }
 673
 674 void intel_pmu_pebs_enable(struct perf_event *event)
 675 {
 676         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 677         struct hw_perf_event *hwc = &event->hw;
 678
 679         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 680
 681         cpuc->pebs_enabled |= 1ULL << hwc->idx;
 682
 683         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
 684                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
 685         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
 686                 cpuc->pebs_enabled |= 1ULL << 63;
 687 }
 688
 689 void intel_pmu_pebs_disable(struct perf_event *event)
 690 {
 691         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 692         struct hw_perf_event *hwc = &event->hw;
 693
 694         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
 695
 696         if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
 697                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
 698         else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
 699                 cpuc->pebs_enabled &= ~(1ULL << 63);
 700
 701         if (cpuc->enabled)
 702                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 703
 704         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
 705 }
 706
 707 void intel_pmu_pebs_enable_all(void)
 708 {
 709         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 710
 711         if (cpuc->pebs_enabled)
 712                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 713 }
 714
 715 void intel_pmu_pebs_disable_all(void)
 716 {
 717         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 718
 719         if (cpuc->pebs_enabled)
 720                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 721 }
 722
 723 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 724 {
 725         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 726         unsigned long from = cpuc->lbr_entries[0].from;
 727         unsigned long old_to, to = cpuc->lbr_entries[0].to;
 728         unsigned long ip = regs->ip;
 729         int is_64bit = 0;
 730
 731         /*
 732          * We don't need to fixup if the PEBS assist is fault like
 733          */
 734         if (!x86_pmu.intel_cap.pebs_trap)
 735                 return 1;
 736
 737         /*
 738          * No LBR entry, no basic block, no rewinding
 739          */
 740         if (!cpuc->lbr_stack.nr || !from || !to)
 741                 return 0;
 742
 743         /*
 744          * Basic blocks should never cross user/kernel boundaries
 745          */
 746         if (kernel_ip(ip) != kernel_ip(to))
 747                 return 0;
 748
 749         /*
 750          * unsigned math, either ip is before the start (impossible) or
 751          * the basic block is larger than 1 page (sanity)
 752          */
 753         if ((ip - to) > PAGE_SIZE)
 754                 return 0;
 755
 756         /*
 757          * We sampled a branch insn, rewind using the LBR stack
 758          */
 759         if (ip == to) {
 760                 set_linear_ip(regs, from);
 761                 return 1;
 762         }
 763
 764         do {
 765                 struct insn insn;
 766                 u8 buf[MAX_INSN_SIZE];
 767                 void *kaddr;
 768
 769                 old_to = to;
 770                 if (!kernel_ip(ip)) {
 771                         int bytes, size = MAX_INSN_SIZE;
 772
 773                         bytes = copy_from_user_nmi(buf, (void __user *)to, size);
 774                         if (bytes != size)
 775                                 return 0;
 776
 777                         kaddr = buf;
 778                 } else
 779                         kaddr = (void *)to;
 780
 781 #ifdef CONFIG_X86_64
 782                 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
 783 #endif
 784                 insn_init(&insn, kaddr, is_64bit);
 785                 insn_get_length(&insn);
 786                 to += insn.length;
 787         } while (to < ip);
 788
 789         if (to == ip) {
 790                 set_linear_ip(regs, old_to);
 791                 return 1;
 792         }
 793
 794         /*
 795          * Even though we decoded the basic block, the instruction stream
 796          * never matched the given IP, either the TO or the IP got corrupted.
 797          */
 798         return 0;
 799 }
 800
 801 static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
 802 {
 803         if (pebs->tsx_tuning) {
 804                 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
 805                 return tsx.cycles_last_block;
 806         }
 807         return 0;
 808 }
 809
 810 static void __intel_pmu_pebs_event(struct perf_event *event,
 811                                    struct pt_regs *iregs, void *__pebs)
 812 {
 813         /*
 814          * We cast to the biggest pebs_record but are careful not to
 815          * unconditionally access the 'extra' entries.
 816          */
 817         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 818         struct pebs_record_hsw *pebs = __pebs;
 819         struct perf_sample_data data;
 820         struct pt_regs regs;
 821         u64 sample_type;
 822         int fll, fst;
 823
 824         if (!intel_pmu_save_and_restart(event))
 825                 return;
 826
 827         fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
 828         fst = event->hw.flags & (PERF_X86_EVENT_PEBS_ST |
 829                                  PERF_X86_EVENT_PEBS_ST_HSW);
 830
 831         perf_sample_data_init(&data, 0, event->hw.last_period);
 832
 833         data.period = event->hw.last_period;
 834         sample_type = event->attr.sample_type;
 835
 836         /*
 837          * if PEBS-LL or PreciseStore
 838          */
 839         if (fll || fst) {
 840                 /*
 841                  * Use latency for weight (only avail with PEBS-LL)
 842                  */
 843                 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
 844                         data.weight = pebs->lat;
 845
 846                 /*
 847                  * data.data_src encodes the data source
 848                  */
 849                 if (sample_type & PERF_SAMPLE_DATA_SRC) {
 850                         if (fll)
 851                                 data.data_src.val = load_latency_data(pebs->dse);
 852                         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
 853                                 data.data_src.val =
 854                                         precise_store_data_hsw(pebs->dse);
 855                         else
 856                                 data.data_src.val = precise_store_data(pebs->dse);
 857                 }
 858         }
 859
 860         /*
 861          * We use the interrupt regs as a base because the PEBS record
 862          * does not contain a full regs set, specifically it seems to
 863          * lack segment descriptors, which get used by things like
 864          * user_mode().
 865          *
 866          * In the simple case fix up only the IP and BP,SP regs, for
 867          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
 868          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
 869          */
 870         regs = *iregs;
 871         regs.flags = pebs->flags;
 872         set_linear_ip(&regs, pebs->ip);
 873         regs.bp = pebs->bp;
 874         regs.sp = pebs->sp;
 875
 876         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
 877                 regs.ip = pebs->real_ip;
 878                 regs.flags |= PERF_EFLAGS_EXACT;
 879         } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(&regs))
 880                 regs.flags |= PERF_EFLAGS_EXACT;
 881         else
 882                 regs.flags &= ~PERF_EFLAGS_EXACT;
 883
 884         if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
 885             x86_pmu.intel_cap.pebs_format >= 1)
 886                 data.addr = pebs->dla;
 887
 888         /* Only set the TSX weight when no memory weight was requested. */
 889         if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll &&
 890             (x86_pmu.intel_cap.pebs_format >= 2))
 891                 data.weight = intel_hsw_weight(pebs);
 892
 893         if (has_branch_stack(event))
 894                 data.br_stack = &cpuc->lbr_stack;
 895
 896         if (perf_event_overflow(event, &data, &regs))
 897                 x86_pmu_stop(event, 0);
 898 }
 899
 900 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
 901 {
 902         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 903         struct debug_store *ds = cpuc->ds;
 904         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
 905         struct pebs_record_core *at, *top;
 906         int n;
 907
 908         if (!x86_pmu.pebs_active)
 909                 return;
 910
 911         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
 912         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
 913
 914         /*
 915          * Whatever else happens, drain the thing
 916          */
 917         ds->pebs_index = ds->pebs_buffer_base;
 918
 919         if (!test_bit(0, cpuc->active_mask))
 920                 return;
 921
 922         WARN_ON_ONCE(!event);
 923
 924         if (!event->attr.precise_ip)
 925                 return;
 926
 927         n = top - at;
 928         if (n <= 0)
 929                 return;
 930
 931         /*
 932          * Should not happen, we program the threshold at 1 and do not
 933          * set a reset value.
 934          */
 935         WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
 936         at += n - 1;
 937
 938         __intel_pmu_pebs_event(event, iregs, at);
 939 }
 940
 941 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
 942 {
 943         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 944         struct debug_store *ds = cpuc->ds;
 945         struct perf_event *event = NULL;
 946         void *at, *top;
 947         u64 status = 0;
 948         int bit;
 949
 950         if (!x86_pmu.pebs_active)
 951                 return;
 952
 953         at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
 954         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
 955
 956         ds->pebs_index = ds->pebs_buffer_base;
 957
 958         if (unlikely(at > top))
 959                 return;
 960
 961         /*
 962          * Should not happen, we program the threshold at 1 and do not
 963          * set a reset value.
 964          */
 965         WARN_ONCE(top - at > x86_pmu.max_pebs_events * x86_pmu.pebs_record_size,
 966                   "Unexpected number of pebs records %ld\n",
 967                   (long)(top - at) / x86_pmu.pebs_record_size);
 968
 969         for (; at < top; at += x86_pmu.pebs_record_size) {
 970                 struct pebs_record_nhm *p = at;
 971
 972                 for_each_set_bit(bit, (unsigned long *)&p->status,
 973                                  x86_pmu.max_pebs_events) {
 974                         event = cpuc->events[bit];
 975                         if (!test_bit(bit, cpuc->active_mask))
 976                                 continue;
 977
 978                         WARN_ON_ONCE(!event);
 979
 980                         if (!event->attr.precise_ip)
 981                                 continue;
 982
 983                         if (__test_and_set_bit(bit, (unsigned long *)&status))
 984                                 continue;
 985
 986                         break;
 987                 }
 988
 989                 if (!event || bit >= x86_pmu.max_pebs_events)
 990                         continue;
 991
 992                 __intel_pmu_pebs_event(event, iregs, at);
 993         }
 994 }
 995
 996 /*
 997  * BTS, PEBS probe and setup
 998  */
 999
1000 void intel_ds_init(void)
1001 {
1002         /*
1003          * No support for 32bit formats
1004          */
1005         if (!boot_cpu_has(X86_FEATURE_DTES64))
1006                 return;
1007
1008         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
1009         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1010         if (x86_pmu.pebs) {
1011                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
1012                 int format = x86_pmu.intel_cap.pebs_format;
1013
1014                 switch (format) {
1015                 case 0:
1016                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1017                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1018                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1019                         break;
1020
1021                 case 1:
1022                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1023                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1024                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1025                         break;
1026
1027                 case 2:
1028                         pr_cont("PEBS fmt2%c, ", pebs_type);
1029                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1030                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1031                         break;
1032
1033                 default:
1034                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1035                         x86_pmu.pebs = 0;
1036                 }
1037         }
1038 }
1039
1040 void perf_restore_debug_store(void)
1041 {
1042         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1043
1044         if (!x86_pmu.bts && !x86_pmu.pebs)
1045                 return;
1046
1047         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1048 }