2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
30 #include "assigned-dev.h"
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <trace/events/kvm.h>
58 #define CREATE_TRACE_POINTS
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
71 #define MAX_IO_MSRS 256
72 #define KVM_MAX_MCE_BANKS 32
73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
75 #define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
92 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
93 static void process_nmi(struct kvm_vcpu *vcpu);
94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
96 struct kvm_x86_ops *kvm_x86_ops;
97 EXPORT_SYMBOL_GPL(kvm_x86_ops);
99 static bool ignore_msrs = 0;
100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
102 unsigned int min_timer_period_us = 500;
103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
105 static bool __read_mostly kvmclock_periodic_sync = true;
106 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
108 bool kvm_has_tsc_control;
109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
110 u32 kvm_max_guest_tsc_khz;
111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
113 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
114 static u32 tsc_tolerance_ppm = 250;
115 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
117 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
118 unsigned int lapic_timer_advance_ns = 0;
119 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
121 static bool backwards_tsc_observed = false;
123 #define KVM_NR_SHARED_MSRS 16
125 struct kvm_shared_msrs_global {
127 u32 msrs[KVM_NR_SHARED_MSRS];
130 struct kvm_shared_msrs {
131 struct user_return_notifier urn;
133 struct kvm_shared_msr_values {
136 } values[KVM_NR_SHARED_MSRS];
139 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
140 static struct kvm_shared_msrs __percpu *shared_msrs;
142 struct kvm_stats_debugfs_item debugfs_entries[] = {
143 { "pf_fixed", VCPU_STAT(pf_fixed) },
144 { "pf_guest", VCPU_STAT(pf_guest) },
145 { "tlb_flush", VCPU_STAT(tlb_flush) },
146 { "invlpg", VCPU_STAT(invlpg) },
147 { "exits", VCPU_STAT(exits) },
148 { "io_exits", VCPU_STAT(io_exits) },
149 { "mmio_exits", VCPU_STAT(mmio_exits) },
150 { "signal_exits", VCPU_STAT(signal_exits) },
151 { "irq_window", VCPU_STAT(irq_window_exits) },
152 { "nmi_window", VCPU_STAT(nmi_window_exits) },
153 { "halt_exits", VCPU_STAT(halt_exits) },
154 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
155 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
156 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
157 { "hypercalls", VCPU_STAT(hypercalls) },
158 { "request_irq", VCPU_STAT(request_irq_exits) },
159 { "irq_exits", VCPU_STAT(irq_exits) },
160 { "host_state_reload", VCPU_STAT(host_state_reload) },
161 { "efer_reload", VCPU_STAT(efer_reload) },
162 { "fpu_reload", VCPU_STAT(fpu_reload) },
163 { "insn_emulation", VCPU_STAT(insn_emulation) },
164 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
165 { "irq_injections", VCPU_STAT(irq_injections) },
166 { "nmi_injections", VCPU_STAT(nmi_injections) },
167 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
168 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
169 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
170 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
171 { "mmu_flooded", VM_STAT(mmu_flooded) },
172 { "mmu_recycled", VM_STAT(mmu_recycled) },
173 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
174 { "mmu_unsync", VM_STAT(mmu_unsync) },
175 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
176 { "largepages", VM_STAT(lpages) },
180 u64 __read_mostly host_xcr0;
182 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
184 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
187 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
188 vcpu->arch.apf.gfns[i] = ~0;
191 static void kvm_on_user_return(struct user_return_notifier *urn)
194 struct kvm_shared_msrs *locals
195 = container_of(urn, struct kvm_shared_msrs, urn);
196 struct kvm_shared_msr_values *values;
198 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
199 values = &locals->values[slot];
200 if (values->host != values->curr) {
201 wrmsrl(shared_msrs_global.msrs[slot], values->host);
202 values->curr = values->host;
205 locals->registered = false;
206 user_return_notifier_unregister(urn);
209 static void shared_msr_update(unsigned slot, u32 msr)
212 unsigned int cpu = smp_processor_id();
213 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
215 /* only read, and nobody should modify it at this time,
216 * so don't need lock */
217 if (slot >= shared_msrs_global.nr) {
218 printk(KERN_ERR "kvm: invalid MSR slot!");
221 rdmsrl_safe(msr, &value);
222 smsr->values[slot].host = value;
223 smsr->values[slot].curr = value;
226 void kvm_define_shared_msr(unsigned slot, u32 msr)
228 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
229 shared_msrs_global.msrs[slot] = msr;
230 if (slot >= shared_msrs_global.nr)
231 shared_msrs_global.nr = slot + 1;
233 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
235 static void kvm_shared_msr_cpu_online(void)
239 for (i = 0; i < shared_msrs_global.nr; ++i)
240 shared_msr_update(i, shared_msrs_global.msrs[i]);
243 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
245 unsigned int cpu = smp_processor_id();
246 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
249 if (((value ^ smsr->values[slot].curr) & mask) == 0)
251 smsr->values[slot].curr = value;
252 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
256 if (!smsr->registered) {
257 smsr->urn.on_user_return = kvm_on_user_return;
258 user_return_notifier_register(&smsr->urn);
259 smsr->registered = true;
263 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
265 static void drop_user_return_notifiers(void)
267 unsigned int cpu = smp_processor_id();
268 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
270 if (smsr->registered)
271 kvm_on_user_return(&smsr->urn);
274 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
276 return vcpu->arch.apic_base;
278 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
280 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
282 u64 old_state = vcpu->arch.apic_base &
283 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
284 u64 new_state = msr_info->data &
285 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
286 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
287 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
289 if (!msr_info->host_initiated &&
290 ((msr_info->data & reserved_bits) != 0 ||
291 new_state == X2APIC_ENABLE ||
292 (new_state == MSR_IA32_APICBASE_ENABLE &&
293 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
294 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
298 kvm_lapic_set_base(vcpu, msr_info->data);
301 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
303 asmlinkage __visible void kvm_spurious_fault(void)
305 /* Fault while not rebooting. We want the trace. */
308 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
310 #define EXCPT_BENIGN 0
311 #define EXCPT_CONTRIBUTORY 1
314 static int exception_class(int vector)
324 return EXCPT_CONTRIBUTORY;
331 #define EXCPT_FAULT 0
333 #define EXCPT_ABORT 2
334 #define EXCPT_INTERRUPT 3
336 static int exception_type(int vector)
340 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
341 return EXCPT_INTERRUPT;
345 /* #DB is trap, as instruction watchpoints are handled elsewhere */
346 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
349 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
352 /* Reserved exceptions will result in fault */
356 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
357 unsigned nr, bool has_error, u32 error_code,
363 kvm_make_request(KVM_REQ_EVENT, vcpu);
365 if (!vcpu->arch.exception.pending) {
367 if (has_error && !is_protmode(vcpu))
369 vcpu->arch.exception.pending = true;
370 vcpu->arch.exception.has_error_code = has_error;
371 vcpu->arch.exception.nr = nr;
372 vcpu->arch.exception.error_code = error_code;
373 vcpu->arch.exception.reinject = reinject;
377 /* to check exception */
378 prev_nr = vcpu->arch.exception.nr;
379 if (prev_nr == DF_VECTOR) {
380 /* triple fault -> shutdown */
381 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
384 class1 = exception_class(prev_nr);
385 class2 = exception_class(nr);
386 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
387 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
388 /* generate double fault per SDM Table 5-5 */
389 vcpu->arch.exception.pending = true;
390 vcpu->arch.exception.has_error_code = true;
391 vcpu->arch.exception.nr = DF_VECTOR;
392 vcpu->arch.exception.error_code = 0;
394 /* replace previous exception with a new one in a hope
395 that instruction re-execution will regenerate lost
400 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
402 kvm_multiple_exception(vcpu, nr, false, 0, false);
404 EXPORT_SYMBOL_GPL(kvm_queue_exception);
406 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
408 kvm_multiple_exception(vcpu, nr, false, 0, true);
410 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
412 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
415 kvm_inject_gp(vcpu, 0);
417 kvm_x86_ops->skip_emulated_instruction(vcpu);
419 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
421 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
423 ++vcpu->stat.pf_guest;
424 vcpu->arch.cr2 = fault->address;
425 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
427 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
429 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
431 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
432 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
434 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
436 return fault->nested_page_fault;
439 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
441 atomic_inc(&vcpu->arch.nmi_queued);
442 kvm_make_request(KVM_REQ_NMI, vcpu);
444 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
446 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
448 kvm_multiple_exception(vcpu, nr, true, error_code, false);
450 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
452 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
454 kvm_multiple_exception(vcpu, nr, true, error_code, true);
456 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
459 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
460 * a #GP and return false.
462 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
464 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
466 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
469 EXPORT_SYMBOL_GPL(kvm_require_cpl);
471 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
473 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
476 kvm_queue_exception(vcpu, UD_VECTOR);
479 EXPORT_SYMBOL_GPL(kvm_require_dr);
482 * This function will be used to read from the physical memory of the currently
483 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
484 * can read from guest physical or from the guest's guest physical memory.
486 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
487 gfn_t ngfn, void *data, int offset, int len,
490 struct x86_exception exception;
494 ngpa = gfn_to_gpa(ngfn);
495 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
496 if (real_gfn == UNMAPPED_GVA)
499 real_gfn = gpa_to_gfn(real_gfn);
501 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
503 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
505 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
506 void *data, int offset, int len, u32 access)
508 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
509 data, offset, len, access);
513 * Load the pae pdptrs. Return true is they are all valid.
515 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
517 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
518 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
521 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
523 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
524 offset * sizeof(u64), sizeof(pdpte),
525 PFERR_USER_MASK|PFERR_WRITE_MASK);
530 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
531 if (is_present_gpte(pdpte[i]) &&
533 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
540 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
541 __set_bit(VCPU_EXREG_PDPTR,
542 (unsigned long *)&vcpu->arch.regs_avail);
543 __set_bit(VCPU_EXREG_PDPTR,
544 (unsigned long *)&vcpu->arch.regs_dirty);
549 EXPORT_SYMBOL_GPL(load_pdptrs);
551 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
553 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
559 if (is_long_mode(vcpu) || !is_pae(vcpu))
562 if (!test_bit(VCPU_EXREG_PDPTR,
563 (unsigned long *)&vcpu->arch.regs_avail))
566 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
567 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
568 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
569 PFERR_USER_MASK | PFERR_WRITE_MASK);
572 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
578 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
580 unsigned long old_cr0 = kvm_read_cr0(vcpu);
581 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
586 if (cr0 & 0xffffffff00000000UL)
590 cr0 &= ~CR0_RESERVED_BITS;
592 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
595 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
598 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
600 if ((vcpu->arch.efer & EFER_LME)) {
605 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
610 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
615 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
618 kvm_x86_ops->set_cr0(vcpu, cr0);
620 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
621 kvm_clear_async_pf_completion_queue(vcpu);
622 kvm_async_pf_hash_reset(vcpu);
625 if ((cr0 ^ old_cr0) & update_bits)
626 kvm_mmu_reset_context(vcpu);
628 if ((cr0 ^ old_cr0) & X86_CR0_CD)
629 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
633 EXPORT_SYMBOL_GPL(kvm_set_cr0);
635 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
637 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
639 EXPORT_SYMBOL_GPL(kvm_lmsw);
641 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
643 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
644 !vcpu->guest_xcr0_loaded) {
645 /* kvm_set_xcr() also depends on this */
646 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
647 vcpu->guest_xcr0_loaded = 1;
651 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
653 if (vcpu->guest_xcr0_loaded) {
654 if (vcpu->arch.xcr0 != host_xcr0)
655 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
656 vcpu->guest_xcr0_loaded = 0;
660 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
663 u64 old_xcr0 = vcpu->arch.xcr0;
666 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
667 if (index != XCR_XFEATURE_ENABLED_MASK)
669 if (!(xcr0 & XFEATURE_MASK_FP))
671 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
675 * Do not allow the guest to set bits that we do not support
676 * saving. However, xcr0 bit 0 is always set, even if the
677 * emulated CPU does not support XSAVE (see fx_init).
679 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
680 if (xcr0 & ~valid_bits)
683 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
684 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
687 if (xcr0 & XFEATURE_MASK_AVX512) {
688 if (!(xcr0 & XFEATURE_MASK_YMM))
690 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
693 kvm_put_guest_xcr0(vcpu);
694 vcpu->arch.xcr0 = xcr0;
696 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
697 kvm_update_cpuid(vcpu);
701 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
703 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
704 __kvm_set_xcr(vcpu, index, xcr)) {
705 kvm_inject_gp(vcpu, 0);
710 EXPORT_SYMBOL_GPL(kvm_set_xcr);
712 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
714 unsigned long old_cr4 = kvm_read_cr4(vcpu);
715 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
716 X86_CR4_SMEP | X86_CR4_SMAP;
718 if (cr4 & CR4_RESERVED_BITS)
721 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
724 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
727 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
730 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
733 if (is_long_mode(vcpu)) {
734 if (!(cr4 & X86_CR4_PAE))
736 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
737 && ((cr4 ^ old_cr4) & pdptr_bits)
738 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
742 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
743 if (!guest_cpuid_has_pcid(vcpu))
746 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
747 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
751 if (kvm_x86_ops->set_cr4(vcpu, cr4))
754 if (((cr4 ^ old_cr4) & pdptr_bits) ||
755 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
756 kvm_mmu_reset_context(vcpu);
758 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
759 kvm_update_cpuid(vcpu);
763 EXPORT_SYMBOL_GPL(kvm_set_cr4);
765 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
768 cr3 &= ~CR3_PCID_INVD;
771 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
772 kvm_mmu_sync_roots(vcpu);
773 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
777 if (is_long_mode(vcpu)) {
778 if (cr3 & CR3_L_MODE_RESERVED_BITS)
780 } else if (is_pae(vcpu) && is_paging(vcpu) &&
781 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
784 vcpu->arch.cr3 = cr3;
785 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
786 kvm_mmu_new_cr3(vcpu);
789 EXPORT_SYMBOL_GPL(kvm_set_cr3);
791 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
793 if (cr8 & CR8_RESERVED_BITS)
795 if (lapic_in_kernel(vcpu))
796 kvm_lapic_set_tpr(vcpu, cr8);
798 vcpu->arch.cr8 = cr8;
801 EXPORT_SYMBOL_GPL(kvm_set_cr8);
803 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
805 if (lapic_in_kernel(vcpu))
806 return kvm_lapic_get_cr8(vcpu);
808 return vcpu->arch.cr8;
810 EXPORT_SYMBOL_GPL(kvm_get_cr8);
812 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
816 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
817 for (i = 0; i < KVM_NR_DB_REGS; i++)
818 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
819 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
823 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
825 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
826 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
829 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
833 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
834 dr7 = vcpu->arch.guest_debug_dr7;
836 dr7 = vcpu->arch.dr7;
837 kvm_x86_ops->set_dr7(vcpu, dr7);
838 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
839 if (dr7 & DR7_BP_EN_MASK)
840 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
843 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
845 u64 fixed = DR6_FIXED_1;
847 if (!guest_cpuid_has_rtm(vcpu))
852 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
856 vcpu->arch.db[dr] = val;
857 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
858 vcpu->arch.eff_db[dr] = val;
863 if (val & 0xffffffff00000000ULL)
865 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
866 kvm_update_dr6(vcpu);
871 if (val & 0xffffffff00000000ULL)
873 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
874 kvm_update_dr7(vcpu);
881 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
883 if (__kvm_set_dr(vcpu, dr, val)) {
884 kvm_inject_gp(vcpu, 0);
889 EXPORT_SYMBOL_GPL(kvm_set_dr);
891 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
895 *val = vcpu->arch.db[dr];
900 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
901 *val = vcpu->arch.dr6;
903 *val = kvm_x86_ops->get_dr6(vcpu);
908 *val = vcpu->arch.dr7;
913 EXPORT_SYMBOL_GPL(kvm_get_dr);
915 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
917 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
921 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
924 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
925 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
928 EXPORT_SYMBOL_GPL(kvm_rdpmc);
931 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
932 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
934 * This list is modified at module load time to reflect the
935 * capabilities of the host cpu. This capabilities test skips MSRs that are
936 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
937 * may depend on host virtualization features rather than host cpu features.
940 static u32 msrs_to_save[] = {
941 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
944 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
946 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
947 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
950 static unsigned num_msrs_to_save;
952 static u32 emulated_msrs[] = {
953 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
954 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
955 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
956 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
957 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
958 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
961 HV_X64_MSR_VP_RUNTIME,
962 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
966 MSR_IA32_TSCDEADLINE,
967 MSR_IA32_MISC_ENABLE,
973 static unsigned num_emulated_msrs;
975 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
977 if (efer & efer_reserved_bits)
980 if (efer & EFER_FFXSR) {
981 struct kvm_cpuid_entry2 *feat;
983 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
984 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
988 if (efer & EFER_SVME) {
989 struct kvm_cpuid_entry2 *feat;
991 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
992 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
998 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1000 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1002 u64 old_efer = vcpu->arch.efer;
1004 if (!kvm_valid_efer(vcpu, efer))
1008 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1012 efer |= vcpu->arch.efer & EFER_LMA;
1014 kvm_x86_ops->set_efer(vcpu, efer);
1016 /* Update reserved bits */
1017 if ((efer ^ old_efer) & EFER_NX)
1018 kvm_mmu_reset_context(vcpu);
1023 void kvm_enable_efer_bits(u64 mask)
1025 efer_reserved_bits &= ~mask;
1027 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1030 * Writes msr value into into the appropriate "register".
1031 * Returns 0 on success, non-0 otherwise.
1032 * Assumes vcpu_load() was already called.
1034 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1036 switch (msr->index) {
1039 case MSR_KERNEL_GS_BASE:
1042 if (is_noncanonical_address(msr->data))
1045 case MSR_IA32_SYSENTER_EIP:
1046 case MSR_IA32_SYSENTER_ESP:
1048 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1049 * non-canonical address is written on Intel but not on
1050 * AMD (which ignores the top 32-bits, because it does
1051 * not implement 64-bit SYSENTER).
1053 * 64-bit code should hence be able to write a non-canonical
1054 * value on AMD. Making the address canonical ensures that
1055 * vmentry does not fail on Intel after writing a non-canonical
1056 * value, and that something deterministic happens if the guest
1057 * invokes 64-bit SYSENTER.
1059 msr->data = get_canonical(msr->data);
1061 return kvm_x86_ops->set_msr(vcpu, msr);
1063 EXPORT_SYMBOL_GPL(kvm_set_msr);
1066 * Adapt set_msr() to msr_io()'s calling convention
1068 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1070 struct msr_data msr;
1074 msr.host_initiated = true;
1075 r = kvm_get_msr(vcpu, &msr);
1083 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1085 struct msr_data msr;
1089 msr.host_initiated = true;
1090 return kvm_set_msr(vcpu, &msr);
1093 #ifdef CONFIG_X86_64
1094 struct pvclock_gtod_data {
1097 struct { /* extract of a clocksource struct */
1109 static struct pvclock_gtod_data pvclock_gtod_data;
1111 static void update_pvclock_gtod(struct timekeeper *tk)
1113 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1116 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1118 write_seqcount_begin(&vdata->seq);
1120 /* copy pvclock gtod data */
1121 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1122 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1123 vdata->clock.mask = tk->tkr_mono.mask;
1124 vdata->clock.mult = tk->tkr_mono.mult;
1125 vdata->clock.shift = tk->tkr_mono.shift;
1127 vdata->boot_ns = boot_ns;
1128 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1130 write_seqcount_end(&vdata->seq);
1134 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1137 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1138 * vcpu_enter_guest. This function is only called from
1139 * the physical CPU that is running vcpu.
1141 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1144 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1148 struct pvclock_wall_clock wc;
1149 struct timespec boot;
1154 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1159 ++version; /* first time write, random junk */
1163 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1166 * The guest calculates current wall clock time by adding
1167 * system time (updated by kvm_guest_time_update below) to the
1168 * wall clock specified here. guest system time equals host
1169 * system time for us, thus we must fill in host boot time here.
1173 if (kvm->arch.kvmclock_offset) {
1174 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1175 boot = timespec_sub(boot, ts);
1177 wc.sec = boot.tv_sec;
1178 wc.nsec = boot.tv_nsec;
1179 wc.version = version;
1181 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1184 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1187 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1189 uint32_t quotient, remainder;
1191 /* Don't try to replace with do_div(), this one calculates
1192 * "(dividend << 32) / divisor" */
1194 : "=a" (quotient), "=d" (remainder)
1195 : "0" (0), "1" (dividend), "r" (divisor) );
1199 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1200 s8 *pshift, u32 *pmultiplier)
1207 tps64 = base_khz * 1000LL;
1208 scaled64 = scaled_khz * 1000LL;
1209 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1214 tps32 = (uint32_t)tps64;
1215 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1216 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1224 *pmultiplier = div_frac(scaled64, tps32);
1226 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1227 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1230 #ifdef CONFIG_X86_64
1231 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1234 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1235 static unsigned long max_tsc_khz;
1237 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1239 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1240 vcpu->arch.virtual_tsc_shift);
1243 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1245 u64 v = (u64)khz * (1000000 + ppm);
1250 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1252 u32 thresh_lo, thresh_hi;
1253 int use_scaling = 0;
1255 /* tsc_khz can be zero if TSC calibration fails */
1256 if (this_tsc_khz == 0)
1259 /* Compute a scale to convert nanoseconds in TSC cycles */
1260 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1261 &vcpu->arch.virtual_tsc_shift,
1262 &vcpu->arch.virtual_tsc_mult);
1263 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1266 * Compute the variation in TSC rate which is acceptable
1267 * within the range of tolerance and decide if the
1268 * rate being applied is within that bounds of the hardware
1269 * rate. If so, no scaling or compensation need be done.
1271 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1272 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1273 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1274 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1277 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1280 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1282 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1283 vcpu->arch.virtual_tsc_mult,
1284 vcpu->arch.virtual_tsc_shift);
1285 tsc += vcpu->arch.this_tsc_write;
1289 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1291 #ifdef CONFIG_X86_64
1293 struct kvm_arch *ka = &vcpu->kvm->arch;
1294 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1296 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1297 atomic_read(&vcpu->kvm->online_vcpus));
1300 * Once the masterclock is enabled, always perform request in
1301 * order to update it.
1303 * In order to enable masterclock, the host clocksource must be TSC
1304 * and the vcpus need to have matched TSCs. When that happens,
1305 * perform request to enable masterclock.
1307 if (ka->use_master_clock ||
1308 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1309 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1311 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1312 atomic_read(&vcpu->kvm->online_vcpus),
1313 ka->use_master_clock, gtod->clock.vclock_mode);
1317 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1319 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1320 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1323 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1325 struct kvm *kvm = vcpu->kvm;
1326 u64 offset, ns, elapsed;
1327 unsigned long flags;
1330 bool already_matched;
1331 u64 data = msr->data;
1333 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1334 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1335 ns = get_kernel_ns();
1336 elapsed = ns - kvm->arch.last_tsc_nsec;
1338 if (vcpu->arch.virtual_tsc_khz) {
1341 /* n.b - signed multiplication and division required */
1342 usdiff = data - kvm->arch.last_tsc_write;
1343 #ifdef CONFIG_X86_64
1344 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1346 /* do_div() only does unsigned */
1347 asm("1: idivl %[divisor]\n"
1348 "2: xor %%edx, %%edx\n"
1349 " movl $0, %[faulted]\n"
1351 ".section .fixup,\"ax\"\n"
1352 "4: movl $1, %[faulted]\n"
1356 _ASM_EXTABLE(1b, 4b)
1358 : "=A"(usdiff), [faulted] "=r" (faulted)
1359 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1362 do_div(elapsed, 1000);
1367 /* idivl overflow => difference is larger than USEC_PER_SEC */
1369 usdiff = USEC_PER_SEC;
1371 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1374 * Special case: TSC write with a small delta (1 second) of virtual
1375 * cycle time against real time is interpreted as an attempt to
1376 * synchronize the CPU.
1378 * For a reliable TSC, we can match TSC offsets, and for an unstable
1379 * TSC, we add elapsed time in this computation. We could let the
1380 * compensation code attempt to catch up if we fall behind, but
1381 * it's better to try to match offsets from the beginning.
1383 if (usdiff < USEC_PER_SEC &&
1384 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1385 if (!check_tsc_unstable()) {
1386 offset = kvm->arch.cur_tsc_offset;
1387 pr_debug("kvm: matched tsc offset for %llu\n", data);
1389 u64 delta = nsec_to_cycles(vcpu, elapsed);
1391 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1392 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1395 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1398 * We split periods of matched TSC writes into generations.
1399 * For each generation, we track the original measured
1400 * nanosecond time, offset, and write, so if TSCs are in
1401 * sync, we can match exact offset, and if not, we can match
1402 * exact software computation in compute_guest_tsc()
1404 * These values are tracked in kvm->arch.cur_xxx variables.
1406 kvm->arch.cur_tsc_generation++;
1407 kvm->arch.cur_tsc_nsec = ns;
1408 kvm->arch.cur_tsc_write = data;
1409 kvm->arch.cur_tsc_offset = offset;
1411 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1412 kvm->arch.cur_tsc_generation, data);
1416 * We also track th most recent recorded KHZ, write and time to
1417 * allow the matching interval to be extended at each write.
1419 kvm->arch.last_tsc_nsec = ns;
1420 kvm->arch.last_tsc_write = data;
1421 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1423 vcpu->arch.last_guest_tsc = data;
1425 /* Keep track of which generation this VCPU has synchronized to */
1426 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1427 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1428 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1430 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1431 update_ia32_tsc_adjust_msr(vcpu, offset);
1432 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1433 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1435 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1437 kvm->arch.nr_vcpus_matched_tsc = 0;
1438 } else if (!already_matched) {
1439 kvm->arch.nr_vcpus_matched_tsc++;
1442 kvm_track_tsc_matching(vcpu);
1443 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1446 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1448 #ifdef CONFIG_X86_64
1450 static cycle_t read_tsc(void)
1452 cycle_t ret = (cycle_t)rdtsc_ordered();
1453 u64 last = pvclock_gtod_data.clock.cycle_last;
1455 if (likely(ret >= last))
1459 * GCC likes to generate cmov here, but this branch is extremely
1460 * predictable (it's just a funciton of time and the likely is
1461 * very likely) and there's a data dependence, so force GCC
1462 * to generate a branch instead. I don't barrier() because
1463 * we don't actually need a barrier, and if this function
1464 * ever gets inlined it will generate worse code.
1470 static inline u64 vgettsc(cycle_t *cycle_now)
1473 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1475 *cycle_now = read_tsc();
1477 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1478 return v * gtod->clock.mult;
1481 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1483 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1489 seq = read_seqcount_begin(>od->seq);
1490 mode = gtod->clock.vclock_mode;
1491 ns = gtod->nsec_base;
1492 ns += vgettsc(cycle_now);
1493 ns >>= gtod->clock.shift;
1494 ns += gtod->boot_ns;
1495 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1501 /* returns true if host is using tsc clocksource */
1502 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1504 /* checked again under seqlock below */
1505 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1508 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1514 * Assuming a stable TSC across physical CPUS, and a stable TSC
1515 * across virtual CPUs, the following condition is possible.
1516 * Each numbered line represents an event visible to both
1517 * CPUs at the next numbered event.
1519 * "timespecX" represents host monotonic time. "tscX" represents
1522 * VCPU0 on CPU0 | VCPU1 on CPU1
1524 * 1. read timespec0,tsc0
1525 * 2. | timespec1 = timespec0 + N
1527 * 3. transition to guest | transition to guest
1528 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1529 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1530 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1532 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1535 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1537 * - 0 < N - M => M < N
1539 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1540 * always the case (the difference between two distinct xtime instances
1541 * might be smaller then the difference between corresponding TSC reads,
1542 * when updating guest vcpus pvclock areas).
1544 * To avoid that problem, do not allow visibility of distinct
1545 * system_timestamp/tsc_timestamp values simultaneously: use a master
1546 * copy of host monotonic time values. Update that master copy
1549 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1553 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1555 #ifdef CONFIG_X86_64
1556 struct kvm_arch *ka = &kvm->arch;
1558 bool host_tsc_clocksource, vcpus_matched;
1560 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1561 atomic_read(&kvm->online_vcpus));
1564 * If the host uses TSC clock, then passthrough TSC as stable
1567 host_tsc_clocksource = kvm_get_time_and_clockread(
1568 &ka->master_kernel_ns,
1569 &ka->master_cycle_now);
1571 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1572 && !backwards_tsc_observed
1573 && !ka->boot_vcpu_runs_old_kvmclock;
1575 if (ka->use_master_clock)
1576 atomic_set(&kvm_guest_has_master_clock, 1);
1578 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1579 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1584 static void kvm_gen_update_masterclock(struct kvm *kvm)
1586 #ifdef CONFIG_X86_64
1588 struct kvm_vcpu *vcpu;
1589 struct kvm_arch *ka = &kvm->arch;
1591 spin_lock(&ka->pvclock_gtod_sync_lock);
1592 kvm_make_mclock_inprogress_request(kvm);
1593 /* no guest entries from this point */
1594 pvclock_update_vm_gtod_copy(kvm);
1596 kvm_for_each_vcpu(i, vcpu, kvm)
1597 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1599 /* guest entries allowed */
1600 kvm_for_each_vcpu(i, vcpu, kvm)
1601 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1603 spin_unlock(&ka->pvclock_gtod_sync_lock);
1607 static int kvm_guest_time_update(struct kvm_vcpu *v)
1609 unsigned long flags, this_tsc_khz;
1610 struct kvm_vcpu_arch *vcpu = &v->arch;
1611 struct kvm_arch *ka = &v->kvm->arch;
1613 u64 tsc_timestamp, host_tsc;
1614 struct pvclock_vcpu_time_info guest_hv_clock;
1616 bool use_master_clock;
1622 * If the host uses TSC clock, then passthrough TSC as stable
1625 spin_lock(&ka->pvclock_gtod_sync_lock);
1626 use_master_clock = ka->use_master_clock;
1627 if (use_master_clock) {
1628 host_tsc = ka->master_cycle_now;
1629 kernel_ns = ka->master_kernel_ns;
1631 spin_unlock(&ka->pvclock_gtod_sync_lock);
1633 /* Keep irq disabled to prevent changes to the clock */
1634 local_irq_save(flags);
1635 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1636 if (unlikely(this_tsc_khz == 0)) {
1637 local_irq_restore(flags);
1638 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1641 if (!use_master_clock) {
1643 kernel_ns = get_kernel_ns();
1646 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1649 * We may have to catch up the TSC to match elapsed wall clock
1650 * time for two reasons, even if kvmclock is used.
1651 * 1) CPU could have been running below the maximum TSC rate
1652 * 2) Broken TSC compensation resets the base at each VCPU
1653 * entry to avoid unknown leaps of TSC even when running
1654 * again on the same CPU. This may cause apparent elapsed
1655 * time to disappear, and the guest to stand still or run
1658 if (vcpu->tsc_catchup) {
1659 u64 tsc = compute_guest_tsc(v, kernel_ns);
1660 if (tsc > tsc_timestamp) {
1661 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1662 tsc_timestamp = tsc;
1666 local_irq_restore(flags);
1668 if (!vcpu->pv_time_enabled)
1671 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1672 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1673 &vcpu->hv_clock.tsc_shift,
1674 &vcpu->hv_clock.tsc_to_system_mul);
1675 vcpu->hw_tsc_khz = this_tsc_khz;
1678 /* With all the info we got, fill in the values */
1679 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1680 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1681 vcpu->last_guest_tsc = tsc_timestamp;
1683 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1684 &guest_hv_clock, sizeof(guest_hv_clock))))
1687 /* This VCPU is paused, but it's legal for a guest to read another
1688 * VCPU's kvmclock, so we really have to follow the specification where
1689 * it says that version is odd if data is being modified, and even after
1692 * Version field updates must be kept separate. This is because
1693 * kvm_write_guest_cached might use a "rep movs" instruction, and
1694 * writes within a string instruction are weakly ordered. So there
1695 * are three writes overall.
1697 * As a small optimization, only write the version field in the first
1698 * and third write. The vcpu->pv_time cache is still valid, because the
1699 * version field is the first in the struct.
1701 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1703 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1704 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1706 sizeof(vcpu->hv_clock.version));
1710 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1711 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1713 if (vcpu->pvclock_set_guest_stopped_request) {
1714 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1715 vcpu->pvclock_set_guest_stopped_request = false;
1718 /* If the host uses TSC clocksource, then it is stable */
1719 if (use_master_clock)
1720 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1722 vcpu->hv_clock.flags = pvclock_flags;
1724 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1726 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1728 sizeof(vcpu->hv_clock));
1732 vcpu->hv_clock.version++;
1733 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1735 sizeof(vcpu->hv_clock.version));
1740 * kvmclock updates which are isolated to a given vcpu, such as
1741 * vcpu->cpu migration, should not allow system_timestamp from
1742 * the rest of the vcpus to remain static. Otherwise ntp frequency
1743 * correction applies to one vcpu's system_timestamp but not
1746 * So in those cases, request a kvmclock update for all vcpus.
1747 * We need to rate-limit these requests though, as they can
1748 * considerably slow guests that have a large number of vcpus.
1749 * The time for a remote vcpu to update its kvmclock is bound
1750 * by the delay we use to rate-limit the updates.
1753 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1755 static void kvmclock_update_fn(struct work_struct *work)
1758 struct delayed_work *dwork = to_delayed_work(work);
1759 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1760 kvmclock_update_work);
1761 struct kvm *kvm = container_of(ka, struct kvm, arch);
1762 struct kvm_vcpu *vcpu;
1764 kvm_for_each_vcpu(i, vcpu, kvm) {
1765 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1766 kvm_vcpu_kick(vcpu);
1770 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1772 struct kvm *kvm = v->kvm;
1774 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1775 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1776 KVMCLOCK_UPDATE_DELAY);
1779 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1781 static void kvmclock_sync_fn(struct work_struct *work)
1783 struct delayed_work *dwork = to_delayed_work(work);
1784 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1785 kvmclock_sync_work);
1786 struct kvm *kvm = container_of(ka, struct kvm, arch);
1788 if (!kvmclock_periodic_sync)
1791 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1792 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1793 KVMCLOCK_SYNC_PERIOD);
1796 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1798 u64 mcg_cap = vcpu->arch.mcg_cap;
1799 unsigned bank_num = mcg_cap & 0xff;
1802 case MSR_IA32_MCG_STATUS:
1803 vcpu->arch.mcg_status = data;
1805 case MSR_IA32_MCG_CTL:
1806 if (!(mcg_cap & MCG_CTL_P))
1808 if (data != 0 && data != ~(u64)0)
1810 vcpu->arch.mcg_ctl = data;
1813 if (msr >= MSR_IA32_MC0_CTL &&
1814 msr < MSR_IA32_MCx_CTL(bank_num)) {
1815 u32 offset = msr - MSR_IA32_MC0_CTL;
1816 /* only 0 or all 1s can be written to IA32_MCi_CTL
1817 * some Linux kernels though clear bit 10 in bank 4 to
1818 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1819 * this to avoid an uncatched #GP in the guest
1821 if ((offset & 0x3) == 0 &&
1822 data != 0 && (data | (1 << 10)) != ~(u64)0)
1824 vcpu->arch.mce_banks[offset] = data;
1832 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1834 struct kvm *kvm = vcpu->kvm;
1835 int lm = is_long_mode(vcpu);
1836 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1837 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1838 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1839 : kvm->arch.xen_hvm_config.blob_size_32;
1840 u32 page_num = data & ~PAGE_MASK;
1841 u64 page_addr = data & PAGE_MASK;
1846 if (page_num >= blob_size)
1849 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1854 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1863 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1865 gpa_t gpa = data & ~0x3f;
1867 /* Bits 2:5 are reserved, Should be zero */
1871 vcpu->arch.apf.msr_val = data;
1873 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1874 kvm_clear_async_pf_completion_queue(vcpu);
1875 kvm_async_pf_hash_reset(vcpu);
1879 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1883 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1884 kvm_async_pf_wakeup_all(vcpu);
1888 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1890 vcpu->arch.pv_time_enabled = false;
1893 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1897 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1900 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1901 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1902 vcpu->arch.st.accum_steal = delta;
1905 static void record_steal_time(struct kvm_vcpu *vcpu)
1907 accumulate_steal_time(vcpu);
1909 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1912 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1913 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1916 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1917 vcpu->arch.st.steal.version += 2;
1918 vcpu->arch.st.accum_steal = 0;
1920 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1921 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1924 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1927 u32 msr = msr_info->index;
1928 u64 data = msr_info->data;
1931 case MSR_AMD64_NB_CFG:
1932 case MSR_IA32_UCODE_REV:
1933 case MSR_IA32_UCODE_WRITE:
1934 case MSR_VM_HSAVE_PA:
1935 case MSR_AMD64_PATCH_LOADER:
1936 case MSR_AMD64_BU_CFG2:
1940 return set_efer(vcpu, data);
1942 data &= ~(u64)0x40; /* ignore flush filter disable */
1943 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1944 data &= ~(u64)0x8; /* ignore TLB cache disable */
1945 data &= ~(u64)0x40000; /* ignore Mc status write enable */
1947 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1952 case MSR_FAM10H_MMIO_CONF_BASE:
1954 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1959 case MSR_IA32_DEBUGCTLMSR:
1961 /* We support the non-activated case already */
1963 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1964 /* Values other than LBR and BTF are vendor-specific,
1965 thus reserved and should throw a #GP */
1968 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1971 case 0x200 ... 0x2ff:
1972 return kvm_mtrr_set_msr(vcpu, msr, data);
1973 case MSR_IA32_APICBASE:
1974 return kvm_set_apic_base(vcpu, msr_info);
1975 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1976 return kvm_x2apic_msr_write(vcpu, msr, data);
1977 case MSR_IA32_TSCDEADLINE:
1978 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1980 case MSR_IA32_TSC_ADJUST:
1981 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1982 if (!msr_info->host_initiated) {
1983 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1984 adjust_tsc_offset_guest(vcpu, adj);
1986 vcpu->arch.ia32_tsc_adjust_msr = data;
1989 case MSR_IA32_MISC_ENABLE:
1990 vcpu->arch.ia32_misc_enable_msr = data;
1992 case MSR_IA32_SMBASE:
1993 if (!msr_info->host_initiated)
1995 vcpu->arch.smbase = data;
1997 case MSR_KVM_WALL_CLOCK_NEW:
1998 case MSR_KVM_WALL_CLOCK:
1999 vcpu->kvm->arch.wall_clock = data;
2000 kvm_write_wall_clock(vcpu->kvm, data);
2002 case MSR_KVM_SYSTEM_TIME_NEW:
2003 case MSR_KVM_SYSTEM_TIME: {
2005 struct kvm_arch *ka = &vcpu->kvm->arch;
2007 kvmclock_reset(vcpu);
2009 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2010 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2012 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2013 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2016 ka->boot_vcpu_runs_old_kvmclock = tmp;
2019 vcpu->arch.time = data;
2020 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2022 /* we verify if the enable bit is set... */
2026 gpa_offset = data & ~(PAGE_MASK | 1);
2028 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2029 &vcpu->arch.pv_time, data & ~1ULL,
2030 sizeof(struct pvclock_vcpu_time_info)))
2031 vcpu->arch.pv_time_enabled = false;
2033 vcpu->arch.pv_time_enabled = true;
2037 case MSR_KVM_ASYNC_PF_EN:
2038 if (kvm_pv_enable_async_pf(vcpu, data))
2041 case MSR_KVM_STEAL_TIME:
2043 if (unlikely(!sched_info_on()))
2046 if (data & KVM_STEAL_RESERVED_MASK)
2049 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2050 data & KVM_STEAL_VALID_BITS,
2051 sizeof(struct kvm_steal_time)))
2054 vcpu->arch.st.msr_val = data;
2056 if (!(data & KVM_MSR_ENABLED))
2059 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2062 case MSR_KVM_PV_EOI_EN:
2063 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2067 case MSR_IA32_MCG_CTL:
2068 case MSR_IA32_MCG_STATUS:
2069 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2070 return set_msr_mce(vcpu, msr, data);
2072 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2073 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2074 pr = true; /* fall through */
2075 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2076 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2077 if (kvm_pmu_is_valid_msr(vcpu, msr))
2078 return kvm_pmu_set_msr(vcpu, msr_info);
2080 if (pr || data != 0)
2081 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2082 "0x%x data 0x%llx\n", msr, data);
2084 case MSR_K7_CLK_CTL:
2086 * Ignore all writes to this no longer documented MSR.
2087 * Writes are only relevant for old K7 processors,
2088 * all pre-dating SVM, but a recommended workaround from
2089 * AMD for these chips. It is possible to specify the
2090 * affected processor models on the command line, hence
2091 * the need to ignore the workaround.
2094 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2095 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2096 case HV_X64_MSR_CRASH_CTL:
2097 return kvm_hv_set_msr_common(vcpu, msr, data,
2098 msr_info->host_initiated);
2099 case MSR_IA32_BBL_CR_CTL3:
2100 /* Drop writes to this legacy MSR -- see rdmsr
2101 * counterpart for further detail.
2103 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2105 case MSR_AMD64_OSVW_ID_LENGTH:
2106 if (!guest_cpuid_has_osvw(vcpu))
2108 vcpu->arch.osvw.length = data;
2110 case MSR_AMD64_OSVW_STATUS:
2111 if (!guest_cpuid_has_osvw(vcpu))
2113 vcpu->arch.osvw.status = data;
2116 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2117 return xen_hvm_config(vcpu, data);
2118 if (kvm_pmu_is_valid_msr(vcpu, msr))
2119 return kvm_pmu_set_msr(vcpu, msr_info);
2121 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2125 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2132 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2136 * Reads an msr value (of 'msr_index') into 'pdata'.
2137 * Returns 0 on success, non-0 otherwise.
2138 * Assumes vcpu_load() was already called.
2140 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2142 return kvm_x86_ops->get_msr(vcpu, msr);
2144 EXPORT_SYMBOL_GPL(kvm_get_msr);
2146 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2149 u64 mcg_cap = vcpu->arch.mcg_cap;
2150 unsigned bank_num = mcg_cap & 0xff;
2153 case MSR_IA32_P5_MC_ADDR:
2154 case MSR_IA32_P5_MC_TYPE:
2157 case MSR_IA32_MCG_CAP:
2158 data = vcpu->arch.mcg_cap;
2160 case MSR_IA32_MCG_CTL:
2161 if (!(mcg_cap & MCG_CTL_P))
2163 data = vcpu->arch.mcg_ctl;
2165 case MSR_IA32_MCG_STATUS:
2166 data = vcpu->arch.mcg_status;
2169 if (msr >= MSR_IA32_MC0_CTL &&
2170 msr < MSR_IA32_MCx_CTL(bank_num)) {
2171 u32 offset = msr - MSR_IA32_MC0_CTL;
2172 data = vcpu->arch.mce_banks[offset];
2181 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2183 switch (msr_info->index) {
2184 case MSR_IA32_PLATFORM_ID:
2185 case MSR_IA32_EBL_CR_POWERON:
2186 case MSR_IA32_DEBUGCTLMSR:
2187 case MSR_IA32_LASTBRANCHFROMIP:
2188 case MSR_IA32_LASTBRANCHTOIP:
2189 case MSR_IA32_LASTINTFROMIP:
2190 case MSR_IA32_LASTINTTOIP:
2192 case MSR_K8_TSEG_ADDR:
2193 case MSR_K8_TSEG_MASK:
2195 case MSR_VM_HSAVE_PA:
2196 case MSR_K8_INT_PENDING_MSG:
2197 case MSR_AMD64_NB_CFG:
2198 case MSR_FAM10H_MMIO_CONF_BASE:
2199 case MSR_AMD64_BU_CFG2:
2202 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2203 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2204 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2205 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2206 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2207 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2210 case MSR_IA32_UCODE_REV:
2211 msr_info->data = 0x100000000ULL;
2214 case 0x200 ... 0x2ff:
2215 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2216 case 0xcd: /* fsb frequency */
2220 * MSR_EBC_FREQUENCY_ID
2221 * Conservative value valid for even the basic CPU models.
2222 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2223 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2224 * and 266MHz for model 3, or 4. Set Core Clock
2225 * Frequency to System Bus Frequency Ratio to 1 (bits
2226 * 31:24) even though these are only valid for CPU
2227 * models > 2, however guests may end up dividing or
2228 * multiplying by zero otherwise.
2230 case MSR_EBC_FREQUENCY_ID:
2231 msr_info->data = 1 << 24;
2233 case MSR_IA32_APICBASE:
2234 msr_info->data = kvm_get_apic_base(vcpu);
2236 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2237 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2239 case MSR_IA32_TSCDEADLINE:
2240 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2242 case MSR_IA32_TSC_ADJUST:
2243 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2245 case MSR_IA32_MISC_ENABLE:
2246 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2248 case MSR_IA32_SMBASE:
2249 if (!msr_info->host_initiated)
2251 msr_info->data = vcpu->arch.smbase;
2253 case MSR_IA32_PERF_STATUS:
2254 /* TSC increment by tick */
2255 msr_info->data = 1000ULL;
2256 /* CPU multiplier */
2257 msr_info->data |= (((uint64_t)4ULL) << 40);
2260 msr_info->data = vcpu->arch.efer;
2262 case MSR_KVM_WALL_CLOCK:
2263 case MSR_KVM_WALL_CLOCK_NEW:
2264 msr_info->data = vcpu->kvm->arch.wall_clock;
2266 case MSR_KVM_SYSTEM_TIME:
2267 case MSR_KVM_SYSTEM_TIME_NEW:
2268 msr_info->data = vcpu->arch.time;
2270 case MSR_KVM_ASYNC_PF_EN:
2271 msr_info->data = vcpu->arch.apf.msr_val;
2273 case MSR_KVM_STEAL_TIME:
2274 msr_info->data = vcpu->arch.st.msr_val;
2276 case MSR_KVM_PV_EOI_EN:
2277 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2279 case MSR_IA32_P5_MC_ADDR:
2280 case MSR_IA32_P5_MC_TYPE:
2281 case MSR_IA32_MCG_CAP:
2282 case MSR_IA32_MCG_CTL:
2283 case MSR_IA32_MCG_STATUS:
2284 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2285 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2286 case MSR_K7_CLK_CTL:
2288 * Provide expected ramp-up count for K7. All other
2289 * are set to zero, indicating minimum divisors for
2292 * This prevents guest kernels on AMD host with CPU
2293 * type 6, model 8 and higher from exploding due to
2294 * the rdmsr failing.
2296 msr_info->data = 0x20000000;
2298 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2299 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2300 case HV_X64_MSR_CRASH_CTL:
2301 return kvm_hv_get_msr_common(vcpu,
2302 msr_info->index, &msr_info->data);
2304 case MSR_IA32_BBL_CR_CTL3:
2305 /* This legacy MSR exists but isn't fully documented in current
2306 * silicon. It is however accessed by winxp in very narrow
2307 * scenarios where it sets bit #19, itself documented as
2308 * a "reserved" bit. Best effort attempt to source coherent
2309 * read data here should the balance of the register be
2310 * interpreted by the guest:
2312 * L2 cache control register 3: 64GB range, 256KB size,
2313 * enabled, latency 0x1, configured
2315 msr_info->data = 0xbe702111;
2317 case MSR_AMD64_OSVW_ID_LENGTH:
2318 if (!guest_cpuid_has_osvw(vcpu))
2320 msr_info->data = vcpu->arch.osvw.length;
2322 case MSR_AMD64_OSVW_STATUS:
2323 if (!guest_cpuid_has_osvw(vcpu))
2325 msr_info->data = vcpu->arch.osvw.status;
2328 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2329 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2331 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2334 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2341 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2344 * Read or write a bunch of msrs. All parameters are kernel addresses.
2346 * @return number of msrs set successfully.
2348 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2349 struct kvm_msr_entry *entries,
2350 int (*do_msr)(struct kvm_vcpu *vcpu,
2351 unsigned index, u64 *data))
2355 idx = srcu_read_lock(&vcpu->kvm->srcu);
2356 for (i = 0; i < msrs->nmsrs; ++i)
2357 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2359 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2365 * Read or write a bunch of msrs. Parameters are user addresses.
2367 * @return number of msrs set successfully.
2369 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2370 int (*do_msr)(struct kvm_vcpu *vcpu,
2371 unsigned index, u64 *data),
2374 struct kvm_msrs msrs;
2375 struct kvm_msr_entry *entries;
2380 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2384 if (msrs.nmsrs >= MAX_IO_MSRS)
2387 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2388 entries = memdup_user(user_msrs->entries, size);
2389 if (IS_ERR(entries)) {
2390 r = PTR_ERR(entries);
2394 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2399 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2410 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2415 case KVM_CAP_IRQCHIP:
2417 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2418 case KVM_CAP_SET_TSS_ADDR:
2419 case KVM_CAP_EXT_CPUID:
2420 case KVM_CAP_EXT_EMUL_CPUID:
2421 case KVM_CAP_CLOCKSOURCE:
2423 case KVM_CAP_NOP_IO_DELAY:
2424 case KVM_CAP_MP_STATE:
2425 case KVM_CAP_SYNC_MMU:
2426 case KVM_CAP_USER_NMI:
2427 case KVM_CAP_REINJECT_CONTROL:
2428 case KVM_CAP_IRQ_INJECT_STATUS:
2429 case KVM_CAP_IOEVENTFD:
2430 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2432 case KVM_CAP_PIT_STATE2:
2433 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2434 case KVM_CAP_XEN_HVM:
2435 case KVM_CAP_ADJUST_CLOCK:
2436 case KVM_CAP_VCPU_EVENTS:
2437 case KVM_CAP_HYPERV:
2438 case KVM_CAP_HYPERV_VAPIC:
2439 case KVM_CAP_HYPERV_SPIN:
2440 case KVM_CAP_PCI_SEGMENT:
2441 case KVM_CAP_DEBUGREGS:
2442 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2444 case KVM_CAP_ASYNC_PF:
2445 case KVM_CAP_GET_TSC_KHZ:
2446 case KVM_CAP_KVMCLOCK_CTRL:
2447 case KVM_CAP_READONLY_MEM:
2448 case KVM_CAP_HYPERV_TIME:
2449 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2450 case KVM_CAP_TSC_DEADLINE_TIMER:
2451 case KVM_CAP_ENABLE_CAP_VM:
2452 case KVM_CAP_DISABLE_QUIRKS:
2453 case KVM_CAP_SET_BOOT_CPU_ID:
2454 case KVM_CAP_SPLIT_IRQCHIP:
2455 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2456 case KVM_CAP_ASSIGN_DEV_IRQ:
2457 case KVM_CAP_PCI_2_3:
2461 case KVM_CAP_X86_SMM:
2462 /* SMBASE is usually relocated above 1M on modern chipsets,
2463 * and SMM handlers might indeed rely on 4G segment limits,
2464 * so do not report SMM to be available if real mode is
2465 * emulated via vm86 mode. Still, do not go to great lengths
2466 * to avoid userspace's usage of the feature, because it is a
2467 * fringe case that is not enabled except via specific settings
2468 * of the module parameters.
2470 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2472 case KVM_CAP_COALESCED_MMIO:
2473 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2476 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2478 case KVM_CAP_NR_VCPUS:
2479 r = KVM_SOFT_MAX_VCPUS;
2481 case KVM_CAP_MAX_VCPUS:
2484 case KVM_CAP_NR_MEMSLOTS:
2485 r = KVM_USER_MEM_SLOTS;
2487 case KVM_CAP_PV_MMU: /* obsolete */
2490 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2492 r = iommu_present(&pci_bus_type);
2496 r = KVM_MAX_MCE_BANKS;
2501 case KVM_CAP_TSC_CONTROL:
2502 r = kvm_has_tsc_control;
2512 long kvm_arch_dev_ioctl(struct file *filp,
2513 unsigned int ioctl, unsigned long arg)
2515 void __user *argp = (void __user *)arg;
2519 case KVM_GET_MSR_INDEX_LIST: {
2520 struct kvm_msr_list __user *user_msr_list = argp;
2521 struct kvm_msr_list msr_list;
2525 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2528 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2529 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2532 if (n < msr_list.nmsrs)
2535 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2536 num_msrs_to_save * sizeof(u32)))
2538 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2540 num_emulated_msrs * sizeof(u32)))
2545 case KVM_GET_SUPPORTED_CPUID:
2546 case KVM_GET_EMULATED_CPUID: {
2547 struct kvm_cpuid2 __user *cpuid_arg = argp;
2548 struct kvm_cpuid2 cpuid;
2551 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2554 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2560 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2565 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2568 mce_cap = KVM_MCE_CAP_SUPPORTED;
2570 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2582 static void wbinvd_ipi(void *garbage)
2587 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2589 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2592 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2594 /* Address WBINVD may be executed by guest */
2595 if (need_emulate_wbinvd(vcpu)) {
2596 if (kvm_x86_ops->has_wbinvd_exit())
2597 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2598 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2599 smp_call_function_single(vcpu->cpu,
2600 wbinvd_ipi, NULL, 1);
2603 kvm_x86_ops->vcpu_load(vcpu, cpu);
2605 /* Apply any externally detected TSC adjustments (due to suspend) */
2606 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2607 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2608 vcpu->arch.tsc_offset_adjustment = 0;
2609 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2612 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2613 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2614 rdtsc() - vcpu->arch.last_host_tsc;
2616 mark_tsc_unstable("KVM discovered backwards TSC");
2617 if (check_tsc_unstable()) {
2618 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2619 vcpu->arch.last_guest_tsc);
2620 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2621 vcpu->arch.tsc_catchup = 1;
2624 * On a host with synchronized TSC, there is no need to update
2625 * kvmclock on vcpu->cpu migration
2627 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2628 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2629 if (vcpu->cpu != cpu)
2630 kvm_migrate_timers(vcpu);
2634 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2637 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2639 kvm_x86_ops->vcpu_put(vcpu);
2640 kvm_put_guest_fpu(vcpu);
2641 vcpu->arch.last_host_tsc = rdtsc();
2644 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2645 struct kvm_lapic_state *s)
2647 kvm_x86_ops->sync_pir_to_irr(vcpu);
2648 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2653 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2654 struct kvm_lapic_state *s)
2656 kvm_apic_post_state_restore(vcpu, s);
2657 update_cr8_intercept(vcpu);
2662 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2663 struct kvm_interrupt *irq)
2665 if (irq->irq >= KVM_NR_INTERRUPTS)
2668 if (!irqchip_in_kernel(vcpu->kvm)) {
2669 kvm_queue_interrupt(vcpu, irq->irq, false);
2670 kvm_make_request(KVM_REQ_EVENT, vcpu);
2675 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2676 * fail for in-kernel 8259.
2678 if (pic_in_kernel(vcpu->kvm))
2681 if (vcpu->arch.pending_external_vector != -1)
2684 vcpu->arch.pending_external_vector = irq->irq;
2688 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2690 kvm_inject_nmi(vcpu);
2695 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2697 kvm_make_request(KVM_REQ_SMI, vcpu);
2702 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2703 struct kvm_tpr_access_ctl *tac)
2707 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2711 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2715 unsigned bank_num = mcg_cap & 0xff, bank;
2718 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2720 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2723 vcpu->arch.mcg_cap = mcg_cap;
2724 /* Init IA32_MCG_CTL to all 1s */
2725 if (mcg_cap & MCG_CTL_P)
2726 vcpu->arch.mcg_ctl = ~(u64)0;
2727 /* Init IA32_MCi_CTL to all 1s */
2728 for (bank = 0; bank < bank_num; bank++)
2729 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2734 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2735 struct kvm_x86_mce *mce)
2737 u64 mcg_cap = vcpu->arch.mcg_cap;
2738 unsigned bank_num = mcg_cap & 0xff;
2739 u64 *banks = vcpu->arch.mce_banks;
2741 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2744 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2745 * reporting is disabled
2747 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2748 vcpu->arch.mcg_ctl != ~(u64)0)
2750 banks += 4 * mce->bank;
2752 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2753 * reporting is disabled for the bank
2755 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2757 if (mce->status & MCI_STATUS_UC) {
2758 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2759 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2760 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2763 if (banks[1] & MCI_STATUS_VAL)
2764 mce->status |= MCI_STATUS_OVER;
2765 banks[2] = mce->addr;
2766 banks[3] = mce->misc;
2767 vcpu->arch.mcg_status = mce->mcg_status;
2768 banks[1] = mce->status;
2769 kvm_queue_exception(vcpu, MC_VECTOR);
2770 } else if (!(banks[1] & MCI_STATUS_VAL)
2771 || !(banks[1] & MCI_STATUS_UC)) {
2772 if (banks[1] & MCI_STATUS_VAL)
2773 mce->status |= MCI_STATUS_OVER;
2774 banks[2] = mce->addr;
2775 banks[3] = mce->misc;
2776 banks[1] = mce->status;
2778 banks[1] |= MCI_STATUS_OVER;
2782 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2783 struct kvm_vcpu_events *events)
2786 events->exception.injected =
2787 vcpu->arch.exception.pending &&
2788 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2789 events->exception.nr = vcpu->arch.exception.nr;
2790 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2791 events->exception.pad = 0;
2792 events->exception.error_code = vcpu->arch.exception.error_code;
2794 events->interrupt.injected =
2795 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2796 events->interrupt.nr = vcpu->arch.interrupt.nr;
2797 events->interrupt.soft = 0;
2798 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2800 events->nmi.injected = vcpu->arch.nmi_injected;
2801 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2802 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2803 events->nmi.pad = 0;
2805 events->sipi_vector = 0; /* never valid when reporting to user space */
2807 events->smi.smm = is_smm(vcpu);
2808 events->smi.pending = vcpu->arch.smi_pending;
2809 events->smi.smm_inside_nmi =
2810 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2811 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2813 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2814 | KVM_VCPUEVENT_VALID_SHADOW
2815 | KVM_VCPUEVENT_VALID_SMM);
2816 memset(&events->reserved, 0, sizeof(events->reserved));
2819 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2820 struct kvm_vcpu_events *events)
2822 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2823 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2824 | KVM_VCPUEVENT_VALID_SHADOW
2825 | KVM_VCPUEVENT_VALID_SMM))
2829 vcpu->arch.exception.pending = events->exception.injected;
2830 vcpu->arch.exception.nr = events->exception.nr;
2831 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2832 vcpu->arch.exception.error_code = events->exception.error_code;
2834 vcpu->arch.interrupt.pending = events->interrupt.injected;
2835 vcpu->arch.interrupt.nr = events->interrupt.nr;
2836 vcpu->arch.interrupt.soft = events->interrupt.soft;
2837 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2838 kvm_x86_ops->set_interrupt_shadow(vcpu,
2839 events->interrupt.shadow);
2841 vcpu->arch.nmi_injected = events->nmi.injected;
2842 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2843 vcpu->arch.nmi_pending = events->nmi.pending;
2844 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2846 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2847 kvm_vcpu_has_lapic(vcpu))
2848 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2850 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2851 if (events->smi.smm)
2852 vcpu->arch.hflags |= HF_SMM_MASK;
2854 vcpu->arch.hflags &= ~HF_SMM_MASK;
2855 vcpu->arch.smi_pending = events->smi.pending;
2856 if (events->smi.smm_inside_nmi)
2857 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2859 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2860 if (kvm_vcpu_has_lapic(vcpu)) {
2861 if (events->smi.latched_init)
2862 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2864 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2868 kvm_make_request(KVM_REQ_EVENT, vcpu);
2873 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2874 struct kvm_debugregs *dbgregs)
2878 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2879 kvm_get_dr(vcpu, 6, &val);
2881 dbgregs->dr7 = vcpu->arch.dr7;
2883 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2886 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2887 struct kvm_debugregs *dbgregs)
2892 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2893 kvm_update_dr0123(vcpu);
2894 vcpu->arch.dr6 = dbgregs->dr6;
2895 kvm_update_dr6(vcpu);
2896 vcpu->arch.dr7 = dbgregs->dr7;
2897 kvm_update_dr7(vcpu);
2902 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2904 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2906 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
2907 u64 xstate_bv = xsave->header.xfeatures;
2911 * Copy legacy XSAVE area, to avoid complications with CPUID
2912 * leaves 0 and 1 in the loop below.
2914 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2917 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2920 * Copy each region from the possibly compacted offset to the
2921 * non-compacted offset.
2923 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
2925 u64 feature = valid & -valid;
2926 int index = fls64(feature) - 1;
2927 void *src = get_xsave_addr(xsave, feature);
2930 u32 size, offset, ecx, edx;
2931 cpuid_count(XSTATE_CPUID, index,
2932 &size, &offset, &ecx, &edx);
2933 memcpy(dest + offset, src, size);
2940 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2942 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
2943 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2947 * Copy legacy XSAVE area, to avoid complications with CPUID
2948 * leaves 0 and 1 in the loop below.
2950 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2952 /* Set XSTATE_BV and possibly XCOMP_BV. */
2953 xsave->header.xfeatures = xstate_bv;
2955 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
2958 * Copy each region from the non-compacted offset to the
2959 * possibly compacted offset.
2961 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
2963 u64 feature = valid & -valid;
2964 int index = fls64(feature) - 1;
2965 void *dest = get_xsave_addr(xsave, feature);
2968 u32 size, offset, ecx, edx;
2969 cpuid_count(XSTATE_CPUID, index,
2970 &size, &offset, &ecx, &edx);
2971 memcpy(dest, src + offset, size);
2978 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2979 struct kvm_xsave *guest_xsave)
2981 if (cpu_has_xsave) {
2982 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2983 fill_xsave((u8 *) guest_xsave->region, vcpu);
2985 memcpy(guest_xsave->region,
2986 &vcpu->arch.guest_fpu.state.fxsave,
2987 sizeof(struct fxregs_state));
2988 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2989 XFEATURE_MASK_FPSSE;
2993 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2994 struct kvm_xsave *guest_xsave)
2997 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2999 if (cpu_has_xsave) {
3001 * Here we allow setting states that are not present in
3002 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3003 * with old userspace.
3005 if (xstate_bv & ~kvm_supported_xcr0())
3007 load_xsave(vcpu, (u8 *)guest_xsave->region);
3009 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3011 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3012 guest_xsave->region, sizeof(struct fxregs_state));
3017 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3018 struct kvm_xcrs *guest_xcrs)
3020 if (!cpu_has_xsave) {
3021 guest_xcrs->nr_xcrs = 0;
3025 guest_xcrs->nr_xcrs = 1;
3026 guest_xcrs->flags = 0;
3027 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3028 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3031 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3032 struct kvm_xcrs *guest_xcrs)
3039 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3042 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3043 /* Only support XCR0 currently */
3044 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3045 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3046 guest_xcrs->xcrs[i].value);
3055 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3056 * stopped by the hypervisor. This function will be called from the host only.
3057 * EINVAL is returned when the host attempts to set the flag for a guest that
3058 * does not support pv clocks.
3060 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3062 if (!vcpu->arch.pv_time_enabled)
3064 vcpu->arch.pvclock_set_guest_stopped_request = true;
3065 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3069 long kvm_arch_vcpu_ioctl(struct file *filp,
3070 unsigned int ioctl, unsigned long arg)
3072 struct kvm_vcpu *vcpu = filp->private_data;
3073 void __user *argp = (void __user *)arg;
3076 struct kvm_lapic_state *lapic;
3077 struct kvm_xsave *xsave;
3078 struct kvm_xcrs *xcrs;
3084 case KVM_GET_LAPIC: {
3086 if (!vcpu->arch.apic)
3088 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3093 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3097 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3102 case KVM_SET_LAPIC: {
3104 if (!vcpu->arch.apic)
3106 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3107 if (IS_ERR(u.lapic))
3108 return PTR_ERR(u.lapic);
3110 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3113 case KVM_INTERRUPT: {
3114 struct kvm_interrupt irq;
3117 if (copy_from_user(&irq, argp, sizeof irq))
3119 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3123 r = kvm_vcpu_ioctl_nmi(vcpu);
3127 r = kvm_vcpu_ioctl_smi(vcpu);
3130 case KVM_SET_CPUID: {
3131 struct kvm_cpuid __user *cpuid_arg = argp;
3132 struct kvm_cpuid cpuid;
3135 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3137 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3140 case KVM_SET_CPUID2: {
3141 struct kvm_cpuid2 __user *cpuid_arg = argp;
3142 struct kvm_cpuid2 cpuid;
3145 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3147 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3148 cpuid_arg->entries);
3151 case KVM_GET_CPUID2: {
3152 struct kvm_cpuid2 __user *cpuid_arg = argp;
3153 struct kvm_cpuid2 cpuid;
3156 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3158 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3159 cpuid_arg->entries);
3163 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3169 r = msr_io(vcpu, argp, do_get_msr, 1);
3172 r = msr_io(vcpu, argp, do_set_msr, 0);
3174 case KVM_TPR_ACCESS_REPORTING: {
3175 struct kvm_tpr_access_ctl tac;
3178 if (copy_from_user(&tac, argp, sizeof tac))
3180 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3184 if (copy_to_user(argp, &tac, sizeof tac))
3189 case KVM_SET_VAPIC_ADDR: {
3190 struct kvm_vapic_addr va;
3193 if (!lapic_in_kernel(vcpu))
3196 if (copy_from_user(&va, argp, sizeof va))
3198 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3201 case KVM_X86_SETUP_MCE: {
3205 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3207 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3210 case KVM_X86_SET_MCE: {
3211 struct kvm_x86_mce mce;
3214 if (copy_from_user(&mce, argp, sizeof mce))
3216 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3219 case KVM_GET_VCPU_EVENTS: {
3220 struct kvm_vcpu_events events;
3222 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3225 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3230 case KVM_SET_VCPU_EVENTS: {
3231 struct kvm_vcpu_events events;
3234 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3237 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3240 case KVM_GET_DEBUGREGS: {
3241 struct kvm_debugregs dbgregs;
3243 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3246 if (copy_to_user(argp, &dbgregs,
3247 sizeof(struct kvm_debugregs)))
3252 case KVM_SET_DEBUGREGS: {
3253 struct kvm_debugregs dbgregs;
3256 if (copy_from_user(&dbgregs, argp,
3257 sizeof(struct kvm_debugregs)))
3260 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3263 case KVM_GET_XSAVE: {
3264 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3269 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3272 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3277 case KVM_SET_XSAVE: {
3278 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3279 if (IS_ERR(u.xsave))
3280 return PTR_ERR(u.xsave);
3282 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3285 case KVM_GET_XCRS: {
3286 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3291 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3294 if (copy_to_user(argp, u.xcrs,
3295 sizeof(struct kvm_xcrs)))
3300 case KVM_SET_XCRS: {
3301 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3303 return PTR_ERR(u.xcrs);
3305 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3308 case KVM_SET_TSC_KHZ: {
3312 user_tsc_khz = (u32)arg;
3314 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3317 if (user_tsc_khz == 0)
3318 user_tsc_khz = tsc_khz;
3320 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3325 case KVM_GET_TSC_KHZ: {
3326 r = vcpu->arch.virtual_tsc_khz;
3329 case KVM_KVMCLOCK_CTRL: {
3330 r = kvm_set_guest_paused(vcpu);
3341 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3343 return VM_FAULT_SIGBUS;
3346 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3350 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3352 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3356 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3359 kvm->arch.ept_identity_map_addr = ident_addr;
3363 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3364 u32 kvm_nr_mmu_pages)
3366 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3369 mutex_lock(&kvm->slots_lock);
3371 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3372 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3374 mutex_unlock(&kvm->slots_lock);
3378 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3380 return kvm->arch.n_max_mmu_pages;
3383 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3388 switch (chip->chip_id) {
3389 case KVM_IRQCHIP_PIC_MASTER:
3390 memcpy(&chip->chip.pic,
3391 &pic_irqchip(kvm)->pics[0],
3392 sizeof(struct kvm_pic_state));
3394 case KVM_IRQCHIP_PIC_SLAVE:
3395 memcpy(&chip->chip.pic,
3396 &pic_irqchip(kvm)->pics[1],
3397 sizeof(struct kvm_pic_state));
3399 case KVM_IRQCHIP_IOAPIC:
3400 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3409 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3414 switch (chip->chip_id) {
3415 case KVM_IRQCHIP_PIC_MASTER:
3416 spin_lock(&pic_irqchip(kvm)->lock);
3417 memcpy(&pic_irqchip(kvm)->pics[0],
3419 sizeof(struct kvm_pic_state));
3420 spin_unlock(&pic_irqchip(kvm)->lock);
3422 case KVM_IRQCHIP_PIC_SLAVE:
3423 spin_lock(&pic_irqchip(kvm)->lock);
3424 memcpy(&pic_irqchip(kvm)->pics[1],
3426 sizeof(struct kvm_pic_state));
3427 spin_unlock(&pic_irqchip(kvm)->lock);
3429 case KVM_IRQCHIP_IOAPIC:
3430 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3436 kvm_pic_update_irq(pic_irqchip(kvm));
3440 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3444 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3445 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3446 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3450 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3454 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3455 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3456 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3457 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3461 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3465 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3466 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3467 sizeof(ps->channels));
3468 ps->flags = kvm->arch.vpit->pit_state.flags;
3469 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3470 memset(&ps->reserved, 0, sizeof(ps->reserved));
3474 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3476 int r = 0, start = 0;
3477 u32 prev_legacy, cur_legacy;
3478 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3479 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3480 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3481 if (!prev_legacy && cur_legacy)
3483 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3484 sizeof(kvm->arch.vpit->pit_state.channels));
3485 kvm->arch.vpit->pit_state.flags = ps->flags;
3486 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3487 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3491 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3492 struct kvm_reinject_control *control)
3494 if (!kvm->arch.vpit)
3496 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3497 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3498 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3503 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3504 * @kvm: kvm instance
3505 * @log: slot id and address to which we copy the log
3507 * Steps 1-4 below provide general overview of dirty page logging. See
3508 * kvm_get_dirty_log_protect() function description for additional details.
3510 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3511 * always flush the TLB (step 4) even if previous step failed and the dirty
3512 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3513 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3514 * writes will be marked dirty for next log read.
3516 * 1. Take a snapshot of the bit and clear it if needed.
3517 * 2. Write protect the corresponding page.
3518 * 3. Copy the snapshot to the userspace.
3519 * 4. Flush TLB's if needed.
3521 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3523 bool is_dirty = false;
3526 mutex_lock(&kvm->slots_lock);
3529 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3531 if (kvm_x86_ops->flush_log_dirty)
3532 kvm_x86_ops->flush_log_dirty(kvm);
3534 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3537 * All the TLBs can be flushed out of mmu lock, see the comments in
3538 * kvm_mmu_slot_remove_write_access().
3540 lockdep_assert_held(&kvm->slots_lock);
3542 kvm_flush_remote_tlbs(kvm);
3544 mutex_unlock(&kvm->slots_lock);
3548 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3551 if (!irqchip_in_kernel(kvm))
3554 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3555 irq_event->irq, irq_event->level,
3560 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3561 struct kvm_enable_cap *cap)
3569 case KVM_CAP_DISABLE_QUIRKS:
3570 kvm->arch.disabled_quirks = cap->args[0];
3573 case KVM_CAP_SPLIT_IRQCHIP: {
3574 mutex_lock(&kvm->lock);
3576 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3577 goto split_irqchip_unlock;
3579 if (irqchip_in_kernel(kvm))
3580 goto split_irqchip_unlock;
3581 if (atomic_read(&kvm->online_vcpus))
3582 goto split_irqchip_unlock;
3583 r = kvm_setup_empty_irq_routing(kvm);
3585 goto split_irqchip_unlock;
3586 /* Pairs with irqchip_in_kernel. */
3588 kvm->arch.irqchip_split = true;
3589 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3591 split_irqchip_unlock:
3592 mutex_unlock(&kvm->lock);
3602 long kvm_arch_vm_ioctl(struct file *filp,
3603 unsigned int ioctl, unsigned long arg)
3605 struct kvm *kvm = filp->private_data;
3606 void __user *argp = (void __user *)arg;
3609 * This union makes it completely explicit to gcc-3.x
3610 * that these two variables' stack usage should be
3611 * combined, not added together.
3614 struct kvm_pit_state ps;
3615 struct kvm_pit_state2 ps2;
3616 struct kvm_pit_config pit_config;
3620 case KVM_SET_TSS_ADDR:
3621 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3623 case KVM_SET_IDENTITY_MAP_ADDR: {
3627 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3629 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3632 case KVM_SET_NR_MMU_PAGES:
3633 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3635 case KVM_GET_NR_MMU_PAGES:
3636 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3638 case KVM_CREATE_IRQCHIP: {
3639 struct kvm_pic *vpic;
3641 mutex_lock(&kvm->lock);
3644 goto create_irqchip_unlock;
3646 if (atomic_read(&kvm->online_vcpus))
3647 goto create_irqchip_unlock;
3649 vpic = kvm_create_pic(kvm);
3651 r = kvm_ioapic_init(kvm);
3653 mutex_lock(&kvm->slots_lock);
3654 kvm_destroy_pic(vpic);
3655 mutex_unlock(&kvm->slots_lock);
3656 goto create_irqchip_unlock;
3659 goto create_irqchip_unlock;
3660 r = kvm_setup_default_irq_routing(kvm);
3662 mutex_lock(&kvm->slots_lock);
3663 mutex_lock(&kvm->irq_lock);
3664 kvm_ioapic_destroy(kvm);
3665 kvm_destroy_pic(vpic);
3666 mutex_unlock(&kvm->irq_lock);
3667 mutex_unlock(&kvm->slots_lock);
3668 goto create_irqchip_unlock;
3670 /* Write kvm->irq_routing before kvm->arch.vpic. */
3672 kvm->arch.vpic = vpic;
3673 create_irqchip_unlock:
3674 mutex_unlock(&kvm->lock);
3677 case KVM_CREATE_PIT:
3678 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3680 case KVM_CREATE_PIT2:
3682 if (copy_from_user(&u.pit_config, argp,
3683 sizeof(struct kvm_pit_config)))
3686 mutex_lock(&kvm->slots_lock);
3689 goto create_pit_unlock;
3691 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3695 mutex_unlock(&kvm->slots_lock);
3697 case KVM_GET_IRQCHIP: {
3698 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3699 struct kvm_irqchip *chip;
3701 chip = memdup_user(argp, sizeof(*chip));
3708 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3709 goto get_irqchip_out;
3710 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3712 goto get_irqchip_out;
3714 if (copy_to_user(argp, chip, sizeof *chip))
3715 goto get_irqchip_out;
3721 case KVM_SET_IRQCHIP: {
3722 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3723 struct kvm_irqchip *chip;
3725 chip = memdup_user(argp, sizeof(*chip));
3732 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3733 goto set_irqchip_out;
3734 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3736 goto set_irqchip_out;
3744 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3747 if (!kvm->arch.vpit)
3749 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3753 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3760 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3763 if (!kvm->arch.vpit)
3765 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3768 case KVM_GET_PIT2: {
3770 if (!kvm->arch.vpit)
3772 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3776 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3781 case KVM_SET_PIT2: {
3783 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3786 if (!kvm->arch.vpit)
3788 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3791 case KVM_REINJECT_CONTROL: {
3792 struct kvm_reinject_control control;
3794 if (copy_from_user(&control, argp, sizeof(control)))
3796 r = kvm_vm_ioctl_reinject(kvm, &control);
3799 case KVM_SET_BOOT_CPU_ID:
3801 mutex_lock(&kvm->lock);
3802 if (atomic_read(&kvm->online_vcpus) != 0)
3805 kvm->arch.bsp_vcpu_id = arg;
3806 mutex_unlock(&kvm->lock);
3808 case KVM_XEN_HVM_CONFIG: {
3810 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3811 sizeof(struct kvm_xen_hvm_config)))
3814 if (kvm->arch.xen_hvm_config.flags)
3819 case KVM_SET_CLOCK: {
3820 struct kvm_clock_data user_ns;
3825 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3833 local_irq_disable();
3834 now_ns = get_kernel_ns();
3835 delta = user_ns.clock - now_ns;
3837 kvm->arch.kvmclock_offset = delta;
3838 kvm_gen_update_masterclock(kvm);
3841 case KVM_GET_CLOCK: {
3842 struct kvm_clock_data user_ns;
3845 local_irq_disable();
3846 now_ns = get_kernel_ns();
3847 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3850 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3853 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3858 case KVM_ENABLE_CAP: {
3859 struct kvm_enable_cap cap;
3862 if (copy_from_user(&cap, argp, sizeof(cap)))
3864 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3868 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
3874 static void kvm_init_msr_list(void)
3879 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
3880 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3884 * Even MSRs that are valid in the host may not be exposed
3885 * to the guests in some cases. We could work around this
3886 * in VMX with the generic MSR save/load machinery, but it
3887 * is not really worthwhile since it will really only
3888 * happen with nested virtualization.
3890 switch (msrs_to_save[i]) {
3891 case MSR_IA32_BNDCFGS:
3892 if (!kvm_x86_ops->mpx_supported())
3900 msrs_to_save[j] = msrs_to_save[i];
3903 num_msrs_to_save = j;
3905 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3906 switch (emulated_msrs[i]) {
3907 case MSR_IA32_SMBASE:
3908 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3916 emulated_msrs[j] = emulated_msrs[i];
3919 num_emulated_msrs = j;
3922 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3930 if (!(vcpu->arch.apic &&
3931 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3932 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
3943 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3950 if (!(vcpu->arch.apic &&
3951 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3953 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
3955 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3965 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3966 struct kvm_segment *var, int seg)
3968 kvm_x86_ops->set_segment(vcpu, var, seg);
3971 void kvm_get_segment(struct kvm_vcpu *vcpu,
3972 struct kvm_segment *var, int seg)
3974 kvm_x86_ops->get_segment(vcpu, var, seg);
3977 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3978 struct x86_exception *exception)
3982 BUG_ON(!mmu_is_nested(vcpu));
3984 /* NPT walks are always user-walks */
3985 access |= PFERR_USER_MASK;
3986 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
3991 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3992 struct x86_exception *exception)
3994 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3995 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3998 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3999 struct x86_exception *exception)
4001 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4002 access |= PFERR_FETCH_MASK;
4003 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4006 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4007 struct x86_exception *exception)
4009 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4010 access |= PFERR_WRITE_MASK;
4011 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4014 /* uses this to access any guest's mapped memory without checking CPL */
4015 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4016 struct x86_exception *exception)
4018 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4021 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4022 struct kvm_vcpu *vcpu, u32 access,
4023 struct x86_exception *exception)
4026 int r = X86EMUL_CONTINUE;
4029 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4031 unsigned offset = addr & (PAGE_SIZE-1);
4032 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4035 if (gpa == UNMAPPED_GVA)
4036 return X86EMUL_PROPAGATE_FAULT;
4037 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4040 r = X86EMUL_IO_NEEDED;
4052 /* used for instruction fetching */
4053 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4054 gva_t addr, void *val, unsigned int bytes,
4055 struct x86_exception *exception)
4057 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4058 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4062 /* Inline kvm_read_guest_virt_helper for speed. */
4063 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4065 if (unlikely(gpa == UNMAPPED_GVA))
4066 return X86EMUL_PROPAGATE_FAULT;
4068 offset = addr & (PAGE_SIZE-1);
4069 if (WARN_ON(offset + bytes > PAGE_SIZE))
4070 bytes = (unsigned)PAGE_SIZE - offset;
4071 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4073 if (unlikely(ret < 0))
4074 return X86EMUL_IO_NEEDED;
4076 return X86EMUL_CONTINUE;
4079 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4080 gva_t addr, void *val, unsigned int bytes,
4081 struct x86_exception *exception)
4083 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4084 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4086 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4089 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4091 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4092 gva_t addr, void *val, unsigned int bytes,
4093 struct x86_exception *exception)
4095 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4096 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4099 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4100 gva_t addr, void *val,
4102 struct x86_exception *exception)
4104 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4106 int r = X86EMUL_CONTINUE;
4109 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4112 unsigned offset = addr & (PAGE_SIZE-1);
4113 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4116 if (gpa == UNMAPPED_GVA)
4117 return X86EMUL_PROPAGATE_FAULT;
4118 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4120 r = X86EMUL_IO_NEEDED;
4131 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4133 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4134 gpa_t *gpa, struct x86_exception *exception,
4137 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4138 | (write ? PFERR_WRITE_MASK : 0);
4140 if (vcpu_match_mmio_gva(vcpu, gva)
4141 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4142 vcpu->arch.access, access)) {
4143 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4144 (gva & (PAGE_SIZE - 1));
4145 trace_vcpu_match_mmio(gva, *gpa, write, false);
4149 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4151 if (*gpa == UNMAPPED_GVA)
4154 /* For APIC access vmexit */
4155 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4158 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4159 trace_vcpu_match_mmio(gva, *gpa, write, true);
4166 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4167 const void *val, int bytes)
4171 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4174 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4178 struct read_write_emulator_ops {
4179 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4181 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4182 void *val, int bytes);
4183 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4184 int bytes, void *val);
4185 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4186 void *val, int bytes);
4190 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4192 if (vcpu->mmio_read_completed) {
4193 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4194 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4195 vcpu->mmio_read_completed = 0;
4202 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4203 void *val, int bytes)
4205 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4208 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4209 void *val, int bytes)
4211 return emulator_write_phys(vcpu, gpa, val, bytes);
4214 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4216 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4217 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4220 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4221 void *val, int bytes)
4223 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4224 return X86EMUL_IO_NEEDED;
4227 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4228 void *val, int bytes)
4230 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4232 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4233 return X86EMUL_CONTINUE;
4236 static const struct read_write_emulator_ops read_emultor = {
4237 .read_write_prepare = read_prepare,
4238 .read_write_emulate = read_emulate,
4239 .read_write_mmio = vcpu_mmio_read,
4240 .read_write_exit_mmio = read_exit_mmio,
4243 static const struct read_write_emulator_ops write_emultor = {
4244 .read_write_emulate = write_emulate,
4245 .read_write_mmio = write_mmio,
4246 .read_write_exit_mmio = write_exit_mmio,
4250 static int emulator_read_write_onepage(unsigned long addr, void *val,
4252 struct x86_exception *exception,
4253 struct kvm_vcpu *vcpu,
4254 const struct read_write_emulator_ops *ops)
4258 bool write = ops->write;
4259 struct kvm_mmio_fragment *frag;
4261 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4264 return X86EMUL_PROPAGATE_FAULT;
4266 /* For APIC access vmexit */
4270 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4271 return X86EMUL_CONTINUE;
4275 * Is this MMIO handled locally?
4277 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4278 if (handled == bytes)
4279 return X86EMUL_CONTINUE;
4285 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4286 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4290 return X86EMUL_CONTINUE;
4293 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4295 void *val, unsigned int bytes,
4296 struct x86_exception *exception,
4297 const struct read_write_emulator_ops *ops)
4299 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4303 if (ops->read_write_prepare &&
4304 ops->read_write_prepare(vcpu, val, bytes))
4305 return X86EMUL_CONTINUE;
4307 vcpu->mmio_nr_fragments = 0;
4309 /* Crossing a page boundary? */
4310 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4313 now = -addr & ~PAGE_MASK;
4314 rc = emulator_read_write_onepage(addr, val, now, exception,
4317 if (rc != X86EMUL_CONTINUE)
4320 if (ctxt->mode != X86EMUL_MODE_PROT64)
4326 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4328 if (rc != X86EMUL_CONTINUE)
4331 if (!vcpu->mmio_nr_fragments)
4334 gpa = vcpu->mmio_fragments[0].gpa;
4336 vcpu->mmio_needed = 1;
4337 vcpu->mmio_cur_fragment = 0;
4339 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4340 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4341 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4342 vcpu->run->mmio.phys_addr = gpa;
4344 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4347 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4351 struct x86_exception *exception)
4353 return emulator_read_write(ctxt, addr, val, bytes,
4354 exception, &read_emultor);
4357 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4361 struct x86_exception *exception)
4363 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4364 exception, &write_emultor);
4367 #define CMPXCHG_TYPE(t, ptr, old, new) \
4368 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4370 #ifdef CONFIG_X86_64
4371 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4373 # define CMPXCHG64(ptr, old, new) \
4374 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4377 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4382 struct x86_exception *exception)
4384 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4390 /* guests cmpxchg8b have to be emulated atomically */
4391 if (bytes > 8 || (bytes & (bytes - 1)))
4394 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4396 if (gpa == UNMAPPED_GVA ||
4397 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4400 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4403 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4404 if (is_error_page(page))
4407 kaddr = kmap_atomic(page);
4408 kaddr += offset_in_page(gpa);
4411 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4414 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4417 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4420 exchanged = CMPXCHG64(kaddr, old, new);
4425 kunmap_atomic(kaddr);
4426 kvm_release_page_dirty(page);
4429 return X86EMUL_CMPXCHG_FAILED;
4431 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4432 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4434 return X86EMUL_CONTINUE;
4437 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4439 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4442 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4444 /* TODO: String I/O for in kernel device */
4447 if (vcpu->arch.pio.in)
4448 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4449 vcpu->arch.pio.size, pd);
4451 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4452 vcpu->arch.pio.port, vcpu->arch.pio.size,
4457 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4458 unsigned short port, void *val,
4459 unsigned int count, bool in)
4461 vcpu->arch.pio.port = port;
4462 vcpu->arch.pio.in = in;
4463 vcpu->arch.pio.count = count;
4464 vcpu->arch.pio.size = size;
4466 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4467 vcpu->arch.pio.count = 0;
4471 vcpu->run->exit_reason = KVM_EXIT_IO;
4472 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4473 vcpu->run->io.size = size;
4474 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4475 vcpu->run->io.count = count;
4476 vcpu->run->io.port = port;
4481 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4482 int size, unsigned short port, void *val,
4485 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4488 if (vcpu->arch.pio.count)
4491 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4494 memcpy(val, vcpu->arch.pio_data, size * count);
4495 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4496 vcpu->arch.pio.count = 0;
4503 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4504 int size, unsigned short port,
4505 const void *val, unsigned int count)
4507 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4509 memcpy(vcpu->arch.pio_data, val, size * count);
4510 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4511 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4514 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4516 return kvm_x86_ops->get_segment_base(vcpu, seg);
4519 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4521 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4524 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4526 if (!need_emulate_wbinvd(vcpu))
4527 return X86EMUL_CONTINUE;
4529 if (kvm_x86_ops->has_wbinvd_exit()) {
4530 int cpu = get_cpu();
4532 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4533 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4534 wbinvd_ipi, NULL, 1);
4536 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4539 return X86EMUL_CONTINUE;
4542 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4544 kvm_x86_ops->skip_emulated_instruction(vcpu);
4545 return kvm_emulate_wbinvd_noskip(vcpu);
4547 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4551 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4553 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4556 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4557 unsigned long *dest)
4559 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4562 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4563 unsigned long value)
4566 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4569 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4571 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4574 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4576 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4577 unsigned long value;
4581 value = kvm_read_cr0(vcpu);
4584 value = vcpu->arch.cr2;
4587 value = kvm_read_cr3(vcpu);
4590 value = kvm_read_cr4(vcpu);
4593 value = kvm_get_cr8(vcpu);
4596 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4603 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4605 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4610 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4613 vcpu->arch.cr2 = val;
4616 res = kvm_set_cr3(vcpu, val);
4619 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4622 res = kvm_set_cr8(vcpu, val);
4625 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4632 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4634 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4637 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4639 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4642 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4644 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4647 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4649 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4652 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4654 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4657 static unsigned long emulator_get_cached_segment_base(
4658 struct x86_emulate_ctxt *ctxt, int seg)
4660 return get_segment_base(emul_to_vcpu(ctxt), seg);
4663 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4664 struct desc_struct *desc, u32 *base3,
4667 struct kvm_segment var;
4669 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4670 *selector = var.selector;
4673 memset(desc, 0, sizeof(*desc));
4679 set_desc_limit(desc, var.limit);
4680 set_desc_base(desc, (unsigned long)var.base);
4681 #ifdef CONFIG_X86_64
4683 *base3 = var.base >> 32;
4685 desc->type = var.type;
4687 desc->dpl = var.dpl;
4688 desc->p = var.present;
4689 desc->avl = var.avl;
4697 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4698 struct desc_struct *desc, u32 base3,
4701 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4702 struct kvm_segment var;
4704 var.selector = selector;
4705 var.base = get_desc_base(desc);
4706 #ifdef CONFIG_X86_64
4707 var.base |= ((u64)base3) << 32;
4709 var.limit = get_desc_limit(desc);
4711 var.limit = (var.limit << 12) | 0xfff;
4712 var.type = desc->type;
4713 var.dpl = desc->dpl;
4718 var.avl = desc->avl;
4719 var.present = desc->p;
4720 var.unusable = !var.present;
4723 kvm_set_segment(vcpu, &var, seg);
4727 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4728 u32 msr_index, u64 *pdata)
4730 struct msr_data msr;
4733 msr.index = msr_index;
4734 msr.host_initiated = false;
4735 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4743 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4744 u32 msr_index, u64 data)
4746 struct msr_data msr;
4749 msr.index = msr_index;
4750 msr.host_initiated = false;
4751 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4754 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4756 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4758 return vcpu->arch.smbase;
4761 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4763 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4765 vcpu->arch.smbase = smbase;
4768 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4771 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4774 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4775 u32 pmc, u64 *pdata)
4777 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4780 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4782 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4785 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4788 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4790 * CR0.TS may reference the host fpu state, not the guest fpu state,
4791 * so it may be clear at this point.
4796 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4801 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4802 struct x86_instruction_info *info,
4803 enum x86_intercept_stage stage)
4805 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4808 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4809 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4811 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4814 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4816 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4819 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4821 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4824 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4826 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4829 static const struct x86_emulate_ops emulate_ops = {
4830 .read_gpr = emulator_read_gpr,
4831 .write_gpr = emulator_write_gpr,
4832 .read_std = kvm_read_guest_virt_system,
4833 .write_std = kvm_write_guest_virt_system,
4834 .fetch = kvm_fetch_guest_virt,
4835 .read_emulated = emulator_read_emulated,
4836 .write_emulated = emulator_write_emulated,
4837 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4838 .invlpg = emulator_invlpg,
4839 .pio_in_emulated = emulator_pio_in_emulated,
4840 .pio_out_emulated = emulator_pio_out_emulated,
4841 .get_segment = emulator_get_segment,
4842 .set_segment = emulator_set_segment,
4843 .get_cached_segment_base = emulator_get_cached_segment_base,
4844 .get_gdt = emulator_get_gdt,
4845 .get_idt = emulator_get_idt,
4846 .set_gdt = emulator_set_gdt,
4847 .set_idt = emulator_set_idt,
4848 .get_cr = emulator_get_cr,
4849 .set_cr = emulator_set_cr,
4850 .cpl = emulator_get_cpl,
4851 .get_dr = emulator_get_dr,
4852 .set_dr = emulator_set_dr,
4853 .get_smbase = emulator_get_smbase,
4854 .set_smbase = emulator_set_smbase,
4855 .set_msr = emulator_set_msr,
4856 .get_msr = emulator_get_msr,
4857 .check_pmc = emulator_check_pmc,
4858 .read_pmc = emulator_read_pmc,
4859 .halt = emulator_halt,
4860 .wbinvd = emulator_wbinvd,
4861 .fix_hypercall = emulator_fix_hypercall,
4862 .get_fpu = emulator_get_fpu,
4863 .put_fpu = emulator_put_fpu,
4864 .intercept = emulator_intercept,
4865 .get_cpuid = emulator_get_cpuid,
4866 .set_nmi_mask = emulator_set_nmi_mask,
4869 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4871 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
4873 * an sti; sti; sequence only disable interrupts for the first
4874 * instruction. So, if the last instruction, be it emulated or
4875 * not, left the system with the INT_STI flag enabled, it
4876 * means that the last instruction is an sti. We should not
4877 * leave the flag on in this case. The same goes for mov ss
4879 if (int_shadow & mask)
4881 if (unlikely(int_shadow || mask)) {
4882 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4884 kvm_make_request(KVM_REQ_EVENT, vcpu);
4888 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
4890 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4891 if (ctxt->exception.vector == PF_VECTOR)
4892 return kvm_propagate_fault(vcpu, &ctxt->exception);
4894 if (ctxt->exception.error_code_valid)
4895 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4896 ctxt->exception.error_code);
4898 kvm_queue_exception(vcpu, ctxt->exception.vector);
4902 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4904 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4907 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4909 ctxt->eflags = kvm_get_rflags(vcpu);
4910 ctxt->eip = kvm_rip_read(vcpu);
4911 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4912 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4913 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
4914 cs_db ? X86EMUL_MODE_PROT32 :
4915 X86EMUL_MODE_PROT16;
4916 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
4917 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4918 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
4919 ctxt->emul_flags = vcpu->arch.hflags;
4921 init_decode_cache(ctxt);
4922 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4925 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4927 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4930 init_emulate_ctxt(vcpu);
4934 ctxt->_eip = ctxt->eip + inc_eip;
4935 ret = emulate_int_real(ctxt, irq);
4937 if (ret != X86EMUL_CONTINUE)
4938 return EMULATE_FAIL;
4940 ctxt->eip = ctxt->_eip;
4941 kvm_rip_write(vcpu, ctxt->eip);
4942 kvm_set_rflags(vcpu, ctxt->eflags);
4944 if (irq == NMI_VECTOR)
4945 vcpu->arch.nmi_pending = 0;
4947 vcpu->arch.interrupt.pending = false;
4949 return EMULATE_DONE;
4951 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4953 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4955 int r = EMULATE_DONE;
4957 ++vcpu->stat.insn_emulation_fail;
4958 trace_kvm_emulate_insn_failed(vcpu);
4959 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
4960 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4961 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4962 vcpu->run->internal.ndata = 0;
4965 kvm_queue_exception(vcpu, UD_VECTOR);
4970 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4971 bool write_fault_to_shadow_pgtable,
4977 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4980 if (!vcpu->arch.mmu.direct_map) {
4982 * Write permission should be allowed since only
4983 * write access need to be emulated.
4985 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4988 * If the mapping is invalid in guest, let cpu retry
4989 * it to generate fault.
4991 if (gpa == UNMAPPED_GVA)
4996 * Do not retry the unhandleable instruction if it faults on the
4997 * readonly host memory, otherwise it will goto a infinite loop:
4998 * retry instruction -> write #PF -> emulation fail -> retry
4999 * instruction -> ...
5001 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5004 * If the instruction failed on the error pfn, it can not be fixed,
5005 * report the error to userspace.
5007 if (is_error_noslot_pfn(pfn))
5010 kvm_release_pfn_clean(pfn);
5012 /* The instructions are well-emulated on direct mmu. */
5013 if (vcpu->arch.mmu.direct_map) {
5014 unsigned int indirect_shadow_pages;
5016 spin_lock(&vcpu->kvm->mmu_lock);
5017 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5018 spin_unlock(&vcpu->kvm->mmu_lock);
5020 if (indirect_shadow_pages)
5021 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5027 * if emulation was due to access to shadowed page table
5028 * and it failed try to unshadow page and re-enter the
5029 * guest to let CPU execute the instruction.
5031 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5034 * If the access faults on its page table, it can not
5035 * be fixed by unprotecting shadow page and it should
5036 * be reported to userspace.
5038 return !write_fault_to_shadow_pgtable;
5041 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5042 unsigned long cr2, int emulation_type)
5044 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5045 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5047 last_retry_eip = vcpu->arch.last_retry_eip;
5048 last_retry_addr = vcpu->arch.last_retry_addr;
5051 * If the emulation is caused by #PF and it is non-page_table
5052 * writing instruction, it means the VM-EXIT is caused by shadow
5053 * page protected, we can zap the shadow page and retry this
5054 * instruction directly.
5056 * Note: if the guest uses a non-page-table modifying instruction
5057 * on the PDE that points to the instruction, then we will unmap
5058 * the instruction and go to an infinite loop. So, we cache the
5059 * last retried eip and the last fault address, if we meet the eip
5060 * and the address again, we can break out of the potential infinite
5063 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5065 if (!(emulation_type & EMULTYPE_RETRY))
5068 if (x86_page_table_writing_insn(ctxt))
5071 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5074 vcpu->arch.last_retry_eip = ctxt->eip;
5075 vcpu->arch.last_retry_addr = cr2;
5077 if (!vcpu->arch.mmu.direct_map)
5078 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5080 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5085 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5086 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5088 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5090 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5091 /* This is a good place to trace that we are exiting SMM. */
5092 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5094 if (unlikely(vcpu->arch.smi_pending)) {
5095 kvm_make_request(KVM_REQ_SMI, vcpu);
5096 vcpu->arch.smi_pending = 0;
5098 /* Process a latched INIT, if any. */
5099 kvm_make_request(KVM_REQ_EVENT, vcpu);
5103 kvm_mmu_reset_context(vcpu);
5106 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5108 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5110 vcpu->arch.hflags = emul_flags;
5112 if (changed & HF_SMM_MASK)
5113 kvm_smm_changed(vcpu);
5116 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5125 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5126 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5131 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5133 struct kvm_run *kvm_run = vcpu->run;
5136 * rflags is the old, "raw" value of the flags. The new value has
5137 * not been saved yet.
5139 * This is correct even for TF set by the guest, because "the
5140 * processor will not generate this exception after the instruction
5141 * that sets the TF flag".
5143 if (unlikely(rflags & X86_EFLAGS_TF)) {
5144 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5145 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5147 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5148 kvm_run->debug.arch.exception = DB_VECTOR;
5149 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5150 *r = EMULATE_USER_EXIT;
5152 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5154 * "Certain debug exceptions may clear bit 0-3. The
5155 * remaining contents of the DR6 register are never
5156 * cleared by the processor".
5158 vcpu->arch.dr6 &= ~15;
5159 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5160 kvm_queue_exception(vcpu, DB_VECTOR);
5165 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5167 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5168 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5169 struct kvm_run *kvm_run = vcpu->run;
5170 unsigned long eip = kvm_get_linear_rip(vcpu);
5171 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5172 vcpu->arch.guest_debug_dr7,
5176 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5177 kvm_run->debug.arch.pc = eip;
5178 kvm_run->debug.arch.exception = DB_VECTOR;
5179 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5180 *r = EMULATE_USER_EXIT;
5185 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5186 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5187 unsigned long eip = kvm_get_linear_rip(vcpu);
5188 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5193 vcpu->arch.dr6 &= ~15;
5194 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5195 kvm_queue_exception(vcpu, DB_VECTOR);
5204 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5211 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5212 bool writeback = true;
5213 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5216 * Clear write_fault_to_shadow_pgtable here to ensure it is
5219 vcpu->arch.write_fault_to_shadow_pgtable = false;
5220 kvm_clear_exception_queue(vcpu);
5222 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5223 init_emulate_ctxt(vcpu);
5226 * We will reenter on the same instruction since
5227 * we do not set complete_userspace_io. This does not
5228 * handle watchpoints yet, those would be handled in
5231 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5234 ctxt->interruptibility = 0;
5235 ctxt->have_exception = false;
5236 ctxt->exception.vector = -1;
5237 ctxt->perm_ok = false;
5239 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5241 r = x86_decode_insn(ctxt, insn, insn_len);
5243 trace_kvm_emulate_insn_start(vcpu);
5244 ++vcpu->stat.insn_emulation;
5245 if (r != EMULATION_OK) {
5246 if (emulation_type & EMULTYPE_TRAP_UD)
5247 return EMULATE_FAIL;
5248 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5250 return EMULATE_DONE;
5251 if (emulation_type & EMULTYPE_SKIP)
5252 return EMULATE_FAIL;
5253 return handle_emulation_failure(vcpu);
5257 if (emulation_type & EMULTYPE_SKIP) {
5258 kvm_rip_write(vcpu, ctxt->_eip);
5259 if (ctxt->eflags & X86_EFLAGS_RF)
5260 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5261 return EMULATE_DONE;
5264 if (retry_instruction(ctxt, cr2, emulation_type))
5265 return EMULATE_DONE;
5267 /* this is needed for vmware backdoor interface to work since it
5268 changes registers values during IO operation */
5269 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5270 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5271 emulator_invalidate_register_cache(ctxt);
5275 r = x86_emulate_insn(ctxt);
5277 if (r == EMULATION_INTERCEPTED)
5278 return EMULATE_DONE;
5280 if (r == EMULATION_FAILED) {
5281 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5283 return EMULATE_DONE;
5285 return handle_emulation_failure(vcpu);
5288 if (ctxt->have_exception) {
5290 if (inject_emulated_exception(vcpu))
5292 } else if (vcpu->arch.pio.count) {
5293 if (!vcpu->arch.pio.in) {
5294 /* FIXME: return into emulator if single-stepping. */
5295 vcpu->arch.pio.count = 0;
5298 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5300 r = EMULATE_USER_EXIT;
5301 } else if (vcpu->mmio_needed) {
5302 if (!vcpu->mmio_is_write)
5304 r = EMULATE_USER_EXIT;
5305 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5306 } else if (r == EMULATION_RESTART)
5312 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5313 toggle_interruptibility(vcpu, ctxt->interruptibility);
5314 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5315 if (vcpu->arch.hflags != ctxt->emul_flags)
5316 kvm_set_hflags(vcpu, ctxt->emul_flags);
5317 kvm_rip_write(vcpu, ctxt->eip);
5318 if (r == EMULATE_DONE)
5319 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5320 if (!ctxt->have_exception ||
5321 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5322 __kvm_set_rflags(vcpu, ctxt->eflags);
5325 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5326 * do nothing, and it will be requested again as soon as
5327 * the shadow expires. But we still need to check here,
5328 * because POPF has no interrupt shadow.
5330 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5331 kvm_make_request(KVM_REQ_EVENT, vcpu);
5333 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5337 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5339 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5341 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5342 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5343 size, port, &val, 1);
5344 /* do not return to emulator after return from userspace */
5345 vcpu->arch.pio.count = 0;
5348 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5350 static void tsc_bad(void *info)
5352 __this_cpu_write(cpu_tsc_khz, 0);
5355 static void tsc_khz_changed(void *data)
5357 struct cpufreq_freqs *freq = data;
5358 unsigned long khz = 0;
5362 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5363 khz = cpufreq_quick_get(raw_smp_processor_id());
5366 __this_cpu_write(cpu_tsc_khz, khz);
5369 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5372 struct cpufreq_freqs *freq = data;
5374 struct kvm_vcpu *vcpu;
5375 int i, send_ipi = 0;
5378 * We allow guests to temporarily run on slowing clocks,
5379 * provided we notify them after, or to run on accelerating
5380 * clocks, provided we notify them before. Thus time never
5383 * However, we have a problem. We can't atomically update
5384 * the frequency of a given CPU from this function; it is
5385 * merely a notifier, which can be called from any CPU.
5386 * Changing the TSC frequency at arbitrary points in time
5387 * requires a recomputation of local variables related to
5388 * the TSC for each VCPU. We must flag these local variables
5389 * to be updated and be sure the update takes place with the
5390 * new frequency before any guests proceed.
5392 * Unfortunately, the combination of hotplug CPU and frequency
5393 * change creates an intractable locking scenario; the order
5394 * of when these callouts happen is undefined with respect to
5395 * CPU hotplug, and they can race with each other. As such,
5396 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5397 * undefined; you can actually have a CPU frequency change take
5398 * place in between the computation of X and the setting of the
5399 * variable. To protect against this problem, all updates of
5400 * the per_cpu tsc_khz variable are done in an interrupt
5401 * protected IPI, and all callers wishing to update the value
5402 * must wait for a synchronous IPI to complete (which is trivial
5403 * if the caller is on the CPU already). This establishes the
5404 * necessary total order on variable updates.
5406 * Note that because a guest time update may take place
5407 * anytime after the setting of the VCPU's request bit, the
5408 * correct TSC value must be set before the request. However,
5409 * to ensure the update actually makes it to any guest which
5410 * starts running in hardware virtualization between the set
5411 * and the acquisition of the spinlock, we must also ping the
5412 * CPU after setting the request bit.
5416 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5418 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5421 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5423 spin_lock(&kvm_lock);
5424 list_for_each_entry(kvm, &vm_list, vm_list) {
5425 kvm_for_each_vcpu(i, vcpu, kvm) {
5426 if (vcpu->cpu != freq->cpu)
5428 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5429 if (vcpu->cpu != smp_processor_id())
5433 spin_unlock(&kvm_lock);
5435 if (freq->old < freq->new && send_ipi) {
5437 * We upscale the frequency. Must make the guest
5438 * doesn't see old kvmclock values while running with
5439 * the new frequency, otherwise we risk the guest sees
5440 * time go backwards.
5442 * In case we update the frequency for another cpu
5443 * (which might be in guest context) send an interrupt
5444 * to kick the cpu out of guest context. Next time
5445 * guest context is entered kvmclock will be updated,
5446 * so the guest will not see stale values.
5448 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5453 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5454 .notifier_call = kvmclock_cpufreq_notifier
5457 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5458 unsigned long action, void *hcpu)
5460 unsigned int cpu = (unsigned long)hcpu;
5464 case CPU_DOWN_FAILED:
5465 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5467 case CPU_DOWN_PREPARE:
5468 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5474 static struct notifier_block kvmclock_cpu_notifier_block = {
5475 .notifier_call = kvmclock_cpu_notifier,
5476 .priority = -INT_MAX
5479 static void kvm_timer_init(void)
5483 max_tsc_khz = tsc_khz;
5485 cpu_notifier_register_begin();
5486 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5487 #ifdef CONFIG_CPU_FREQ
5488 struct cpufreq_policy policy;
5489 memset(&policy, 0, sizeof(policy));
5491 cpufreq_get_policy(&policy, cpu);
5492 if (policy.cpuinfo.max_freq)
5493 max_tsc_khz = policy.cpuinfo.max_freq;
5496 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5497 CPUFREQ_TRANSITION_NOTIFIER);
5499 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5500 for_each_online_cpu(cpu)
5501 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5503 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5504 cpu_notifier_register_done();
5508 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5510 int kvm_is_in_guest(void)
5512 return __this_cpu_read(current_vcpu) != NULL;
5515 static int kvm_is_user_mode(void)
5519 if (__this_cpu_read(current_vcpu))
5520 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5522 return user_mode != 0;
5525 static unsigned long kvm_get_guest_ip(void)
5527 unsigned long ip = 0;
5529 if (__this_cpu_read(current_vcpu))
5530 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5535 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5536 .is_in_guest = kvm_is_in_guest,
5537 .is_user_mode = kvm_is_user_mode,
5538 .get_guest_ip = kvm_get_guest_ip,
5541 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5543 __this_cpu_write(current_vcpu, vcpu);
5545 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5547 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5549 __this_cpu_write(current_vcpu, NULL);
5551 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5553 static void kvm_set_mmio_spte_mask(void)
5556 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5559 * Set the reserved bits and the present bit of an paging-structure
5560 * entry to generate page fault with PFER.RSV = 1.
5562 /* Mask the reserved physical address bits. */
5563 mask = rsvd_bits(maxphyaddr, 51);
5565 /* Bit 62 is always reserved for 32bit host. */
5566 mask |= 0x3ull << 62;
5568 /* Set the present bit. */
5571 #ifdef CONFIG_X86_64
5573 * If reserved bit is not supported, clear the present bit to disable
5576 if (maxphyaddr == 52)
5580 kvm_mmu_set_mmio_spte_mask(mask);
5583 #ifdef CONFIG_X86_64
5584 static void pvclock_gtod_update_fn(struct work_struct *work)
5588 struct kvm_vcpu *vcpu;
5591 spin_lock(&kvm_lock);
5592 list_for_each_entry(kvm, &vm_list, vm_list)
5593 kvm_for_each_vcpu(i, vcpu, kvm)
5594 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5595 atomic_set(&kvm_guest_has_master_clock, 0);
5596 spin_unlock(&kvm_lock);
5599 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5602 * Notification about pvclock gtod data update.
5604 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5607 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5608 struct timekeeper *tk = priv;
5610 update_pvclock_gtod(tk);
5612 /* disable master clock if host does not trust, or does not
5613 * use, TSC clocksource
5615 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5616 atomic_read(&kvm_guest_has_master_clock) != 0)
5617 queue_work(system_long_wq, &pvclock_gtod_work);
5622 static struct notifier_block pvclock_gtod_notifier = {
5623 .notifier_call = pvclock_gtod_notify,
5627 int kvm_arch_init(void *opaque)
5630 struct kvm_x86_ops *ops = opaque;
5633 printk(KERN_ERR "kvm: already loaded the other module\n");
5638 if (!ops->cpu_has_kvm_support()) {
5639 printk(KERN_ERR "kvm: no hardware support\n");
5643 if (ops->disabled_by_bios()) {
5644 printk(KERN_ERR "kvm: disabled by bios\n");
5650 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5652 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5656 r = kvm_mmu_module_init();
5658 goto out_free_percpu;
5660 kvm_set_mmio_spte_mask();
5664 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5665 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5669 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5672 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5675 #ifdef CONFIG_X86_64
5676 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5682 free_percpu(shared_msrs);
5687 void kvm_arch_exit(void)
5689 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5691 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5692 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5693 CPUFREQ_TRANSITION_NOTIFIER);
5694 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5695 #ifdef CONFIG_X86_64
5696 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5699 kvm_mmu_module_exit();
5700 free_percpu(shared_msrs);
5703 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5705 ++vcpu->stat.halt_exits;
5706 if (lapic_in_kernel(vcpu)) {
5707 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5710 vcpu->run->exit_reason = KVM_EXIT_HLT;
5714 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5716 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5718 kvm_x86_ops->skip_emulated_instruction(vcpu);
5719 return kvm_vcpu_halt(vcpu);
5721 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5724 * kvm_pv_kick_cpu_op: Kick a vcpu.
5726 * @apicid - apicid of vcpu to be kicked.
5728 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5730 struct kvm_lapic_irq lapic_irq;
5732 lapic_irq.shorthand = 0;
5733 lapic_irq.dest_mode = 0;
5734 lapic_irq.dest_id = apicid;
5735 lapic_irq.msi_redir_hint = false;
5737 lapic_irq.delivery_mode = APIC_DM_REMRD;
5738 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5741 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5743 unsigned long nr, a0, a1, a2, a3, ret;
5744 int op_64_bit, r = 1;
5746 kvm_x86_ops->skip_emulated_instruction(vcpu);
5748 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5749 return kvm_hv_hypercall(vcpu);
5751 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5752 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5753 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5754 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5755 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5757 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5759 op_64_bit = is_64_bit_mode(vcpu);
5768 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5774 case KVM_HC_VAPIC_POLL_IRQ:
5777 case KVM_HC_KICK_CPU:
5778 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5788 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5789 ++vcpu->stat.hypercalls;
5792 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5794 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5796 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5797 char instruction[3];
5798 unsigned long rip = kvm_rip_read(vcpu);
5800 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5802 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5806 * Check if userspace requested an interrupt window, and that the
5807 * interrupt window is open.
5809 * No need to exit to userspace if we already have an interrupt queued.
5811 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5813 if (!vcpu->run->request_interrupt_window || pic_in_kernel(vcpu->kvm))
5816 if (kvm_cpu_has_interrupt(vcpu))
5819 return (irqchip_split(vcpu->kvm)
5820 ? kvm_apic_accept_pic_intr(vcpu)
5821 : kvm_arch_interrupt_allowed(vcpu));
5824 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5826 struct kvm_run *kvm_run = vcpu->run;
5828 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5829 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
5830 kvm_run->cr8 = kvm_get_cr8(vcpu);
5831 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5832 if (!irqchip_in_kernel(vcpu->kvm))
5833 kvm_run->ready_for_interrupt_injection =
5834 kvm_arch_interrupt_allowed(vcpu) &&
5835 !kvm_cpu_has_interrupt(vcpu) &&
5836 !kvm_event_needs_reinjection(vcpu);
5837 else if (!pic_in_kernel(vcpu->kvm))
5838 kvm_run->ready_for_interrupt_injection =
5839 kvm_apic_accept_pic_intr(vcpu) &&
5840 !kvm_cpu_has_interrupt(vcpu);
5842 kvm_run->ready_for_interrupt_injection = 1;
5845 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5849 if (!kvm_x86_ops->update_cr8_intercept)
5852 if (!vcpu->arch.apic)
5855 if (!vcpu->arch.apic->vapic_addr)
5856 max_irr = kvm_lapic_find_highest_irr(vcpu);
5863 tpr = kvm_lapic_get_cr8(vcpu);
5865 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5868 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5872 /* try to reinject previous events if any */
5873 if (vcpu->arch.exception.pending) {
5874 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5875 vcpu->arch.exception.has_error_code,
5876 vcpu->arch.exception.error_code);
5878 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5879 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5882 if (vcpu->arch.exception.nr == DB_VECTOR &&
5883 (vcpu->arch.dr7 & DR7_GD)) {
5884 vcpu->arch.dr7 &= ~DR7_GD;
5885 kvm_update_dr7(vcpu);
5888 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5889 vcpu->arch.exception.has_error_code,
5890 vcpu->arch.exception.error_code,
5891 vcpu->arch.exception.reinject);
5895 if (vcpu->arch.nmi_injected) {
5896 kvm_x86_ops->set_nmi(vcpu);
5900 if (vcpu->arch.interrupt.pending) {
5901 kvm_x86_ops->set_irq(vcpu);
5905 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5906 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5911 /* try to inject new event if pending */
5912 if (vcpu->arch.nmi_pending) {
5913 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5914 --vcpu->arch.nmi_pending;
5915 vcpu->arch.nmi_injected = true;
5916 kvm_x86_ops->set_nmi(vcpu);
5918 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5920 * Because interrupts can be injected asynchronously, we are
5921 * calling check_nested_events again here to avoid a race condition.
5922 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5923 * proposal and current concerns. Perhaps we should be setting
5924 * KVM_REQ_EVENT only on certain events and not unconditionally?
5926 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5927 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5931 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5932 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5934 kvm_x86_ops->set_irq(vcpu);
5940 static void process_nmi(struct kvm_vcpu *vcpu)
5945 * x86 is limited to one NMI running, and one NMI pending after it.
5946 * If an NMI is already in progress, limit further NMIs to just one.
5947 * Otherwise, allow two (and we'll inject the first one immediately).
5949 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5952 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5953 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5954 kvm_make_request(KVM_REQ_EVENT, vcpu);
5957 #define put_smstate(type, buf, offset, val) \
5958 *(type *)((buf) + (offset) - 0x7e00) = val
5960 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5963 flags |= seg->g << 23;
5964 flags |= seg->db << 22;
5965 flags |= seg->l << 21;
5966 flags |= seg->avl << 20;
5967 flags |= seg->present << 15;
5968 flags |= seg->dpl << 13;
5969 flags |= seg->s << 12;
5970 flags |= seg->type << 8;
5974 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5976 struct kvm_segment seg;
5979 kvm_get_segment(vcpu, &seg, n);
5980 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5983 offset = 0x7f84 + n * 12;
5985 offset = 0x7f2c + (n - 3) * 12;
5987 put_smstate(u32, buf, offset + 8, seg.base);
5988 put_smstate(u32, buf, offset + 4, seg.limit);
5989 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5992 #ifdef CONFIG_X86_64
5993 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5995 struct kvm_segment seg;
5999 kvm_get_segment(vcpu, &seg, n);
6000 offset = 0x7e00 + n * 16;
6002 flags = process_smi_get_segment_flags(&seg) >> 8;
6003 put_smstate(u16, buf, offset, seg.selector);
6004 put_smstate(u16, buf, offset + 2, flags);
6005 put_smstate(u32, buf, offset + 4, seg.limit);
6006 put_smstate(u64, buf, offset + 8, seg.base);
6010 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6013 struct kvm_segment seg;
6017 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6018 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6019 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6020 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6022 for (i = 0; i < 8; i++)
6023 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6025 kvm_get_dr(vcpu, 6, &val);
6026 put_smstate(u32, buf, 0x7fcc, (u32)val);
6027 kvm_get_dr(vcpu, 7, &val);
6028 put_smstate(u32, buf, 0x7fc8, (u32)val);
6030 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6031 put_smstate(u32, buf, 0x7fc4, seg.selector);
6032 put_smstate(u32, buf, 0x7f64, seg.base);
6033 put_smstate(u32, buf, 0x7f60, seg.limit);
6034 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6036 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6037 put_smstate(u32, buf, 0x7fc0, seg.selector);
6038 put_smstate(u32, buf, 0x7f80, seg.base);
6039 put_smstate(u32, buf, 0x7f7c, seg.limit);
6040 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6042 kvm_x86_ops->get_gdt(vcpu, &dt);
6043 put_smstate(u32, buf, 0x7f74, dt.address);
6044 put_smstate(u32, buf, 0x7f70, dt.size);
6046 kvm_x86_ops->get_idt(vcpu, &dt);
6047 put_smstate(u32, buf, 0x7f58, dt.address);
6048 put_smstate(u32, buf, 0x7f54, dt.size);
6050 for (i = 0; i < 6; i++)
6051 process_smi_save_seg_32(vcpu, buf, i);
6053 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6056 put_smstate(u32, buf, 0x7efc, 0x00020000);
6057 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6060 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6062 #ifdef CONFIG_X86_64
6064 struct kvm_segment seg;
6068 for (i = 0; i < 16; i++)
6069 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6071 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6072 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6074 kvm_get_dr(vcpu, 6, &val);
6075 put_smstate(u64, buf, 0x7f68, val);
6076 kvm_get_dr(vcpu, 7, &val);
6077 put_smstate(u64, buf, 0x7f60, val);
6079 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6080 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6081 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6083 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6086 put_smstate(u32, buf, 0x7efc, 0x00020064);
6088 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6090 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6091 put_smstate(u16, buf, 0x7e90, seg.selector);
6092 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6093 put_smstate(u32, buf, 0x7e94, seg.limit);
6094 put_smstate(u64, buf, 0x7e98, seg.base);
6096 kvm_x86_ops->get_idt(vcpu, &dt);
6097 put_smstate(u32, buf, 0x7e84, dt.size);
6098 put_smstate(u64, buf, 0x7e88, dt.address);
6100 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6101 put_smstate(u16, buf, 0x7e70, seg.selector);
6102 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6103 put_smstate(u32, buf, 0x7e74, seg.limit);
6104 put_smstate(u64, buf, 0x7e78, seg.base);
6106 kvm_x86_ops->get_gdt(vcpu, &dt);
6107 put_smstate(u32, buf, 0x7e64, dt.size);
6108 put_smstate(u64, buf, 0x7e68, dt.address);
6110 for (i = 0; i < 6; i++)
6111 process_smi_save_seg_64(vcpu, buf, i);
6117 static void process_smi(struct kvm_vcpu *vcpu)
6119 struct kvm_segment cs, ds;
6125 vcpu->arch.smi_pending = true;
6129 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6130 vcpu->arch.hflags |= HF_SMM_MASK;
6131 memset(buf, 0, 512);
6132 if (guest_cpuid_has_longmode(vcpu))
6133 process_smi_save_state_64(vcpu, buf);
6135 process_smi_save_state_32(vcpu, buf);
6137 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6139 if (kvm_x86_ops->get_nmi_mask(vcpu))
6140 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6142 kvm_x86_ops->set_nmi_mask(vcpu, true);
6144 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6145 kvm_rip_write(vcpu, 0x8000);
6147 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6148 kvm_x86_ops->set_cr0(vcpu, cr0);
6149 vcpu->arch.cr0 = cr0;
6151 kvm_x86_ops->set_cr4(vcpu, 0);
6153 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6154 dt.address = dt.size = 0;
6155 kvm_x86_ops->set_idt(vcpu, &dt);
6157 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6159 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6160 cs.base = vcpu->arch.smbase;
6165 cs.limit = ds.limit = 0xffffffff;
6166 cs.type = ds.type = 0x3;
6167 cs.dpl = ds.dpl = 0;
6172 cs.avl = ds.avl = 0;
6173 cs.present = ds.present = 1;
6174 cs.unusable = ds.unusable = 0;
6175 cs.padding = ds.padding = 0;
6177 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6178 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6179 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6180 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6181 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6182 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6184 if (guest_cpuid_has_longmode(vcpu))
6185 kvm_x86_ops->set_efer(vcpu, 0);
6187 kvm_update_cpuid(vcpu);
6188 kvm_mmu_reset_context(vcpu);
6191 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6193 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6196 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
6198 if (irqchip_split(vcpu->kvm))
6199 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
6201 kvm_x86_ops->sync_pir_to_irr(vcpu);
6202 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
6204 kvm_x86_ops->load_eoi_exitmap(vcpu);
6207 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6209 ++vcpu->stat.tlb_flush;
6210 kvm_x86_ops->tlb_flush(vcpu);
6213 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6215 struct page *page = NULL;
6217 if (!lapic_in_kernel(vcpu))
6220 if (!kvm_x86_ops->set_apic_access_page_addr)
6223 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6224 if (is_error_page(page))
6226 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6229 * Do not pin apic access page in memory, the MMU notifier
6230 * will call us again if it is migrated or swapped out.
6234 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6236 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6237 unsigned long address)
6240 * The physical address of apic access page is stored in the VMCS.
6241 * Update it when it becomes invalid.
6243 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6244 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6248 * Returns 1 to let vcpu_run() continue the guest execution loop without
6249 * exiting to the userspace. Otherwise, the value will be returned to the
6252 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6255 bool req_int_win = !lapic_in_kernel(vcpu) &&
6256 vcpu->run->request_interrupt_window;
6257 bool req_immediate_exit = false;
6259 if (vcpu->requests) {
6260 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6261 kvm_mmu_unload(vcpu);
6262 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6263 __kvm_migrate_timers(vcpu);
6264 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6265 kvm_gen_update_masterclock(vcpu->kvm);
6266 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6267 kvm_gen_kvmclock_update(vcpu);
6268 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6269 r = kvm_guest_time_update(vcpu);
6273 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6274 kvm_mmu_sync_roots(vcpu);
6275 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6276 kvm_vcpu_flush_tlb(vcpu);
6277 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6278 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6282 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6283 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6287 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6288 vcpu->fpu_active = 0;
6289 kvm_x86_ops->fpu_deactivate(vcpu);
6291 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6292 /* Page is swapped out. Do synthetic halt */
6293 vcpu->arch.apf.halted = true;
6297 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6298 record_steal_time(vcpu);
6299 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6301 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6303 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6304 kvm_pmu_handle_event(vcpu);
6305 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6306 kvm_pmu_deliver_pmi(vcpu);
6307 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6308 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6309 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6310 (void *) vcpu->arch.eoi_exit_bitmap)) {
6311 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6312 vcpu->run->eoi.vector =
6313 vcpu->arch.pending_ioapic_eoi;
6318 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6319 vcpu_scan_ioapic(vcpu);
6320 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6321 kvm_vcpu_reload_apic_access_page(vcpu);
6322 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6323 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6324 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6328 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6329 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6330 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6337 * KVM_REQ_EVENT is not set when posted interrupts are set by
6338 * VT-d hardware, so we have to update RVI unconditionally.
6340 if (kvm_lapic_enabled(vcpu)) {
6342 * Update architecture specific hints for APIC
6343 * virtual interrupt delivery.
6345 if (kvm_x86_ops->hwapic_irr_update)
6346 kvm_x86_ops->hwapic_irr_update(vcpu,
6347 kvm_lapic_find_highest_irr(vcpu));
6350 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6351 kvm_apic_accept_events(vcpu);
6352 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6357 if (inject_pending_event(vcpu, req_int_win) != 0)
6358 req_immediate_exit = true;
6359 /* enable NMI/IRQ window open exits if needed */
6360 else if (vcpu->arch.nmi_pending)
6361 kvm_x86_ops->enable_nmi_window(vcpu);
6362 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6363 kvm_x86_ops->enable_irq_window(vcpu);
6365 if (kvm_lapic_enabled(vcpu)) {
6366 update_cr8_intercept(vcpu);
6367 kvm_lapic_sync_to_vapic(vcpu);
6371 r = kvm_mmu_reload(vcpu);
6373 goto cancel_injection;
6378 kvm_x86_ops->prepare_guest_switch(vcpu);
6379 if (vcpu->fpu_active)
6380 kvm_load_guest_fpu(vcpu);
6381 kvm_load_guest_xcr0(vcpu);
6383 vcpu->mode = IN_GUEST_MODE;
6385 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6387 /* We should set ->mode before check ->requests,
6388 * see the comment in make_all_cpus_request.
6390 smp_mb__after_srcu_read_unlock();
6392 local_irq_disable();
6394 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6395 || need_resched() || signal_pending(current)) {
6396 vcpu->mode = OUTSIDE_GUEST_MODE;
6400 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6402 goto cancel_injection;
6405 if (req_immediate_exit)
6406 smp_send_reschedule(vcpu->cpu);
6408 __kvm_guest_enter();
6410 if (unlikely(vcpu->arch.switch_db_regs)) {
6412 set_debugreg(vcpu->arch.eff_db[0], 0);
6413 set_debugreg(vcpu->arch.eff_db[1], 1);
6414 set_debugreg(vcpu->arch.eff_db[2], 2);
6415 set_debugreg(vcpu->arch.eff_db[3], 3);
6416 set_debugreg(vcpu->arch.dr6, 6);
6417 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6420 trace_kvm_entry(vcpu->vcpu_id);
6421 wait_lapic_expire(vcpu);
6422 kvm_x86_ops->run(vcpu);
6425 * Do this here before restoring debug registers on the host. And
6426 * since we do this before handling the vmexit, a DR access vmexit
6427 * can (a) read the correct value of the debug registers, (b) set
6428 * KVM_DEBUGREG_WONT_EXIT again.
6430 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6433 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6434 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6435 for (i = 0; i < KVM_NR_DB_REGS; i++)
6436 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6440 * If the guest has used debug registers, at least dr7
6441 * will be disabled while returning to the host.
6442 * If we don't have active breakpoints in the host, we don't
6443 * care about the messed up debug address registers. But if
6444 * we have some of them active, restore the old state.
6446 if (hw_breakpoint_active())
6447 hw_breakpoint_restore();
6449 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6452 vcpu->mode = OUTSIDE_GUEST_MODE;
6455 /* Interrupt is enabled by handle_external_intr() */
6456 kvm_x86_ops->handle_external_intr(vcpu);
6461 * We must have an instruction between local_irq_enable() and
6462 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6463 * the interrupt shadow. The stat.exits increment will do nicely.
6464 * But we need to prevent reordering, hence this barrier():
6472 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6475 * Profile KVM exit RIPs:
6477 if (unlikely(prof_on == KVM_PROFILING)) {
6478 unsigned long rip = kvm_rip_read(vcpu);
6479 profile_hit(KVM_PROFILING, (void *)rip);
6482 if (unlikely(vcpu->arch.tsc_always_catchup))
6483 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6485 if (vcpu->arch.apic_attention)
6486 kvm_lapic_sync_from_vapic(vcpu);
6488 r = kvm_x86_ops->handle_exit(vcpu);
6492 kvm_x86_ops->cancel_injection(vcpu);
6493 if (unlikely(vcpu->arch.apic_attention))
6494 kvm_lapic_sync_from_vapic(vcpu);
6499 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6501 if (!kvm_arch_vcpu_runnable(vcpu) &&
6502 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6503 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6504 kvm_vcpu_block(vcpu);
6505 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6507 if (kvm_x86_ops->post_block)
6508 kvm_x86_ops->post_block(vcpu);
6510 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6514 kvm_apic_accept_events(vcpu);
6515 switch(vcpu->arch.mp_state) {
6516 case KVM_MP_STATE_HALTED:
6517 vcpu->arch.pv.pv_unhalted = false;
6518 vcpu->arch.mp_state =
6519 KVM_MP_STATE_RUNNABLE;
6520 case KVM_MP_STATE_RUNNABLE:
6521 vcpu->arch.apf.halted = false;
6523 case KVM_MP_STATE_INIT_RECEIVED:
6532 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6534 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6535 !vcpu->arch.apf.halted);
6538 static int vcpu_run(struct kvm_vcpu *vcpu)
6541 struct kvm *kvm = vcpu->kvm;
6543 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6546 if (kvm_vcpu_running(vcpu)) {
6547 r = vcpu_enter_guest(vcpu);
6549 r = vcpu_block(kvm, vcpu);
6555 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6556 if (kvm_cpu_has_pending_timer(vcpu))
6557 kvm_inject_pending_timer_irqs(vcpu);
6559 if (dm_request_for_irq_injection(vcpu)) {
6561 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6562 ++vcpu->stat.request_irq_exits;
6566 kvm_check_async_pf_completion(vcpu);
6568 if (signal_pending(current)) {
6570 vcpu->run->exit_reason = KVM_EXIT_INTR;
6571 ++vcpu->stat.signal_exits;
6574 if (need_resched()) {
6575 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6577 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6581 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6586 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6589 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6590 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6591 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6592 if (r != EMULATE_DONE)
6597 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6599 BUG_ON(!vcpu->arch.pio.count);
6601 return complete_emulated_io(vcpu);
6605 * Implements the following, as a state machine:
6609 * for each mmio piece in the fragment
6617 * for each mmio piece in the fragment
6622 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6624 struct kvm_run *run = vcpu->run;
6625 struct kvm_mmio_fragment *frag;
6628 BUG_ON(!vcpu->mmio_needed);
6630 /* Complete previous fragment */
6631 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6632 len = min(8u, frag->len);
6633 if (!vcpu->mmio_is_write)
6634 memcpy(frag->data, run->mmio.data, len);
6636 if (frag->len <= 8) {
6637 /* Switch to the next fragment. */
6639 vcpu->mmio_cur_fragment++;
6641 /* Go forward to the next mmio piece. */
6647 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6648 vcpu->mmio_needed = 0;
6650 /* FIXME: return into emulator if single-stepping. */
6651 if (vcpu->mmio_is_write)
6653 vcpu->mmio_read_completed = 1;
6654 return complete_emulated_io(vcpu);
6657 run->exit_reason = KVM_EXIT_MMIO;
6658 run->mmio.phys_addr = frag->gpa;
6659 if (vcpu->mmio_is_write)
6660 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6661 run->mmio.len = min(8u, frag->len);
6662 run->mmio.is_write = vcpu->mmio_is_write;
6663 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6668 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6670 struct fpu *fpu = ¤t->thread.fpu;
6674 fpu__activate_curr(fpu);
6676 if (vcpu->sigset_active)
6677 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6679 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6680 kvm_vcpu_block(vcpu);
6681 kvm_apic_accept_events(vcpu);
6682 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6687 /* re-sync apic's tpr */
6688 if (!lapic_in_kernel(vcpu)) {
6689 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6695 if (unlikely(vcpu->arch.complete_userspace_io)) {
6696 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6697 vcpu->arch.complete_userspace_io = NULL;
6702 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6707 post_kvm_run_save(vcpu);
6708 if (vcpu->sigset_active)
6709 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6714 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6716 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6718 * We are here if userspace calls get_regs() in the middle of
6719 * instruction emulation. Registers state needs to be copied
6720 * back from emulation context to vcpu. Userspace shouldn't do
6721 * that usually, but some bad designed PV devices (vmware
6722 * backdoor interface) need this to work
6724 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6725 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6727 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6728 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6729 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6730 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6731 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6732 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6733 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6734 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6735 #ifdef CONFIG_X86_64
6736 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6737 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6738 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6739 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6740 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6741 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6742 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6743 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6746 regs->rip = kvm_rip_read(vcpu);
6747 regs->rflags = kvm_get_rflags(vcpu);
6752 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6754 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6755 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6757 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6758 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6759 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6760 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6761 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6762 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6763 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6764 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6765 #ifdef CONFIG_X86_64
6766 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6767 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6768 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6769 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6770 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6771 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6772 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6773 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6776 kvm_rip_write(vcpu, regs->rip);
6777 kvm_set_rflags(vcpu, regs->rflags);
6779 vcpu->arch.exception.pending = false;
6781 kvm_make_request(KVM_REQ_EVENT, vcpu);
6786 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6788 struct kvm_segment cs;
6790 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6794 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6796 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6797 struct kvm_sregs *sregs)
6801 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6802 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6803 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6804 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6805 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6806 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6808 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6809 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6811 kvm_x86_ops->get_idt(vcpu, &dt);
6812 sregs->idt.limit = dt.size;
6813 sregs->idt.base = dt.address;
6814 kvm_x86_ops->get_gdt(vcpu, &dt);
6815 sregs->gdt.limit = dt.size;
6816 sregs->gdt.base = dt.address;
6818 sregs->cr0 = kvm_read_cr0(vcpu);
6819 sregs->cr2 = vcpu->arch.cr2;
6820 sregs->cr3 = kvm_read_cr3(vcpu);
6821 sregs->cr4 = kvm_read_cr4(vcpu);
6822 sregs->cr8 = kvm_get_cr8(vcpu);
6823 sregs->efer = vcpu->arch.efer;
6824 sregs->apic_base = kvm_get_apic_base(vcpu);
6826 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6828 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6829 set_bit(vcpu->arch.interrupt.nr,
6830 (unsigned long *)sregs->interrupt_bitmap);
6835 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6836 struct kvm_mp_state *mp_state)
6838 kvm_apic_accept_events(vcpu);
6839 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6840 vcpu->arch.pv.pv_unhalted)
6841 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6843 mp_state->mp_state = vcpu->arch.mp_state;
6848 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6849 struct kvm_mp_state *mp_state)
6851 if (!kvm_vcpu_has_lapic(vcpu) &&
6852 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6855 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6856 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6857 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6859 vcpu->arch.mp_state = mp_state->mp_state;
6860 kvm_make_request(KVM_REQ_EVENT, vcpu);
6864 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6865 int reason, bool has_error_code, u32 error_code)
6867 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6870 init_emulate_ctxt(vcpu);
6872 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6873 has_error_code, error_code);
6876 return EMULATE_FAIL;
6878 kvm_rip_write(vcpu, ctxt->eip);
6879 kvm_set_rflags(vcpu, ctxt->eflags);
6880 kvm_make_request(KVM_REQ_EVENT, vcpu);
6881 return EMULATE_DONE;
6883 EXPORT_SYMBOL_GPL(kvm_task_switch);
6885 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6886 struct kvm_sregs *sregs)
6888 struct msr_data apic_base_msr;
6889 int mmu_reset_needed = 0;
6890 int pending_vec, max_bits, idx;
6893 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6896 dt.size = sregs->idt.limit;
6897 dt.address = sregs->idt.base;
6898 kvm_x86_ops->set_idt(vcpu, &dt);
6899 dt.size = sregs->gdt.limit;
6900 dt.address = sregs->gdt.base;
6901 kvm_x86_ops->set_gdt(vcpu, &dt);
6903 vcpu->arch.cr2 = sregs->cr2;
6904 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6905 vcpu->arch.cr3 = sregs->cr3;
6906 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6908 kvm_set_cr8(vcpu, sregs->cr8);
6910 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6911 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6912 apic_base_msr.data = sregs->apic_base;
6913 apic_base_msr.host_initiated = true;
6914 kvm_set_apic_base(vcpu, &apic_base_msr);
6916 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6917 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6918 vcpu->arch.cr0 = sregs->cr0;
6920 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6921 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6922 if (sregs->cr4 & X86_CR4_OSXSAVE)
6923 kvm_update_cpuid(vcpu);
6925 idx = srcu_read_lock(&vcpu->kvm->srcu);
6926 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6927 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6928 mmu_reset_needed = 1;
6930 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6932 if (mmu_reset_needed)
6933 kvm_mmu_reset_context(vcpu);
6935 max_bits = KVM_NR_INTERRUPTS;
6936 pending_vec = find_first_bit(
6937 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6938 if (pending_vec < max_bits) {
6939 kvm_queue_interrupt(vcpu, pending_vec, false);
6940 pr_debug("Set back pending irq %d\n", pending_vec);
6943 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6944 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6945 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6946 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6947 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6948 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6950 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6951 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6953 update_cr8_intercept(vcpu);
6955 /* Older userspace won't unhalt the vcpu on reset. */
6956 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6957 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6959 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6961 kvm_make_request(KVM_REQ_EVENT, vcpu);
6966 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6967 struct kvm_guest_debug *dbg)
6969 unsigned long rflags;
6972 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6974 if (vcpu->arch.exception.pending)
6976 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6977 kvm_queue_exception(vcpu, DB_VECTOR);
6979 kvm_queue_exception(vcpu, BP_VECTOR);
6983 * Read rflags as long as potentially injected trace flags are still
6986 rflags = kvm_get_rflags(vcpu);
6988 vcpu->guest_debug = dbg->control;
6989 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6990 vcpu->guest_debug = 0;
6992 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6993 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6994 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6995 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6997 for (i = 0; i < KVM_NR_DB_REGS; i++)
6998 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7000 kvm_update_dr7(vcpu);
7002 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7003 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7004 get_segment_base(vcpu, VCPU_SREG_CS);
7007 * Trigger an rflags update that will inject or remove the trace
7010 kvm_set_rflags(vcpu, rflags);
7012 kvm_x86_ops->update_db_bp_intercept(vcpu);
7022 * Translate a guest virtual address to a guest physical address.
7024 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7025 struct kvm_translation *tr)
7027 unsigned long vaddr = tr->linear_address;
7031 idx = srcu_read_lock(&vcpu->kvm->srcu);
7032 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7033 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7034 tr->physical_address = gpa;
7035 tr->valid = gpa != UNMAPPED_GVA;
7042 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7044 struct fxregs_state *fxsave =
7045 &vcpu->arch.guest_fpu.state.fxsave;
7047 memcpy(fpu->fpr, fxsave->st_space, 128);
7048 fpu->fcw = fxsave->cwd;
7049 fpu->fsw = fxsave->swd;
7050 fpu->ftwx = fxsave->twd;
7051 fpu->last_opcode = fxsave->fop;
7052 fpu->last_ip = fxsave->rip;
7053 fpu->last_dp = fxsave->rdp;
7054 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7059 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7061 struct fxregs_state *fxsave =
7062 &vcpu->arch.guest_fpu.state.fxsave;
7064 memcpy(fxsave->st_space, fpu->fpr, 128);
7065 fxsave->cwd = fpu->fcw;
7066 fxsave->swd = fpu->fsw;
7067 fxsave->twd = fpu->ftwx;
7068 fxsave->fop = fpu->last_opcode;
7069 fxsave->rip = fpu->last_ip;
7070 fxsave->rdp = fpu->last_dp;
7071 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7076 static void fx_init(struct kvm_vcpu *vcpu)
7078 fpstate_init(&vcpu->arch.guest_fpu.state);
7080 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7081 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7084 * Ensure guest xcr0 is valid for loading
7086 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7088 vcpu->arch.cr0 |= X86_CR0_ET;
7091 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7093 if (vcpu->guest_fpu_loaded)
7097 * Restore all possible states in the guest,
7098 * and assume host would use all available bits.
7099 * Guest xcr0 would be loaded later.
7101 kvm_put_guest_xcr0(vcpu);
7102 vcpu->guest_fpu_loaded = 1;
7103 __kernel_fpu_begin();
7104 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7108 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7110 kvm_put_guest_xcr0(vcpu);
7112 if (!vcpu->guest_fpu_loaded) {
7113 vcpu->fpu_counter = 0;
7117 vcpu->guest_fpu_loaded = 0;
7118 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7120 ++vcpu->stat.fpu_reload;
7122 * If using eager FPU mode, or if the guest is a frequent user
7123 * of the FPU, just leave the FPU active for next time.
7124 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7125 * the FPU in bursts will revert to loading it on demand.
7127 if (!vcpu->arch.eager_fpu) {
7128 if (++vcpu->fpu_counter < 5)
7129 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7134 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7136 kvmclock_reset(vcpu);
7138 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7139 kvm_x86_ops->vcpu_free(vcpu);
7142 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7145 struct kvm_vcpu *vcpu;
7147 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7148 printk_once(KERN_WARNING
7149 "kvm: SMP vm created on host with unstable TSC; "
7150 "guest TSC will not be reliable\n");
7152 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7157 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7161 kvm_vcpu_mtrr_init(vcpu);
7162 r = vcpu_load(vcpu);
7165 kvm_vcpu_reset(vcpu, false);
7166 kvm_mmu_setup(vcpu);
7171 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7173 struct msr_data msr;
7174 struct kvm *kvm = vcpu->kvm;
7176 if (vcpu_load(vcpu))
7179 msr.index = MSR_IA32_TSC;
7180 msr.host_initiated = true;
7181 kvm_write_tsc(vcpu, &msr);
7184 if (!kvmclock_periodic_sync)
7187 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7188 KVMCLOCK_SYNC_PERIOD);
7191 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7194 vcpu->arch.apf.msr_val = 0;
7196 r = vcpu_load(vcpu);
7198 kvm_mmu_unload(vcpu);
7201 kvm_x86_ops->vcpu_free(vcpu);
7204 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7206 vcpu->arch.hflags = 0;
7208 atomic_set(&vcpu->arch.nmi_queued, 0);
7209 vcpu->arch.nmi_pending = 0;
7210 vcpu->arch.nmi_injected = false;
7211 kvm_clear_interrupt_queue(vcpu);
7212 kvm_clear_exception_queue(vcpu);
7214 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7215 kvm_update_dr0123(vcpu);
7216 vcpu->arch.dr6 = DR6_INIT;
7217 kvm_update_dr6(vcpu);
7218 vcpu->arch.dr7 = DR7_FIXED_1;
7219 kvm_update_dr7(vcpu);
7223 kvm_make_request(KVM_REQ_EVENT, vcpu);
7224 vcpu->arch.apf.msr_val = 0;
7225 vcpu->arch.st.msr_val = 0;
7227 kvmclock_reset(vcpu);
7229 kvm_clear_async_pf_completion_queue(vcpu);
7230 kvm_async_pf_hash_reset(vcpu);
7231 vcpu->arch.apf.halted = false;
7234 kvm_pmu_reset(vcpu);
7235 vcpu->arch.smbase = 0x30000;
7238 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7239 vcpu->arch.regs_avail = ~0;
7240 vcpu->arch.regs_dirty = ~0;
7242 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7245 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7247 struct kvm_segment cs;
7249 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7250 cs.selector = vector << 8;
7251 cs.base = vector << 12;
7252 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7253 kvm_rip_write(vcpu, 0);
7256 int kvm_arch_hardware_enable(void)
7259 struct kvm_vcpu *vcpu;
7264 bool stable, backwards_tsc = false;
7266 kvm_shared_msr_cpu_online();
7267 ret = kvm_x86_ops->hardware_enable();
7271 local_tsc = rdtsc();
7272 stable = !check_tsc_unstable();
7273 list_for_each_entry(kvm, &vm_list, vm_list) {
7274 kvm_for_each_vcpu(i, vcpu, kvm) {
7275 if (!stable && vcpu->cpu == smp_processor_id())
7276 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7277 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7278 backwards_tsc = true;
7279 if (vcpu->arch.last_host_tsc > max_tsc)
7280 max_tsc = vcpu->arch.last_host_tsc;
7286 * Sometimes, even reliable TSCs go backwards. This happens on
7287 * platforms that reset TSC during suspend or hibernate actions, but
7288 * maintain synchronization. We must compensate. Fortunately, we can
7289 * detect that condition here, which happens early in CPU bringup,
7290 * before any KVM threads can be running. Unfortunately, we can't
7291 * bring the TSCs fully up to date with real time, as we aren't yet far
7292 * enough into CPU bringup that we know how much real time has actually
7293 * elapsed; our helper function, get_kernel_ns() will be using boot
7294 * variables that haven't been updated yet.
7296 * So we simply find the maximum observed TSC above, then record the
7297 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7298 * the adjustment will be applied. Note that we accumulate
7299 * adjustments, in case multiple suspend cycles happen before some VCPU
7300 * gets a chance to run again. In the event that no KVM threads get a
7301 * chance to run, we will miss the entire elapsed period, as we'll have
7302 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7303 * loose cycle time. This isn't too big a deal, since the loss will be
7304 * uniform across all VCPUs (not to mention the scenario is extremely
7305 * unlikely). It is possible that a second hibernate recovery happens
7306 * much faster than a first, causing the observed TSC here to be
7307 * smaller; this would require additional padding adjustment, which is
7308 * why we set last_host_tsc to the local tsc observed here.
7310 * N.B. - this code below runs only on platforms with reliable TSC,
7311 * as that is the only way backwards_tsc is set above. Also note
7312 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7313 * have the same delta_cyc adjustment applied if backwards_tsc
7314 * is detected. Note further, this adjustment is only done once,
7315 * as we reset last_host_tsc on all VCPUs to stop this from being
7316 * called multiple times (one for each physical CPU bringup).
7318 * Platforms with unreliable TSCs don't have to deal with this, they
7319 * will be compensated by the logic in vcpu_load, which sets the TSC to
7320 * catchup mode. This will catchup all VCPUs to real time, but cannot
7321 * guarantee that they stay in perfect synchronization.
7323 if (backwards_tsc) {
7324 u64 delta_cyc = max_tsc - local_tsc;
7325 backwards_tsc_observed = true;
7326 list_for_each_entry(kvm, &vm_list, vm_list) {
7327 kvm_for_each_vcpu(i, vcpu, kvm) {
7328 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7329 vcpu->arch.last_host_tsc = local_tsc;
7330 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7334 * We have to disable TSC offset matching.. if you were
7335 * booting a VM while issuing an S4 host suspend....
7336 * you may have some problem. Solving this issue is
7337 * left as an exercise to the reader.
7339 kvm->arch.last_tsc_nsec = 0;
7340 kvm->arch.last_tsc_write = 0;
7347 void kvm_arch_hardware_disable(void)
7349 kvm_x86_ops->hardware_disable();
7350 drop_user_return_notifiers();
7353 int kvm_arch_hardware_setup(void)
7357 r = kvm_x86_ops->hardware_setup();
7361 kvm_init_msr_list();
7365 void kvm_arch_hardware_unsetup(void)
7367 kvm_x86_ops->hardware_unsetup();
7370 void kvm_arch_check_processor_compat(void *rtn)
7372 kvm_x86_ops->check_processor_compatibility(rtn);
7375 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7377 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7379 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7381 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7383 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7386 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7388 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7391 struct static_key kvm_no_apic_vcpu __read_mostly;
7393 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7399 BUG_ON(vcpu->kvm == NULL);
7402 vcpu->arch.pv.pv_unhalted = false;
7403 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7404 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7405 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7407 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7409 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7414 vcpu->arch.pio_data = page_address(page);
7416 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7418 r = kvm_mmu_create(vcpu);
7420 goto fail_free_pio_data;
7422 if (irqchip_in_kernel(kvm)) {
7423 r = kvm_create_lapic(vcpu);
7425 goto fail_mmu_destroy;
7427 static_key_slow_inc(&kvm_no_apic_vcpu);
7429 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7431 if (!vcpu->arch.mce_banks) {
7433 goto fail_free_lapic;
7435 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7437 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7439 goto fail_free_mce_banks;
7444 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7445 vcpu->arch.pv_time_enabled = false;
7447 vcpu->arch.guest_supported_xcr0 = 0;
7448 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7450 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7452 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7454 kvm_async_pf_hash_reset(vcpu);
7457 vcpu->arch.pending_external_vector = -1;
7461 fail_free_mce_banks:
7462 kfree(vcpu->arch.mce_banks);
7464 kvm_free_lapic(vcpu);
7466 kvm_mmu_destroy(vcpu);
7468 free_page((unsigned long)vcpu->arch.pio_data);
7473 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7477 kvm_pmu_destroy(vcpu);
7478 kfree(vcpu->arch.mce_banks);
7479 kvm_free_lapic(vcpu);
7480 idx = srcu_read_lock(&vcpu->kvm->srcu);
7481 kvm_mmu_destroy(vcpu);
7482 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7483 free_page((unsigned long)vcpu->arch.pio_data);
7484 if (!lapic_in_kernel(vcpu))
7485 static_key_slow_dec(&kvm_no_apic_vcpu);
7488 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7490 kvm_x86_ops->sched_in(vcpu, cpu);
7493 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7498 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7499 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7500 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7501 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7502 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7504 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7505 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7506 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7507 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7508 &kvm->arch.irq_sources_bitmap);
7510 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7511 mutex_init(&kvm->arch.apic_map_lock);
7512 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7514 pvclock_update_vm_gtod_copy(kvm);
7516 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7517 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7522 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7525 r = vcpu_load(vcpu);
7527 kvm_mmu_unload(vcpu);
7531 static void kvm_free_vcpus(struct kvm *kvm)
7534 struct kvm_vcpu *vcpu;
7537 * Unpin any mmu pages first.
7539 kvm_for_each_vcpu(i, vcpu, kvm) {
7540 kvm_clear_async_pf_completion_queue(vcpu);
7541 kvm_unload_vcpu_mmu(vcpu);
7543 kvm_for_each_vcpu(i, vcpu, kvm)
7544 kvm_arch_vcpu_free(vcpu);
7546 mutex_lock(&kvm->lock);
7547 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7548 kvm->vcpus[i] = NULL;
7550 atomic_set(&kvm->online_vcpus, 0);
7551 mutex_unlock(&kvm->lock);
7554 void kvm_arch_sync_events(struct kvm *kvm)
7556 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7557 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7558 kvm_free_all_assigned_devices(kvm);
7562 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7566 struct kvm_memslots *slots = kvm_memslots(kvm);
7567 struct kvm_memory_slot *slot, old;
7569 /* Called with kvm->slots_lock held. */
7570 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7573 slot = id_to_memslot(slots, id);
7575 if (WARN_ON(slot->npages))
7579 * MAP_SHARED to prevent internal slot pages from being moved
7582 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7583 MAP_SHARED | MAP_ANONYMOUS, 0);
7584 if (IS_ERR((void *)hva))
7585 return PTR_ERR((void *)hva);
7594 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7595 struct kvm_userspace_memory_region m;
7597 m.slot = id | (i << 16);
7599 m.guest_phys_addr = gpa;
7600 m.userspace_addr = hva;
7601 m.memory_size = size;
7602 r = __kvm_set_memory_region(kvm, &m);
7608 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7614 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7616 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7620 mutex_lock(&kvm->slots_lock);
7621 r = __x86_set_memory_region(kvm, id, gpa, size);
7622 mutex_unlock(&kvm->slots_lock);
7626 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7628 void kvm_arch_destroy_vm(struct kvm *kvm)
7630 if (current->mm == kvm->mm) {
7632 * Free memory regions allocated on behalf of userspace,
7633 * unless the the memory map has changed due to process exit
7636 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7637 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7638 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
7640 kvm_iommu_unmap_guest(kvm);
7641 kfree(kvm->arch.vpic);
7642 kfree(kvm->arch.vioapic);
7643 kvm_free_vcpus(kvm);
7644 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7647 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7648 struct kvm_memory_slot *dont)
7652 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7653 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7654 kvfree(free->arch.rmap[i]);
7655 free->arch.rmap[i] = NULL;
7660 if (!dont || free->arch.lpage_info[i - 1] !=
7661 dont->arch.lpage_info[i - 1]) {
7662 kvfree(free->arch.lpage_info[i - 1]);
7663 free->arch.lpage_info[i - 1] = NULL;
7668 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7669 unsigned long npages)
7673 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7678 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7679 slot->base_gfn, level) + 1;
7681 slot->arch.rmap[i] =
7682 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7683 if (!slot->arch.rmap[i])
7688 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7689 sizeof(*slot->arch.lpage_info[i - 1]));
7690 if (!slot->arch.lpage_info[i - 1])
7693 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7694 slot->arch.lpage_info[i - 1][0].write_count = 1;
7695 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7696 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7697 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7699 * If the gfn and userspace address are not aligned wrt each
7700 * other, or if explicitly asked to, disable large page
7701 * support for this slot
7703 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7704 !kvm_largepages_enabled()) {
7707 for (j = 0; j < lpages; ++j)
7708 slot->arch.lpage_info[i - 1][j].write_count = 1;
7715 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7716 kvfree(slot->arch.rmap[i]);
7717 slot->arch.rmap[i] = NULL;
7721 kvfree(slot->arch.lpage_info[i - 1]);
7722 slot->arch.lpage_info[i - 1] = NULL;
7727 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7730 * memslots->generation has been incremented.
7731 * mmio generation may have reached its maximum value.
7733 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7736 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7737 struct kvm_memory_slot *memslot,
7738 const struct kvm_userspace_memory_region *mem,
7739 enum kvm_mr_change change)
7744 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7745 struct kvm_memory_slot *new)
7747 /* Still write protect RO slot */
7748 if (new->flags & KVM_MEM_READONLY) {
7749 kvm_mmu_slot_remove_write_access(kvm, new);
7754 * Call kvm_x86_ops dirty logging hooks when they are valid.
7756 * kvm_x86_ops->slot_disable_log_dirty is called when:
7758 * - KVM_MR_CREATE with dirty logging is disabled
7759 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7761 * The reason is, in case of PML, we need to set D-bit for any slots
7762 * with dirty logging disabled in order to eliminate unnecessary GPA
7763 * logging in PML buffer (and potential PML buffer full VMEXT). This
7764 * guarantees leaving PML enabled during guest's lifetime won't have
7765 * any additonal overhead from PML when guest is running with dirty
7766 * logging disabled for memory slots.
7768 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7769 * to dirty logging mode.
7771 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7773 * In case of write protect:
7775 * Write protect all pages for dirty logging.
7777 * All the sptes including the large sptes which point to this
7778 * slot are set to readonly. We can not create any new large
7779 * spte on this slot until the end of the logging.
7781 * See the comments in fast_page_fault().
7783 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7784 if (kvm_x86_ops->slot_enable_log_dirty)
7785 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7787 kvm_mmu_slot_remove_write_access(kvm, new);
7789 if (kvm_x86_ops->slot_disable_log_dirty)
7790 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7794 void kvm_arch_commit_memory_region(struct kvm *kvm,
7795 const struct kvm_userspace_memory_region *mem,
7796 const struct kvm_memory_slot *old,
7797 const struct kvm_memory_slot *new,
7798 enum kvm_mr_change change)
7800 int nr_mmu_pages = 0;
7802 if (!kvm->arch.n_requested_mmu_pages)
7803 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7806 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7809 * Dirty logging tracks sptes in 4k granularity, meaning that large
7810 * sptes have to be split. If live migration is successful, the guest
7811 * in the source machine will be destroyed and large sptes will be
7812 * created in the destination. However, if the guest continues to run
7813 * in the source machine (for example if live migration fails), small
7814 * sptes will remain around and cause bad performance.
7816 * Scan sptes if dirty logging has been stopped, dropping those
7817 * which can be collapsed into a single large-page spte. Later
7818 * page faults will create the large-page sptes.
7820 if ((change != KVM_MR_DELETE) &&
7821 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7822 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7823 kvm_mmu_zap_collapsible_sptes(kvm, new);
7826 * Set up write protection and/or dirty logging for the new slot.
7828 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7829 * been zapped so no dirty logging staff is needed for old slot. For
7830 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7831 * new and it's also covered when dealing with the new slot.
7833 * FIXME: const-ify all uses of struct kvm_memory_slot.
7835 if (change != KVM_MR_DELETE)
7836 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
7839 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7841 kvm_mmu_invalidate_zap_all_pages(kvm);
7844 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7845 struct kvm_memory_slot *slot)
7847 kvm_mmu_invalidate_zap_all_pages(kvm);
7850 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
7852 if (!list_empty_careful(&vcpu->async_pf.done))
7855 if (kvm_apic_has_events(vcpu))
7858 if (vcpu->arch.pv.pv_unhalted)
7861 if (atomic_read(&vcpu->arch.nmi_queued))
7864 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
7867 if (kvm_arch_interrupt_allowed(vcpu) &&
7868 kvm_cpu_has_interrupt(vcpu))
7874 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7876 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7877 kvm_x86_ops->check_nested_events(vcpu, false);
7879 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
7882 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7884 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7887 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7889 return kvm_x86_ops->interrupt_allowed(vcpu);
7892 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
7894 if (is_64_bit_mode(vcpu))
7895 return kvm_rip_read(vcpu);
7896 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7897 kvm_rip_read(vcpu));
7899 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
7901 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7903 return kvm_get_linear_rip(vcpu) == linear_rip;
7905 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7907 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7909 unsigned long rflags;
7911 rflags = kvm_x86_ops->get_rflags(vcpu);
7912 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7913 rflags &= ~X86_EFLAGS_TF;
7916 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7918 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7920 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7921 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7922 rflags |= X86_EFLAGS_TF;
7923 kvm_x86_ops->set_rflags(vcpu, rflags);
7926 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7928 __kvm_set_rflags(vcpu, rflags);
7929 kvm_make_request(KVM_REQ_EVENT, vcpu);
7931 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7933 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7937 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7941 r = kvm_mmu_reload(vcpu);
7945 if (!vcpu->arch.mmu.direct_map &&
7946 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7949 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7952 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7954 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7957 static inline u32 kvm_async_pf_next_probe(u32 key)
7959 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7962 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7964 u32 key = kvm_async_pf_hash_fn(gfn);
7966 while (vcpu->arch.apf.gfns[key] != ~0)
7967 key = kvm_async_pf_next_probe(key);
7969 vcpu->arch.apf.gfns[key] = gfn;
7972 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7975 u32 key = kvm_async_pf_hash_fn(gfn);
7977 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7978 (vcpu->arch.apf.gfns[key] != gfn &&
7979 vcpu->arch.apf.gfns[key] != ~0); i++)
7980 key = kvm_async_pf_next_probe(key);
7985 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7987 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7990 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7994 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7996 vcpu->arch.apf.gfns[i] = ~0;
7998 j = kvm_async_pf_next_probe(j);
7999 if (vcpu->arch.apf.gfns[j] == ~0)
8001 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8003 * k lies cyclically in ]i,j]
8005 * |....j i.k.| or |.k..j i...|
8007 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8008 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8013 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8016 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8020 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8021 struct kvm_async_pf *work)
8023 struct x86_exception fault;
8025 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8026 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8028 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8029 (vcpu->arch.apf.send_user_only &&
8030 kvm_x86_ops->get_cpl(vcpu) == 0))
8031 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8032 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8033 fault.vector = PF_VECTOR;
8034 fault.error_code_valid = true;
8035 fault.error_code = 0;
8036 fault.nested_page_fault = false;
8037 fault.address = work->arch.token;
8038 kvm_inject_page_fault(vcpu, &fault);
8042 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8043 struct kvm_async_pf *work)
8045 struct x86_exception fault;
8047 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8048 if (work->wakeup_all)
8049 work->arch.token = ~0; /* broadcast wakeup */
8051 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8053 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8054 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8055 fault.vector = PF_VECTOR;
8056 fault.error_code_valid = true;
8057 fault.error_code = 0;
8058 fault.nested_page_fault = false;
8059 fault.address = work->arch.token;
8060 kvm_inject_page_fault(vcpu, &fault);
8062 vcpu->arch.apf.halted = false;
8063 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8066 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8068 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8071 return !kvm_event_needs_reinjection(vcpu) &&
8072 kvm_x86_ops->interrupt_allowed(vcpu);
8075 void kvm_arch_start_assignment(struct kvm *kvm)
8077 atomic_inc(&kvm->arch.assigned_device_count);
8079 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8081 void kvm_arch_end_assignment(struct kvm *kvm)
8083 atomic_dec(&kvm->arch.assigned_device_count);
8085 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8087 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8089 return atomic_read(&kvm->arch.assigned_device_count);
8091 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8093 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8095 atomic_inc(&kvm->arch.noncoherent_dma_count);
8097 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8099 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8101 atomic_dec(&kvm->arch.noncoherent_dma_count);
8103 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8105 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8107 return atomic_read(&kvm->arch.noncoherent_dma_count);
8109 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8111 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8112 struct irq_bypass_producer *prod)
8114 struct kvm_kernel_irqfd *irqfd =
8115 container_of(cons, struct kvm_kernel_irqfd, consumer);
8117 if (kvm_x86_ops->update_pi_irte) {
8118 irqfd->producer = prod;
8119 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8120 prod->irq, irqfd->gsi, 1);
8126 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8127 struct irq_bypass_producer *prod)
8130 struct kvm_kernel_irqfd *irqfd =
8131 container_of(cons, struct kvm_kernel_irqfd, consumer);
8133 if (!kvm_x86_ops->update_pi_irte) {
8134 WARN_ON(irqfd->producer != NULL);
8138 WARN_ON(irqfd->producer != prod);
8139 irqfd->producer = NULL;
8142 * When producer of consumer is unregistered, we change back to
8143 * remapped mode, so we can re-use the current implementation
8144 * when the irq is masked/disabed or the consumer side (KVM
8145 * int this case doesn't want to receive the interrupts.
8147 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8149 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8150 " fails: %d\n", irqfd->consumer.token, ret);
8153 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8154 uint32_t guest_irq, bool set)
8156 if (!kvm_x86_ops->update_pi_irte)
8159 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8162 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8163 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8164 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8165 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8166 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8167 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8168 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8169 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8170 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8171 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8172 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8173 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8174 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8175 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8176 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8177 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8178 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);