drivers/clk/tegra/clk-tegra20.c

   1 /*
   2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/clk-provider.h>
  20 #include <linux/clkdev.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/clk/tegra.h>
  24 #include <linux/delay.h>
  25
  26 #include "clk.h"
  27
  28 #define RST_DEVICES_L 0x004
  29 #define RST_DEVICES_H 0x008
  30 #define RST_DEVICES_U 0x00c
  31 #define RST_DEVICES_SET_L 0x300
  32 #define RST_DEVICES_CLR_L 0x304
  33 #define RST_DEVICES_SET_H 0x308
  34 #define RST_DEVICES_CLR_H 0x30c
  35 #define RST_DEVICES_SET_U 0x310
  36 #define RST_DEVICES_CLR_U 0x314
  37 #define RST_DEVICES_NUM 3
  38
  39 #define CLK_OUT_ENB_L 0x010
  40 #define CLK_OUT_ENB_H 0x014
  41 #define CLK_OUT_ENB_U 0x018
  42 #define CLK_OUT_ENB_SET_L 0x320
  43 #define CLK_OUT_ENB_CLR_L 0x324
  44 #define CLK_OUT_ENB_SET_H 0x328
  45 #define CLK_OUT_ENB_CLR_H 0x32c
  46 #define CLK_OUT_ENB_SET_U 0x330
  47 #define CLK_OUT_ENB_CLR_U 0x334
  48 #define CLK_OUT_ENB_NUM 3
  49
  50 #define OSC_CTRL 0x50
  51 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
  52 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
  53 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
  54 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
  55 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
  56 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
  57
  58 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
  59 #define OSC_CTRL_PLL_REF_DIV_1          (0<<28)
  60 #define OSC_CTRL_PLL_REF_DIV_2          (1<<28)
  61 #define OSC_CTRL_PLL_REF_DIV_4          (2<<28)
  62
  63 #define OSC_FREQ_DET 0x58
  64 #define OSC_FREQ_DET_TRIG (1<<31)
  65
  66 #define OSC_FREQ_DET_STATUS 0x5c
  67 #define OSC_FREQ_DET_BUSY (1<<31)
  68 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
  69
  70 #define PLLS_BASE 0xf0
  71 #define PLLS_MISC 0xf4
  72 #define PLLC_BASE 0x80
  73 #define PLLC_MISC 0x8c
  74 #define PLLM_BASE 0x90
  75 #define PLLM_MISC 0x9c
  76 #define PLLP_BASE 0xa0
  77 #define PLLP_MISC 0xac
  78 #define PLLA_BASE 0xb0
  79 #define PLLA_MISC 0xbc
  80 #define PLLU_BASE 0xc0
  81 #define PLLU_MISC 0xcc
  82 #define PLLD_BASE 0xd0
  83 #define PLLD_MISC 0xdc
  84 #define PLLX_BASE 0xe0
  85 #define PLLX_MISC 0xe4
  86 #define PLLE_BASE 0xe8
  87 #define PLLE_MISC 0xec
  88
  89 #define PLL_BASE_LOCK 27
  90 #define PLLE_MISC_LOCK 11
  91
  92 #define PLL_MISC_LOCK_ENABLE 18
  93 #define PLLDU_MISC_LOCK_ENABLE 22
  94 #define PLLE_MISC_LOCK_ENABLE 9
  95
  96 #define PLLC_OUT 0x84
  97 #define PLLM_OUT 0x94
  98 #define PLLP_OUTA 0xa4
  99 #define PLLP_OUTB 0xa8
 100 #define PLLA_OUT 0xb4
 101
 102 #define CCLK_BURST_POLICY 0x20
 103 #define SUPER_CCLK_DIVIDER 0x24
 104 #define SCLK_BURST_POLICY 0x28
 105 #define SUPER_SCLK_DIVIDER 0x2c
 106 #define CLK_SYSTEM_RATE 0x30
 107
 108 #define CCLK_BURST_POLICY_SHIFT 28
 109 #define CCLK_RUN_POLICY_SHIFT   4
 110 #define CCLK_IDLE_POLICY_SHIFT  0
 111 #define CCLK_IDLE_POLICY        1
 112 #define CCLK_RUN_POLICY         2
 113 #define CCLK_BURST_POLICY_PLLX  8
 114
 115 #define CLK_SOURCE_I2S1 0x100
 116 #define CLK_SOURCE_I2S2 0x104
 117 #define CLK_SOURCE_SPDIF_OUT 0x108
 118 #define CLK_SOURCE_SPDIF_IN 0x10c
 119 #define CLK_SOURCE_PWM 0x110
 120 #define CLK_SOURCE_SPI 0x114
 121 #define CLK_SOURCE_SBC1 0x134
 122 #define CLK_SOURCE_SBC2 0x118
 123 #define CLK_SOURCE_SBC3 0x11c
 124 #define CLK_SOURCE_SBC4 0x1b4
 125 #define CLK_SOURCE_XIO 0x120
 126 #define CLK_SOURCE_TWC 0x12c
 127 #define CLK_SOURCE_IDE 0x144
 128 #define CLK_SOURCE_NDFLASH 0x160
 129 #define CLK_SOURCE_VFIR 0x168
 130 #define CLK_SOURCE_SDMMC1 0x150
 131 #define CLK_SOURCE_SDMMC2 0x154
 132 #define CLK_SOURCE_SDMMC3 0x1bc
 133 #define CLK_SOURCE_SDMMC4 0x164
 134 #define CLK_SOURCE_CVE 0x140
 135 #define CLK_SOURCE_TVO 0x188
 136 #define CLK_SOURCE_TVDAC 0x194
 137 #define CLK_SOURCE_HDMI 0x18c
 138 #define CLK_SOURCE_DISP1 0x138
 139 #define CLK_SOURCE_DISP2 0x13c
 140 #define CLK_SOURCE_CSITE 0x1d4
 141 #define CLK_SOURCE_LA 0x1f8
 142 #define CLK_SOURCE_OWR 0x1cc
 143 #define CLK_SOURCE_NOR 0x1d0
 144 #define CLK_SOURCE_MIPI 0x174
 145 #define CLK_SOURCE_I2C1 0x124
 146 #define CLK_SOURCE_I2C2 0x198
 147 #define CLK_SOURCE_I2C3 0x1b8
 148 #define CLK_SOURCE_DVC 0x128
 149 #define CLK_SOURCE_UARTA 0x178
 150 #define CLK_SOURCE_UARTB 0x17c
 151 #define CLK_SOURCE_UARTC 0x1a0
 152 #define CLK_SOURCE_UARTD 0x1c0
 153 #define CLK_SOURCE_UARTE 0x1c4
 154 #define CLK_SOURCE_3D 0x158
 155 #define CLK_SOURCE_2D 0x15c
 156 #define CLK_SOURCE_MPE 0x170
 157 #define CLK_SOURCE_EPP 0x16c
 158 #define CLK_SOURCE_HOST1X 0x180
 159 #define CLK_SOURCE_VDE 0x1c8
 160 #define CLK_SOURCE_VI 0x148
 161 #define CLK_SOURCE_VI_SENSOR 0x1a8
 162 #define CLK_SOURCE_EMC 0x19c
 163
 164 #define AUDIO_SYNC_CLK 0x38
 165
 166 #define PMC_CTRL 0x0
 167 #define PMC_CTRL_BLINK_ENB 7
 168 #define PMC_DPD_PADS_ORIDE 0x1c
 169 #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
 170 #define PMC_BLINK_TIMER 0x40
 171
 172 /* Tegra CPU clock and reset control regs */
 173 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
 174 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
 175 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
 176
 177 #define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
 178 #define CPU_RESET(cpu)  (0x1111ul << (cpu))
 179
 180 #ifdef CONFIG_PM_SLEEP
 181 static struct cpu_clk_suspend_context {
 182         u32 pllx_misc;
 183         u32 pllx_base;
 184
 185         u32 cpu_burst;
 186         u32 clk_csite_src;
 187         u32 cclk_divider;
 188 } tegra20_cpu_clk_sctx;
 189 #endif
 190
 191 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 192
 193 static void __iomem *clk_base;
 194 static void __iomem *pmc_base;
 195
 196 static DEFINE_SPINLOCK(pll_div_lock);
 197 static DEFINE_SPINLOCK(sysrate_lock);
 198
 199 #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
 200                             _clk_num, _regs, _gate_flags, _clk_id)      \
 201         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 202                         30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,      \
 203                         _regs, _clk_num, periph_clk_enb_refcnt,         \
 204                         _gate_flags, _clk_id)
 205
 206 #define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
 207                             _clk_num, _regs, _gate_flags, _clk_id)      \
 208         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 209                         30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,    \
 210                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 211                         _clk_id)
 212
 213 #define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
 214                               _clk_num, _regs, _gate_flags, _clk_id)    \
 215         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 216                         30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, _regs, \
 217                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 218                         _clk_id)
 219
 220 #define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
 221                               _mux_shift, _mux_width, _clk_num, _regs,  \
 222                               _gate_flags, _clk_id)                     \
 223         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 224                         _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs,   \
 225                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 226                         _clk_id)
 227
 228 /* IDs assigned here must be in sync with DT bindings definition
 229  * for Tegra20 clocks .
 230  */
 231 enum tegra20_clk {
 232         cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
 233         ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
 234         gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
 235         kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
 236         dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
 237         usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
 238         pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
 239         iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
 240         uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
 241         osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
 242         pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
 243         pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_s, pll_u,
 244         pll_x, cop, audio, pll_ref, twd, clk_max,
 245 };
 246
 247 static struct clk *clks[clk_max];
 248 static struct clk_onecell_data clk_data;
 249
 250 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
 251         { 12000000, 600000000, 600, 12, 1, 8 },
 252         { 13000000, 600000000, 600, 13, 1, 8 },
 253         { 19200000, 600000000, 500, 16, 1, 6 },
 254         { 26000000, 600000000, 600, 26, 1, 8 },
 255         { 0, 0, 0, 0, 0, 0 },
 256 };
 257
 258 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
 259         { 12000000, 666000000, 666, 12, 1, 8},
 260         { 13000000, 666000000, 666, 13, 1, 8},
 261         { 19200000, 666000000, 555, 16, 1, 8},
 262         { 26000000, 666000000, 666, 26, 1, 8},
 263         { 12000000, 600000000, 600, 12, 1, 8},
 264         { 13000000, 600000000, 600, 13, 1, 8},
 265         { 19200000, 600000000, 375, 12, 1, 6},
 266         { 26000000, 600000000, 600, 26, 1, 8},
 267         { 0, 0, 0, 0, 0, 0 },
 268 };
 269
 270 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
 271         { 12000000, 216000000, 432, 12, 2, 8},
 272         { 13000000, 216000000, 432, 13, 2, 8},
 273         { 19200000, 216000000, 90,   4, 2, 1},
 274         { 26000000, 216000000, 432, 26, 2, 8},
 275         { 12000000, 432000000, 432, 12, 1, 8},
 276         { 13000000, 432000000, 432, 13, 1, 8},
 277         { 19200000, 432000000, 90,   4, 1, 1},
 278         { 26000000, 432000000, 432, 26, 1, 8},
 279         { 0, 0, 0, 0, 0, 0 },
 280 };
 281
 282 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
 283         { 28800000, 56448000, 49, 25, 1, 1},
 284         { 28800000, 73728000, 64, 25, 1, 1},
 285         { 28800000, 24000000,  5,  6, 1, 1},
 286         { 0, 0, 0, 0, 0, 0 },
 287 };
 288
 289 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
 290         { 12000000, 216000000, 216, 12, 1, 4},
 291         { 13000000, 216000000, 216, 13, 1, 4},
 292         { 19200000, 216000000, 135, 12, 1, 3},
 293         { 26000000, 216000000, 216, 26, 1, 4},
 294
 295         { 12000000, 594000000, 594, 12, 1, 8},
 296         { 13000000, 594000000, 594, 13, 1, 8},
 297         { 19200000, 594000000, 495, 16, 1, 8},
 298         { 26000000, 594000000, 594, 26, 1, 8},
 299
 300         { 12000000, 1000000000, 1000, 12, 1, 12},
 301         { 13000000, 1000000000, 1000, 13, 1, 12},
 302         { 19200000, 1000000000, 625,  12, 1, 8},
 303         { 26000000, 1000000000, 1000, 26, 1, 12},
 304
 305         { 0, 0, 0, 0, 0, 0 },
 306 };
 307
 308 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
 309         { 12000000, 480000000, 960, 12, 2, 0},
 310         { 13000000, 480000000, 960, 13, 2, 0},
 311         { 19200000, 480000000, 200, 4,  2, 0},
 312         { 26000000, 480000000, 960, 26, 2, 0},
 313         { 0, 0, 0, 0, 0, 0 },
 314 };
 315
 316 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
 317         /* 1 GHz */
 318         { 12000000, 1000000000, 1000, 12, 1, 12},
 319         { 13000000, 1000000000, 1000, 13, 1, 12},
 320         { 19200000, 1000000000, 625,  12, 1, 8},
 321         { 26000000, 1000000000, 1000, 26, 1, 12},
 322
 323         /* 912 MHz */
 324         { 12000000, 912000000,  912,  12, 1, 12},
 325         { 13000000, 912000000,  912,  13, 1, 12},
 326         { 19200000, 912000000,  760,  16, 1, 8},
 327         { 26000000, 912000000,  912,  26, 1, 12},
 328
 329         /* 816 MHz */
 330         { 12000000, 816000000,  816,  12, 1, 12},
 331         { 13000000, 816000000,  816,  13, 1, 12},
 332         { 19200000, 816000000,  680,  16, 1, 8},
 333         { 26000000, 816000000,  816,  26, 1, 12},
 334
 335         /* 760 MHz */
 336         { 12000000, 760000000,  760,  12, 1, 12},
 337         { 13000000, 760000000,  760,  13, 1, 12},
 338         { 19200000, 760000000,  950,  24, 1, 8},
 339         { 26000000, 760000000,  760,  26, 1, 12},
 340
 341         /* 750 MHz */
 342         { 12000000, 750000000,  750,  12, 1, 12},
 343         { 13000000, 750000000,  750,  13, 1, 12},
 344         { 19200000, 750000000,  625,  16, 1, 8},
 345         { 26000000, 750000000,  750,  26, 1, 12},
 346
 347         /* 608 MHz */
 348         { 12000000, 608000000,  608,  12, 1, 12},
 349         { 13000000, 608000000,  608,  13, 1, 12},
 350         { 19200000, 608000000,  380,  12, 1, 8},
 351         { 26000000, 608000000,  608,  26, 1, 12},
 352
 353         /* 456 MHz */
 354         { 12000000, 456000000,  456,  12, 1, 12},
 355         { 13000000, 456000000,  456,  13, 1, 12},
 356         { 19200000, 456000000,  380,  16, 1, 8},
 357         { 26000000, 456000000,  456,  26, 1, 12},
 358
 359         /* 312 MHz */
 360         { 12000000, 312000000,  312,  12, 1, 12},
 361         { 13000000, 312000000,  312,  13, 1, 12},
 362         { 19200000, 312000000,  260,  16, 1, 8},
 363         { 26000000, 312000000,  312,  26, 1, 12},
 364
 365         { 0, 0, 0, 0, 0, 0 },
 366 };
 367
 368 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
 369         { 12000000, 100000000,  200,  24, 1, 0 },
 370         { 0, 0, 0, 0, 0, 0 },
 371 };
 372
 373 /* PLL parameters */
 374 static struct tegra_clk_pll_params pll_c_params = {
 375         .input_min = 2000000,
 376         .input_max = 31000000,
 377         .cf_min = 1000000,
 378         .cf_max = 6000000,
 379         .vco_min = 20000000,
 380         .vco_max = 1400000000,
 381         .base_reg = PLLC_BASE,
 382         .misc_reg = PLLC_MISC,
 383         .lock_bit_idx = PLL_BASE_LOCK,
 384         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 385         .lock_delay = 300,
 386 };
 387
 388 static struct tegra_clk_pll_params pll_m_params = {
 389         .input_min = 2000000,
 390         .input_max = 31000000,
 391         .cf_min = 1000000,
 392         .cf_max = 6000000,
 393         .vco_min = 20000000,
 394         .vco_max = 1200000000,
 395         .base_reg = PLLM_BASE,
 396         .misc_reg = PLLM_MISC,
 397         .lock_bit_idx = PLL_BASE_LOCK,
 398         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 399         .lock_delay = 300,
 400 };
 401
 402 static struct tegra_clk_pll_params pll_p_params = {
 403         .input_min = 2000000,
 404         .input_max = 31000000,
 405         .cf_min = 1000000,
 406         .cf_max = 6000000,
 407         .vco_min = 20000000,
 408         .vco_max = 1400000000,
 409         .base_reg = PLLP_BASE,
 410         .misc_reg = PLLP_MISC,
 411         .lock_bit_idx = PLL_BASE_LOCK,
 412         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 413         .lock_delay = 300,
 414 };
 415
 416 static struct tegra_clk_pll_params pll_a_params = {
 417         .input_min = 2000000,
 418         .input_max = 31000000,
 419         .cf_min = 1000000,
 420         .cf_max = 6000000,
 421         .vco_min = 20000000,
 422         .vco_max = 1400000000,
 423         .base_reg = PLLA_BASE,
 424         .misc_reg = PLLA_MISC,
 425         .lock_bit_idx = PLL_BASE_LOCK,
 426         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 427         .lock_delay = 300,
 428 };
 429
 430 static struct tegra_clk_pll_params pll_d_params = {
 431         .input_min = 2000000,
 432         .input_max = 40000000,
 433         .cf_min = 1000000,
 434         .cf_max = 6000000,
 435         .vco_min = 40000000,
 436         .vco_max = 1000000000,
 437         .base_reg = PLLD_BASE,
 438         .misc_reg = PLLD_MISC,
 439         .lock_bit_idx = PLL_BASE_LOCK,
 440         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 441         .lock_delay = 1000,
 442 };
 443
 444 static struct tegra_clk_pll_params pll_u_params = {
 445         .input_min = 2000000,
 446         .input_max = 40000000,
 447         .cf_min = 1000000,
 448         .cf_max = 6000000,
 449         .vco_min = 48000000,
 450         .vco_max = 960000000,
 451         .base_reg = PLLU_BASE,
 452         .misc_reg = PLLU_MISC,
 453         .lock_bit_idx = PLL_BASE_LOCK,
 454         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 455         .lock_delay = 1000,
 456 };
 457
 458 static struct tegra_clk_pll_params pll_x_params = {
 459         .input_min = 2000000,
 460         .input_max = 31000000,
 461         .cf_min = 1000000,
 462         .cf_max = 6000000,
 463         .vco_min = 20000000,
 464         .vco_max = 1200000000,
 465         .base_reg = PLLX_BASE,
 466         .misc_reg = PLLX_MISC,
 467         .lock_bit_idx = PLL_BASE_LOCK,
 468         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 469         .lock_delay = 300,
 470 };
 471
 472 static struct tegra_clk_pll_params pll_e_params = {
 473         .input_min = 12000000,
 474         .input_max = 12000000,
 475         .cf_min = 0,
 476         .cf_max = 0,
 477         .vco_min = 0,
 478         .vco_max = 0,
 479         .base_reg = PLLE_BASE,
 480         .misc_reg = PLLE_MISC,
 481         .lock_bit_idx = PLLE_MISC_LOCK,
 482         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
 483         .lock_delay = 0,
 484 };
 485
 486 /* Peripheral clock registers */
 487 static struct tegra_clk_periph_regs periph_l_regs = {
 488         .enb_reg = CLK_OUT_ENB_L,
 489         .enb_set_reg = CLK_OUT_ENB_SET_L,
 490         .enb_clr_reg = CLK_OUT_ENB_CLR_L,
 491         .rst_reg = RST_DEVICES_L,
 492         .rst_set_reg = RST_DEVICES_SET_L,
 493         .rst_clr_reg = RST_DEVICES_CLR_L,
 494 };
 495
 496 static struct tegra_clk_periph_regs periph_h_regs = {
 497         .enb_reg = CLK_OUT_ENB_H,
 498         .enb_set_reg = CLK_OUT_ENB_SET_H,
 499         .enb_clr_reg = CLK_OUT_ENB_CLR_H,
 500         .rst_reg = RST_DEVICES_H,
 501         .rst_set_reg = RST_DEVICES_SET_H,
 502         .rst_clr_reg = RST_DEVICES_CLR_H,
 503 };
 504
 505 static struct tegra_clk_periph_regs periph_u_regs = {
 506         .enb_reg = CLK_OUT_ENB_U,
 507         .enb_set_reg = CLK_OUT_ENB_SET_U,
 508         .enb_clr_reg = CLK_OUT_ENB_CLR_U,
 509         .rst_reg = RST_DEVICES_U,
 510         .rst_set_reg = RST_DEVICES_SET_U,
 511         .rst_clr_reg = RST_DEVICES_CLR_U,
 512 };
 513
 514 static unsigned long tegra20_clk_measure_input_freq(void)
 515 {
 516         u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
 517         u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
 518         u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
 519         unsigned long input_freq;
 520
 521         switch (auto_clk_control) {
 522         case OSC_CTRL_OSC_FREQ_12MHZ:
 523                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 524                 input_freq = 12000000;
 525                 break;
 526         case OSC_CTRL_OSC_FREQ_13MHZ:
 527                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 528                 input_freq = 13000000;
 529                 break;
 530         case OSC_CTRL_OSC_FREQ_19_2MHZ:
 531                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 532                 input_freq = 19200000;
 533                 break;
 534         case OSC_CTRL_OSC_FREQ_26MHZ:
 535                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 536                 input_freq = 26000000;
 537                 break;
 538         default:
 539                 pr_err("Unexpected clock autodetect value %d",
 540                        auto_clk_control);
 541                 BUG();
 542                 return 0;
 543         }
 544
 545         return input_freq;
 546 }
 547
 548 static unsigned int tegra20_get_pll_ref_div(void)
 549 {
 550         u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
 551                 OSC_CTRL_PLL_REF_DIV_MASK;
 552
 553         switch (pll_ref_div) {
 554         case OSC_CTRL_PLL_REF_DIV_1:
 555                 return 1;
 556         case OSC_CTRL_PLL_REF_DIV_2:
 557                 return 2;
 558         case OSC_CTRL_PLL_REF_DIV_4:
 559                 return 4;
 560         default:
 561                 pr_err("Invalied pll ref divider %d\n", pll_ref_div);
 562                 BUG();
 563         }
 564         return 0;
 565 }
 566
 567 static void tegra20_pll_init(void)
 568 {
 569         struct clk *clk;
 570
 571         /* PLLC */
 572         clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
 573                             0, &pll_c_params, TEGRA_PLL_HAS_CPCON,
 574                             pll_c_freq_table, NULL);
 575         clk_register_clkdev(clk, "pll_c", NULL);
 576         clks[pll_c] = clk;
 577
 578         /* PLLC_OUT1 */
 579         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
 580                                 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 581                                 8, 8, 1, NULL);
 582         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
 583                                 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
 584                                 0, NULL);
 585         clk_register_clkdev(clk, "pll_c_out1", NULL);
 586         clks[pll_c_out1] = clk;
 587
 588         /* PLLP */
 589         clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, NULL, 0,
 590                             216000000, &pll_p_params, TEGRA_PLL_FIXED |
 591                             TEGRA_PLL_HAS_CPCON, pll_p_freq_table, NULL);
 592         clk_register_clkdev(clk, "pll_p", NULL);
 593         clks[pll_p] = clk;
 594
 595         /* PLLP_OUT1 */
 596         clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
 597                                 clk_base + PLLP_OUTA, 0,
 598                                 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
 599                                 8, 8, 1, &pll_div_lock);
 600         clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
 601                                 clk_base + PLLP_OUTA, 1, 0,
 602                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 603                                 &pll_div_lock);
 604         clk_register_clkdev(clk, "pll_p_out1", NULL);
 605         clks[pll_p_out1] = clk;
 606
 607         /* PLLP_OUT2 */
 608         clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
 609                                 clk_base + PLLP_OUTA, 0,
 610                                 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
 611                                 24, 8, 1, &pll_div_lock);
 612         clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
 613                                 clk_base + PLLP_OUTA, 17, 16,
 614                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 615                                 &pll_div_lock);
 616         clk_register_clkdev(clk, "pll_p_out2", NULL);
 617         clks[pll_p_out2] = clk;
 618
 619         /* PLLP_OUT3 */
 620         clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
 621                                 clk_base + PLLP_OUTB, 0,
 622                                 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
 623                                 8, 8, 1, &pll_div_lock);
 624         clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
 625                                 clk_base + PLLP_OUTB, 1, 0,
 626                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 627                                 &pll_div_lock);
 628         clk_register_clkdev(clk, "pll_p_out3", NULL);
 629         clks[pll_p_out3] = clk;
 630
 631         /* PLLP_OUT4 */
 632         clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
 633                                 clk_base + PLLP_OUTB, 0,
 634                                 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
 635                                 24, 8, 1, &pll_div_lock);
 636         clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
 637                                 clk_base + PLLP_OUTB, 17, 16,
 638                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 639                                 &pll_div_lock);
 640         clk_register_clkdev(clk, "pll_p_out4", NULL);
 641         clks[pll_p_out4] = clk;
 642
 643         /* PLLM */
 644         clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
 645                             CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
 646                             &pll_m_params, TEGRA_PLL_HAS_CPCON,
 647                             pll_m_freq_table, NULL);
 648         clk_register_clkdev(clk, "pll_m", NULL);
 649         clks[pll_m] = clk;
 650
 651         /* PLLM_OUT1 */
 652         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
 653                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 654                                 8, 8, 1, NULL);
 655         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
 656                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
 657                                 CLK_SET_RATE_PARENT, 0, NULL);
 658         clk_register_clkdev(clk, "pll_m_out1", NULL);
 659         clks[pll_m_out1] = clk;
 660
 661         /* PLLX */
 662         clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
 663                             0, &pll_x_params, TEGRA_PLL_HAS_CPCON,
 664                             pll_x_freq_table, NULL);
 665         clk_register_clkdev(clk, "pll_x", NULL);
 666         clks[pll_x] = clk;
 667
 668         /* PLLU */
 669         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
 670                             0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON,
 671                             pll_u_freq_table, NULL);
 672         clk_register_clkdev(clk, "pll_u", NULL);
 673         clks[pll_u] = clk;
 674
 675         /* PLLD */
 676         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
 677                             0, &pll_d_params, TEGRA_PLL_HAS_CPCON,
 678                             pll_d_freq_table, NULL);
 679         clk_register_clkdev(clk, "pll_d", NULL);
 680         clks[pll_d] = clk;
 681
 682         /* PLLD_OUT0 */
 683         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
 684                                         CLK_SET_RATE_PARENT, 1, 2);
 685         clk_register_clkdev(clk, "pll_d_out0", NULL);
 686         clks[pll_d_out0] = clk;
 687
 688         /* PLLA */
 689         clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
 690                             0, &pll_a_params, TEGRA_PLL_HAS_CPCON,
 691                             pll_a_freq_table, NULL);
 692         clk_register_clkdev(clk, "pll_a", NULL);
 693         clks[pll_a] = clk;
 694
 695         /* PLLA_OUT0 */
 696         clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
 697                                 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 698                                 8, 8, 1, NULL);
 699         clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
 700                                 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
 701                                 CLK_SET_RATE_PARENT, 0, NULL);
 702         clk_register_clkdev(clk, "pll_a_out0", NULL);
 703         clks[pll_a_out0] = clk;
 704
 705         /* PLLE */
 706         clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
 707                              0, 100000000, &pll_e_params,
 708                              0, pll_e_freq_table, NULL);
 709         clk_register_clkdev(clk, "pll_e", NULL);
 710         clks[pll_e] = clk;
 711 }
 712
 713 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
 714                                       "pll_p", "pll_p_out4",
 715                                       "pll_p_out3", "clk_d", "pll_x" };
 716 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
 717                                       "pll_p_out3", "pll_p_out2", "clk_d",
 718                                       "clk_32k", "pll_m_out1" };
 719
 720 static void tegra20_super_clk_init(void)
 721 {
 722         struct clk *clk;
 723
 724         /* CCLK */
 725         clk = tegra_clk_register_super_mux("cclk", cclk_parents,
 726                               ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
 727                               clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
 728         clk_register_clkdev(clk, "cclk", NULL);
 729         clks[cclk] = clk;
 730
 731         /* SCLK */
 732         clk = tegra_clk_register_super_mux("sclk", sclk_parents,
 733                               ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT,
 734                               clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
 735         clk_register_clkdev(clk, "sclk", NULL);
 736         clks[sclk] = clk;
 737
 738         /* HCLK */
 739         clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
 740                                    clk_base + CLK_SYSTEM_RATE, 4, 2, 0,
 741                                    &sysrate_lock);
 742         clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
 743                                 clk_base + CLK_SYSTEM_RATE, 7,
 744                                 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
 745         clk_register_clkdev(clk, "hclk", NULL);
 746         clks[hclk] = clk;
 747
 748         /* PCLK */
 749         clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
 750                                    clk_base + CLK_SYSTEM_RATE, 0, 2, 0,
 751                                    &sysrate_lock);
 752         clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
 753                                 clk_base + CLK_SYSTEM_RATE, 3,
 754                                 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
 755         clk_register_clkdev(clk, "pclk", NULL);
 756         clks[pclk] = clk;
 757
 758         /* twd */
 759         clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
 760         clk_register_clkdev(clk, "twd", NULL);
 761         clks[twd] = clk;
 762 }
 763
 764 static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused",
 765                                       "pll_a_out0", "unused", "unused",
 766                                       "unused"};
 767
 768 static void __init tegra20_audio_clk_init(void)
 769 {
 770         struct clk *clk;
 771
 772         /* audio */
 773         clk = clk_register_mux(NULL, "audio_mux", audio_parents,
 774                                 ARRAY_SIZE(audio_parents), 0,
 775                                 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
 776         clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
 777                                 clk_base + AUDIO_SYNC_CLK, 4,
 778                                 CLK_GATE_SET_TO_DISABLE, NULL);
 779         clk_register_clkdev(clk, "audio", NULL);
 780         clks[audio] = clk;
 781
 782         /* audio_2x */
 783         clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
 784                                         CLK_SET_RATE_PARENT, 2, 1);
 785         clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
 786                                     TEGRA_PERIPH_NO_RESET, clk_base,
 787                                     CLK_SET_RATE_PARENT, 89, &periph_u_regs,
 788                                     periph_clk_enb_refcnt);
 789         clk_register_clkdev(clk, "audio_2x", NULL);
 790         clks[audio_2x] = clk;
 791
 792 }
 793
 794 static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
 795                                      "clk_m"};
 796 static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
 797                                      "clk_m"};
 798 static const char *spdif_out_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
 799                                           "clk_m"};
 800 static const char *spdif_in_parents[] = {"pll_p", "pll_c", "pll_m"};
 801 static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m",
 802                                     "clk_32k"};
 803 static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
 804 static const char *mux_pllmcpa[] = {"pll_m", "pll_c", "pll_c", "pll_a"};
 805 static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c",
 806                                         "clk_m"};
 807 static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"};
 808
 809 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
 810         TEGRA_INIT_DATA_MUX("i2s1",     NULL,           "tegra20-i2s.0", i2s1_parents,      CLK_SOURCE_I2S1,      11,   &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
 811         TEGRA_INIT_DATA_MUX("i2s2",     NULL,           "tegra20-i2s.1", i2s2_parents,      CLK_SOURCE_I2S2,      18,   &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
 812         TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out",   "tegra20-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10,   &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
 813         TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in",     "tegra20-spdif", spdif_in_parents,  CLK_SOURCE_SPDIF_IN,  10,   &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
 814         TEGRA_INIT_DATA_MUX("sbc1",     NULL,           "spi_tegra.0",   mux_pllpcm_clkm,   CLK_SOURCE_SBC1,      41,   &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
 815         TEGRA_INIT_DATA_MUX("sbc2",     NULL,           "spi_tegra.1",   mux_pllpcm_clkm,   CLK_SOURCE_SBC2,      44,   &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
 816         TEGRA_INIT_DATA_MUX("sbc3",     NULL,           "spi_tegra.2",   mux_pllpcm_clkm,   CLK_SOURCE_SBC3,      46,   &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
 817         TEGRA_INIT_DATA_MUX("sbc4",     NULL,           "spi_tegra.3",   mux_pllpcm_clkm,   CLK_SOURCE_SBC4,      68,   &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
 818         TEGRA_INIT_DATA_MUX("spi",      NULL,           "spi",           mux_pllpcm_clkm,   CLK_SOURCE_SPI,       43,   &periph_h_regs, TEGRA_PERIPH_ON_APB, spi),
 819         TEGRA_INIT_DATA_MUX("xio",      NULL,           "xio",           mux_pllpcm_clkm,   CLK_SOURCE_XIO,       45,   &periph_h_regs, 0, xio),
 820         TEGRA_INIT_DATA_MUX("twc",      NULL,           "twc",           mux_pllpcm_clkm,   CLK_SOURCE_TWC,       16,   &periph_l_regs, TEGRA_PERIPH_ON_APB, twc),
 821         TEGRA_INIT_DATA_MUX("ide",      NULL,           "ide",           mux_pllpcm_clkm,   CLK_SOURCE_XIO,       25,   &periph_l_regs, 0, ide),
 822         TEGRA_INIT_DATA_MUX("ndflash",  NULL,           "tegra_nand",    mux_pllpcm_clkm,   CLK_SOURCE_NDFLASH,   13,   &periph_l_regs, 0, ndflash),
 823         TEGRA_INIT_DATA_MUX("vfir",     NULL,           "vfir",          mux_pllpcm_clkm,   CLK_SOURCE_VFIR,      7,    &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
 824         TEGRA_INIT_DATA_MUX("csite",    NULL,           "csite",         mux_pllpcm_clkm,   CLK_SOURCE_CSITE,     73,   &periph_u_regs, 0, csite),
 825         TEGRA_INIT_DATA_MUX("la",       NULL,           "la",            mux_pllpcm_clkm,   CLK_SOURCE_LA,        76,   &periph_u_regs, 0, la),
 826         TEGRA_INIT_DATA_MUX("owr",      NULL,           "tegra_w1",      mux_pllpcm_clkm,   CLK_SOURCE_OWR,       71,   &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
 827         TEGRA_INIT_DATA_MUX("mipi",     NULL,           "mipi",          mux_pllpcm_clkm,   CLK_SOURCE_MIPI,      50,   &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
 828         TEGRA_INIT_DATA_MUX("vde",      NULL,           "vde",           mux_pllpcm_clkm,   CLK_SOURCE_VDE,       61,   &periph_h_regs, 0, vde),
 829         TEGRA_INIT_DATA_MUX("vi",       "vi",           "tegra_camera",  mux_pllmcpa,       CLK_SOURCE_VI,        20,   &periph_l_regs, 0, vi),
 830         TEGRA_INIT_DATA_MUX("epp",      NULL,           "epp",           mux_pllmcpa,       CLK_SOURCE_EPP,       19,   &periph_l_regs, 0, epp),
 831         TEGRA_INIT_DATA_MUX("mpe",      NULL,           "mpe",           mux_pllmcpa,       CLK_SOURCE_MPE,       60,   &periph_h_regs, 0, mpe),
 832         TEGRA_INIT_DATA_MUX("host1x",   NULL,           "host1x",        mux_pllmcpa,       CLK_SOURCE_HOST1X,    28,   &periph_l_regs, 0, host1x),
 833         TEGRA_INIT_DATA_MUX("3d",       NULL,           "3d",            mux_pllmcpa,       CLK_SOURCE_3D,        24,   &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
 834         TEGRA_INIT_DATA_MUX("2d",       NULL,           "2d",            mux_pllmcpa,       CLK_SOURCE_2D,        21,   &periph_l_regs, 0, gr2d),
 835         TEGRA_INIT_DATA_MUX("nor",      NULL,           "tegra-nor",     mux_pllpcm_clkm,   CLK_SOURCE_NOR,       42,   &periph_h_regs, 0, nor),
 836         TEGRA_INIT_DATA_MUX("sdmmc1",   NULL,           "sdhci-tegra.0", mux_pllpcm_clkm,   CLK_SOURCE_SDMMC1,    14,   &periph_l_regs, 0, sdmmc1),
 837         TEGRA_INIT_DATA_MUX("sdmmc2",   NULL,           "sdhci-tegra.1", mux_pllpcm_clkm,   CLK_SOURCE_SDMMC2,    9,    &periph_l_regs, 0, sdmmc2),
 838         TEGRA_INIT_DATA_MUX("sdmmc3",   NULL,           "sdhci-tegra.2", mux_pllpcm_clkm,   CLK_SOURCE_SDMMC3,    69,   &periph_u_regs, 0, sdmmc3),
 839         TEGRA_INIT_DATA_MUX("sdmmc4",   NULL,           "sdhci-tegra.3", mux_pllpcm_clkm,   CLK_SOURCE_SDMMC4,    15,   &periph_l_regs, 0, sdmmc4),
 840         TEGRA_INIT_DATA_MUX("cve",      NULL,           "cve",           mux_pllpdc_clkm,   CLK_SOURCE_CVE,       49,   &periph_h_regs, 0, cve),
 841         TEGRA_INIT_DATA_MUX("tvo",      NULL,           "tvo",           mux_pllpdc_clkm,   CLK_SOURCE_TVO,       49,   &periph_h_regs, 0, tvo),
 842         TEGRA_INIT_DATA_MUX("tvdac",    NULL,           "tvdac",         mux_pllpdc_clkm,   CLK_SOURCE_TVDAC,     53,   &periph_h_regs, 0, tvdac),
 843         TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor",   "tegra_camera",  mux_pllmcpa,       CLK_SOURCE_VI_SENSOR, 20,   &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
 844         TEGRA_INIT_DATA_DIV16("i2c1",   "div-clk",      "tegra-i2c.0",   mux_pllpcm_clkm,   CLK_SOURCE_I2C1,      12,   &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
 845         TEGRA_INIT_DATA_DIV16("i2c2",   "div-clk",      "tegra-i2c.1",   mux_pllpcm_clkm,   CLK_SOURCE_I2C2,      54,   &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
 846         TEGRA_INIT_DATA_DIV16("i2c3",   "div-clk",      "tegra-i2c.2",   mux_pllpcm_clkm,   CLK_SOURCE_I2C3,      67,   &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
 847         TEGRA_INIT_DATA_DIV16("dvc",    "div-clk",      "tegra-i2c.3",   mux_pllpcm_clkm,   CLK_SOURCE_DVC,       47,   &periph_h_regs, TEGRA_PERIPH_ON_APB, dvc),
 848         TEGRA_INIT_DATA_MUX("hdmi",     NULL,           "hdmi",          mux_pllpdc_clkm,   CLK_SOURCE_HDMI,      51,   &periph_h_regs, 0, hdmi),
 849         TEGRA_INIT_DATA("pwm",          NULL,           "tegra-pwm",     pwm_parents,       CLK_SOURCE_PWM,       28, 3, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, TEGRA_PERIPH_ON_APB, pwm),
 850 };
 851
 852 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
 853         TEGRA_INIT_DATA_NODIV("uarta",  NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6,  &periph_l_regs, TEGRA_PERIPH_ON_APB, uarta),
 854         TEGRA_INIT_DATA_NODIV("uartb",  NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7,  &periph_l_regs, TEGRA_PERIPH_ON_APB, uartb),
 855         TEGRA_INIT_DATA_NODIV("uartc",  NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, &periph_h_regs, TEGRA_PERIPH_ON_APB, uartc),
 856         TEGRA_INIT_DATA_NODIV("uartd",  NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, &periph_u_regs, TEGRA_PERIPH_ON_APB, uartd),
 857         TEGRA_INIT_DATA_NODIV("uarte",  NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, &periph_u_regs, TEGRA_PERIPH_ON_APB, uarte),
 858         TEGRA_INIT_DATA_NODIV("disp1",  NULL, "tegradc.0",    mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, &periph_l_regs, 0, disp1),
 859         TEGRA_INIT_DATA_NODIV("disp2",  NULL, "tegradc.1",    mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, &periph_l_regs, 0, disp2),
 860 };
 861
 862 static void __init tegra20_periph_clk_init(void)
 863 {
 864         struct tegra_periph_init_data *data;
 865         struct clk *clk;
 866         int i;
 867
 868         /* apbdma */
 869         clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
 870                                     0, 34, &periph_h_regs,
 871                                     periph_clk_enb_refcnt);
 872         clk_register_clkdev(clk, NULL, "tegra-apbdma");
 873         clks[apbdma] = clk;
 874
 875         /* rtc */
 876         clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
 877                                     TEGRA_PERIPH_NO_RESET,
 878                                     clk_base, 0, 4, &periph_l_regs,
 879                                     periph_clk_enb_refcnt);
 880         clk_register_clkdev(clk, NULL, "rtc-tegra");
 881         clks[rtc] = clk;
 882
 883         /* timer */
 884         clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
 885                                     0, 5, &periph_l_regs,
 886                                     periph_clk_enb_refcnt);
 887         clk_register_clkdev(clk, NULL, "timer");
 888         clks[timer] = clk;
 889
 890         /* kbc */
 891         clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
 892                                     TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
 893                                     clk_base, 0, 36, &periph_h_regs,
 894                                     periph_clk_enb_refcnt);
 895         clk_register_clkdev(clk, NULL, "tegra-kbc");
 896         clks[kbc] = clk;
 897
 898         /* csus */
 899         clk = tegra_clk_register_periph_gate("csus", "clk_m",
 900                                     TEGRA_PERIPH_NO_RESET,
 901                                     clk_base, 0, 92, &periph_u_regs,
 902                                     periph_clk_enb_refcnt);
 903         clk_register_clkdev(clk, "csus", "tengra_camera");
 904         clks[csus] = clk;
 905
 906         /* vcp */
 907         clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0,
 908                                     clk_base, 0, 29, &periph_l_regs,
 909                                     periph_clk_enb_refcnt);
 910         clk_register_clkdev(clk, "vcp", "tegra-avp");
 911         clks[vcp] = clk;
 912
 913         /* bsea */
 914         clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0,
 915                                     clk_base, 0, 62, &periph_h_regs,
 916                                     periph_clk_enb_refcnt);
 917         clk_register_clkdev(clk, "bsea", "tegra-avp");
 918         clks[bsea] = clk;
 919
 920         /* bsev */
 921         clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0,
 922                                     clk_base, 0, 63, &periph_h_regs,
 923                                     periph_clk_enb_refcnt);
 924         clk_register_clkdev(clk, "bsev", "tegra-aes");
 925         clks[bsev] = clk;
 926
 927         /* emc */
 928         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
 929                                ARRAY_SIZE(mux_pllmcp_clkm), 0,
 930                                clk_base + CLK_SOURCE_EMC,
 931                                30, 2, 0, NULL);
 932         clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
 933                                     57, &periph_h_regs, periph_clk_enb_refcnt);
 934         clk_register_clkdev(clk, "emc", NULL);
 935         clks[emc] = clk;
 936
 937         /* usbd */
 938         clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
 939                                     22, &periph_l_regs, periph_clk_enb_refcnt);
 940         clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
 941         clks[usbd] = clk;
 942
 943         /* usb2 */
 944         clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
 945                                     58, &periph_h_regs, periph_clk_enb_refcnt);
 946         clk_register_clkdev(clk, NULL, "tegra-ehci.1");
 947         clks[usb2] = clk;
 948
 949         /* usb3 */
 950         clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
 951                                     59, &periph_h_regs, periph_clk_enb_refcnt);
 952         clk_register_clkdev(clk, NULL, "tegra-ehci.2");
 953         clks[usb3] = clk;
 954
 955         /* dsi */
 956         clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
 957                                     48, &periph_h_regs, periph_clk_enb_refcnt);
 958         clk_register_clkdev(clk, NULL, "dsi");
 959         clks[dsi] = clk;
 960
 961         /* csi */
 962         clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
 963                                     0, 52, &periph_h_regs,
 964                                     periph_clk_enb_refcnt);
 965         clk_register_clkdev(clk, "csi", "tegra_camera");
 966         clks[csi] = clk;
 967
 968         /* isp */
 969         clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
 970                                     &periph_l_regs, periph_clk_enb_refcnt);
 971         clk_register_clkdev(clk, "isp", "tegra_camera");
 972         clks[isp] = clk;
 973
 974         /* pex */
 975         clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
 976                                     &periph_u_regs, periph_clk_enb_refcnt);
 977         clk_register_clkdev(clk, "pex", NULL);
 978         clks[pex] = clk;
 979
 980         /* afi */
 981         clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
 982                                     &periph_u_regs, periph_clk_enb_refcnt);
 983         clk_register_clkdev(clk, "afi", NULL);
 984         clks[afi] = clk;
 985
 986         /* pcie_xclk */
 987         clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base,
 988                                     0, 74, &periph_u_regs,
 989                                     periph_clk_enb_refcnt);
 990         clk_register_clkdev(clk, "pcie_xclk", NULL);
 991         clks[pcie_xclk] = clk;
 992
 993         /* cdev1 */
 994         clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
 995                                       26000000);
 996         clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
 997                                     clk_base, 0, 94, &periph_u_regs,
 998                                     periph_clk_enb_refcnt);
 999         clk_register_clkdev(clk, "cdev1", NULL);
1000         clks[cdev1] = clk;
1001
1002         /* cdev2 */
1003         clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT,
1004                                       26000000);
1005         clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
1006                                     clk_base, 0, 93, &periph_u_regs,
1007                                     periph_clk_enb_refcnt);
1008         clk_register_clkdev(clk, "cdev2", NULL);
1009         clks[cdev2] = clk;
1010
1011         for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1012                 data = &tegra_periph_clk_list[i];
1013                 clk = tegra_clk_register_periph(data->name, data->parent_names,
1014                                 data->num_parents, &data->periph,
1015                                 clk_base, data->offset);
1016                 clk_register_clkdev(clk, data->con_id, data->dev_id);
1017                 clks[data->clk_id] = clk;
1018         }
1019
1020         for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1021                 data = &tegra_periph_nodiv_clk_list[i];
1022                 clk = tegra_clk_register_periph_nodiv(data->name,
1023                                         data->parent_names,
1024                                         data->num_parents, &data->periph,
1025                                         clk_base, data->offset);
1026                 clk_register_clkdev(clk, data->con_id, data->dev_id);
1027                 clks[data->clk_id] = clk;
1028         }
1029 }
1030
1031
1032 static void __init tegra20_fixed_clk_init(void)
1033 {
1034         struct clk *clk;
1035
1036         /* clk_32k */
1037         clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1038                                       32768);
1039         clk_register_clkdev(clk, "clk_32k", NULL);
1040         clks[clk_32k] = clk;
1041 }
1042
1043 static void __init tegra20_pmc_clk_init(void)
1044 {
1045         struct clk *clk;
1046
1047         /* blink */
1048         writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1049         clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1050                                 pmc_base + PMC_DPD_PADS_ORIDE,
1051                                 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1052         clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1053                                 pmc_base + PMC_CTRL,
1054                                 PMC_CTRL_BLINK_ENB, 0, NULL);
1055         clk_register_clkdev(clk, "blink", NULL);
1056         clks[blink] = clk;
1057 }
1058
1059 static void __init tegra20_osc_clk_init(void)
1060 {
1061         struct clk *clk;
1062         unsigned long input_freq;
1063         unsigned int pll_ref_div;
1064
1065         input_freq = tegra20_clk_measure_input_freq();
1066
1067         /* clk_m */
1068         clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT |
1069                                       CLK_IGNORE_UNUSED, input_freq);
1070         clk_register_clkdev(clk, "clk_m", NULL);
1071         clks[clk_m] = clk;
1072
1073         /* pll_ref */
1074         pll_ref_div = tegra20_get_pll_ref_div();
1075         clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1076                                         CLK_SET_RATE_PARENT, 1, pll_ref_div);
1077         clk_register_clkdev(clk, "pll_ref", NULL);
1078         clks[pll_ref] = clk;
1079 }
1080
1081 /* Tegra20 CPU clock and reset control functions */
1082 static void tegra20_wait_cpu_in_reset(u32 cpu)
1083 {
1084         unsigned int reg;
1085
1086         do {
1087                 reg = readl(clk_base +
1088                             TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1089                 cpu_relax();
1090         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1091
1092         return;
1093 }
1094
1095 static void tegra20_put_cpu_in_reset(u32 cpu)
1096 {
1097         writel(CPU_RESET(cpu),
1098                clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1099         dmb();
1100 }
1101
1102 static void tegra20_cpu_out_of_reset(u32 cpu)
1103 {
1104         writel(CPU_RESET(cpu),
1105                clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1106         wmb();
1107 }
1108
1109 static void tegra20_enable_cpu_clock(u32 cpu)
1110 {
1111         unsigned int reg;
1112
1113         reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1114         writel(reg & ~CPU_CLOCK(cpu),
1115                clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1116         barrier();
1117         reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1118 }
1119
1120 static void tegra20_disable_cpu_clock(u32 cpu)
1121 {
1122         unsigned int reg;
1123
1124         reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1125         writel(reg | CPU_CLOCK(cpu),
1126                clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1127 }
1128
1129 #ifdef CONFIG_PM_SLEEP
1130 static bool tegra20_cpu_rail_off_ready(void)
1131 {
1132         unsigned int cpu_rst_status;
1133
1134         cpu_rst_status = readl(clk_base +
1135                                TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1136
1137         return !!(cpu_rst_status & 0x2);
1138 }
1139
1140 static void tegra20_cpu_clock_suspend(void)
1141 {
1142         /* switch coresite to clk_m, save off original source */
1143         tegra20_cpu_clk_sctx.clk_csite_src =
1144                                 readl(clk_base + CLK_SOURCE_CSITE);
1145         writel(3<<30, clk_base + CLK_SOURCE_CSITE);
1146
1147         tegra20_cpu_clk_sctx.cpu_burst =
1148                                 readl(clk_base + CCLK_BURST_POLICY);
1149         tegra20_cpu_clk_sctx.pllx_base =
1150                                 readl(clk_base + PLLX_BASE);
1151         tegra20_cpu_clk_sctx.pllx_misc =
1152                                 readl(clk_base + PLLX_MISC);
1153         tegra20_cpu_clk_sctx.cclk_divider =
1154                                 readl(clk_base + SUPER_CCLK_DIVIDER);
1155 }
1156
1157 static void tegra20_cpu_clock_resume(void)
1158 {
1159         unsigned int reg, policy;
1160
1161         /* Is CPU complex already running on PLLX? */
1162         reg = readl(clk_base + CCLK_BURST_POLICY);
1163         policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF;
1164
1165         if (policy == CCLK_IDLE_POLICY)
1166                 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF;
1167         else if (policy == CCLK_RUN_POLICY)
1168                 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF;
1169         else
1170                 BUG();
1171
1172         if (reg != CCLK_BURST_POLICY_PLLX) {
1173                 /* restore PLLX settings if CPU is on different PLL */
1174                 writel(tegra20_cpu_clk_sctx.pllx_misc,
1175                                         clk_base + PLLX_MISC);
1176                 writel(tegra20_cpu_clk_sctx.pllx_base,
1177                                         clk_base + PLLX_BASE);
1178
1179                 /* wait for PLL stabilization if PLLX was enabled */
1180                 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))
1181                         udelay(300);
1182         }
1183
1184         /*
1185          * Restore original burst policy setting for calls resulting from CPU
1186          * LP2 in idle or system suspend.
1187          */
1188         writel(tegra20_cpu_clk_sctx.cclk_divider,
1189                                         clk_base + SUPER_CCLK_DIVIDER);
1190         writel(tegra20_cpu_clk_sctx.cpu_burst,
1191                                         clk_base + CCLK_BURST_POLICY);
1192
1193         writel(tegra20_cpu_clk_sctx.clk_csite_src,
1194                                         clk_base + CLK_SOURCE_CSITE);
1195 }
1196 #endif
1197
1198 static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1199         .wait_for_reset = tegra20_wait_cpu_in_reset,
1200         .put_in_reset   = tegra20_put_cpu_in_reset,
1201         .out_of_reset   = tegra20_cpu_out_of_reset,
1202         .enable_clock   = tegra20_enable_cpu_clock,
1203         .disable_clock  = tegra20_disable_cpu_clock,
1204 #ifdef CONFIG_PM_SLEEP
1205         .rail_off_ready = tegra20_cpu_rail_off_ready,
1206         .suspend        = tegra20_cpu_clock_suspend,
1207         .resume         = tegra20_cpu_clock_resume,
1208 #endif
1209 };
1210
1211 static __initdata struct tegra_clk_init_table init_table[] = {
1212         {pll_p, clk_max, 216000000, 1},
1213         {pll_p_out1, clk_max, 28800000, 1},
1214         {pll_p_out2, clk_max, 48000000, 1},
1215         {pll_p_out3, clk_max, 72000000, 1},
1216         {pll_p_out4, clk_max, 24000000, 1},
1217         {pll_c, clk_max, 600000000, 1},
1218         {pll_c_out1, clk_max, 120000000, 1},
1219         {sclk, pll_c_out1, 0, 1},
1220         {hclk, clk_max, 0, 1},
1221         {pclk, clk_max, 60000000, 1},
1222         {csite, clk_max, 0, 1},
1223         {emc, clk_max, 0, 1},
1224         {cclk, clk_max, 0, 1},
1225         {uarta, pll_p, 0, 0},
1226         {uartb, pll_p, 0, 0},
1227         {uartc, pll_p, 0, 0},
1228         {uartd, pll_p, 0, 0},
1229         {uarte, pll_p, 0, 0},
1230         {usbd, clk_max, 12000000, 0},
1231         {usb2, clk_max, 12000000, 0},
1232         {usb3, clk_max, 12000000, 0},
1233         {pll_a, clk_max, 56448000, 1},
1234         {pll_a_out0, clk_max, 11289600, 1},
1235         {cdev1, clk_max, 0, 1},
1236         {blink, clk_max, 32768, 1},
1237         {i2s1, pll_a_out0, 11289600, 0},
1238         {i2s2, pll_a_out0, 11289600, 0},
1239         {sdmmc1, pll_p, 48000000, 0},
1240         {sdmmc3, pll_p, 48000000, 0},
1241         {sdmmc4, pll_p, 48000000, 0},
1242         {spi, pll_p, 20000000, 0},
1243         {sbc1, pll_p, 100000000, 0},
1244         {sbc2, pll_p, 100000000, 0},
1245         {sbc3, pll_p, 100000000, 0},
1246         {sbc4, pll_p, 100000000, 0},
1247         {host1x, pll_c, 150000000, 0},
1248         {disp1, pll_p, 600000000, 0},
1249         {disp2, pll_p, 600000000, 0},
1250         {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
1251 };
1252
1253 /*
1254  * Some clocks may be used by different drivers depending on the board
1255  * configuration.  List those here to register them twice in the clock lookup
1256  * table under two names.
1257  */
1258 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1259         TEGRA_CLK_DUPLICATE(usbd,   "utmip-pad",    NULL),
1260         TEGRA_CLK_DUPLICATE(usbd,   "tegra-ehci.0", NULL),
1261         TEGRA_CLK_DUPLICATE(usbd,   "tegra-otg",    NULL),
1262         TEGRA_CLK_DUPLICATE(cclk,   NULL,           "cpu"),
1263         TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* Must be the last entry */
1264 };
1265
1266 static const struct of_device_id pmc_match[] __initconst = {
1267         { .compatible = "nvidia,tegra20-pmc" },
1268         {},
1269 };
1270
1271 void __init tegra20_clock_init(struct device_node *np)
1272 {
1273         int i;
1274         struct device_node *node;
1275
1276         clk_base = of_iomap(np, 0);
1277         if (!clk_base) {
1278                 pr_err("Can't map CAR registers\n");
1279                 BUG();
1280         }
1281
1282         node = of_find_matching_node(NULL, pmc_match);
1283         if (!node) {
1284                 pr_err("Failed to find pmc node\n");
1285                 BUG();
1286         }
1287
1288         pmc_base = of_iomap(node, 0);
1289         if (!pmc_base) {
1290                 pr_err("Can't map pmc registers\n");
1291                 BUG();
1292         }
1293
1294         tegra20_osc_clk_init();
1295         tegra20_pmc_clk_init();
1296         tegra20_fixed_clk_init();
1297         tegra20_pll_init();
1298         tegra20_super_clk_init();
1299         tegra20_periph_clk_init();
1300         tegra20_audio_clk_init();
1301
1302
1303         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1304                 if (IS_ERR(clks[i])) {
1305                         pr_err("Tegra20 clk %d: register failed with %ld\n",
1306                                i, PTR_ERR(clks[i]));
1307                         BUG();
1308                 }
1309                 if (!clks[i])
1310                         clks[i] = ERR_PTR(-EINVAL);
1311         }
1312
1313         tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
1314
1315         clk_data.clks = clks;
1316         clk_data.clk_num = ARRAY_SIZE(clks);
1317         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1318
1319         tegra_init_from_table(init_table, clks, clk_max);
1320
1321         tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1322 }