drivers/crypto/talitos.c

   1 /*
   2  * talitos - Freescale Integrated Security Engine (SEC) device driver
   3  *
   4  * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
   5  *
   6  * Scatterlist Crypto API glue code copied from files with the following:
   7  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
   8  *
   9  * Crypto algorithm registration code copied from hifn driver:
  10  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
  11  * All rights reserved.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/device.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/crypto.h>
  34 #include <linux/hw_random.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/io.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/rtnetlink.h>
  40 #include <linux/slab.h>
  41
  42 #include <crypto/algapi.h>
  43 #include <crypto/aes.h>
  44 #include <crypto/des.h>
  45 #include <crypto/sha.h>
  46 #include <crypto/md5.h>
  47 #include <crypto/aead.h>
  48 #include <crypto/authenc.h>
  49 #include <crypto/skcipher.h>
  50 #include <crypto/hash.h>
  51 #include <crypto/internal/hash.h>
  52 #include <crypto/scatterwalk.h>
  53
  54 #include "talitos.h"
  55
  56 static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
  57 {
  58         talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
  59         talitos_ptr->eptr = upper_32_bits(dma_addr);
  60 }
  61
  62 /*
  63  * map virtual single (contiguous) pointer to h/w descriptor pointer
  64  */
  65 static void map_single_talitos_ptr(struct device *dev,
  66                                    struct talitos_ptr *talitos_ptr,
  67                                    unsigned short len, void *data,
  68                                    unsigned char extent,
  69                                    enum dma_data_direction dir)
  70 {
  71         dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
  72
  73         talitos_ptr->len = cpu_to_be16(len);
  74         to_talitos_ptr(talitos_ptr, dma_addr);
  75         talitos_ptr->j_extent = extent;
  76 }
  77
  78 /*
  79  * unmap bus single (contiguous) h/w descriptor pointer
  80  */
  81 static void unmap_single_talitos_ptr(struct device *dev,
  82                                      struct talitos_ptr *talitos_ptr,
  83                                      enum dma_data_direction dir)
  84 {
  85         dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
  86                          be16_to_cpu(talitos_ptr->len), dir);
  87 }
  88
  89 static int reset_channel(struct device *dev, int ch)
  90 {
  91         struct talitos_private *priv = dev_get_drvdata(dev);
  92         unsigned int timeout = TALITOS_TIMEOUT;
  93
  94         setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
  95
  96         while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
  97                && --timeout)
  98                 cpu_relax();
  99
 100         if (timeout == 0) {
 101                 dev_err(dev, "failed to reset channel %d\n", ch);
 102                 return -EIO;
 103         }
 104
 105         /* set 36-bit addressing, done writeback enable and done IRQ enable */
 106         setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
 107                   TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
 108
 109         /* and ICCR writeback, if available */
 110         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 111                 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
 112                           TALITOS_CCCR_LO_IWSE);
 113
 114         return 0;
 115 }
 116
 117 static int reset_device(struct device *dev)
 118 {
 119         struct talitos_private *priv = dev_get_drvdata(dev);
 120         unsigned int timeout = TALITOS_TIMEOUT;
 121         u32 mcr = TALITOS_MCR_SWR;
 122
 123         setbits32(priv->reg + TALITOS_MCR, mcr);
 124
 125         while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
 126                && --timeout)
 127                 cpu_relax();
 128
 129         if (priv->irq[1]) {
 130                 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
 131                 setbits32(priv->reg + TALITOS_MCR, mcr);
 132         }
 133
 134         if (timeout == 0) {
 135                 dev_err(dev, "failed to reset device\n");
 136                 return -EIO;
 137         }
 138
 139         return 0;
 140 }
 141
 142 /*
 143  * Reset and initialize the device
 144  */
 145 static int init_device(struct device *dev)
 146 {
 147         struct talitos_private *priv = dev_get_drvdata(dev);
 148         int ch, err;
 149
 150         /*
 151          * Master reset
 152          * errata documentation: warning: certain SEC interrupts
 153          * are not fully cleared by writing the MCR:SWR bit,
 154          * set bit twice to completely reset
 155          */
 156         err = reset_device(dev);
 157         if (err)
 158                 return err;
 159
 160         err = reset_device(dev);
 161         if (err)
 162                 return err;
 163
 164         /* reset channels */
 165         for (ch = 0; ch < priv->num_channels; ch++) {
 166                 err = reset_channel(dev, ch);
 167                 if (err)
 168                         return err;
 169         }
 170
 171         /* enable channel done and error interrupts */
 172         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
 173         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
 174
 175         /* disable integrity check error interrupts (use writeback instead) */
 176         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 177                 setbits32(priv->reg + TALITOS_MDEUICR_LO,
 178                           TALITOS_MDEUICR_LO_ICE);
 179
 180         return 0;
 181 }
 182
 183 /**
 184  * talitos_submit - submits a descriptor to the device for processing
 185  * @dev:        the SEC device to be used
 186  * @ch:         the SEC device channel to be used
 187  * @desc:       the descriptor to be processed by the device
 188  * @callback:   whom to call when processing is complete
 189  * @context:    a handle for use by caller (optional)
 190  *
 191  * desc must contain valid dma-mapped (bus physical) address pointers.
 192  * callback must check err and feedback in descriptor header
 193  * for device processing status.
 194  */
 195 int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
 196                    void (*callback)(struct device *dev,
 197                                     struct talitos_desc *desc,
 198                                     void *context, int error),
 199                    void *context)
 200 {
 201         struct talitos_private *priv = dev_get_drvdata(dev);
 202         struct talitos_request *request;
 203         unsigned long flags;
 204         int head;
 205
 206         spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
 207
 208         if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
 209                 /* h/w fifo is full */
 210                 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
 211                 return -EAGAIN;
 212         }
 213
 214         head = priv->chan[ch].head;
 215         request = &priv->chan[ch].fifo[head];
 216
 217         /* map descriptor and save caller data */
 218         request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
 219                                            DMA_BIDIRECTIONAL);
 220         request->callback = callback;
 221         request->context = context;
 222
 223         /* increment fifo head */
 224         priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
 225
 226         smp_wmb();
 227         request->desc = desc;
 228
 229         /* GO! */
 230         wmb();
 231         out_be32(priv->chan[ch].reg + TALITOS_FF,
 232                  upper_32_bits(request->dma_desc));
 233         out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
 234                  lower_32_bits(request->dma_desc));
 235
 236         spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
 237
 238         return -EINPROGRESS;
 239 }
 240 EXPORT_SYMBOL(talitos_submit);
 241
 242 /*
 243  * process what was done, notify callback of error if not
 244  */
 245 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
 246 {
 247         struct talitos_private *priv = dev_get_drvdata(dev);
 248         struct talitos_request *request, saved_req;
 249         unsigned long flags;
 250         int tail, status;
 251
 252         spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 253
 254         tail = priv->chan[ch].tail;
 255         while (priv->chan[ch].fifo[tail].desc) {
 256                 request = &priv->chan[ch].fifo[tail];
 257
 258                 /* descriptors with their done bits set don't get the error */
 259                 rmb();
 260                 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
 261                         status = 0;
 262                 else
 263                         if (!error)
 264                                 break;
 265                         else
 266                                 status = error;
 267
 268                 dma_unmap_single(dev, request->dma_desc,
 269                                  sizeof(struct talitos_desc),
 270                                  DMA_BIDIRECTIONAL);
 271
 272                 /* copy entries so we can call callback outside lock */
 273                 saved_req.desc = request->desc;
 274                 saved_req.callback = request->callback;
 275                 saved_req.context = request->context;
 276
 277                 /* release request entry in fifo */
 278                 smp_wmb();
 279                 request->desc = NULL;
 280
 281                 /* increment fifo tail */
 282                 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
 283
 284                 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
 285
 286                 atomic_dec(&priv->chan[ch].submit_count);
 287
 288                 saved_req.callback(dev, saved_req.desc, saved_req.context,
 289                                    status);
 290                 /* channel may resume processing in single desc error case */
 291                 if (error && !reset_ch && status == error)
 292                         return;
 293                 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 294                 tail = priv->chan[ch].tail;
 295         }
 296
 297         spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
 298 }
 299
 300 /*
 301  * process completed requests for channels that have done status
 302  */
 303 #define DEF_TALITOS_DONE(name, ch_done_mask)                            \
 304 static void talitos_done_##name(unsigned long data)                     \
 305 {                                                                       \
 306         struct device *dev = (struct device *)data;                     \
 307         struct talitos_private *priv = dev_get_drvdata(dev);            \
 308         unsigned long flags;                                            \
 309                                                                         \
 310         if (ch_done_mask & 1)                                           \
 311                 flush_channel(dev, 0, 0, 0);                            \
 312         if (priv->num_channels == 1)                                    \
 313                 goto out;                                               \
 314         if (ch_done_mask & (1 << 2))                                    \
 315                 flush_channel(dev, 1, 0, 0);                            \
 316         if (ch_done_mask & (1 << 4))                                    \
 317                 flush_channel(dev, 2, 0, 0);                            \
 318         if (ch_done_mask & (1 << 6))                                    \
 319                 flush_channel(dev, 3, 0, 0);                            \
 320                                                                         \
 321 out:                                                                    \
 322         /* At this point, all completed channels have been processed */ \
 323         /* Unmask done interrupts for channels completed later on. */   \
 324         spin_lock_irqsave(&priv->reg_lock, flags);                      \
 325         setbits32(priv->reg + TALITOS_IMR, ch_done_mask);               \
 326         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);     \
 327         spin_unlock_irqrestore(&priv->reg_lock, flags);                 \
 328 }
 329 DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
 330 DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
 331 DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
 332
 333 /*
 334  * locate current (offending) descriptor
 335  */
 336 static u32 current_desc_hdr(struct device *dev, int ch)
 337 {
 338         struct talitos_private *priv = dev_get_drvdata(dev);
 339         int tail = priv->chan[ch].tail;
 340         dma_addr_t cur_desc;
 341
 342         cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
 343
 344         while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
 345                 tail = (tail + 1) & (priv->fifo_len - 1);
 346                 if (tail == priv->chan[ch].tail) {
 347                         dev_err(dev, "couldn't locate current descriptor\n");
 348                         return 0;
 349                 }
 350         }
 351
 352         return priv->chan[ch].fifo[tail].desc->hdr;
 353 }
 354
 355 /*
 356  * user diagnostics; report root cause of error based on execution unit status
 357  */
 358 static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
 359 {
 360         struct talitos_private *priv = dev_get_drvdata(dev);
 361         int i;
 362
 363         if (!desc_hdr)
 364                 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
 365
 366         switch (desc_hdr & DESC_HDR_SEL0_MASK) {
 367         case DESC_HDR_SEL0_AFEU:
 368                 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
 369                         in_be32(priv->reg + TALITOS_AFEUISR),
 370                         in_be32(priv->reg + TALITOS_AFEUISR_LO));
 371                 break;
 372         case DESC_HDR_SEL0_DEU:
 373                 dev_err(dev, "DEUISR 0x%08x_%08x\n",
 374                         in_be32(priv->reg + TALITOS_DEUISR),
 375                         in_be32(priv->reg + TALITOS_DEUISR_LO));
 376                 break;
 377         case DESC_HDR_SEL0_MDEUA:
 378         case DESC_HDR_SEL0_MDEUB:
 379                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 380                         in_be32(priv->reg + TALITOS_MDEUISR),
 381                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 382                 break;
 383         case DESC_HDR_SEL0_RNG:
 384                 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
 385                         in_be32(priv->reg + TALITOS_RNGUISR),
 386                         in_be32(priv->reg + TALITOS_RNGUISR_LO));
 387                 break;
 388         case DESC_HDR_SEL0_PKEU:
 389                 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
 390                         in_be32(priv->reg + TALITOS_PKEUISR),
 391                         in_be32(priv->reg + TALITOS_PKEUISR_LO));
 392                 break;
 393         case DESC_HDR_SEL0_AESU:
 394                 dev_err(dev, "AESUISR 0x%08x_%08x\n",
 395                         in_be32(priv->reg + TALITOS_AESUISR),
 396                         in_be32(priv->reg + TALITOS_AESUISR_LO));
 397                 break;
 398         case DESC_HDR_SEL0_CRCU:
 399                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 400                         in_be32(priv->reg + TALITOS_CRCUISR),
 401                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 402                 break;
 403         case DESC_HDR_SEL0_KEU:
 404                 dev_err(dev, "KEUISR 0x%08x_%08x\n",
 405                         in_be32(priv->reg + TALITOS_KEUISR),
 406                         in_be32(priv->reg + TALITOS_KEUISR_LO));
 407                 break;
 408         }
 409
 410         switch (desc_hdr & DESC_HDR_SEL1_MASK) {
 411         case DESC_HDR_SEL1_MDEUA:
 412         case DESC_HDR_SEL1_MDEUB:
 413                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 414                         in_be32(priv->reg + TALITOS_MDEUISR),
 415                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 416                 break;
 417         case DESC_HDR_SEL1_CRCU:
 418                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 419                         in_be32(priv->reg + TALITOS_CRCUISR),
 420                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 421                 break;
 422         }
 423
 424         for (i = 0; i < 8; i++)
 425                 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
 426                         in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
 427                         in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
 428 }
 429
 430 /*
 431  * recover from error interrupts
 432  */
 433 static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
 434 {
 435         struct talitos_private *priv = dev_get_drvdata(dev);
 436         unsigned int timeout = TALITOS_TIMEOUT;
 437         int ch, error, reset_dev = 0, reset_ch = 0;
 438         u32 v, v_lo;
 439
 440         for (ch = 0; ch < priv->num_channels; ch++) {
 441                 /* skip channels without errors */
 442                 if (!(isr & (1 << (ch * 2 + 1))))
 443                         continue;
 444
 445                 error = -EINVAL;
 446
 447                 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
 448                 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
 449
 450                 if (v_lo & TALITOS_CCPSR_LO_DOF) {
 451                         dev_err(dev, "double fetch fifo overflow error\n");
 452                         error = -EAGAIN;
 453                         reset_ch = 1;
 454                 }
 455                 if (v_lo & TALITOS_CCPSR_LO_SOF) {
 456                         /* h/w dropped descriptor */
 457                         dev_err(dev, "single fetch fifo overflow error\n");
 458                         error = -EAGAIN;
 459                 }
 460                 if (v_lo & TALITOS_CCPSR_LO_MDTE)
 461                         dev_err(dev, "master data transfer error\n");
 462                 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
 463                         dev_err(dev, "s/g data length zero error\n");
 464                 if (v_lo & TALITOS_CCPSR_LO_FPZ)
 465                         dev_err(dev, "fetch pointer zero error\n");
 466                 if (v_lo & TALITOS_CCPSR_LO_IDH)
 467                         dev_err(dev, "illegal descriptor header error\n");
 468                 if (v_lo & TALITOS_CCPSR_LO_IEU)
 469                         dev_err(dev, "invalid execution unit error\n");
 470                 if (v_lo & TALITOS_CCPSR_LO_EU)
 471                         report_eu_error(dev, ch, current_desc_hdr(dev, ch));
 472                 if (v_lo & TALITOS_CCPSR_LO_GB)
 473                         dev_err(dev, "gather boundary error\n");
 474                 if (v_lo & TALITOS_CCPSR_LO_GRL)
 475                         dev_err(dev, "gather return/length error\n");
 476                 if (v_lo & TALITOS_CCPSR_LO_SB)
 477                         dev_err(dev, "scatter boundary error\n");
 478                 if (v_lo & TALITOS_CCPSR_LO_SRL)
 479                         dev_err(dev, "scatter return/length error\n");
 480
 481                 flush_channel(dev, ch, error, reset_ch);
 482
 483                 if (reset_ch) {
 484                         reset_channel(dev, ch);
 485                 } else {
 486                         setbits32(priv->chan[ch].reg + TALITOS_CCCR,
 487                                   TALITOS_CCCR_CONT);
 488                         setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
 489                         while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
 490                                TALITOS_CCCR_CONT) && --timeout)
 491                                 cpu_relax();
 492                         if (timeout == 0) {
 493                                 dev_err(dev, "failed to restart channel %d\n",
 494                                         ch);
 495                                 reset_dev = 1;
 496                         }
 497                 }
 498         }
 499         if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
 500                 dev_err(dev, "done overflow, internal time out, or rngu error: "
 501                         "ISR 0x%08x_%08x\n", isr, isr_lo);
 502
 503                 /* purge request queues */
 504                 for (ch = 0; ch < priv->num_channels; ch++)
 505                         flush_channel(dev, ch, -EIO, 1);
 506
 507                 /* reset and reinitialize the device */
 508                 init_device(dev);
 509         }
 510 }
 511
 512 #define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet)           \
 513 static irqreturn_t talitos_interrupt_##name(int irq, void *data)               \
 514 {                                                                              \
 515         struct device *dev = data;                                             \
 516         struct talitos_private *priv = dev_get_drvdata(dev);                   \
 517         u32 isr, isr_lo;                                                       \
 518         unsigned long flags;                                                   \
 519                                                                                \
 520         spin_lock_irqsave(&priv->reg_lock, flags);                             \
 521         isr = in_be32(priv->reg + TALITOS_ISR);                                \
 522         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);                          \
 523         /* Acknowledge interrupt */                                            \
 524         out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
 525         out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);                          \
 526                                                                                \
 527         if (unlikely(isr & ch_err_mask || isr_lo)) {                           \
 528                 spin_unlock_irqrestore(&priv->reg_lock, flags);                \
 529                 talitos_error(dev, isr & ch_err_mask, isr_lo);                 \
 530         }                                                                      \
 531         else {                                                                 \
 532                 if (likely(isr & ch_done_mask)) {                              \
 533                         /* mask further done interrupts. */                    \
 534                         clrbits32(priv->reg + TALITOS_IMR, ch_done_mask);      \
 535                         /* done_task will unmask done interrupts at exit */    \
 536                         tasklet_schedule(&priv->done_task[tlet]);              \
 537                 }                                                              \
 538                 spin_unlock_irqrestore(&priv->reg_lock, flags);                \
 539         }                                                                      \
 540                                                                                \
 541         return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED :  \
 542                                                                 IRQ_NONE;      \
 543 }
 544 DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
 545 DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
 546 DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
 547
 548 /*
 549  * hwrng
 550  */
 551 static int talitos_rng_data_present(struct hwrng *rng, int wait)
 552 {
 553         struct device *dev = (struct device *)rng->priv;
 554         struct talitos_private *priv = dev_get_drvdata(dev);
 555         u32 ofl;
 556         int i;
 557
 558         for (i = 0; i < 20; i++) {
 559                 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
 560                       TALITOS_RNGUSR_LO_OFL;
 561                 if (ofl || !wait)
 562                         break;
 563                 udelay(10);
 564         }
 565
 566         return !!ofl;
 567 }
 568
 569 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
 570 {
 571         struct device *dev = (struct device *)rng->priv;
 572         struct talitos_private *priv = dev_get_drvdata(dev);
 573
 574         /* rng fifo requires 64-bit accesses */
 575         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
 576         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
 577
 578         return sizeof(u32);
 579 }
 580
 581 static int talitos_rng_init(struct hwrng *rng)
 582 {
 583         struct device *dev = (struct device *)rng->priv;
 584         struct talitos_private *priv = dev_get_drvdata(dev);
 585         unsigned int timeout = TALITOS_TIMEOUT;
 586
 587         setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
 588         while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
 589                && --timeout)
 590                 cpu_relax();
 591         if (timeout == 0) {
 592                 dev_err(dev, "failed to reset rng hw\n");
 593                 return -ENODEV;
 594         }
 595
 596         /* start generating */
 597         setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
 598
 599         return 0;
 600 }
 601
 602 static int talitos_register_rng(struct device *dev)
 603 {
 604         struct talitos_private *priv = dev_get_drvdata(dev);
 605
 606         priv->rng.name          = dev_driver_string(dev),
 607         priv->rng.init          = talitos_rng_init,
 608         priv->rng.data_present  = talitos_rng_data_present,
 609         priv->rng.data_read     = talitos_rng_data_read,
 610         priv->rng.priv          = (unsigned long)dev;
 611
 612         return hwrng_register(&priv->rng);
 613 }
 614
 615 static void talitos_unregister_rng(struct device *dev)
 616 {
 617         struct talitos_private *priv = dev_get_drvdata(dev);
 618
 619         hwrng_unregister(&priv->rng);
 620 }
 621
 622 /*
 623  * crypto alg
 624  */
 625 #define TALITOS_CRA_PRIORITY            3000
 626 #define TALITOS_MAX_KEY_SIZE            96
 627 #define TALITOS_MAX_IV_LENGTH           16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
 628
 629 #define MD5_BLOCK_SIZE    64
 630
 631 struct talitos_ctx {
 632         struct device *dev;
 633         int ch;
 634         __be32 desc_hdr_template;
 635         u8 key[TALITOS_MAX_KEY_SIZE];
 636         u8 iv[TALITOS_MAX_IV_LENGTH];
 637         unsigned int keylen;
 638         unsigned int enckeylen;
 639         unsigned int authkeylen;
 640         unsigned int authsize;
 641 };
 642
 643 #define HASH_MAX_BLOCK_SIZE             SHA512_BLOCK_SIZE
 644 #define TALITOS_MDEU_MAX_CONTEXT_SIZE   TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
 645
 646 struct talitos_ahash_req_ctx {
 647         u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
 648         unsigned int hw_context_size;
 649         u8 buf[HASH_MAX_BLOCK_SIZE];
 650         u8 bufnext[HASH_MAX_BLOCK_SIZE];
 651         unsigned int swinit;
 652         unsigned int first;
 653         unsigned int last;
 654         unsigned int to_hash_later;
 655         u64 nbuf;
 656         struct scatterlist bufsl[2];
 657         struct scatterlist *psrc;
 658 };
 659
 660 static int aead_setauthsize(struct crypto_aead *authenc,
 661                             unsigned int authsize)
 662 {
 663         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 664
 665         ctx->authsize = authsize;
 666
 667         return 0;
 668 }
 669
 670 static int aead_setkey(struct crypto_aead *authenc,
 671                        const u8 *key, unsigned int keylen)
 672 {
 673         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 674         struct crypto_authenc_keys keys;
 675
 676         if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
 677                 goto badkey;
 678
 679         if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
 680                 goto badkey;
 681
 682         memcpy(ctx->key, keys.authkey, keys.authkeylen);
 683         memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
 684
 685         ctx->keylen = keys.authkeylen + keys.enckeylen;
 686         ctx->enckeylen = keys.enckeylen;
 687         ctx->authkeylen = keys.authkeylen;
 688
 689         return 0;
 690
 691 badkey:
 692         crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
 693         return -EINVAL;
 694 }
 695
 696 /*
 697  * talitos_edesc - s/w-extended descriptor
 698  * @assoc_nents: number of segments in associated data scatterlist
 699  * @src_nents: number of segments in input scatterlist
 700  * @dst_nents: number of segments in output scatterlist
 701  * @assoc_chained: whether assoc is chained or not
 702  * @src_chained: whether src is chained or not
 703  * @dst_chained: whether dst is chained or not
 704  * @iv_dma: dma address of iv for checking continuity and link table
 705  * @dma_len: length of dma mapped link_tbl space
 706  * @dma_link_tbl: bus physical address of link_tbl
 707  * @desc: h/w descriptor
 708  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
 709  *
 710  * if decrypting (with authcheck), or either one of src_nents or dst_nents
 711  * is greater than 1, an integrity check value is concatenated to the end
 712  * of link_tbl data
 713  */
 714 struct talitos_edesc {
 715         int assoc_nents;
 716         int src_nents;
 717         int dst_nents;
 718         bool assoc_chained;
 719         bool src_chained;
 720         bool dst_chained;
 721         dma_addr_t iv_dma;
 722         int dma_len;
 723         dma_addr_t dma_link_tbl;
 724         struct talitos_desc desc;
 725         struct talitos_ptr link_tbl[0];
 726 };
 727
 728 static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
 729                           unsigned int nents, enum dma_data_direction dir,
 730                           bool chained)
 731 {
 732         if (unlikely(chained))
 733                 while (sg) {
 734                         dma_map_sg(dev, sg, 1, dir);
 735                         sg = scatterwalk_sg_next(sg);
 736                 }
 737         else
 738                 dma_map_sg(dev, sg, nents, dir);
 739         return nents;
 740 }
 741
 742 static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
 743                                    enum dma_data_direction dir)
 744 {
 745         while (sg) {
 746                 dma_unmap_sg(dev, sg, 1, dir);
 747                 sg = scatterwalk_sg_next(sg);
 748         }
 749 }
 750
 751 static void talitos_sg_unmap(struct device *dev,
 752                              struct talitos_edesc *edesc,
 753                              struct scatterlist *src,
 754                              struct scatterlist *dst)
 755 {
 756         unsigned int src_nents = edesc->src_nents ? : 1;
 757         unsigned int dst_nents = edesc->dst_nents ? : 1;
 758
 759         if (src != dst) {
 760                 if (edesc->src_chained)
 761                         talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
 762                 else
 763                         dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
 764
 765                 if (dst) {
 766                         if (edesc->dst_chained)
 767                                 talitos_unmap_sg_chain(dev, dst,
 768                                                        DMA_FROM_DEVICE);
 769                         else
 770                                 dma_unmap_sg(dev, dst, dst_nents,
 771                                              DMA_FROM_DEVICE);
 772                 }
 773         } else
 774                 if (edesc->src_chained)
 775                         talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
 776                 else
 777                         dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
 778 }
 779
 780 static void ipsec_esp_unmap(struct device *dev,
 781                             struct talitos_edesc *edesc,
 782                             struct aead_request *areq)
 783 {
 784         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
 785         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
 786         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
 787         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
 788
 789         if (edesc->assoc_chained)
 790                 talitos_unmap_sg_chain(dev, areq->assoc, DMA_TO_DEVICE);
 791         else
 792                 /* assoc_nents counts also for IV in non-contiguous cases */
 793                 dma_unmap_sg(dev, areq->assoc,
 794                              edesc->assoc_nents ? edesc->assoc_nents - 1 : 1,
 795                              DMA_TO_DEVICE);
 796
 797         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
 798
 799         if (edesc->dma_len)
 800                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
 801                                  DMA_BIDIRECTIONAL);
 802 }
 803
 804 /*
 805  * ipsec_esp descriptor callbacks
 806  */
 807 static void ipsec_esp_encrypt_done(struct device *dev,
 808                                    struct talitos_desc *desc, void *context,
 809                                    int err)
 810 {
 811         struct aead_request *areq = context;
 812         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
 813         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 814         struct talitos_edesc *edesc;
 815         struct scatterlist *sg;
 816         void *icvdata;
 817
 818         edesc = container_of(desc, struct talitos_edesc, desc);
 819
 820         ipsec_esp_unmap(dev, edesc, areq);
 821
 822         /* copy the generated ICV to dst */
 823         if (edesc->dst_nents) {
 824                 icvdata = &edesc->link_tbl[edesc->src_nents +
 825                                            edesc->dst_nents + 2 +
 826                                            edesc->assoc_nents];
 827                 sg = sg_last(areq->dst, edesc->dst_nents);
 828                 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
 829                        icvdata, ctx->authsize);
 830         }
 831
 832         kfree(edesc);
 833
 834         aead_request_complete(areq, err);
 835 }
 836
 837 static void ipsec_esp_decrypt_swauth_done(struct device *dev,
 838                                           struct talitos_desc *desc,
 839                                           void *context, int err)
 840 {
 841         struct aead_request *req = context;
 842         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
 843         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 844         struct talitos_edesc *edesc;
 845         struct scatterlist *sg;
 846         void *icvdata;
 847
 848         edesc = container_of(desc, struct talitos_edesc, desc);
 849
 850         ipsec_esp_unmap(dev, edesc, req);
 851
 852         if (!err) {
 853                 /* auth check */
 854                 if (edesc->dma_len)
 855                         icvdata = &edesc->link_tbl[edesc->src_nents +
 856                                                    edesc->dst_nents + 2 +
 857                                                    edesc->assoc_nents];
 858                 else
 859                         icvdata = &edesc->link_tbl[0];
 860
 861                 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
 862                 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
 863                              ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
 864         }
 865
 866         kfree(edesc);
 867
 868         aead_request_complete(req, err);
 869 }
 870
 871 static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
 872                                           struct talitos_desc *desc,
 873                                           void *context, int err)
 874 {
 875         struct aead_request *req = context;
 876         struct talitos_edesc *edesc;
 877
 878         edesc = container_of(desc, struct talitos_edesc, desc);
 879
 880         ipsec_esp_unmap(dev, edesc, req);
 881
 882         /* check ICV auth status */
 883         if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
 884                      DESC_HDR_LO_ICCR1_PASS))
 885                 err = -EBADMSG;
 886
 887         kfree(edesc);
 888
 889         aead_request_complete(req, err);
 890 }
 891
 892 /*
 893  * convert scatterlist to SEC h/w link table format
 894  * stop at cryptlen bytes
 895  */
 896 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
 897                            int cryptlen, struct talitos_ptr *link_tbl_ptr)
 898 {
 899         int n_sg = sg_count;
 900
 901         while (n_sg--) {
 902                 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
 903                 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
 904                 link_tbl_ptr->j_extent = 0;
 905                 link_tbl_ptr++;
 906                 cryptlen -= sg_dma_len(sg);
 907                 sg = scatterwalk_sg_next(sg);
 908         }
 909
 910         /* adjust (decrease) last one (or two) entry's len to cryptlen */
 911         link_tbl_ptr--;
 912         while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
 913                 /* Empty this entry, and move to previous one */
 914                 cryptlen += be16_to_cpu(link_tbl_ptr->len);
 915                 link_tbl_ptr->len = 0;
 916                 sg_count--;
 917                 link_tbl_ptr--;
 918         }
 919         be16_add_cpu(&link_tbl_ptr->len, cryptlen);
 920
 921         /* tag end of link table */
 922         link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 923
 924         return sg_count;
 925 }
 926
 927 /*
 928  * fill in and submit ipsec_esp descriptor
 929  */
 930 static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
 931                      u64 seq, void (*callback) (struct device *dev,
 932                                                 struct talitos_desc *desc,
 933                                                 void *context, int error))
 934 {
 935         struct crypto_aead *aead = crypto_aead_reqtfm(areq);
 936         struct talitos_ctx *ctx = crypto_aead_ctx(aead);
 937         struct device *dev = ctx->dev;
 938         struct talitos_desc *desc = &edesc->desc;
 939         unsigned int cryptlen = areq->cryptlen;
 940         unsigned int authsize = ctx->authsize;
 941         unsigned int ivsize = crypto_aead_ivsize(aead);
 942         int sg_count, ret;
 943         int sg_link_tbl_len;
 944
 945         /* hmac key */
 946         map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
 947                                0, DMA_TO_DEVICE);
 948
 949         /* hmac data */
 950         desc->ptr[1].len = cpu_to_be16(areq->assoclen + ivsize);
 951         if (edesc->assoc_nents) {
 952                 int tbl_off = edesc->src_nents + edesc->dst_nents + 2;
 953                 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
 954
 955                 to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
 956                                sizeof(struct talitos_ptr));
 957                 desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
 958
 959                 /* assoc_nents - 1 entries for assoc, 1 for IV */
 960                 sg_count = sg_to_link_tbl(areq->assoc, edesc->assoc_nents - 1,
 961                                           areq->assoclen, tbl_ptr);
 962
 963                 /* add IV to link table */
 964                 tbl_ptr += sg_count - 1;
 965                 tbl_ptr->j_extent = 0;
 966                 tbl_ptr++;
 967                 to_talitos_ptr(tbl_ptr, edesc->iv_dma);
 968                 tbl_ptr->len = cpu_to_be16(ivsize);
 969                 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 970
 971                 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
 972                                            edesc->dma_len, DMA_BIDIRECTIONAL);
 973         } else {
 974                 to_talitos_ptr(&desc->ptr[1], sg_dma_address(areq->assoc));
 975                 desc->ptr[1].j_extent = 0;
 976         }
 977
 978         /* cipher iv */
 979         to_talitos_ptr(&desc->ptr[2], edesc->iv_dma);
 980         desc->ptr[2].len = cpu_to_be16(ivsize);
 981         desc->ptr[2].j_extent = 0;
 982         /* Sync needed for the aead_givencrypt case */
 983         dma_sync_single_for_device(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
 984
 985         /* cipher key */
 986         map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
 987                                (char *)&ctx->key + ctx->authkeylen, 0,
 988                                DMA_TO_DEVICE);
 989
 990         /*
 991          * cipher in
 992          * map and adjust cipher len to aead request cryptlen.
 993          * extent is bytes of HMAC postpended to ciphertext,
 994          * typically 12 for ipsec
 995          */
 996         desc->ptr[4].len = cpu_to_be16(cryptlen);
 997         desc->ptr[4].j_extent = authsize;
 998
 999         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1000                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1001                                                            : DMA_TO_DEVICE,
1002                                   edesc->src_chained);
1003
1004         if (sg_count == 1) {
1005                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
1006         } else {
1007                 sg_link_tbl_len = cryptlen;
1008
1009                 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
1010                         sg_link_tbl_len = cryptlen + authsize;
1011
1012                 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
1013                                           &edesc->link_tbl[0]);
1014                 if (sg_count > 1) {
1015                         desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1016                         to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
1017                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1018                                                    edesc->dma_len,
1019                                                    DMA_BIDIRECTIONAL);
1020                 } else {
1021                         /* Only one segment now, so no link tbl needed */
1022                         to_talitos_ptr(&desc->ptr[4],
1023                                        sg_dma_address(areq->src));
1024                 }
1025         }
1026
1027         /* cipher out */
1028         desc->ptr[5].len = cpu_to_be16(cryptlen);
1029         desc->ptr[5].j_extent = authsize;
1030
1031         if (areq->src != areq->dst)
1032                 sg_count = talitos_map_sg(dev, areq->dst,
1033                                           edesc->dst_nents ? : 1,
1034                                           DMA_FROM_DEVICE, edesc->dst_chained);
1035
1036         if (sg_count == 1) {
1037                 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
1038         } else {
1039                 int tbl_off = edesc->src_nents + 1;
1040                 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
1041
1042                 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1043                                tbl_off * sizeof(struct talitos_ptr));
1044                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1045                                           tbl_ptr);
1046
1047                 /* Add an entry to the link table for ICV data */
1048                 tbl_ptr += sg_count - 1;
1049                 tbl_ptr->j_extent = 0;
1050                 tbl_ptr++;
1051                 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1052                 tbl_ptr->len = cpu_to_be16(authsize);
1053
1054                 /* icv data follows link tables */
1055                 to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl +
1056                                (tbl_off + edesc->dst_nents + 1 +
1057                                 edesc->assoc_nents) *
1058                                sizeof(struct talitos_ptr));
1059                 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1060                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1061                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1062         }
1063
1064         /* iv out */
1065         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1066                                DMA_FROM_DEVICE);
1067
1068         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1069         if (ret != -EINPROGRESS) {
1070                 ipsec_esp_unmap(dev, edesc, areq);
1071                 kfree(edesc);
1072         }
1073         return ret;
1074 }
1075
1076 /*
1077  * derive number of elements in scatterlist
1078  */
1079 static int sg_count(struct scatterlist *sg_list, int nbytes, bool *chained)
1080 {
1081         struct scatterlist *sg = sg_list;
1082         int sg_nents = 0;
1083
1084         *chained = false;
1085         while (nbytes > 0) {
1086                 sg_nents++;
1087                 nbytes -= sg->length;
1088                 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1089                         *chained = true;
1090                 sg = scatterwalk_sg_next(sg);
1091         }
1092
1093         return sg_nents;
1094 }
1095
1096 /*
1097  * allocate and map the extended descriptor
1098  */
1099 static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1100                                                  struct scatterlist *assoc,
1101                                                  struct scatterlist *src,
1102                                                  struct scatterlist *dst,
1103                                                  u8 *iv,
1104                                                  unsigned int assoclen,
1105                                                  unsigned int cryptlen,
1106                                                  unsigned int authsize,
1107                                                  unsigned int ivsize,
1108                                                  int icv_stashing,
1109                                                  u32 cryptoflags)
1110 {
1111         struct talitos_edesc *edesc;
1112         int assoc_nents = 0, src_nents, dst_nents, alloc_len, dma_len;
1113         bool assoc_chained = false, src_chained = false, dst_chained = false;
1114         dma_addr_t iv_dma = 0;
1115         gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1116                       GFP_ATOMIC;
1117
1118         if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1119                 dev_err(dev, "length exceeds h/w max limit\n");
1120                 return ERR_PTR(-EINVAL);
1121         }
1122
1123         if (iv)
1124                 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
1125
1126         if (assoc) {
1127                 /*
1128                  * Currently it is assumed that iv is provided whenever assoc
1129                  * is.
1130                  */
1131                 BUG_ON(!iv);
1132
1133                 assoc_nents = sg_count(assoc, assoclen, &assoc_chained);
1134                 talitos_map_sg(dev, assoc, assoc_nents, DMA_TO_DEVICE,
1135                                assoc_chained);
1136                 assoc_nents = (assoc_nents == 1) ? 0 : assoc_nents;
1137
1138                 if (assoc_nents || sg_dma_address(assoc) + assoclen != iv_dma)
1139                         assoc_nents = assoc_nents ? assoc_nents + 1 : 2;
1140         }
1141
1142         src_nents = sg_count(src, cryptlen + authsize, &src_chained);
1143         src_nents = (src_nents == 1) ? 0 : src_nents;
1144
1145         if (!dst) {
1146                 dst_nents = 0;
1147         } else {
1148                 if (dst == src) {
1149                         dst_nents = src_nents;
1150                 } else {
1151                         dst_nents = sg_count(dst, cryptlen + authsize,
1152                                              &dst_chained);
1153                         dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1154                 }
1155         }
1156
1157         /*
1158          * allocate space for base edesc plus the link tables,
1159          * allowing for two separate entries for ICV and generated ICV (+ 2),
1160          * and the ICV data itself
1161          */
1162         alloc_len = sizeof(struct talitos_edesc);
1163         if (assoc_nents || src_nents || dst_nents) {
1164                 dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
1165                           sizeof(struct talitos_ptr) + authsize;
1166                 alloc_len += dma_len;
1167         } else {
1168                 dma_len = 0;
1169                 alloc_len += icv_stashing ? authsize : 0;
1170         }
1171
1172         edesc = kmalloc(alloc_len, GFP_DMA | flags);
1173         if (!edesc) {
1174                 talitos_unmap_sg_chain(dev, assoc, DMA_TO_DEVICE);
1175                 if (iv_dma)
1176                         dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
1177                 dev_err(dev, "could not allocate edescriptor\n");
1178                 return ERR_PTR(-ENOMEM);
1179         }
1180
1181         edesc->assoc_nents = assoc_nents;
1182         edesc->src_nents = src_nents;
1183         edesc->dst_nents = dst_nents;
1184         edesc->assoc_chained = assoc_chained;
1185         edesc->src_chained = src_chained;
1186         edesc->dst_chained = dst_chained;
1187         edesc->iv_dma = iv_dma;
1188         edesc->dma_len = dma_len;
1189         if (dma_len)
1190                 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1191                                                      edesc->dma_len,
1192                                                      DMA_BIDIRECTIONAL);
1193
1194         return edesc;
1195 }
1196
1197 static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
1198                                               int icv_stashing)
1199 {
1200         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1201         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1202         unsigned int ivsize = crypto_aead_ivsize(authenc);
1203
1204         return talitos_edesc_alloc(ctx->dev, areq->assoc, areq->src, areq->dst,
1205                                    iv, areq->assoclen, areq->cryptlen,
1206                                    ctx->authsize, ivsize, icv_stashing,
1207                                    areq->base.flags);
1208 }
1209
1210 static int aead_encrypt(struct aead_request *req)
1211 {
1212         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1213         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1214         struct talitos_edesc *edesc;
1215
1216         /* allocate extended descriptor */
1217         edesc = aead_edesc_alloc(req, req->iv, 0);
1218         if (IS_ERR(edesc))
1219                 return PTR_ERR(edesc);
1220
1221         /* set encrypt */
1222         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1223
1224         return ipsec_esp(edesc, req, 0, ipsec_esp_encrypt_done);
1225 }
1226
1227 static int aead_decrypt(struct aead_request *req)
1228 {
1229         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1230         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1231         unsigned int authsize = ctx->authsize;
1232         struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1233         struct talitos_edesc *edesc;
1234         struct scatterlist *sg;
1235         void *icvdata;
1236
1237         req->cryptlen -= authsize;
1238
1239         /* allocate extended descriptor */
1240         edesc = aead_edesc_alloc(req, req->iv, 1);
1241         if (IS_ERR(edesc))
1242                 return PTR_ERR(edesc);
1243
1244         if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
1245             ((!edesc->src_nents && !edesc->dst_nents) ||
1246              priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
1247
1248                 /* decrypt and check the ICV */
1249                 edesc->desc.hdr = ctx->desc_hdr_template |
1250                                   DESC_HDR_DIR_INBOUND |
1251                                   DESC_HDR_MODE1_MDEU_CICV;
1252
1253                 /* reset integrity check result bits */
1254                 edesc->desc.hdr_lo = 0;
1255
1256                 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_hwauth_done);
1257         }
1258
1259         /* Have to check the ICV with software */
1260         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1261
1262         /* stash incoming ICV for later cmp with ICV generated by the h/w */
1263         if (edesc->dma_len)
1264                 icvdata = &edesc->link_tbl[edesc->src_nents +
1265                                            edesc->dst_nents + 2 +
1266                                            edesc->assoc_nents];
1267         else
1268                 icvdata = &edesc->link_tbl[0];
1269
1270         sg = sg_last(req->src, edesc->src_nents ? : 1);
1271
1272         memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1273                ctx->authsize);
1274
1275         return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_swauth_done);
1276 }
1277
1278 static int aead_givencrypt(struct aead_givcrypt_request *req)
1279 {
1280         struct aead_request *areq = &req->areq;
1281         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1282         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1283         struct talitos_edesc *edesc;
1284
1285         /* allocate extended descriptor */
1286         edesc = aead_edesc_alloc(areq, req->giv, 0);
1287         if (IS_ERR(edesc))
1288                 return PTR_ERR(edesc);
1289
1290         /* set encrypt */
1291         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1292
1293         memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1294         /* avoid consecutive packets going out with same IV */
1295         *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1296
1297         return ipsec_esp(edesc, areq, req->seq, ipsec_esp_encrypt_done);
1298 }
1299
1300 static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1301                              const u8 *key, unsigned int keylen)
1302 {
1303         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1304
1305         memcpy(&ctx->key, key, keylen);
1306         ctx->keylen = keylen;
1307
1308         return 0;
1309 }
1310
1311 static void common_nonsnoop_unmap(struct device *dev,
1312                                   struct talitos_edesc *edesc,
1313                                   struct ablkcipher_request *areq)
1314 {
1315         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1316         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1317         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1318
1319         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1320
1321         if (edesc->dma_len)
1322                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1323                                  DMA_BIDIRECTIONAL);
1324 }
1325
1326 static void ablkcipher_done(struct device *dev,
1327                             struct talitos_desc *desc, void *context,
1328                             int err)
1329 {
1330         struct ablkcipher_request *areq = context;
1331         struct talitos_edesc *edesc;
1332
1333         edesc = container_of(desc, struct talitos_edesc, desc);
1334
1335         common_nonsnoop_unmap(dev, edesc, areq);
1336
1337         kfree(edesc);
1338
1339         areq->base.complete(&areq->base, err);
1340 }
1341
1342 static int common_nonsnoop(struct talitos_edesc *edesc,
1343                            struct ablkcipher_request *areq,
1344                            void (*callback) (struct device *dev,
1345                                              struct talitos_desc *desc,
1346                                              void *context, int error))
1347 {
1348         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1349         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1350         struct device *dev = ctx->dev;
1351         struct talitos_desc *desc = &edesc->desc;
1352         unsigned int cryptlen = areq->nbytes;
1353         unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1354         int sg_count, ret;
1355
1356         /* first DWORD empty */
1357         desc->ptr[0].len = 0;
1358         to_talitos_ptr(&desc->ptr[0], 0);
1359         desc->ptr[0].j_extent = 0;
1360
1361         /* cipher iv */
1362         to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
1363         desc->ptr[1].len = cpu_to_be16(ivsize);
1364         desc->ptr[1].j_extent = 0;
1365
1366         /* cipher key */
1367         map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1368                                (char *)&ctx->key, 0, DMA_TO_DEVICE);
1369
1370         /*
1371          * cipher in
1372          */
1373         desc->ptr[3].len = cpu_to_be16(cryptlen);
1374         desc->ptr[3].j_extent = 0;
1375
1376         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1377                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1378                                                            : DMA_TO_DEVICE,
1379                                   edesc->src_chained);
1380
1381         if (sg_count == 1) {
1382                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
1383         } else {
1384                 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1385                                           &edesc->link_tbl[0]);
1386                 if (sg_count > 1) {
1387                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1388                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1389                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1390                                                    edesc->dma_len,
1391                                                    DMA_BIDIRECTIONAL);
1392                 } else {
1393                         /* Only one segment now, so no link tbl needed */
1394                         to_talitos_ptr(&desc->ptr[3],
1395                                        sg_dma_address(areq->src));
1396                 }
1397         }
1398
1399         /* cipher out */
1400         desc->ptr[4].len = cpu_to_be16(cryptlen);
1401         desc->ptr[4].j_extent = 0;
1402
1403         if (areq->src != areq->dst)
1404                 sg_count = talitos_map_sg(dev, areq->dst,
1405                                           edesc->dst_nents ? : 1,
1406                                           DMA_FROM_DEVICE, edesc->dst_chained);
1407
1408         if (sg_count == 1) {
1409                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
1410         } else {
1411                 struct talitos_ptr *link_tbl_ptr =
1412                         &edesc->link_tbl[edesc->src_nents + 1];
1413
1414                 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1415                                               (edesc->src_nents + 1) *
1416                                               sizeof(struct talitos_ptr));
1417                 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1418                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1419                                           link_tbl_ptr);
1420                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1421                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1422         }
1423
1424         /* iv out */
1425         map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1426                                DMA_FROM_DEVICE);
1427
1428         /* last DWORD empty */
1429         desc->ptr[6].len = 0;
1430         to_talitos_ptr(&desc->ptr[6], 0);
1431         desc->ptr[6].j_extent = 0;
1432
1433         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1434         if (ret != -EINPROGRESS) {
1435                 common_nonsnoop_unmap(dev, edesc, areq);
1436                 kfree(edesc);
1437         }
1438         return ret;
1439 }
1440
1441 static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1442                                                     areq)
1443 {
1444         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1445         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1446         unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1447
1448         return talitos_edesc_alloc(ctx->dev, NULL, areq->src, areq->dst,
1449                                    areq->info, 0, areq->nbytes, 0, ivsize, 0,
1450                                    areq->base.flags);
1451 }
1452
1453 static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1454 {
1455         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1456         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1457         struct talitos_edesc *edesc;
1458
1459         /* allocate extended descriptor */
1460         edesc = ablkcipher_edesc_alloc(areq);
1461         if (IS_ERR(edesc))
1462                 return PTR_ERR(edesc);
1463
1464         /* set encrypt */
1465         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1466
1467         return common_nonsnoop(edesc, areq, ablkcipher_done);
1468 }
1469
1470 static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1471 {
1472         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1473         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1474         struct talitos_edesc *edesc;
1475
1476         /* allocate extended descriptor */
1477         edesc = ablkcipher_edesc_alloc(areq);
1478         if (IS_ERR(edesc))
1479                 return PTR_ERR(edesc);
1480
1481         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1482
1483         return common_nonsnoop(edesc, areq, ablkcipher_done);
1484 }
1485
1486 static void common_nonsnoop_hash_unmap(struct device *dev,
1487                                        struct talitos_edesc *edesc,
1488                                        struct ahash_request *areq)
1489 {
1490         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1491
1492         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1493
1494         /* When using hashctx-in, must unmap it. */
1495         if (edesc->desc.ptr[1].len)
1496                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1497                                          DMA_TO_DEVICE);
1498
1499         if (edesc->desc.ptr[2].len)
1500                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1501                                          DMA_TO_DEVICE);
1502
1503         talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1504
1505         if (edesc->dma_len)
1506                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1507                                  DMA_BIDIRECTIONAL);
1508
1509 }
1510
1511 static void ahash_done(struct device *dev,
1512                        struct talitos_desc *desc, void *context,
1513                        int err)
1514 {
1515         struct ahash_request *areq = context;
1516         struct talitos_edesc *edesc =
1517                  container_of(desc, struct talitos_edesc, desc);
1518         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1519
1520         if (!req_ctx->last && req_ctx->to_hash_later) {
1521                 /* Position any partial block for next update/final/finup */
1522                 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
1523                 req_ctx->nbuf = req_ctx->to_hash_later;
1524         }
1525         common_nonsnoop_hash_unmap(dev, edesc, areq);
1526
1527         kfree(edesc);
1528
1529         areq->base.complete(&areq->base, err);
1530 }
1531
1532 static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1533                                 struct ahash_request *areq, unsigned int length,
1534                                 void (*callback) (struct device *dev,
1535                                                   struct talitos_desc *desc,
1536                                                   void *context, int error))
1537 {
1538         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1539         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1540         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1541         struct device *dev = ctx->dev;
1542         struct talitos_desc *desc = &edesc->desc;
1543         int sg_count, ret;
1544
1545         /* first DWORD empty */
1546         desc->ptr[0] = zero_entry;
1547
1548         /* hash context in */
1549         if (!req_ctx->first || req_ctx->swinit) {
1550                 map_single_talitos_ptr(dev, &desc->ptr[1],
1551                                        req_ctx->hw_context_size,
1552                                        (char *)req_ctx->hw_context, 0,
1553                                        DMA_TO_DEVICE);
1554                 req_ctx->swinit = 0;
1555         } else {
1556                 desc->ptr[1] = zero_entry;
1557                 /* Indicate next op is not the first. */
1558                 req_ctx->first = 0;
1559         }
1560
1561         /* HMAC key */
1562         if (ctx->keylen)
1563                 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1564                                        (char *)&ctx->key, 0, DMA_TO_DEVICE);
1565         else
1566                 desc->ptr[2] = zero_entry;
1567
1568         /*
1569          * data in
1570          */
1571         desc->ptr[3].len = cpu_to_be16(length);
1572         desc->ptr[3].j_extent = 0;
1573
1574         sg_count = talitos_map_sg(dev, req_ctx->psrc,
1575                                   edesc->src_nents ? : 1,
1576                                   DMA_TO_DEVICE, edesc->src_chained);
1577
1578         if (sg_count == 1) {
1579                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1580         } else {
1581                 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1582                                           &edesc->link_tbl[0]);
1583                 if (sg_count > 1) {
1584                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1585                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1586                         dma_sync_single_for_device(ctx->dev,
1587                                                    edesc->dma_link_tbl,
1588                                                    edesc->dma_len,
1589                                                    DMA_BIDIRECTIONAL);
1590                 } else {
1591                         /* Only one segment now, so no link tbl needed */
1592                         to_talitos_ptr(&desc->ptr[3],
1593                                        sg_dma_address(req_ctx->psrc));
1594                 }
1595         }
1596
1597         /* fifth DWORD empty */
1598         desc->ptr[4] = zero_entry;
1599
1600         /* hash/HMAC out -or- hash context out */
1601         if (req_ctx->last)
1602                 map_single_talitos_ptr(dev, &desc->ptr[5],
1603                                        crypto_ahash_digestsize(tfm),
1604                                        areq->result, 0, DMA_FROM_DEVICE);
1605         else
1606                 map_single_talitos_ptr(dev, &desc->ptr[5],
1607                                        req_ctx->hw_context_size,
1608                                        req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1609
1610         /* last DWORD empty */
1611         desc->ptr[6] = zero_entry;
1612
1613         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1614         if (ret != -EINPROGRESS) {
1615                 common_nonsnoop_hash_unmap(dev, edesc, areq);
1616                 kfree(edesc);
1617         }
1618         return ret;
1619 }
1620
1621 static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1622                                                unsigned int nbytes)
1623 {
1624         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1625         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1626         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1627
1628         return talitos_edesc_alloc(ctx->dev, NULL, req_ctx->psrc, NULL, NULL, 0,
1629                                    nbytes, 0, 0, 0, areq->base.flags);
1630 }
1631
1632 static int ahash_init(struct ahash_request *areq)
1633 {
1634         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1635         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1636
1637         /* Initialize the context */
1638         req_ctx->nbuf = 0;
1639         req_ctx->first = 1; /* first indicates h/w must init its context */
1640         req_ctx->swinit = 0; /* assume h/w init of context */
1641         req_ctx->hw_context_size =
1642                 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1643                         ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1644                         : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1645
1646         return 0;
1647 }
1648
1649 /*
1650  * on h/w without explicit sha224 support, we initialize h/w context
1651  * manually with sha224 constants, and tell it to run sha256.
1652  */
1653 static int ahash_init_sha224_swinit(struct ahash_request *areq)
1654 {
1655         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1656
1657         ahash_init(areq);
1658         req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1659
1660         req_ctx->hw_context[0] = SHA224_H0;
1661         req_ctx->hw_context[1] = SHA224_H1;
1662         req_ctx->hw_context[2] = SHA224_H2;
1663         req_ctx->hw_context[3] = SHA224_H3;
1664         req_ctx->hw_context[4] = SHA224_H4;
1665         req_ctx->hw_context[5] = SHA224_H5;
1666         req_ctx->hw_context[6] = SHA224_H6;
1667         req_ctx->hw_context[7] = SHA224_H7;
1668
1669         /* init 64-bit count */
1670         req_ctx->hw_context[8] = 0;
1671         req_ctx->hw_context[9] = 0;
1672
1673         return 0;
1674 }
1675
1676 static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1677 {
1678         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1679         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1680         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1681         struct talitos_edesc *edesc;
1682         unsigned int blocksize =
1683                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1684         unsigned int nbytes_to_hash;
1685         unsigned int to_hash_later;
1686         unsigned int nsg;
1687         bool chained;
1688
1689         if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1690                 /* Buffer up to one whole block */
1691                 sg_copy_to_buffer(areq->src,
1692                                   sg_count(areq->src, nbytes, &chained),
1693                                   req_ctx->buf + req_ctx->nbuf, nbytes);
1694                 req_ctx->nbuf += nbytes;
1695                 return 0;
1696         }
1697
1698         /* At least (blocksize + 1) bytes are available to hash */
1699         nbytes_to_hash = nbytes + req_ctx->nbuf;
1700         to_hash_later = nbytes_to_hash & (blocksize - 1);
1701
1702         if (req_ctx->last)
1703                 to_hash_later = 0;
1704         else if (to_hash_later)
1705                 /* There is a partial block. Hash the full block(s) now */
1706                 nbytes_to_hash -= to_hash_later;
1707         else {
1708                 /* Keep one block buffered */
1709                 nbytes_to_hash -= blocksize;
1710                 to_hash_later = blocksize;
1711         }
1712
1713         /* Chain in any previously buffered data */
1714         if (req_ctx->nbuf) {
1715                 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1716                 sg_init_table(req_ctx->bufsl, nsg);
1717                 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1718                 if (nsg > 1)
1719                         scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
1720                 req_ctx->psrc = req_ctx->bufsl;
1721         } else
1722                 req_ctx->psrc = areq->src;
1723
1724         if (to_hash_later) {
1725                 int nents = sg_count(areq->src, nbytes, &chained);
1726                 sg_pcopy_to_buffer(areq->src, nents,
1727                                       req_ctx->bufnext,
1728                                       to_hash_later,
1729                                       nbytes - to_hash_later);
1730         }
1731         req_ctx->to_hash_later = to_hash_later;
1732
1733         /* Allocate extended descriptor */
1734         edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1735         if (IS_ERR(edesc))
1736                 return PTR_ERR(edesc);
1737
1738         edesc->desc.hdr = ctx->desc_hdr_template;
1739
1740         /* On last one, request SEC to pad; otherwise continue */
1741         if (req_ctx->last)
1742                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1743         else
1744                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1745
1746         /* request SEC to INIT hash. */
1747         if (req_ctx->first && !req_ctx->swinit)
1748                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1749
1750         /* When the tfm context has a keylen, it's an HMAC.
1751          * A first or last (ie. not middle) descriptor must request HMAC.
1752          */
1753         if (ctx->keylen && (req_ctx->first || req_ctx->last))
1754                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1755
1756         return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1757                                     ahash_done);
1758 }
1759
1760 static int ahash_update(struct ahash_request *areq)
1761 {
1762         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1763
1764         req_ctx->last = 0;
1765
1766         return ahash_process_req(areq, areq->nbytes);
1767 }
1768
1769 static int ahash_final(struct ahash_request *areq)
1770 {
1771         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1772
1773         req_ctx->last = 1;
1774
1775         return ahash_process_req(areq, 0);
1776 }
1777
1778 static int ahash_finup(struct ahash_request *areq)
1779 {
1780         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1781
1782         req_ctx->last = 1;
1783
1784         return ahash_process_req(areq, areq->nbytes);
1785 }
1786
1787 static int ahash_digest(struct ahash_request *areq)
1788 {
1789         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1790         struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
1791
1792         ahash->init(areq);
1793         req_ctx->last = 1;
1794
1795         return ahash_process_req(areq, areq->nbytes);
1796 }
1797
1798 struct keyhash_result {
1799         struct completion completion;
1800         int err;
1801 };
1802
1803 static void keyhash_complete(struct crypto_async_request *req, int err)
1804 {
1805         struct keyhash_result *res = req->data;
1806
1807         if (err == -EINPROGRESS)
1808                 return;
1809
1810         res->err = err;
1811         complete(&res->completion);
1812 }
1813
1814 static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1815                    u8 *hash)
1816 {
1817         struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1818
1819         struct scatterlist sg[1];
1820         struct ahash_request *req;
1821         struct keyhash_result hresult;
1822         int ret;
1823
1824         init_completion(&hresult.completion);
1825
1826         req = ahash_request_alloc(tfm, GFP_KERNEL);
1827         if (!req)
1828                 return -ENOMEM;
1829
1830         /* Keep tfm keylen == 0 during hash of the long key */
1831         ctx->keylen = 0;
1832         ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1833                                    keyhash_complete, &hresult);
1834
1835         sg_init_one(&sg[0], key, keylen);
1836
1837         ahash_request_set_crypt(req, sg, hash, keylen);
1838         ret = crypto_ahash_digest(req);
1839         switch (ret) {
1840         case 0:
1841                 break;
1842         case -EINPROGRESS:
1843         case -EBUSY:
1844                 ret = wait_for_completion_interruptible(
1845                         &hresult.completion);
1846                 if (!ret)
1847                         ret = hresult.err;
1848                 break;
1849         default:
1850                 break;
1851         }
1852         ahash_request_free(req);
1853
1854         return ret;
1855 }
1856
1857 static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1858                         unsigned int keylen)
1859 {
1860         struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1861         unsigned int blocksize =
1862                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1863         unsigned int digestsize = crypto_ahash_digestsize(tfm);
1864         unsigned int keysize = keylen;
1865         u8 hash[SHA512_DIGEST_SIZE];
1866         int ret;
1867
1868         if (keylen <= blocksize)
1869                 memcpy(ctx->key, key, keysize);
1870         else {
1871                 /* Must get the hash of the long key */
1872                 ret = keyhash(tfm, key, keylen, hash);
1873
1874                 if (ret) {
1875                         crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1876                         return -EINVAL;
1877                 }
1878
1879                 keysize = digestsize;
1880                 memcpy(ctx->key, hash, digestsize);
1881         }
1882
1883         ctx->keylen = keysize;
1884
1885         return 0;
1886 }
1887
1888
1889 struct talitos_alg_template {
1890         u32 type;
1891         union {
1892                 struct crypto_alg crypto;
1893                 struct ahash_alg hash;
1894         } alg;
1895         __be32 desc_hdr_template;
1896 };
1897
1898 static struct talitos_alg_template driver_algs[] = {
1899         /* AEAD algorithms.  These use a single-pass ipsec_esp descriptor */
1900         {       .type = CRYPTO_ALG_TYPE_AEAD,
1901                 .alg.crypto = {
1902                         .cra_name = "authenc(hmac(sha1),cbc(aes))",
1903                         .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1904                         .cra_blocksize = AES_BLOCK_SIZE,
1905                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1906                         .cra_aead = {
1907                                 .ivsize = AES_BLOCK_SIZE,
1908                                 .maxauthsize = SHA1_DIGEST_SIZE,
1909                         }
1910                 },
1911                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1912                                      DESC_HDR_SEL0_AESU |
1913                                      DESC_HDR_MODE0_AESU_CBC |
1914                                      DESC_HDR_SEL1_MDEUA |
1915                                      DESC_HDR_MODE1_MDEU_INIT |
1916                                      DESC_HDR_MODE1_MDEU_PAD |
1917                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1918         },
1919         {       .type = CRYPTO_ALG_TYPE_AEAD,
1920                 .alg.crypto = {
1921                         .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1922                         .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1923                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1924                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1925                         .cra_aead = {
1926                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1927                                 .maxauthsize = SHA1_DIGEST_SIZE,
1928                         }
1929                 },
1930                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1931                                      DESC_HDR_SEL0_DEU |
1932                                      DESC_HDR_MODE0_DEU_CBC |
1933                                      DESC_HDR_MODE0_DEU_3DES |
1934                                      DESC_HDR_SEL1_MDEUA |
1935                                      DESC_HDR_MODE1_MDEU_INIT |
1936                                      DESC_HDR_MODE1_MDEU_PAD |
1937                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1938         },
1939         {       .type = CRYPTO_ALG_TYPE_AEAD,
1940                 .alg.crypto = {
1941                         .cra_name = "authenc(hmac(sha224),cbc(aes))",
1942                         .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
1943                         .cra_blocksize = AES_BLOCK_SIZE,
1944                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1945                         .cra_aead = {
1946                                 .ivsize = AES_BLOCK_SIZE,
1947                                 .maxauthsize = SHA224_DIGEST_SIZE,
1948                         }
1949                 },
1950                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1951                                      DESC_HDR_SEL0_AESU |
1952                                      DESC_HDR_MODE0_AESU_CBC |
1953                                      DESC_HDR_SEL1_MDEUA |
1954                                      DESC_HDR_MODE1_MDEU_INIT |
1955                                      DESC_HDR_MODE1_MDEU_PAD |
1956                                      DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1957         },
1958         {       .type = CRYPTO_ALG_TYPE_AEAD,
1959                 .alg.crypto = {
1960                         .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
1961                         .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
1962                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1963                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1964                         .cra_aead = {
1965                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1966                                 .maxauthsize = SHA224_DIGEST_SIZE,
1967                         }
1968                 },
1969                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1970                                      DESC_HDR_SEL0_DEU |
1971                                      DESC_HDR_MODE0_DEU_CBC |
1972                                      DESC_HDR_MODE0_DEU_3DES |
1973                                      DESC_HDR_SEL1_MDEUA |
1974                                      DESC_HDR_MODE1_MDEU_INIT |
1975                                      DESC_HDR_MODE1_MDEU_PAD |
1976                                      DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1977         },
1978         {       .type = CRYPTO_ALG_TYPE_AEAD,
1979                 .alg.crypto = {
1980                         .cra_name = "authenc(hmac(sha256),cbc(aes))",
1981                         .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1982                         .cra_blocksize = AES_BLOCK_SIZE,
1983                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1984                         .cra_aead = {
1985                                 .ivsize = AES_BLOCK_SIZE,
1986                                 .maxauthsize = SHA256_DIGEST_SIZE,
1987                         }
1988                 },
1989                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1990                                      DESC_HDR_SEL0_AESU |
1991                                      DESC_HDR_MODE0_AESU_CBC |
1992                                      DESC_HDR_SEL1_MDEUA |
1993                                      DESC_HDR_MODE1_MDEU_INIT |
1994                                      DESC_HDR_MODE1_MDEU_PAD |
1995                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1996         },
1997         {       .type = CRYPTO_ALG_TYPE_AEAD,
1998                 .alg.crypto = {
1999                         .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
2000                         .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
2001                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2002                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2003                         .cra_aead = {
2004                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2005                                 .maxauthsize = SHA256_DIGEST_SIZE,
2006                         }
2007                 },
2008                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2009                                      DESC_HDR_SEL0_DEU |
2010                                      DESC_HDR_MODE0_DEU_CBC |
2011                                      DESC_HDR_MODE0_DEU_3DES |
2012                                      DESC_HDR_SEL1_MDEUA |
2013                                      DESC_HDR_MODE1_MDEU_INIT |
2014                                      DESC_HDR_MODE1_MDEU_PAD |
2015                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2016         },
2017         {       .type = CRYPTO_ALG_TYPE_AEAD,
2018                 .alg.crypto = {
2019                         .cra_name = "authenc(hmac(sha384),cbc(aes))",
2020                         .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2021                         .cra_blocksize = AES_BLOCK_SIZE,
2022                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2023                         .cra_aead = {
2024                                 .ivsize = AES_BLOCK_SIZE,
2025                                 .maxauthsize = SHA384_DIGEST_SIZE,
2026                         }
2027                 },
2028                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2029                                      DESC_HDR_SEL0_AESU |
2030                                      DESC_HDR_MODE0_AESU_CBC |
2031                                      DESC_HDR_SEL1_MDEUB |
2032                                      DESC_HDR_MODE1_MDEU_INIT |
2033                                      DESC_HDR_MODE1_MDEU_PAD |
2034                                      DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2035         },
2036         {       .type = CRYPTO_ALG_TYPE_AEAD,
2037                 .alg.crypto = {
2038                         .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2039                         .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2040                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2041                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2042                         .cra_aead = {
2043                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2044                                 .maxauthsize = SHA384_DIGEST_SIZE,
2045                         }
2046                 },
2047                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2048                                      DESC_HDR_SEL0_DEU |
2049                                      DESC_HDR_MODE0_DEU_CBC |
2050                                      DESC_HDR_MODE0_DEU_3DES |
2051                                      DESC_HDR_SEL1_MDEUB |
2052                                      DESC_HDR_MODE1_MDEU_INIT |
2053                                      DESC_HDR_MODE1_MDEU_PAD |
2054                                      DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2055         },
2056         {       .type = CRYPTO_ALG_TYPE_AEAD,
2057                 .alg.crypto = {
2058                         .cra_name = "authenc(hmac(sha512),cbc(aes))",
2059                         .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2060                         .cra_blocksize = AES_BLOCK_SIZE,
2061                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2062                         .cra_aead = {
2063                                 .ivsize = AES_BLOCK_SIZE,
2064                                 .maxauthsize = SHA512_DIGEST_SIZE,
2065                         }
2066                 },
2067                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2068                                      DESC_HDR_SEL0_AESU |
2069                                      DESC_HDR_MODE0_AESU_CBC |
2070                                      DESC_HDR_SEL1_MDEUB |
2071                                      DESC_HDR_MODE1_MDEU_INIT |
2072                                      DESC_HDR_MODE1_MDEU_PAD |
2073                                      DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2074         },
2075         {       .type = CRYPTO_ALG_TYPE_AEAD,
2076                 .alg.crypto = {
2077                         .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2078                         .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2079                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2080                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2081                         .cra_aead = {
2082                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2083                                 .maxauthsize = SHA512_DIGEST_SIZE,
2084                         }
2085                 },
2086                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2087                                      DESC_HDR_SEL0_DEU |
2088                                      DESC_HDR_MODE0_DEU_CBC |
2089                                      DESC_HDR_MODE0_DEU_3DES |
2090                                      DESC_HDR_SEL1_MDEUB |
2091                                      DESC_HDR_MODE1_MDEU_INIT |
2092                                      DESC_HDR_MODE1_MDEU_PAD |
2093                                      DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2094         },
2095         {       .type = CRYPTO_ALG_TYPE_AEAD,
2096                 .alg.crypto = {
2097                         .cra_name = "authenc(hmac(md5),cbc(aes))",
2098                         .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2099                         .cra_blocksize = AES_BLOCK_SIZE,
2100                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2101                         .cra_aead = {
2102                                 .ivsize = AES_BLOCK_SIZE,
2103                                 .maxauthsize = MD5_DIGEST_SIZE,
2104                         }
2105                 },
2106                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2107                                      DESC_HDR_SEL0_AESU |
2108                                      DESC_HDR_MODE0_AESU_CBC |
2109                                      DESC_HDR_SEL1_MDEUA |
2110                                      DESC_HDR_MODE1_MDEU_INIT |
2111                                      DESC_HDR_MODE1_MDEU_PAD |
2112                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2113         },
2114         {       .type = CRYPTO_ALG_TYPE_AEAD,
2115                 .alg.crypto = {
2116                         .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2117                         .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2118                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2119                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2120                         .cra_aead = {
2121                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2122                                 .maxauthsize = MD5_DIGEST_SIZE,
2123                         }
2124                 },
2125                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2126                                      DESC_HDR_SEL0_DEU |
2127                                      DESC_HDR_MODE0_DEU_CBC |
2128                                      DESC_HDR_MODE0_DEU_3DES |
2129                                      DESC_HDR_SEL1_MDEUA |
2130                                      DESC_HDR_MODE1_MDEU_INIT |
2131                                      DESC_HDR_MODE1_MDEU_PAD |
2132                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2133         },
2134         /* ABLKCIPHER algorithms. */
2135         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2136                 .alg.crypto = {
2137                         .cra_name = "cbc(aes)",
2138                         .cra_driver_name = "cbc-aes-talitos",
2139                         .cra_blocksize = AES_BLOCK_SIZE,
2140                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2141                                      CRYPTO_ALG_ASYNC,
2142                         .cra_ablkcipher = {
2143                                 .min_keysize = AES_MIN_KEY_SIZE,
2144                                 .max_keysize = AES_MAX_KEY_SIZE,
2145                                 .ivsize = AES_BLOCK_SIZE,
2146                         }
2147                 },
2148                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2149                                      DESC_HDR_SEL0_AESU |
2150                                      DESC_HDR_MODE0_AESU_CBC,
2151         },
2152         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2153                 .alg.crypto = {
2154                         .cra_name = "cbc(des3_ede)",
2155                         .cra_driver_name = "cbc-3des-talitos",
2156                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2157                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2158                                      CRYPTO_ALG_ASYNC,
2159                         .cra_ablkcipher = {
2160                                 .min_keysize = DES3_EDE_KEY_SIZE,
2161                                 .max_keysize = DES3_EDE_KEY_SIZE,
2162                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2163                         }
2164                 },
2165                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2166                                      DESC_HDR_SEL0_DEU |
2167                                      DESC_HDR_MODE0_DEU_CBC |
2168                                      DESC_HDR_MODE0_DEU_3DES,
2169         },
2170         /* AHASH algorithms. */
2171         {       .type = CRYPTO_ALG_TYPE_AHASH,
2172                 .alg.hash = {
2173                         .halg.digestsize = MD5_DIGEST_SIZE,
2174                         .halg.base = {
2175                                 .cra_name = "md5",
2176                                 .cra_driver_name = "md5-talitos",
2177                                 .cra_blocksize = MD5_BLOCK_SIZE,
2178                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2179                                              CRYPTO_ALG_ASYNC,
2180                         }
2181                 },
2182                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2183                                      DESC_HDR_SEL0_MDEUA |
2184                                      DESC_HDR_MODE0_MDEU_MD5,
2185         },
2186         {       .type = CRYPTO_ALG_TYPE_AHASH,
2187                 .alg.hash = {
2188                         .halg.digestsize = SHA1_DIGEST_SIZE,
2189                         .halg.base = {
2190                                 .cra_name = "sha1",
2191                                 .cra_driver_name = "sha1-talitos",
2192                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2193                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2194                                              CRYPTO_ALG_ASYNC,
2195                         }
2196                 },
2197                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2198                                      DESC_HDR_SEL0_MDEUA |
2199                                      DESC_HDR_MODE0_MDEU_SHA1,
2200         },
2201         {       .type = CRYPTO_ALG_TYPE_AHASH,
2202                 .alg.hash = {
2203                         .halg.digestsize = SHA224_DIGEST_SIZE,
2204                         .halg.base = {
2205                                 .cra_name = "sha224",
2206                                 .cra_driver_name = "sha224-talitos",
2207                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2208                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2209                                              CRYPTO_ALG_ASYNC,
2210                         }
2211                 },
2212                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2213                                      DESC_HDR_SEL0_MDEUA |
2214                                      DESC_HDR_MODE0_MDEU_SHA224,
2215         },
2216         {       .type = CRYPTO_ALG_TYPE_AHASH,
2217                 .alg.hash = {
2218                         .halg.digestsize = SHA256_DIGEST_SIZE,
2219                         .halg.base = {
2220                                 .cra_name = "sha256",
2221                                 .cra_driver_name = "sha256-talitos",
2222                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2223                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2224                                              CRYPTO_ALG_ASYNC,
2225                         }
2226                 },
2227                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2228                                      DESC_HDR_SEL0_MDEUA |
2229                                      DESC_HDR_MODE0_MDEU_SHA256,
2230         },
2231         {       .type = CRYPTO_ALG_TYPE_AHASH,
2232                 .alg.hash = {
2233                         .halg.digestsize = SHA384_DIGEST_SIZE,
2234                         .halg.base = {
2235                                 .cra_name = "sha384",
2236                                 .cra_driver_name = "sha384-talitos",
2237                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2238                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2239                                              CRYPTO_ALG_ASYNC,
2240                         }
2241                 },
2242                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2243                                      DESC_HDR_SEL0_MDEUB |
2244                                      DESC_HDR_MODE0_MDEUB_SHA384,
2245         },
2246         {       .type = CRYPTO_ALG_TYPE_AHASH,
2247                 .alg.hash = {
2248                         .halg.digestsize = SHA512_DIGEST_SIZE,
2249                         .halg.base = {
2250                                 .cra_name = "sha512",
2251                                 .cra_driver_name = "sha512-talitos",
2252                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2253                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2254                                              CRYPTO_ALG_ASYNC,
2255                         }
2256                 },
2257                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2258                                      DESC_HDR_SEL0_MDEUB |
2259                                      DESC_HDR_MODE0_MDEUB_SHA512,
2260         },
2261         {       .type = CRYPTO_ALG_TYPE_AHASH,
2262                 .alg.hash = {
2263                         .halg.digestsize = MD5_DIGEST_SIZE,
2264                         .halg.base = {
2265                                 .cra_name = "hmac(md5)",
2266                                 .cra_driver_name = "hmac-md5-talitos",
2267                                 .cra_blocksize = MD5_BLOCK_SIZE,
2268                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2269                                              CRYPTO_ALG_ASYNC,
2270                         }
2271                 },
2272                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2273                                      DESC_HDR_SEL0_MDEUA |
2274                                      DESC_HDR_MODE0_MDEU_MD5,
2275         },
2276         {       .type = CRYPTO_ALG_TYPE_AHASH,
2277                 .alg.hash = {
2278                         .halg.digestsize = SHA1_DIGEST_SIZE,
2279                         .halg.base = {
2280                                 .cra_name = "hmac(sha1)",
2281                                 .cra_driver_name = "hmac-sha1-talitos",
2282                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2283                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2284                                              CRYPTO_ALG_ASYNC,
2285                         }
2286                 },
2287                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2288                                      DESC_HDR_SEL0_MDEUA |
2289                                      DESC_HDR_MODE0_MDEU_SHA1,
2290         },
2291         {       .type = CRYPTO_ALG_TYPE_AHASH,
2292                 .alg.hash = {
2293                         .halg.digestsize = SHA224_DIGEST_SIZE,
2294                         .halg.base = {
2295                                 .cra_name = "hmac(sha224)",
2296                                 .cra_driver_name = "hmac-sha224-talitos",
2297                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2298                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2299                                              CRYPTO_ALG_ASYNC,
2300                         }
2301                 },
2302                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2303                                      DESC_HDR_SEL0_MDEUA |
2304                                      DESC_HDR_MODE0_MDEU_SHA224,
2305         },
2306         {       .type = CRYPTO_ALG_TYPE_AHASH,
2307                 .alg.hash = {
2308                         .halg.digestsize = SHA256_DIGEST_SIZE,
2309                         .halg.base = {
2310                                 .cra_name = "hmac(sha256)",
2311                                 .cra_driver_name = "hmac-sha256-talitos",
2312                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2313                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2314                                              CRYPTO_ALG_ASYNC,
2315                         }
2316                 },
2317                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2318                                      DESC_HDR_SEL0_MDEUA |
2319                                      DESC_HDR_MODE0_MDEU_SHA256,
2320         },
2321         {       .type = CRYPTO_ALG_TYPE_AHASH,
2322                 .alg.hash = {
2323                         .halg.digestsize = SHA384_DIGEST_SIZE,
2324                         .halg.base = {
2325                                 .cra_name = "hmac(sha384)",
2326                                 .cra_driver_name = "hmac-sha384-talitos",
2327                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2328                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2329                                              CRYPTO_ALG_ASYNC,
2330                         }
2331                 },
2332                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2333                                      DESC_HDR_SEL0_MDEUB |
2334                                      DESC_HDR_MODE0_MDEUB_SHA384,
2335         },
2336         {       .type = CRYPTO_ALG_TYPE_AHASH,
2337                 .alg.hash = {
2338                         .halg.digestsize = SHA512_DIGEST_SIZE,
2339                         .halg.base = {
2340                                 .cra_name = "hmac(sha512)",
2341                                 .cra_driver_name = "hmac-sha512-talitos",
2342                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2343                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2344                                              CRYPTO_ALG_ASYNC,
2345                         }
2346                 },
2347                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2348                                      DESC_HDR_SEL0_MDEUB |
2349                                      DESC_HDR_MODE0_MDEUB_SHA512,
2350         }
2351 };
2352
2353 struct talitos_crypto_alg {
2354         struct list_head entry;
2355         struct device *dev;
2356         struct talitos_alg_template algt;
2357 };
2358
2359 static int talitos_cra_init(struct crypto_tfm *tfm)
2360 {
2361         struct crypto_alg *alg = tfm->__crt_alg;
2362         struct talitos_crypto_alg *talitos_alg;
2363         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2364         struct talitos_private *priv;
2365
2366         if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2367                 talitos_alg = container_of(__crypto_ahash_alg(alg),
2368                                            struct talitos_crypto_alg,
2369                                            algt.alg.hash);
2370         else
2371                 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2372                                            algt.alg.crypto);
2373
2374         /* update context with ptr to dev */
2375         ctx->dev = talitos_alg->dev;
2376
2377         /* assign SEC channel to tfm in round-robin fashion */
2378         priv = dev_get_drvdata(ctx->dev);
2379         ctx->ch = atomic_inc_return(&priv->last_chan) &
2380                   (priv->num_channels - 1);
2381
2382         /* copy descriptor header template value */
2383         ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
2384
2385         /* select done notification */
2386         ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2387
2388         return 0;
2389 }
2390
2391 static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2392 {
2393         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2394
2395         talitos_cra_init(tfm);
2396
2397         /* random first IV */
2398         get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
2399
2400         return 0;
2401 }
2402
2403 static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2404 {
2405         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2406
2407         talitos_cra_init(tfm);
2408
2409         ctx->keylen = 0;
2410         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2411                                  sizeof(struct talitos_ahash_req_ctx));
2412
2413         return 0;
2414 }
2415
2416 /*
2417  * given the alg's descriptor header template, determine whether descriptor
2418  * type and primary/secondary execution units required match the hw
2419  * capabilities description provided in the device tree node.
2420  */
2421 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2422 {
2423         struct talitos_private *priv = dev_get_drvdata(dev);
2424         int ret;
2425
2426         ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2427               (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2428
2429         if (SECONDARY_EU(desc_hdr_template))
2430                 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2431                               & priv->exec_units);
2432
2433         return ret;
2434 }
2435
2436 static int talitos_remove(struct platform_device *ofdev)
2437 {
2438         struct device *dev = &ofdev->dev;
2439         struct talitos_private *priv = dev_get_drvdata(dev);
2440         struct talitos_crypto_alg *t_alg, *n;
2441         int i;
2442
2443         list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
2444                 switch (t_alg->algt.type) {
2445                 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2446                 case CRYPTO_ALG_TYPE_AEAD:
2447                         crypto_unregister_alg(&t_alg->algt.alg.crypto);
2448                         break;
2449                 case CRYPTO_ALG_TYPE_AHASH:
2450                         crypto_unregister_ahash(&t_alg->algt.alg.hash);
2451                         break;
2452                 }
2453                 list_del(&t_alg->entry);
2454                 kfree(t_alg);
2455         }
2456
2457         if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2458                 talitos_unregister_rng(dev);
2459
2460         for (i = 0; i < priv->num_channels; i++)
2461                 kfree(priv->chan[i].fifo);
2462
2463         kfree(priv->chan);
2464
2465         for (i = 0; i < 2; i++)
2466                 if (priv->irq[i]) {
2467                         free_irq(priv->irq[i], dev);
2468                         irq_dispose_mapping(priv->irq[i]);
2469                 }
2470
2471         tasklet_kill(&priv->done_task[0]);
2472         if (priv->irq[1])
2473                 tasklet_kill(&priv->done_task[1]);
2474
2475         iounmap(priv->reg);
2476
2477         dev_set_drvdata(dev, NULL);
2478
2479         kfree(priv);
2480
2481         return 0;
2482 }
2483
2484 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2485                                                     struct talitos_alg_template
2486                                                            *template)
2487 {
2488         struct talitos_private *priv = dev_get_drvdata(dev);
2489         struct talitos_crypto_alg *t_alg;
2490         struct crypto_alg *alg;
2491
2492         t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2493         if (!t_alg)
2494                 return ERR_PTR(-ENOMEM);
2495
2496         t_alg->algt = *template;
2497
2498         switch (t_alg->algt.type) {
2499         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2500                 alg = &t_alg->algt.alg.crypto;
2501                 alg->cra_init = talitos_cra_init;
2502                 alg->cra_type = &crypto_ablkcipher_type;
2503                 alg->cra_ablkcipher.setkey = ablkcipher_setkey;
2504                 alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
2505                 alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
2506                 alg->cra_ablkcipher.geniv = "eseqiv";
2507                 break;
2508         case CRYPTO_ALG_TYPE_AEAD:
2509                 alg = &t_alg->algt.alg.crypto;
2510                 alg->cra_init = talitos_cra_init_aead;
2511                 alg->cra_type = &crypto_aead_type;
2512                 alg->cra_aead.setkey = aead_setkey;
2513                 alg->cra_aead.setauthsize = aead_setauthsize;
2514                 alg->cra_aead.encrypt = aead_encrypt;
2515                 alg->cra_aead.decrypt = aead_decrypt;
2516                 alg->cra_aead.givencrypt = aead_givencrypt;
2517                 alg->cra_aead.geniv = "<built-in>";
2518                 break;
2519         case CRYPTO_ALG_TYPE_AHASH:
2520                 alg = &t_alg->algt.alg.hash.halg.base;
2521                 alg->cra_init = talitos_cra_init_ahash;
2522                 alg->cra_type = &crypto_ahash_type;
2523                 t_alg->algt.alg.hash.init = ahash_init;
2524                 t_alg->algt.alg.hash.update = ahash_update;
2525                 t_alg->algt.alg.hash.final = ahash_final;
2526                 t_alg->algt.alg.hash.finup = ahash_finup;
2527                 t_alg->algt.alg.hash.digest = ahash_digest;
2528                 t_alg->algt.alg.hash.setkey = ahash_setkey;
2529
2530                 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
2531                     !strncmp(alg->cra_name, "hmac", 4)) {
2532                         kfree(t_alg);
2533                         return ERR_PTR(-ENOTSUPP);
2534                 }
2535                 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
2536                     (!strcmp(alg->cra_name, "sha224") ||
2537                      !strcmp(alg->cra_name, "hmac(sha224)"))) {
2538                         t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2539                         t_alg->algt.desc_hdr_template =
2540                                         DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2541                                         DESC_HDR_SEL0_MDEUA |
2542                                         DESC_HDR_MODE0_MDEU_SHA256;
2543                 }
2544                 break;
2545         default:
2546                 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2547                 return ERR_PTR(-EINVAL);
2548         }
2549
2550         alg->cra_module = THIS_MODULE;
2551         alg->cra_priority = TALITOS_CRA_PRIORITY;
2552         alg->cra_alignmask = 0;
2553         alg->cra_ctxsize = sizeof(struct talitos_ctx);
2554         alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
2555
2556         t_alg->dev = dev;
2557
2558         return t_alg;
2559 }
2560
2561 static int talitos_probe_irq(struct platform_device *ofdev)
2562 {
2563         struct device *dev = &ofdev->dev;
2564         struct device_node *np = ofdev->dev.of_node;
2565         struct talitos_private *priv = dev_get_drvdata(dev);
2566         int err;
2567
2568         priv->irq[0] = irq_of_parse_and_map(np, 0);
2569         if (!priv->irq[0]) {
2570                 dev_err(dev, "failed to map irq\n");
2571                 return -EINVAL;
2572         }
2573
2574         priv->irq[1] = irq_of_parse_and_map(np, 1);
2575
2576         /* get the primary irq line */
2577         if (!priv->irq[1]) {
2578                 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2579                                   dev_driver_string(dev), dev);
2580                 goto primary_out;
2581         }
2582
2583         err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2584                           dev_driver_string(dev), dev);
2585         if (err)
2586                 goto primary_out;
2587
2588         /* get the secondary irq line */
2589         err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2590                           dev_driver_string(dev), dev);
2591         if (err) {
2592                 dev_err(dev, "failed to request secondary irq\n");
2593                 irq_dispose_mapping(priv->irq[1]);
2594                 priv->irq[1] = 0;
2595         }
2596
2597         return err;
2598
2599 primary_out:
2600         if (err) {
2601                 dev_err(dev, "failed to request primary irq\n");
2602                 irq_dispose_mapping(priv->irq[0]);
2603                 priv->irq[0] = 0;
2604         }
2605
2606         return err;
2607 }
2608
2609 static int talitos_probe(struct platform_device *ofdev)
2610 {
2611         struct device *dev = &ofdev->dev;
2612         struct device_node *np = ofdev->dev.of_node;
2613         struct talitos_private *priv;
2614         const unsigned int *prop;
2615         int i, err;
2616
2617         priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2618         if (!priv)
2619                 return -ENOMEM;
2620
2621         dev_set_drvdata(dev, priv);
2622
2623         priv->ofdev = ofdev;
2624
2625         spin_lock_init(&priv->reg_lock);
2626
2627         err = talitos_probe_irq(ofdev);
2628         if (err)
2629                 goto err_out;
2630
2631         if (!priv->irq[1]) {
2632                 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2633                              (unsigned long)dev);
2634         } else {
2635                 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2636                              (unsigned long)dev);
2637                 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2638                              (unsigned long)dev);
2639         }
2640
2641         INIT_LIST_HEAD(&priv->alg_list);
2642
2643         priv->reg = of_iomap(np, 0);
2644         if (!priv->reg) {
2645                 dev_err(dev, "failed to of_iomap\n");
2646                 err = -ENOMEM;
2647                 goto err_out;
2648         }
2649
2650         /* get SEC version capabilities from device tree */
2651         prop = of_get_property(np, "fsl,num-channels", NULL);
2652         if (prop)
2653                 priv->num_channels = *prop;
2654
2655         prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2656         if (prop)
2657                 priv->chfifo_len = *prop;
2658
2659         prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2660         if (prop)
2661                 priv->exec_units = *prop;
2662
2663         prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2664         if (prop)
2665                 priv->desc_types = *prop;
2666
2667         if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2668             !priv->exec_units || !priv->desc_types) {
2669                 dev_err(dev, "invalid property data in device tree node\n");
2670                 err = -EINVAL;
2671                 goto err_out;
2672         }
2673
2674         if (of_device_is_compatible(np, "fsl,sec3.0"))
2675                 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2676
2677         if (of_device_is_compatible(np, "fsl,sec2.1"))
2678                 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
2679                                   TALITOS_FTR_SHA224_HWINIT |
2680                                   TALITOS_FTR_HMAC_OK;
2681
2682         priv->chan = kzalloc(sizeof(struct talitos_channel) *
2683                              priv->num_channels, GFP_KERNEL);
2684         if (!priv->chan) {
2685                 dev_err(dev, "failed to allocate channel management space\n");
2686                 err = -ENOMEM;
2687                 goto err_out;
2688         }
2689
2690         for (i = 0; i < priv->num_channels; i++) {
2691                 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2692                 if (!priv->irq[1] || !(i & 1))
2693                         priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2694         }
2695
2696         for (i = 0; i < priv->num_channels; i++) {
2697                 spin_lock_init(&priv->chan[i].head_lock);
2698                 spin_lock_init(&priv->chan[i].tail_lock);
2699         }
2700
2701         priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2702
2703         for (i = 0; i < priv->num_channels; i++) {
2704                 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2705                                              priv->fifo_len, GFP_KERNEL);
2706                 if (!priv->chan[i].fifo) {
2707                         dev_err(dev, "failed to allocate request fifo %d\n", i);
2708                         err = -ENOMEM;
2709                         goto err_out;
2710                 }
2711         }
2712
2713         for (i = 0; i < priv->num_channels; i++)
2714                 atomic_set(&priv->chan[i].submit_count,
2715                            -(priv->chfifo_len - 1));
2716
2717         dma_set_mask(dev, DMA_BIT_MASK(36));
2718
2719         /* reset and initialize the h/w */
2720         err = init_device(dev);
2721         if (err) {
2722                 dev_err(dev, "failed to initialize device\n");
2723                 goto err_out;
2724         }
2725
2726         /* register the RNG, if available */
2727         if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2728                 err = talitos_register_rng(dev);
2729                 if (err) {
2730                         dev_err(dev, "failed to register hwrng: %d\n", err);
2731                         goto err_out;
2732                 } else
2733                         dev_info(dev, "hwrng\n");
2734         }
2735
2736         /* register crypto algorithms the device supports */
2737         for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2738                 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2739                         struct talitos_crypto_alg *t_alg;
2740                         char *name = NULL;
2741
2742                         t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2743                         if (IS_ERR(t_alg)) {
2744                                 err = PTR_ERR(t_alg);
2745                                 if (err == -ENOTSUPP)
2746                                         continue;
2747                                 goto err_out;
2748                         }
2749
2750                         switch (t_alg->algt.type) {
2751                         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2752                         case CRYPTO_ALG_TYPE_AEAD:
2753                                 err = crypto_register_alg(
2754                                                 &t_alg->algt.alg.crypto);
2755                                 name = t_alg->algt.alg.crypto.cra_driver_name;
2756                                 break;
2757                         case CRYPTO_ALG_TYPE_AHASH:
2758                                 err = crypto_register_ahash(
2759                                                 &t_alg->algt.alg.hash);
2760                                 name =
2761                                  t_alg->algt.alg.hash.halg.base.cra_driver_name;
2762                                 break;
2763                         }
2764                         if (err) {
2765                                 dev_err(dev, "%s alg registration failed\n",
2766                                         name);
2767                                 kfree(t_alg);
2768                         } else
2769                                 list_add_tail(&t_alg->entry, &priv->alg_list);
2770                 }
2771         }
2772         if (!list_empty(&priv->alg_list))
2773                 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2774                          (char *)of_get_property(np, "compatible", NULL));
2775
2776         return 0;
2777
2778 err_out:
2779         talitos_remove(ofdev);
2780
2781         return err;
2782 }
2783
2784 static const struct of_device_id talitos_match[] = {
2785         {
2786                 .compatible = "fsl,sec2.0",
2787         },
2788         {},
2789 };
2790 MODULE_DEVICE_TABLE(of, talitos_match);
2791
2792 static struct platform_driver talitos_driver = {
2793         .driver = {
2794                 .name = "talitos",
2795                 .owner = THIS_MODULE,
2796                 .of_match_table = talitos_match,
2797         },
2798         .probe = talitos_probe,
2799         .remove = talitos_remove,
2800 };
2801
2802 module_platform_driver(talitos_driver);
2803
2804 MODULE_LICENSE("GPL");
2805 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2806 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");