drivers/dma/dw/core.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  * Copyright (C) 2013 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/mm.h>
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/pm_runtime.h>
  26
  27 #include "../dmaengine.h"
  28 #include "internal.h"
  29
  30 /*
  31  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  32  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  33  * of which use ARM any more).  See the "Databook" from Synopsys for
  34  * information beyond what licensees probably provide.
  35  *
  36  * The driver has been tested with the Atmel AT32AP7000, which does not
  37  * support descriptor writeback.
  38  */
  39
  40 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  41                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  42                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  43                 bool _is_slave = is_slave_direction(_dwc->direction);   \
  44                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
  45                         DW_DMA_MSIZE_16;                        \
  46                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
  47                         DW_DMA_MSIZE_16;                        \
  48                                                                 \
  49                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  50                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  51                  | DWC_CTLL_LLP_D_EN                            \
  52                  | DWC_CTLL_LLP_S_EN                            \
  53                  | DWC_CTLL_DMS(_dwc->dst_master)               \
  54                  | DWC_CTLL_SMS(_dwc->src_master));             \
  55         })
  56
  57 /*
  58  * Number of descriptors to allocate for each channel. This should be
  59  * made configurable somehow; preferably, the clients (at least the
  60  * ones using slave transfers) should be able to give us a hint.
  61  */
  62 #define NR_DESCS_PER_CHANNEL    64
  63
  64 /* The set of bus widths supported by the DMA controller */
  65 #define DW_DMA_BUSWIDTHS                          \
  66         BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED)       | \
  67         BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)          | \
  68         BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)         | \
  69         BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
  70
  71 /*----------------------------------------------------------------------*/
  72
  73 static struct device *chan2dev(struct dma_chan *chan)
  74 {
  75         return &chan->dev->device;
  76 }
  77
  78 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  79 {
  80         return to_dw_desc(dwc->active_list.next);
  81 }
  82
  83 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  84 {
  85         struct dw_desc *desc, *_desc;
  86         struct dw_desc *ret = NULL;
  87         unsigned int i = 0;
  88         unsigned long flags;
  89
  90         spin_lock_irqsave(&dwc->lock, flags);
  91         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
  92                 i++;
  93                 if (async_tx_test_ack(&desc->txd)) {
  94                         list_del(&desc->desc_node);
  95                         ret = desc;
  96                         break;
  97                 }
  98                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
  99         }
 100         spin_unlock_irqrestore(&dwc->lock, flags);
 101
 102         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 103
 104         return ret;
 105 }
 106
 107 /*
 108  * Move a descriptor, including any children, to the free list.
 109  * `desc' must not be on any lists.
 110  */
 111 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 112 {
 113         unsigned long flags;
 114
 115         if (desc) {
 116                 struct dw_desc *child;
 117
 118                 spin_lock_irqsave(&dwc->lock, flags);
 119                 list_for_each_entry(child, &desc->tx_list, desc_node)
 120                         dev_vdbg(chan2dev(&dwc->chan),
 121                                         "moving child desc %p to freelist\n",
 122                                         child);
 123                 list_splice_init(&desc->tx_list, &dwc->free_list);
 124                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 125                 list_add(&desc->desc_node, &dwc->free_list);
 126                 spin_unlock_irqrestore(&dwc->lock, flags);
 127         }
 128 }
 129
 130 static void dwc_initialize(struct dw_dma_chan *dwc)
 131 {
 132         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 133         struct dw_dma_slave *dws = dwc->chan.private;
 134         u32 cfghi = DWC_CFGH_FIFO_MODE;
 135         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 136
 137         if (dwc->initialized == true)
 138                 return;
 139
 140         if (dws) {
 141                 /*
 142                  * We need controller-specific data to set up slave
 143                  * transfers.
 144                  */
 145                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 146
 147                 cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
 148                 cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
 149         } else {
 150                 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
 151                 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
 152         }
 153
 154         channel_writel(dwc, CFG_LO, cfglo);
 155         channel_writel(dwc, CFG_HI, cfghi);
 156
 157         /* Enable interrupts */
 158         channel_set_bit(dw, MASK.XFER, dwc->mask);
 159         channel_set_bit(dw, MASK.BLOCK, dwc->mask);
 160         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 161
 162         dwc->initialized = true;
 163 }
 164
 165 /*----------------------------------------------------------------------*/
 166
 167 static inline unsigned int dwc_fast_ffs(unsigned long long v)
 168 {
 169         /*
 170          * We can be a lot more clever here, but this should take care
 171          * of the most common optimization.
 172          */
 173         if (!(v & 7))
 174                 return 3;
 175         else if (!(v & 3))
 176                 return 2;
 177         else if (!(v & 1))
 178                 return 1;
 179         return 0;
 180 }
 181
 182 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 183 {
 184         dev_err(chan2dev(&dwc->chan),
 185                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 186                 channel_readl(dwc, SAR),
 187                 channel_readl(dwc, DAR),
 188                 channel_readl(dwc, LLP),
 189                 channel_readl(dwc, CTL_HI),
 190                 channel_readl(dwc, CTL_LO));
 191 }
 192
 193 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 194 {
 195         channel_clear_bit(dw, CH_EN, dwc->mask);
 196         while (dma_readl(dw, CH_EN) & dwc->mask)
 197                 cpu_relax();
 198 }
 199
 200 /*----------------------------------------------------------------------*/
 201
 202 /* Perform single block transfer */
 203 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 204                                        struct dw_desc *desc)
 205 {
 206         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 207         u32             ctllo;
 208
 209         /*
 210          * Software emulation of LLP mode relies on interrupts to continue
 211          * multi block transfer.
 212          */
 213         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 214
 215         channel_writel(dwc, SAR, desc->lli.sar);
 216         channel_writel(dwc, DAR, desc->lli.dar);
 217         channel_writel(dwc, CTL_LO, ctllo);
 218         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 219         channel_set_bit(dw, CH_EN, dwc->mask);
 220
 221         /* Move pointer to next descriptor */
 222         dwc->tx_node_active = dwc->tx_node_active->next;
 223 }
 224
 225 /* Called with dwc->lock held and bh disabled */
 226 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 227 {
 228         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 229         unsigned long   was_soft_llp;
 230
 231         /* ASSERT:  channel is idle */
 232         if (dma_readl(dw, CH_EN) & dwc->mask) {
 233                 dev_err(chan2dev(&dwc->chan),
 234                         "%s: BUG: Attempted to start non-idle channel\n",
 235                         __func__);
 236                 dwc_dump_chan_regs(dwc);
 237
 238                 /* The tasklet will hopefully advance the queue... */
 239                 return;
 240         }
 241
 242         if (dwc->nollp) {
 243                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 244                                                 &dwc->flags);
 245                 if (was_soft_llp) {
 246                         dev_err(chan2dev(&dwc->chan),
 247                                 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
 248                         return;
 249                 }
 250
 251                 dwc_initialize(dwc);
 252
 253                 dwc->residue = first->total_len;
 254                 dwc->tx_node_active = &first->tx_list;
 255
 256                 /* Submit first block */
 257                 dwc_do_single_block(dwc, first);
 258
 259                 return;
 260         }
 261
 262         dwc_initialize(dwc);
 263
 264         channel_writel(dwc, LLP, first->txd.phys);
 265         channel_writel(dwc, CTL_LO,
 266                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 267         channel_writel(dwc, CTL_HI, 0);
 268         channel_set_bit(dw, CH_EN, dwc->mask);
 269 }
 270
 271 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
 272 {
 273         struct dw_desc *desc;
 274
 275         if (list_empty(&dwc->queue))
 276                 return;
 277
 278         list_move(dwc->queue.next, &dwc->active_list);
 279         desc = dwc_first_active(dwc);
 280         dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
 281         dwc_dostart(dwc, desc);
 282 }
 283
 284 /*----------------------------------------------------------------------*/
 285
 286 static void
 287 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 288                 bool callback_required)
 289 {
 290         dma_async_tx_callback           callback = NULL;
 291         void                            *param = NULL;
 292         struct dma_async_tx_descriptor  *txd = &desc->txd;
 293         struct dw_desc                  *child;
 294         unsigned long                   flags;
 295
 296         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 297
 298         spin_lock_irqsave(&dwc->lock, flags);
 299         dma_cookie_complete(txd);
 300         if (callback_required) {
 301                 callback = txd->callback;
 302                 param = txd->callback_param;
 303         }
 304
 305         /* async_tx_ack */
 306         list_for_each_entry(child, &desc->tx_list, desc_node)
 307                 async_tx_ack(&child->txd);
 308         async_tx_ack(&desc->txd);
 309
 310         list_splice_init(&desc->tx_list, &dwc->free_list);
 311         list_move(&desc->desc_node, &dwc->free_list);
 312
 313         dma_descriptor_unmap(txd);
 314         spin_unlock_irqrestore(&dwc->lock, flags);
 315
 316         if (callback)
 317                 callback(param);
 318 }
 319
 320 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 321 {
 322         struct dw_desc *desc, *_desc;
 323         LIST_HEAD(list);
 324         unsigned long flags;
 325
 326         spin_lock_irqsave(&dwc->lock, flags);
 327         if (dma_readl(dw, CH_EN) & dwc->mask) {
 328                 dev_err(chan2dev(&dwc->chan),
 329                         "BUG: XFER bit set, but channel not idle!\n");
 330
 331                 /* Try to continue after resetting the channel... */
 332                 dwc_chan_disable(dw, dwc);
 333         }
 334
 335         /*
 336          * Submit queued descriptors ASAP, i.e. before we go through
 337          * the completed ones.
 338          */
 339         list_splice_init(&dwc->active_list, &list);
 340         dwc_dostart_first_queued(dwc);
 341
 342         spin_unlock_irqrestore(&dwc->lock, flags);
 343
 344         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 345                 dwc_descriptor_complete(dwc, desc, true);
 346 }
 347
 348 /* Returns how many bytes were already received from source */
 349 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
 350 {
 351         u32 ctlhi = channel_readl(dwc, CTL_HI);
 352         u32 ctllo = channel_readl(dwc, CTL_LO);
 353
 354         return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
 355 }
 356
 357 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 358 {
 359         dma_addr_t llp;
 360         struct dw_desc *desc, *_desc;
 361         struct dw_desc *child;
 362         u32 status_xfer;
 363         unsigned long flags;
 364
 365         spin_lock_irqsave(&dwc->lock, flags);
 366         llp = channel_readl(dwc, LLP);
 367         status_xfer = dma_readl(dw, RAW.XFER);
 368
 369         if (status_xfer & dwc->mask) {
 370                 /* Everything we've submitted is done */
 371                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 372
 373                 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 374                         struct list_head *head, *active = dwc->tx_node_active;
 375
 376                         /*
 377                          * We are inside first active descriptor.
 378                          * Otherwise something is really wrong.
 379                          */
 380                         desc = dwc_first_active(dwc);
 381
 382                         head = &desc->tx_list;
 383                         if (active != head) {
 384                                 /* Update desc to reflect last sent one */
 385                                 if (active != head->next)
 386                                         desc = to_dw_desc(active->prev);
 387
 388                                 dwc->residue -= desc->len;
 389
 390                                 child = to_dw_desc(active);
 391
 392                                 /* Submit next block */
 393                                 dwc_do_single_block(dwc, child);
 394
 395                                 spin_unlock_irqrestore(&dwc->lock, flags);
 396                                 return;
 397                         }
 398
 399                         /* We are done here */
 400                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 401                 }
 402
 403                 dwc->residue = 0;
 404
 405                 spin_unlock_irqrestore(&dwc->lock, flags);
 406
 407                 dwc_complete_all(dw, dwc);
 408                 return;
 409         }
 410
 411         if (list_empty(&dwc->active_list)) {
 412                 dwc->residue = 0;
 413                 spin_unlock_irqrestore(&dwc->lock, flags);
 414                 return;
 415         }
 416
 417         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 418                 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
 419                 spin_unlock_irqrestore(&dwc->lock, flags);
 420                 return;
 421         }
 422
 423         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
 424
 425         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 426                 /* Initial residue value */
 427                 dwc->residue = desc->total_len;
 428
 429                 /* Check first descriptors addr */
 430                 if (desc->txd.phys == llp) {
 431                         spin_unlock_irqrestore(&dwc->lock, flags);
 432                         return;
 433                 }
 434
 435                 /* Check first descriptors llp */
 436                 if (desc->lli.llp == llp) {
 437                         /* This one is currently in progress */
 438                         dwc->residue -= dwc_get_sent(dwc);
 439                         spin_unlock_irqrestore(&dwc->lock, flags);
 440                         return;
 441                 }
 442
 443                 dwc->residue -= desc->len;
 444                 list_for_each_entry(child, &desc->tx_list, desc_node) {
 445                         if (child->lli.llp == llp) {
 446                                 /* Currently in progress */
 447                                 dwc->residue -= dwc_get_sent(dwc);
 448                                 spin_unlock_irqrestore(&dwc->lock, flags);
 449                                 return;
 450                         }
 451                         dwc->residue -= child->len;
 452                 }
 453
 454                 /*
 455                  * No descriptors so far seem to be in progress, i.e.
 456                  * this one must be done.
 457                  */
 458                 spin_unlock_irqrestore(&dwc->lock, flags);
 459                 dwc_descriptor_complete(dwc, desc, true);
 460                 spin_lock_irqsave(&dwc->lock, flags);
 461         }
 462
 463         dev_err(chan2dev(&dwc->chan),
 464                 "BUG: All descriptors done, but channel not idle!\n");
 465
 466         /* Try to continue after resetting the channel... */
 467         dwc_chan_disable(dw, dwc);
 468
 469         dwc_dostart_first_queued(dwc);
 470         spin_unlock_irqrestore(&dwc->lock, flags);
 471 }
 472
 473 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 474 {
 475         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 476                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 477 }
 478
 479 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 480 {
 481         struct dw_desc *bad_desc;
 482         struct dw_desc *child;
 483         unsigned long flags;
 484
 485         dwc_scan_descriptors(dw, dwc);
 486
 487         spin_lock_irqsave(&dwc->lock, flags);
 488
 489         /*
 490          * The descriptor currently at the head of the active list is
 491          * borked. Since we don't have any way to report errors, we'll
 492          * just have to scream loudly and try to carry on.
 493          */
 494         bad_desc = dwc_first_active(dwc);
 495         list_del_init(&bad_desc->desc_node);
 496         list_move(dwc->queue.next, dwc->active_list.prev);
 497
 498         /* Clear the error flag and try to restart the controller */
 499         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 500         if (!list_empty(&dwc->active_list))
 501                 dwc_dostart(dwc, dwc_first_active(dwc));
 502
 503         /*
 504          * WARN may seem harsh, but since this only happens
 505          * when someone submits a bad physical address in a
 506          * descriptor, we should consider ourselves lucky that the
 507          * controller flagged an error instead of scribbling over
 508          * random memory locations.
 509          */
 510         dev_WARN(chan2dev(&dwc->chan), true,
 511                         "Bad descriptor submitted for DMA!\n cookie: %d\n",
 512                         bad_desc->txd.cookie);
 513
 514         dwc_dump_lli(dwc, &bad_desc->lli);
 515         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 516                 dwc_dump_lli(dwc, &child->lli);
 517
 518         spin_unlock_irqrestore(&dwc->lock, flags);
 519
 520         /* Pretend the descriptor completed successfully */
 521         dwc_descriptor_complete(dwc, bad_desc, true);
 522 }
 523
 524 /* --------------------- Cyclic DMA API extensions -------------------- */
 525
 526 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 527 {
 528         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 529         return channel_readl(dwc, SAR);
 530 }
 531 EXPORT_SYMBOL(dw_dma_get_src_addr);
 532
 533 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 534 {
 535         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 536         return channel_readl(dwc, DAR);
 537 }
 538 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 539
 540 /* Called with dwc->lock held and all DMAC interrupts disabled */
 541 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 542                 u32 status_block, u32 status_err, u32 status_xfer)
 543 {
 544         unsigned long flags;
 545
 546         if (status_block & dwc->mask) {
 547                 void (*callback)(void *param);
 548                 void *callback_param;
 549
 550                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 551                                 channel_readl(dwc, LLP));
 552                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 553
 554                 callback = dwc->cdesc->period_callback;
 555                 callback_param = dwc->cdesc->period_callback_param;
 556
 557                 if (callback)
 558                         callback(callback_param);
 559         }
 560
 561         /*
 562          * Error and transfer complete are highly unlikely, and will most
 563          * likely be due to a configuration error by the user.
 564          */
 565         if (unlikely(status_err & dwc->mask) ||
 566                         unlikely(status_xfer & dwc->mask)) {
 567                 int i;
 568
 569                 dev_err(chan2dev(&dwc->chan),
 570                         "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
 571                         status_xfer ? "xfer" : "error");
 572
 573                 spin_lock_irqsave(&dwc->lock, flags);
 574
 575                 dwc_dump_chan_regs(dwc);
 576
 577                 dwc_chan_disable(dw, dwc);
 578
 579                 /* Make sure DMA does not restart by loading a new list */
 580                 channel_writel(dwc, LLP, 0);
 581                 channel_writel(dwc, CTL_LO, 0);
 582                 channel_writel(dwc, CTL_HI, 0);
 583
 584                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 585                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 586                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 587
 588                 for (i = 0; i < dwc->cdesc->periods; i++)
 589                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 590
 591                 spin_unlock_irqrestore(&dwc->lock, flags);
 592         }
 593 }
 594
 595 /* ------------------------------------------------------------------------- */
 596
 597 static void dw_dma_tasklet(unsigned long data)
 598 {
 599         struct dw_dma *dw = (struct dw_dma *)data;
 600         struct dw_dma_chan *dwc;
 601         u32 status_block;
 602         u32 status_xfer;
 603         u32 status_err;
 604         int i;
 605
 606         status_block = dma_readl(dw, RAW.BLOCK);
 607         status_xfer = dma_readl(dw, RAW.XFER);
 608         status_err = dma_readl(dw, RAW.ERROR);
 609
 610         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 611
 612         for (i = 0; i < dw->dma.chancnt; i++) {
 613                 dwc = &dw->chan[i];
 614                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 615                         dwc_handle_cyclic(dw, dwc, status_block, status_err,
 616                                         status_xfer);
 617                 else if (status_err & (1 << i))
 618                         dwc_handle_error(dw, dwc);
 619                 else if (status_xfer & (1 << i))
 620                         dwc_scan_descriptors(dw, dwc);
 621         }
 622
 623         /*
 624          * Re-enable interrupts.
 625          */
 626         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 627         channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 628         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 629 }
 630
 631 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 632 {
 633         struct dw_dma *dw = dev_id;
 634         u32 status;
 635
 636         /* Check if we have any interrupt from the DMAC which is not in use */
 637         if (!dw->in_use)
 638                 return IRQ_NONE;
 639
 640         status = dma_readl(dw, STATUS_INT);
 641         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
 642
 643         /* Check if we have any interrupt from the DMAC */
 644         if (!status)
 645                 return IRQ_NONE;
 646
 647         /*
 648          * Just disable the interrupts. We'll turn them back on in the
 649          * softirq handler.
 650          */
 651         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 652         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 653         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 654
 655         status = dma_readl(dw, STATUS_INT);
 656         if (status) {
 657                 dev_err(dw->dma.dev,
 658                         "BUG: Unexpected interrupts pending: 0x%x\n",
 659                         status);
 660
 661                 /* Try to recover */
 662                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 663                 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
 664                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 665                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 666                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 667         }
 668
 669         tasklet_schedule(&dw->tasklet);
 670
 671         return IRQ_HANDLED;
 672 }
 673
 674 /*----------------------------------------------------------------------*/
 675
 676 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 677 {
 678         struct dw_desc          *desc = txd_to_dw_desc(tx);
 679         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 680         dma_cookie_t            cookie;
 681         unsigned long           flags;
 682
 683         spin_lock_irqsave(&dwc->lock, flags);
 684         cookie = dma_cookie_assign(tx);
 685
 686         /*
 687          * REVISIT: We should attempt to chain as many descriptors as
 688          * possible, perhaps even appending to those already submitted
 689          * for DMA. But this is hard to do in a race-free manner.
 690          */
 691
 692         dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
 693         list_add_tail(&desc->desc_node, &dwc->queue);
 694
 695         spin_unlock_irqrestore(&dwc->lock, flags);
 696
 697         return cookie;
 698 }
 699
 700 static struct dma_async_tx_descriptor *
 701 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 702                 size_t len, unsigned long flags)
 703 {
 704         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 705         struct dw_dma           *dw = to_dw_dma(chan->device);
 706         struct dw_desc          *desc;
 707         struct dw_desc          *first;
 708         struct dw_desc          *prev;
 709         size_t                  xfer_count;
 710         size_t                  offset;
 711         unsigned int            src_width;
 712         unsigned int            dst_width;
 713         unsigned int            data_width;
 714         u32                     ctllo;
 715
 716         dev_vdbg(chan2dev(chan),
 717                         "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
 718                         &dest, &src, len, flags);
 719
 720         if (unlikely(!len)) {
 721                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 722                 return NULL;
 723         }
 724
 725         dwc->direction = DMA_MEM_TO_MEM;
 726
 727         data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
 728                            dw->data_width[dwc->dst_master]);
 729
 730         src_width = dst_width = min_t(unsigned int, data_width,
 731                                       dwc_fast_ffs(src | dest | len));
 732
 733         ctllo = DWC_DEFAULT_CTLLO(chan)
 734                         | DWC_CTLL_DST_WIDTH(dst_width)
 735                         | DWC_CTLL_SRC_WIDTH(src_width)
 736                         | DWC_CTLL_DST_INC
 737                         | DWC_CTLL_SRC_INC
 738                         | DWC_CTLL_FC_M2M;
 739         prev = first = NULL;
 740
 741         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 742                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 743                                            dwc->block_size);
 744
 745                 desc = dwc_desc_get(dwc);
 746                 if (!desc)
 747                         goto err_desc_get;
 748
 749                 desc->lli.sar = src + offset;
 750                 desc->lli.dar = dest + offset;
 751                 desc->lli.ctllo = ctllo;
 752                 desc->lli.ctlhi = xfer_count;
 753                 desc->len = xfer_count << src_width;
 754
 755                 if (!first) {
 756                         first = desc;
 757                 } else {
 758                         prev->lli.llp = desc->txd.phys;
 759                         list_add_tail(&desc->desc_node,
 760                                         &first->tx_list);
 761                 }
 762                 prev = desc;
 763         }
 764
 765         if (flags & DMA_PREP_INTERRUPT)
 766                 /* Trigger interrupt after last block */
 767                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 768
 769         prev->lli.llp = 0;
 770         first->txd.flags = flags;
 771         first->total_len = len;
 772
 773         return &first->txd;
 774
 775 err_desc_get:
 776         dwc_desc_put(dwc, first);
 777         return NULL;
 778 }
 779
 780 static struct dma_async_tx_descriptor *
 781 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 782                 unsigned int sg_len, enum dma_transfer_direction direction,
 783                 unsigned long flags, void *context)
 784 {
 785         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 786         struct dw_dma           *dw = to_dw_dma(chan->device);
 787         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 788         struct dw_desc          *prev;
 789         struct dw_desc          *first;
 790         u32                     ctllo;
 791         dma_addr_t              reg;
 792         unsigned int            reg_width;
 793         unsigned int            mem_width;
 794         unsigned int            data_width;
 795         unsigned int            i;
 796         struct scatterlist      *sg;
 797         size_t                  total_len = 0;
 798
 799         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 800
 801         if (unlikely(!is_slave_direction(direction) || !sg_len))
 802                 return NULL;
 803
 804         dwc->direction = direction;
 805
 806         prev = first = NULL;
 807
 808         switch (direction) {
 809         case DMA_MEM_TO_DEV:
 810                 reg_width = __ffs(sconfig->dst_addr_width);
 811                 reg = sconfig->dst_addr;
 812                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 813                                 | DWC_CTLL_DST_WIDTH(reg_width)
 814                                 | DWC_CTLL_DST_FIX
 815                                 | DWC_CTLL_SRC_INC);
 816
 817                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 818                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 819
 820                 data_width = dw->data_width[dwc->src_master];
 821
 822                 for_each_sg(sgl, sg, sg_len, i) {
 823                         struct dw_desc  *desc;
 824                         u32             len, dlen, mem;
 825
 826                         mem = sg_dma_address(sg);
 827                         len = sg_dma_len(sg);
 828
 829                         mem_width = min_t(unsigned int,
 830                                           data_width, dwc_fast_ffs(mem | len));
 831
 832 slave_sg_todev_fill_desc:
 833                         desc = dwc_desc_get(dwc);
 834                         if (!desc)
 835                                 goto err_desc_get;
 836
 837                         desc->lli.sar = mem;
 838                         desc->lli.dar = reg;
 839                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 840                         if ((len >> mem_width) > dwc->block_size) {
 841                                 dlen = dwc->block_size << mem_width;
 842                                 mem += dlen;
 843                                 len -= dlen;
 844                         } else {
 845                                 dlen = len;
 846                                 len = 0;
 847                         }
 848
 849                         desc->lli.ctlhi = dlen >> mem_width;
 850                         desc->len = dlen;
 851
 852                         if (!first) {
 853                                 first = desc;
 854                         } else {
 855                                 prev->lli.llp = desc->txd.phys;
 856                                 list_add_tail(&desc->desc_node,
 857                                                 &first->tx_list);
 858                         }
 859                         prev = desc;
 860                         total_len += dlen;
 861
 862                         if (len)
 863                                 goto slave_sg_todev_fill_desc;
 864                 }
 865                 break;
 866         case DMA_DEV_TO_MEM:
 867                 reg_width = __ffs(sconfig->src_addr_width);
 868                 reg = sconfig->src_addr;
 869                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 870                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 871                                 | DWC_CTLL_DST_INC
 872                                 | DWC_CTLL_SRC_FIX);
 873
 874                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 875                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 876
 877                 data_width = dw->data_width[dwc->dst_master];
 878
 879                 for_each_sg(sgl, sg, sg_len, i) {
 880                         struct dw_desc  *desc;
 881                         u32             len, dlen, mem;
 882
 883                         mem = sg_dma_address(sg);
 884                         len = sg_dma_len(sg);
 885
 886                         mem_width = min_t(unsigned int,
 887                                           data_width, dwc_fast_ffs(mem | len));
 888
 889 slave_sg_fromdev_fill_desc:
 890                         desc = dwc_desc_get(dwc);
 891                         if (!desc)
 892                                 goto err_desc_get;
 893
 894                         desc->lli.sar = reg;
 895                         desc->lli.dar = mem;
 896                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 897                         if ((len >> reg_width) > dwc->block_size) {
 898                                 dlen = dwc->block_size << reg_width;
 899                                 mem += dlen;
 900                                 len -= dlen;
 901                         } else {
 902                                 dlen = len;
 903                                 len = 0;
 904                         }
 905                         desc->lli.ctlhi = dlen >> reg_width;
 906                         desc->len = dlen;
 907
 908                         if (!first) {
 909                                 first = desc;
 910                         } else {
 911                                 prev->lli.llp = desc->txd.phys;
 912                                 list_add_tail(&desc->desc_node,
 913                                                 &first->tx_list);
 914                         }
 915                         prev = desc;
 916                         total_len += dlen;
 917
 918                         if (len)
 919                                 goto slave_sg_fromdev_fill_desc;
 920                 }
 921                 break;
 922         default:
 923                 return NULL;
 924         }
 925
 926         if (flags & DMA_PREP_INTERRUPT)
 927                 /* Trigger interrupt after last block */
 928                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 929
 930         prev->lli.llp = 0;
 931         first->total_len = total_len;
 932
 933         return &first->txd;
 934
 935 err_desc_get:
 936         dev_err(chan2dev(chan),
 937                 "not enough descriptors available. Direction %d\n", direction);
 938         dwc_desc_put(dwc, first);
 939         return NULL;
 940 }
 941
 942 bool dw_dma_filter(struct dma_chan *chan, void *param)
 943 {
 944         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 945         struct dw_dma_slave *dws = param;
 946
 947         if (!dws || dws->dma_dev != chan->device->dev)
 948                 return false;
 949
 950         /* We have to copy data since dws can be temporary storage */
 951
 952         dwc->src_id = dws->src_id;
 953         dwc->dst_id = dws->dst_id;
 954
 955         dwc->src_master = dws->src_master;
 956         dwc->dst_master = dws->dst_master;
 957
 958         return true;
 959 }
 960 EXPORT_SYMBOL_GPL(dw_dma_filter);
 961
 962 /*
 963  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 964  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 965  *
 966  * NOTE: burst size 2 is not supported by controller.
 967  *
 968  * This can be done by finding least significant bit set: n & (n - 1)
 969  */
 970 static inline void convert_burst(u32 *maxburst)
 971 {
 972         if (*maxburst > 1)
 973                 *maxburst = fls(*maxburst) - 2;
 974         else
 975                 *maxburst = 0;
 976 }
 977
 978 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 979 {
 980         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 981
 982         /* Check if chan will be configured for slave transfers */
 983         if (!is_slave_direction(sconfig->direction))
 984                 return -EINVAL;
 985
 986         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 987         dwc->direction = sconfig->direction;
 988
 989         convert_burst(&dwc->dma_sconfig.src_maxburst);
 990         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 991
 992         return 0;
 993 }
 994
 995 static int dwc_pause(struct dma_chan *chan)
 996 {
 997         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 998         unsigned long           flags;
 999         unsigned int            count = 20;     /* timeout iterations */
1000         u32                     cfglo;
1001
1002         spin_lock_irqsave(&dwc->lock, flags);
1003
1004         cfglo = channel_readl(dwc, CFG_LO);
1005         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
1006         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
1007                 udelay(2);
1008
1009         dwc->paused = true;
1010
1011         spin_unlock_irqrestore(&dwc->lock, flags);
1012
1013         return 0;
1014 }
1015
1016 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1017 {
1018         u32 cfglo = channel_readl(dwc, CFG_LO);
1019
1020         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1021
1022         dwc->paused = false;
1023 }
1024
1025 static int dwc_resume(struct dma_chan *chan)
1026 {
1027         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1028         unsigned long           flags;
1029
1030         if (!dwc->paused)
1031                 return 0;
1032
1033         spin_lock_irqsave(&dwc->lock, flags);
1034
1035         dwc_chan_resume(dwc);
1036
1037         spin_unlock_irqrestore(&dwc->lock, flags);
1038
1039         return 0;
1040 }
1041
1042 static int dwc_terminate_all(struct dma_chan *chan)
1043 {
1044         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1045         struct dw_dma           *dw = to_dw_dma(chan->device);
1046         struct dw_desc          *desc, *_desc;
1047         unsigned long           flags;
1048         LIST_HEAD(list);
1049
1050         spin_lock_irqsave(&dwc->lock, flags);
1051
1052         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1053
1054         dwc_chan_disable(dw, dwc);
1055
1056         dwc_chan_resume(dwc);
1057
1058         /* active_list entries will end up before queued entries */
1059         list_splice_init(&dwc->queue, &list);
1060         list_splice_init(&dwc->active_list, &list);
1061
1062         spin_unlock_irqrestore(&dwc->lock, flags);
1063
1064         /* Flush all pending and queued descriptors */
1065         list_for_each_entry_safe(desc, _desc, &list, desc_node)
1066                 dwc_descriptor_complete(dwc, desc, false);
1067
1068         return 0;
1069 }
1070
1071 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1072 {
1073         unsigned long flags;
1074         u32 residue;
1075
1076         spin_lock_irqsave(&dwc->lock, flags);
1077
1078         residue = dwc->residue;
1079         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1080                 residue -= dwc_get_sent(dwc);
1081
1082         spin_unlock_irqrestore(&dwc->lock, flags);
1083         return residue;
1084 }
1085
1086 static enum dma_status
1087 dwc_tx_status(struct dma_chan *chan,
1088               dma_cookie_t cookie,
1089               struct dma_tx_state *txstate)
1090 {
1091         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1092         enum dma_status         ret;
1093
1094         ret = dma_cookie_status(chan, cookie, txstate);
1095         if (ret == DMA_COMPLETE)
1096                 return ret;
1097
1098         dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1099
1100         ret = dma_cookie_status(chan, cookie, txstate);
1101         if (ret != DMA_COMPLETE)
1102                 dma_set_residue(txstate, dwc_get_residue(dwc));
1103
1104         if (dwc->paused && ret == DMA_IN_PROGRESS)
1105                 return DMA_PAUSED;
1106
1107         return ret;
1108 }
1109
1110 static void dwc_issue_pending(struct dma_chan *chan)
1111 {
1112         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1113         unsigned long           flags;
1114
1115         spin_lock_irqsave(&dwc->lock, flags);
1116         if (list_empty(&dwc->active_list))
1117                 dwc_dostart_first_queued(dwc);
1118         spin_unlock_irqrestore(&dwc->lock, flags);
1119 }
1120
1121 /*----------------------------------------------------------------------*/
1122
1123 static void dw_dma_off(struct dw_dma *dw)
1124 {
1125         int i;
1126
1127         dma_writel(dw, CFG, 0);
1128
1129         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1130         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1131         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1132         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1133         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1134
1135         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1136                 cpu_relax();
1137
1138         for (i = 0; i < dw->dma.chancnt; i++)
1139                 dw->chan[i].initialized = false;
1140 }
1141
1142 static void dw_dma_on(struct dw_dma *dw)
1143 {
1144         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1145 }
1146
1147 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1148 {
1149         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1150         struct dw_dma           *dw = to_dw_dma(chan->device);
1151         struct dw_desc          *desc;
1152         int                     i;
1153         unsigned long           flags;
1154
1155         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1156
1157         /* ASSERT:  channel is idle */
1158         if (dma_readl(dw, CH_EN) & dwc->mask) {
1159                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1160                 return -EIO;
1161         }
1162
1163         dma_cookie_init(chan);
1164
1165         /*
1166          * NOTE: some controllers may have additional features that we
1167          * need to initialize here, like "scatter-gather" (which
1168          * doesn't mean what you think it means), and status writeback.
1169          */
1170
1171         /* Enable controller here if needed */
1172         if (!dw->in_use)
1173                 dw_dma_on(dw);
1174         dw->in_use |= dwc->mask;
1175
1176         spin_lock_irqsave(&dwc->lock, flags);
1177         i = dwc->descs_allocated;
1178         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1179                 dma_addr_t phys;
1180
1181                 spin_unlock_irqrestore(&dwc->lock, flags);
1182
1183                 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1184                 if (!desc)
1185                         goto err_desc_alloc;
1186
1187                 memset(desc, 0, sizeof(struct dw_desc));
1188
1189                 INIT_LIST_HEAD(&desc->tx_list);
1190                 dma_async_tx_descriptor_init(&desc->txd, chan);
1191                 desc->txd.tx_submit = dwc_tx_submit;
1192                 desc->txd.flags = DMA_CTRL_ACK;
1193                 desc->txd.phys = phys;
1194
1195                 dwc_desc_put(dwc, desc);
1196
1197                 spin_lock_irqsave(&dwc->lock, flags);
1198                 i = ++dwc->descs_allocated;
1199         }
1200
1201         spin_unlock_irqrestore(&dwc->lock, flags);
1202
1203         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1204
1205         return i;
1206
1207 err_desc_alloc:
1208         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1209
1210         return i;
1211 }
1212
1213 static void dwc_free_chan_resources(struct dma_chan *chan)
1214 {
1215         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1216         struct dw_dma           *dw = to_dw_dma(chan->device);
1217         struct dw_desc          *desc, *_desc;
1218         unsigned long           flags;
1219         LIST_HEAD(list);
1220
1221         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1222                         dwc->descs_allocated);
1223
1224         /* ASSERT:  channel is idle */
1225         BUG_ON(!list_empty(&dwc->active_list));
1226         BUG_ON(!list_empty(&dwc->queue));
1227         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1228
1229         spin_lock_irqsave(&dwc->lock, flags);
1230         list_splice_init(&dwc->free_list, &list);
1231         dwc->descs_allocated = 0;
1232         dwc->initialized = false;
1233
1234         /* Disable interrupts */
1235         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1236         channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1237         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1238
1239         spin_unlock_irqrestore(&dwc->lock, flags);
1240
1241         /* Disable controller in case it was a last user */
1242         dw->in_use &= ~dwc->mask;
1243         if (!dw->in_use)
1244                 dw_dma_off(dw);
1245
1246         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1247                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1248                 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1249         }
1250
1251         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1252 }
1253
1254 /* --------------------- Cyclic DMA API extensions -------------------- */
1255
1256 /**
1257  * dw_dma_cyclic_start - start the cyclic DMA transfer
1258  * @chan: the DMA channel to start
1259  *
1260  * Must be called with soft interrupts disabled. Returns zero on success or
1261  * -errno on failure.
1262  */
1263 int dw_dma_cyclic_start(struct dma_chan *chan)
1264 {
1265         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1266         unsigned long           flags;
1267
1268         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1269                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1270                 return -ENODEV;
1271         }
1272
1273         spin_lock_irqsave(&dwc->lock, flags);
1274         dwc_dostart(dwc, dwc->cdesc->desc[0]);
1275         spin_unlock_irqrestore(&dwc->lock, flags);
1276
1277         return 0;
1278 }
1279 EXPORT_SYMBOL(dw_dma_cyclic_start);
1280
1281 /**
1282  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1283  * @chan: the DMA channel to stop
1284  *
1285  * Must be called with soft interrupts disabled.
1286  */
1287 void dw_dma_cyclic_stop(struct dma_chan *chan)
1288 {
1289         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1290         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1291         unsigned long           flags;
1292
1293         spin_lock_irqsave(&dwc->lock, flags);
1294
1295         dwc_chan_disable(dw, dwc);
1296
1297         spin_unlock_irqrestore(&dwc->lock, flags);
1298 }
1299 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1300
1301 /**
1302  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1303  * @chan: the DMA channel to prepare
1304  * @buf_addr: physical DMA address where the buffer starts
1305  * @buf_len: total number of bytes for the entire buffer
1306  * @period_len: number of bytes for each period
1307  * @direction: transfer direction, to or from device
1308  *
1309  * Must be called before trying to start the transfer. Returns a valid struct
1310  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1311  */
1312 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1313                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1314                 enum dma_transfer_direction direction)
1315 {
1316         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1317         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1318         struct dw_cyclic_desc           *cdesc;
1319         struct dw_cyclic_desc           *retval = NULL;
1320         struct dw_desc                  *desc;
1321         struct dw_desc                  *last = NULL;
1322         unsigned long                   was_cyclic;
1323         unsigned int                    reg_width;
1324         unsigned int                    periods;
1325         unsigned int                    i;
1326         unsigned long                   flags;
1327
1328         spin_lock_irqsave(&dwc->lock, flags);
1329         if (dwc->nollp) {
1330                 spin_unlock_irqrestore(&dwc->lock, flags);
1331                 dev_dbg(chan2dev(&dwc->chan),
1332                                 "channel doesn't support LLP transfers\n");
1333                 return ERR_PTR(-EINVAL);
1334         }
1335
1336         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1337                 spin_unlock_irqrestore(&dwc->lock, flags);
1338                 dev_dbg(chan2dev(&dwc->chan),
1339                                 "queue and/or active list are not empty\n");
1340                 return ERR_PTR(-EBUSY);
1341         }
1342
1343         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1344         spin_unlock_irqrestore(&dwc->lock, flags);
1345         if (was_cyclic) {
1346                 dev_dbg(chan2dev(&dwc->chan),
1347                                 "channel already prepared for cyclic DMA\n");
1348                 return ERR_PTR(-EBUSY);
1349         }
1350
1351         retval = ERR_PTR(-EINVAL);
1352
1353         if (unlikely(!is_slave_direction(direction)))
1354                 goto out_err;
1355
1356         dwc->direction = direction;
1357
1358         if (direction == DMA_MEM_TO_DEV)
1359                 reg_width = __ffs(sconfig->dst_addr_width);
1360         else
1361                 reg_width = __ffs(sconfig->src_addr_width);
1362
1363         periods = buf_len / period_len;
1364
1365         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1366         if (period_len > (dwc->block_size << reg_width))
1367                 goto out_err;
1368         if (unlikely(period_len & ((1 << reg_width) - 1)))
1369                 goto out_err;
1370         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1371                 goto out_err;
1372
1373         retval = ERR_PTR(-ENOMEM);
1374
1375         if (periods > NR_DESCS_PER_CHANNEL)
1376                 goto out_err;
1377
1378         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1379         if (!cdesc)
1380                 goto out_err;
1381
1382         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1383         if (!cdesc->desc)
1384                 goto out_err_alloc;
1385
1386         for (i = 0; i < periods; i++) {
1387                 desc = dwc_desc_get(dwc);
1388                 if (!desc)
1389                         goto out_err_desc_get;
1390
1391                 switch (direction) {
1392                 case DMA_MEM_TO_DEV:
1393                         desc->lli.dar = sconfig->dst_addr;
1394                         desc->lli.sar = buf_addr + (period_len * i);
1395                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1396                                         | DWC_CTLL_DST_WIDTH(reg_width)
1397                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1398                                         | DWC_CTLL_DST_FIX
1399                                         | DWC_CTLL_SRC_INC
1400                                         | DWC_CTLL_INT_EN);
1401
1402                         desc->lli.ctllo |= sconfig->device_fc ?
1403                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1404                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1405
1406                         break;
1407                 case DMA_DEV_TO_MEM:
1408                         desc->lli.dar = buf_addr + (period_len * i);
1409                         desc->lli.sar = sconfig->src_addr;
1410                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1411                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1412                                         | DWC_CTLL_DST_WIDTH(reg_width)
1413                                         | DWC_CTLL_DST_INC
1414                                         | DWC_CTLL_SRC_FIX
1415                                         | DWC_CTLL_INT_EN);
1416
1417                         desc->lli.ctllo |= sconfig->device_fc ?
1418                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1419                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1420
1421                         break;
1422                 default:
1423                         break;
1424                 }
1425
1426                 desc->lli.ctlhi = (period_len >> reg_width);
1427                 cdesc->desc[i] = desc;
1428
1429                 if (last)
1430                         last->lli.llp = desc->txd.phys;
1431
1432                 last = desc;
1433         }
1434
1435         /* Let's make a cyclic list */
1436         last->lli.llp = cdesc->desc[0]->txd.phys;
1437
1438         dev_dbg(chan2dev(&dwc->chan),
1439                         "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1440                         &buf_addr, buf_len, period_len, periods);
1441
1442         cdesc->periods = periods;
1443         dwc->cdesc = cdesc;
1444
1445         return cdesc;
1446
1447 out_err_desc_get:
1448         while (i--)
1449                 dwc_desc_put(dwc, cdesc->desc[i]);
1450 out_err_alloc:
1451         kfree(cdesc);
1452 out_err:
1453         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1454         return (struct dw_cyclic_desc *)retval;
1455 }
1456 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1457
1458 /**
1459  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1460  * @chan: the DMA channel to free
1461  */
1462 void dw_dma_cyclic_free(struct dma_chan *chan)
1463 {
1464         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1465         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1466         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1467         int                     i;
1468         unsigned long           flags;
1469
1470         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1471
1472         if (!cdesc)
1473                 return;
1474
1475         spin_lock_irqsave(&dwc->lock, flags);
1476
1477         dwc_chan_disable(dw, dwc);
1478
1479         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1480         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1481         dma_writel(dw, CLEAR.XFER, dwc->mask);
1482
1483         spin_unlock_irqrestore(&dwc->lock, flags);
1484
1485         for (i = 0; i < cdesc->periods; i++)
1486                 dwc_desc_put(dwc, cdesc->desc[i]);
1487
1488         kfree(cdesc->desc);
1489         kfree(cdesc);
1490
1491         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1492 }
1493 EXPORT_SYMBOL(dw_dma_cyclic_free);
1494
1495 /*----------------------------------------------------------------------*/
1496
1497 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1498 {
1499         struct dw_dma           *dw;
1500         bool                    autocfg = false;
1501         unsigned int            dw_params;
1502         unsigned int            max_blk_size = 0;
1503         int                     err;
1504         int                     i;
1505
1506         dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1507         if (!dw)
1508                 return -ENOMEM;
1509
1510         dw->regs = chip->regs;
1511         chip->dw = dw;
1512
1513         pm_runtime_get_sync(chip->dev);
1514
1515         if (!pdata) {
1516                 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1517                 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1518
1519                 autocfg = dw_params >> DW_PARAMS_EN & 1;
1520                 if (!autocfg) {
1521                         err = -EINVAL;
1522                         goto err_pdata;
1523                 }
1524
1525                 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1526                 if (!pdata) {
1527                         err = -ENOMEM;
1528                         goto err_pdata;
1529                 }
1530
1531                 /* Get hardware configuration parameters */
1532                 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1533                 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1534                 for (i = 0; i < pdata->nr_masters; i++) {
1535                         pdata->data_width[i] =
1536                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1537                 }
1538                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1539
1540                 /* Fill platform data with the default values */
1541                 pdata->is_private = true;
1542                 pdata->is_memcpy = true;
1543                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1544                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1545         } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1546                 err = -EINVAL;
1547                 goto err_pdata;
1548         }
1549
1550         dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1551                                 GFP_KERNEL);
1552         if (!dw->chan) {
1553                 err = -ENOMEM;
1554                 goto err_pdata;
1555         }
1556
1557         /* Get hardware configuration parameters */
1558         dw->nr_masters = pdata->nr_masters;
1559         for (i = 0; i < dw->nr_masters; i++)
1560                 dw->data_width[i] = pdata->data_width[i];
1561
1562         /* Calculate all channel mask before DMA setup */
1563         dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1564
1565         /* Force dma off, just in case */
1566         dw_dma_off(dw);
1567
1568         /* Create a pool of consistent memory blocks for hardware descriptors */
1569         dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1570                                          sizeof(struct dw_desc), 4, 0);
1571         if (!dw->desc_pool) {
1572                 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1573                 err = -ENOMEM;
1574                 goto err_pdata;
1575         }
1576
1577         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1578
1579         err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1580                           "dw_dmac", dw);
1581         if (err)
1582                 goto err_pdata;
1583
1584         INIT_LIST_HEAD(&dw->dma.channels);
1585         for (i = 0; i < pdata->nr_channels; i++) {
1586                 struct dw_dma_chan      *dwc = &dw->chan[i];
1587
1588                 dwc->chan.device = &dw->dma;
1589                 dma_cookie_init(&dwc->chan);
1590                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1591                         list_add_tail(&dwc->chan.device_node,
1592                                         &dw->dma.channels);
1593                 else
1594                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1595
1596                 /* 7 is highest priority & 0 is lowest. */
1597                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1598                         dwc->priority = pdata->nr_channels - i - 1;
1599                 else
1600                         dwc->priority = i;
1601
1602                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1603                 spin_lock_init(&dwc->lock);
1604                 dwc->mask = 1 << i;
1605
1606                 INIT_LIST_HEAD(&dwc->active_list);
1607                 INIT_LIST_HEAD(&dwc->queue);
1608                 INIT_LIST_HEAD(&dwc->free_list);
1609
1610                 channel_clear_bit(dw, CH_EN, dwc->mask);
1611
1612                 dwc->direction = DMA_TRANS_NONE;
1613
1614                 /* Hardware configuration */
1615                 if (autocfg) {
1616                         unsigned int dwc_params;
1617                         unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1618                         void __iomem *addr = chip->regs + r * sizeof(u32);
1619
1620                         dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1621
1622                         dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1623                                            dwc_params);
1624
1625                         /*
1626                          * Decode maximum block size for given channel. The
1627                          * stored 4 bit value represents blocks from 0x00 for 3
1628                          * up to 0x0a for 4095.
1629                          */
1630                         dwc->block_size =
1631                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1632                         dwc->nollp =
1633                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1634                 } else {
1635                         dwc->block_size = pdata->block_size;
1636
1637                         /* Check if channel supports multi block transfer */
1638                         channel_writel(dwc, LLP, 0xfffffffc);
1639                         dwc->nollp =
1640                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1641                         channel_writel(dwc, LLP, 0);
1642                 }
1643         }
1644
1645         /* Clear all interrupts on all channels. */
1646         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1647         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1648         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1649         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1650         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1651
1652         /* Set capabilities */
1653         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1654         if (pdata->is_private)
1655                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1656         if (pdata->is_memcpy)
1657                 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1658
1659         dw->dma.dev = chip->dev;
1660         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1661         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1662
1663         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1664         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1665
1666         dw->dma.device_config = dwc_config;
1667         dw->dma.device_pause = dwc_pause;
1668         dw->dma.device_resume = dwc_resume;
1669         dw->dma.device_terminate_all = dwc_terminate_all;
1670
1671         dw->dma.device_tx_status = dwc_tx_status;
1672         dw->dma.device_issue_pending = dwc_issue_pending;
1673
1674         /* DMA capabilities */
1675         dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1676         dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1677         dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1678                              BIT(DMA_MEM_TO_MEM);
1679         dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1680
1681         err = dma_async_device_register(&dw->dma);
1682         if (err)
1683                 goto err_dma_register;
1684
1685         dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1686                  pdata->nr_channels);
1687
1688         pm_runtime_put_sync_suspend(chip->dev);
1689
1690         return 0;
1691
1692 err_dma_register:
1693         free_irq(chip->irq, dw);
1694 err_pdata:
1695         pm_runtime_put_sync_suspend(chip->dev);
1696         return err;
1697 }
1698 EXPORT_SYMBOL_GPL(dw_dma_probe);
1699
1700 int dw_dma_remove(struct dw_dma_chip *chip)
1701 {
1702         struct dw_dma           *dw = chip->dw;
1703         struct dw_dma_chan      *dwc, *_dwc;
1704
1705         pm_runtime_get_sync(chip->dev);
1706
1707         dw_dma_off(dw);
1708         dma_async_device_unregister(&dw->dma);
1709
1710         free_irq(chip->irq, dw);
1711         tasklet_kill(&dw->tasklet);
1712
1713         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1714                         chan.device_node) {
1715                 list_del(&dwc->chan.device_node);
1716                 channel_clear_bit(dw, CH_EN, dwc->mask);
1717         }
1718
1719         pm_runtime_put_sync_suspend(chip->dev);
1720         return 0;
1721 }
1722 EXPORT_SYMBOL_GPL(dw_dma_remove);
1723
1724 int dw_dma_disable(struct dw_dma_chip *chip)
1725 {
1726         struct dw_dma *dw = chip->dw;
1727
1728         dw_dma_off(dw);
1729         return 0;
1730 }
1731 EXPORT_SYMBOL_GPL(dw_dma_disable);
1732
1733 int dw_dma_enable(struct dw_dma_chip *chip)
1734 {
1735         struct dw_dma *dw = chip->dw;
1736
1737         dw_dma_on(dw);
1738         return 0;
1739 }
1740 EXPORT_SYMBOL_GPL(dw_dma_enable);
1741
1742 MODULE_LICENSE("GPL v2");
1743 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1744 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1745 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");