drivers/dma/edma.c

   1 /*
   2  * TI EDMA DMA engine driver
   3  *
   4  * Copyright 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/list.h>
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26
  27 #include <linux/platform_data/edma.h>
  28
  29 #include "dmaengine.h"
  30 #include "virt-dma.h"
  31
  32 /*
  33  * This will go away when the private EDMA API is folded
  34  * into this driver and the platform device(s) are
  35  * instantiated in the arch code. We can only get away
  36  * with this simplification because DA8XX may not be built
  37  * in the same kernel image with other DaVinci parts. This
  38  * avoids having to sprinkle dmaengine driver platform devices
  39  * and data throughout all the existing board files.
  40  */
  41 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
  42 #define EDMA_CTLRS      2
  43 #define EDMA_CHANS      32
  44 #else
  45 #define EDMA_CTLRS      1
  46 #define EDMA_CHANS      64
  47 #endif /* CONFIG_ARCH_DAVINCI_DA8XX */
  48
  49 /* Max of 16 segments per channel to conserve PaRAM slots */
  50 #define MAX_NR_SG               16
  51 #define EDMA_MAX_SLOTS          MAX_NR_SG
  52 #define EDMA_DESCRIPTORS        16
  53
  54 struct edma_desc {
  55         struct virt_dma_desc            vdesc;
  56         struct list_head                node;
  57         int                             absync;
  58         int                             pset_nr;
  59         int                             processed;
  60         struct edmacc_param             pset[0];
  61 };
  62
  63 struct edma_cc;
  64
  65 struct edma_chan {
  66         struct virt_dma_chan            vchan;
  67         struct list_head                node;
  68         struct edma_desc                *edesc;
  69         struct edma_cc                  *ecc;
  70         int                             ch_num;
  71         bool                            alloced;
  72         int                             slot[EDMA_MAX_SLOTS];
  73         int                             missed;
  74         struct dma_slave_config         cfg;
  75 };
  76
  77 struct edma_cc {
  78         int                             ctlr;
  79         struct dma_device               dma_slave;
  80         struct edma_chan                slave_chans[EDMA_CHANS];
  81         int                             num_slave_chans;
  82         int                             dummy_slot;
  83 };
  84
  85 static inline struct edma_cc *to_edma_cc(struct dma_device *d)
  86 {
  87         return container_of(d, struct edma_cc, dma_slave);
  88 }
  89
  90 static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
  91 {
  92         return container_of(c, struct edma_chan, vchan.chan);
  93 }
  94
  95 static inline struct edma_desc
  96 *to_edma_desc(struct dma_async_tx_descriptor *tx)
  97 {
  98         return container_of(tx, struct edma_desc, vdesc.tx);
  99 }
 100
 101 static void edma_desc_free(struct virt_dma_desc *vdesc)
 102 {
 103         kfree(container_of(vdesc, struct edma_desc, vdesc));
 104 }
 105
 106 /* Dispatch a queued descriptor to the controller (caller holds lock) */
 107 static void edma_execute(struct edma_chan *echan)
 108 {
 109         struct virt_dma_desc *vdesc;
 110         struct edma_desc *edesc;
 111         struct device *dev = echan->vchan.chan.device->dev;
 112         int i, j, left, nslots;
 113
 114         /* If either we processed all psets or we're still not started */
 115         if (!echan->edesc ||
 116             echan->edesc->pset_nr == echan->edesc->processed) {
 117                 /* Get next vdesc */
 118                 vdesc = vchan_next_desc(&echan->vchan);
 119                 if (!vdesc) {
 120                         echan->edesc = NULL;
 121                         return;
 122                 }
 123                 list_del(&vdesc->node);
 124                 echan->edesc = to_edma_desc(&vdesc->tx);
 125         }
 126
 127         edesc = echan->edesc;
 128
 129         /* Find out how many left */
 130         left = edesc->pset_nr - edesc->processed;
 131         nslots = min(MAX_NR_SG, left);
 132
 133         /* Write descriptor PaRAM set(s) */
 134         for (i = 0; i < nslots; i++) {
 135                 j = i + edesc->processed;
 136                 edma_write_slot(echan->slot[i], &edesc->pset[j]);
 137                 dev_dbg(echan->vchan.chan.device->dev,
 138                         "\n pset[%d]:\n"
 139                         "  chnum\t%d\n"
 140                         "  slot\t%d\n"
 141                         "  opt\t%08x\n"
 142                         "  src\t%08x\n"
 143                         "  dst\t%08x\n"
 144                         "  abcnt\t%08x\n"
 145                         "  ccnt\t%08x\n"
 146                         "  bidx\t%08x\n"
 147                         "  cidx\t%08x\n"
 148                         "  lkrld\t%08x\n",
 149                         j, echan->ch_num, echan->slot[i],
 150                         edesc->pset[j].opt,
 151                         edesc->pset[j].src,
 152                         edesc->pset[j].dst,
 153                         edesc->pset[j].a_b_cnt,
 154                         edesc->pset[j].ccnt,
 155                         edesc->pset[j].src_dst_bidx,
 156                         edesc->pset[j].src_dst_cidx,
 157                         edesc->pset[j].link_bcntrld);
 158                 /* Link to the previous slot if not the last set */
 159                 if (i != (nslots - 1))
 160                         edma_link(echan->slot[i], echan->slot[i+1]);
 161         }
 162
 163         edesc->processed += nslots;
 164
 165         /*
 166          * If this is either the last set in a set of SG-list transactions
 167          * then setup a link to the dummy slot, this results in all future
 168          * events being absorbed and that's OK because we're done
 169          */
 170         if (edesc->processed == edesc->pset_nr)
 171                 edma_link(echan->slot[nslots-1], echan->ecc->dummy_slot);
 172
 173         edma_resume(echan->ch_num);
 174
 175         if (edesc->processed <= MAX_NR_SG) {
 176                 dev_dbg(dev, "first transfer starting %d\n", echan->ch_num);
 177                 edma_start(echan->ch_num);
 178         }
 179
 180         /*
 181          * This happens due to setup times between intermediate transfers
 182          * in long SG lists which have to be broken up into transfers of
 183          * MAX_NR_SG
 184          */
 185         if (echan->missed) {
 186                 dev_dbg(dev, "missed event in execute detected\n");
 187                 edma_clean_channel(echan->ch_num);
 188                 edma_stop(echan->ch_num);
 189                 edma_start(echan->ch_num);
 190                 edma_trigger_channel(echan->ch_num);
 191                 echan->missed = 0;
 192         }
 193 }
 194
 195 static int edma_terminate_all(struct edma_chan *echan)
 196 {
 197         unsigned long flags;
 198         LIST_HEAD(head);
 199
 200         spin_lock_irqsave(&echan->vchan.lock, flags);
 201
 202         /*
 203          * Stop DMA activity: we assume the callback will not be called
 204          * after edma_dma() returns (even if it does, it will see
 205          * echan->edesc is NULL and exit.)
 206          */
 207         if (echan->edesc) {
 208                 echan->edesc = NULL;
 209                 edma_stop(echan->ch_num);
 210         }
 211
 212         vchan_get_all_descriptors(&echan->vchan, &head);
 213         spin_unlock_irqrestore(&echan->vchan.lock, flags);
 214         vchan_dma_desc_free_list(&echan->vchan, &head);
 215
 216         return 0;
 217 }
 218
 219 static int edma_slave_config(struct edma_chan *echan,
 220         struct dma_slave_config *cfg)
 221 {
 222         if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
 223             cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
 224                 return -EINVAL;
 225
 226         memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
 227
 228         return 0;
 229 }
 230
 231 static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 232                         unsigned long arg)
 233 {
 234         int ret = 0;
 235         struct dma_slave_config *config;
 236         struct edma_chan *echan = to_edma_chan(chan);
 237
 238         switch (cmd) {
 239         case DMA_TERMINATE_ALL:
 240                 edma_terminate_all(echan);
 241                 break;
 242         case DMA_SLAVE_CONFIG:
 243                 config = (struct dma_slave_config *)arg;
 244                 ret = edma_slave_config(echan, config);
 245                 break;
 246         default:
 247                 ret = -ENOSYS;
 248         }
 249
 250         return ret;
 251 }
 252
 253 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
 254         struct dma_chan *chan, struct scatterlist *sgl,
 255         unsigned int sg_len, enum dma_transfer_direction direction,
 256         unsigned long tx_flags, void *context)
 257 {
 258         struct edma_chan *echan = to_edma_chan(chan);
 259         struct device *dev = chan->device->dev;
 260         struct edma_desc *edesc;
 261         dma_addr_t dev_addr;
 262         enum dma_slave_buswidth dev_width;
 263         u32 burst;
 264         struct scatterlist *sg;
 265         int acnt, bcnt, ccnt, src, dst, cidx;
 266         int src_bidx, dst_bidx, src_cidx, dst_cidx;
 267         int i, nslots;
 268
 269         if (unlikely(!echan || !sgl || !sg_len))
 270                 return NULL;
 271
 272         if (direction == DMA_DEV_TO_MEM) {
 273                 dev_addr = echan->cfg.src_addr;
 274                 dev_width = echan->cfg.src_addr_width;
 275                 burst = echan->cfg.src_maxburst;
 276         } else if (direction == DMA_MEM_TO_DEV) {
 277                 dev_addr = echan->cfg.dst_addr;
 278                 dev_width = echan->cfg.dst_addr_width;
 279                 burst = echan->cfg.dst_maxburst;
 280         } else {
 281                 dev_err(dev, "%s: bad direction?\n", __func__);
 282                 return NULL;
 283         }
 284
 285         if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
 286                 dev_err(dev, "Undefined slave buswidth\n");
 287                 return NULL;
 288         }
 289
 290         edesc = kzalloc(sizeof(*edesc) + sg_len *
 291                 sizeof(edesc->pset[0]), GFP_ATOMIC);
 292         if (!edesc) {
 293                 dev_dbg(dev, "Failed to allocate a descriptor\n");
 294                 return NULL;
 295         }
 296
 297         edesc->pset_nr = sg_len;
 298
 299         /* Allocate a PaRAM slot, if needed */
 300         nslots = min_t(unsigned, MAX_NR_SG, sg_len);
 301
 302         for (i = 0; i < nslots; i++) {
 303                 if (echan->slot[i] < 0) {
 304                         echan->slot[i] =
 305                                 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
 306                                                 EDMA_SLOT_ANY);
 307                         if (echan->slot[i] < 0) {
 308                                 dev_err(dev, "Failed to allocate slot\n");
 309                                 kfree(edesc);
 310                                 return NULL;
 311                         }
 312                 }
 313         }
 314
 315         /* Configure PaRAM sets for each SG */
 316         for_each_sg(sgl, sg, sg_len, i) {
 317
 318                 acnt = dev_width;
 319
 320                 /*
 321                  * If the maxburst is equal to the fifo width, use
 322                  * A-synced transfers. This allows for large contiguous
 323                  * buffer transfers using only one PaRAM set.
 324                  */
 325                 if (burst == 1) {
 326                         edesc->absync = false;
 327                         ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
 328                         bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
 329                         if (bcnt)
 330                                 ccnt++;
 331                         else
 332                                 bcnt = SZ_64K - 1;
 333                         cidx = acnt;
 334                 /*
 335                  * If maxburst is greater than the fifo address_width,
 336                  * use AB-synced transfers where A count is the fifo
 337                  * address_width and B count is the maxburst. In this
 338                  * case, we are limited to transfers of C count frames
 339                  * of (address_width * maxburst) where C count is limited
 340                  * to SZ_64K-1. This places an upper bound on the length
 341                  * of an SG segment that can be handled.
 342                  */
 343                 } else {
 344                         edesc->absync = true;
 345                         bcnt = burst;
 346                         ccnt = sg_dma_len(sg) / (acnt * bcnt);
 347                         if (ccnt > (SZ_64K - 1)) {
 348                                 dev_err(dev, "Exceeded max SG segment size\n");
 349                                 return NULL;
 350                         }
 351                         cidx = acnt * bcnt;
 352                 }
 353
 354                 if (direction == DMA_MEM_TO_DEV) {
 355                         src = sg_dma_address(sg);
 356                         dst = dev_addr;
 357                         src_bidx = acnt;
 358                         src_cidx = cidx;
 359                         dst_bidx = 0;
 360                         dst_cidx = 0;
 361                 } else {
 362                         src = dev_addr;
 363                         dst = sg_dma_address(sg);
 364                         src_bidx = 0;
 365                         src_cidx = 0;
 366                         dst_bidx = acnt;
 367                         dst_cidx = cidx;
 368                 }
 369
 370                 edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
 371                 /* Configure A or AB synchronized transfers */
 372                 if (edesc->absync)
 373                         edesc->pset[i].opt |= SYNCDIM;
 374
 375                 /* If this is the last in a current SG set of transactions,
 376                    enable interrupts so that next set is processed */
 377                 if (!((i+1) % MAX_NR_SG))
 378                         edesc->pset[i].opt |= TCINTEN;
 379
 380                 /* If this is the last set, enable completion interrupt flag */
 381                 if (i == sg_len - 1)
 382                         edesc->pset[i].opt |= TCINTEN;
 383
 384                 edesc->pset[i].src = src;
 385                 edesc->pset[i].dst = dst;
 386
 387                 edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
 388                 edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
 389
 390                 edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
 391                 edesc->pset[i].ccnt = ccnt;
 392                 edesc->pset[i].link_bcntrld = 0xffffffff;
 393
 394         }
 395
 396         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
 397 }
 398
 399 static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
 400 {
 401         struct edma_chan *echan = data;
 402         struct device *dev = echan->vchan.chan.device->dev;
 403         struct edma_desc *edesc;
 404         unsigned long flags;
 405         struct edmacc_param p;
 406
 407         /* Pause the channel */
 408         edma_pause(echan->ch_num);
 409
 410         switch (ch_status) {
 411         case DMA_COMPLETE:
 412                 spin_lock_irqsave(&echan->vchan.lock, flags);
 413
 414                 edesc = echan->edesc;
 415                 if (edesc) {
 416                         if (edesc->processed == edesc->pset_nr) {
 417                                 dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
 418                                 edma_stop(echan->ch_num);
 419                                 vchan_cookie_complete(&edesc->vdesc);
 420                         } else {
 421                                 dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
 422                         }
 423
 424                         edma_execute(echan);
 425                 }
 426
 427                 spin_unlock_irqrestore(&echan->vchan.lock, flags);
 428
 429                 break;
 430         case DMA_CC_ERROR:
 431                 spin_lock_irqsave(&echan->vchan.lock, flags);
 432
 433                 edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
 434
 435                 /*
 436                  * Issue later based on missed flag which will be sure
 437                  * to happen as:
 438                  * (1) we finished transmitting an intermediate slot and
 439                  *     edma_execute is coming up.
 440                  * (2) or we finished current transfer and issue will
 441                  *     call edma_execute.
 442                  *
 443                  * Important note: issuing can be dangerous here and
 444                  * lead to some nasty recursion when we are in a NULL
 445                  * slot. So we avoid doing so and set the missed flag.
 446                  */
 447                 if (p.a_b_cnt == 0 && p.ccnt == 0) {
 448                         dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n");
 449                         echan->missed = 1;
 450                 } else {
 451                         /*
 452                          * The slot is already programmed but the event got
 453                          * missed, so its safe to issue it here.
 454                          */
 455                         dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
 456                         edma_clean_channel(echan->ch_num);
 457                         edma_stop(echan->ch_num);
 458                         edma_start(echan->ch_num);
 459                         edma_trigger_channel(echan->ch_num);
 460                 }
 461
 462                 spin_unlock_irqrestore(&echan->vchan.lock, flags);
 463
 464                 break;
 465         default:
 466                 break;
 467         }
 468 }
 469
 470 /* Alloc channel resources */
 471 static int edma_alloc_chan_resources(struct dma_chan *chan)
 472 {
 473         struct edma_chan *echan = to_edma_chan(chan);
 474         struct device *dev = chan->device->dev;
 475         int ret;
 476         int a_ch_num;
 477         LIST_HEAD(descs);
 478
 479         a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
 480                                         chan, EVENTQ_DEFAULT);
 481
 482         if (a_ch_num < 0) {
 483                 ret = -ENODEV;
 484                 goto err_no_chan;
 485         }
 486
 487         if (a_ch_num != echan->ch_num) {
 488                 dev_err(dev, "failed to allocate requested channel %u:%u\n",
 489                         EDMA_CTLR(echan->ch_num),
 490                         EDMA_CHAN_SLOT(echan->ch_num));
 491                 ret = -ENODEV;
 492                 goto err_wrong_chan;
 493         }
 494
 495         echan->alloced = true;
 496         echan->slot[0] = echan->ch_num;
 497
 498         dev_info(dev, "allocated channel for %u:%u\n",
 499                  EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
 500
 501         return 0;
 502
 503 err_wrong_chan:
 504         edma_free_channel(a_ch_num);
 505 err_no_chan:
 506         return ret;
 507 }
 508
 509 /* Free channel resources */
 510 static void edma_free_chan_resources(struct dma_chan *chan)
 511 {
 512         struct edma_chan *echan = to_edma_chan(chan);
 513         struct device *dev = chan->device->dev;
 514         int i;
 515
 516         /* Terminate transfers */
 517         edma_stop(echan->ch_num);
 518
 519         vchan_free_chan_resources(&echan->vchan);
 520
 521         /* Free EDMA PaRAM slots */
 522         for (i = 1; i < EDMA_MAX_SLOTS; i++) {
 523                 if (echan->slot[i] >= 0) {
 524                         edma_free_slot(echan->slot[i]);
 525                         echan->slot[i] = -1;
 526                 }
 527         }
 528
 529         /* Free EDMA channel */
 530         if (echan->alloced) {
 531                 edma_free_channel(echan->ch_num);
 532                 echan->alloced = false;
 533         }
 534
 535         dev_info(dev, "freeing channel for %u\n", echan->ch_num);
 536 }
 537
 538 /* Send pending descriptor to hardware */
 539 static void edma_issue_pending(struct dma_chan *chan)
 540 {
 541         struct edma_chan *echan = to_edma_chan(chan);
 542         unsigned long flags;
 543
 544         spin_lock_irqsave(&echan->vchan.lock, flags);
 545         if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
 546                 edma_execute(echan);
 547         spin_unlock_irqrestore(&echan->vchan.lock, flags);
 548 }
 549
 550 static size_t edma_desc_size(struct edma_desc *edesc)
 551 {
 552         int i;
 553         size_t size;
 554
 555         if (edesc->absync)
 556                 for (size = i = 0; i < edesc->pset_nr; i++)
 557                         size += (edesc->pset[i].a_b_cnt & 0xffff) *
 558                                 (edesc->pset[i].a_b_cnt >> 16) *
 559                                  edesc->pset[i].ccnt;
 560         else
 561                 size = (edesc->pset[0].a_b_cnt & 0xffff) *
 562                         (edesc->pset[0].a_b_cnt >> 16) +
 563                         (edesc->pset[0].a_b_cnt & 0xffff) *
 564                         (SZ_64K - 1) * edesc->pset[0].ccnt;
 565
 566         return size;
 567 }
 568
 569 /* Check request completion status */
 570 static enum dma_status edma_tx_status(struct dma_chan *chan,
 571                                       dma_cookie_t cookie,
 572                                       struct dma_tx_state *txstate)
 573 {
 574         struct edma_chan *echan = to_edma_chan(chan);
 575         struct virt_dma_desc *vdesc;
 576         enum dma_status ret;
 577         unsigned long flags;
 578
 579         ret = dma_cookie_status(chan, cookie, txstate);
 580         if (ret == DMA_SUCCESS || !txstate)
 581                 return ret;
 582
 583         spin_lock_irqsave(&echan->vchan.lock, flags);
 584         vdesc = vchan_find_desc(&echan->vchan, cookie);
 585         if (vdesc) {
 586                 txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
 587         } else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
 588                 struct edma_desc *edesc = echan->edesc;
 589                 txstate->residue = edma_desc_size(edesc);
 590         }
 591         spin_unlock_irqrestore(&echan->vchan.lock, flags);
 592
 593         return ret;
 594 }
 595
 596 static void __init edma_chan_init(struct edma_cc *ecc,
 597                                   struct dma_device *dma,
 598                                   struct edma_chan *echans)
 599 {
 600         int i, j;
 601
 602         for (i = 0; i < EDMA_CHANS; i++) {
 603                 struct edma_chan *echan = &echans[i];
 604                 echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
 605                 echan->ecc = ecc;
 606                 echan->vchan.desc_free = edma_desc_free;
 607
 608                 vchan_init(&echan->vchan, dma);
 609
 610                 INIT_LIST_HEAD(&echan->node);
 611                 for (j = 0; j < EDMA_MAX_SLOTS; j++)
 612                         echan->slot[j] = -1;
 613         }
 614 }
 615
 616 static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
 617                           struct device *dev)
 618 {
 619         dma->device_prep_slave_sg = edma_prep_slave_sg;
 620         dma->device_alloc_chan_resources = edma_alloc_chan_resources;
 621         dma->device_free_chan_resources = edma_free_chan_resources;
 622         dma->device_issue_pending = edma_issue_pending;
 623         dma->device_tx_status = edma_tx_status;
 624         dma->device_control = edma_control;
 625         dma->dev = dev;
 626
 627         INIT_LIST_HEAD(&dma->channels);
 628 }
 629
 630 static int edma_probe(struct platform_device *pdev)
 631 {
 632         struct edma_cc *ecc;
 633         int ret;
 634
 635         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 636         if (ret)
 637                 return ret;
 638
 639         ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
 640         if (!ecc) {
 641                 dev_err(&pdev->dev, "Can't allocate controller\n");
 642                 return -ENOMEM;
 643         }
 644
 645         ecc->ctlr = pdev->id;
 646         ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
 647         if (ecc->dummy_slot < 0) {
 648                 dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
 649                 return -EIO;
 650         }
 651
 652         dma_cap_zero(ecc->dma_slave.cap_mask);
 653         dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
 654
 655         edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
 656
 657         edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
 658
 659         ret = dma_async_device_register(&ecc->dma_slave);
 660         if (ret)
 661                 goto err_reg1;
 662
 663         platform_set_drvdata(pdev, ecc);
 664
 665         dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
 666
 667         return 0;
 668
 669 err_reg1:
 670         edma_free_slot(ecc->dummy_slot);
 671         return ret;
 672 }
 673
 674 static int edma_remove(struct platform_device *pdev)
 675 {
 676         struct device *dev = &pdev->dev;
 677         struct edma_cc *ecc = dev_get_drvdata(dev);
 678
 679         dma_async_device_unregister(&ecc->dma_slave);
 680         edma_free_slot(ecc->dummy_slot);
 681
 682         return 0;
 683 }
 684
 685 static struct platform_driver edma_driver = {
 686         .probe          = edma_probe,
 687         .remove         = edma_remove,
 688         .driver = {
 689                 .name = "edma-dma-engine",
 690                 .owner = THIS_MODULE,
 691         },
 692 };
 693
 694 bool edma_filter_fn(struct dma_chan *chan, void *param)
 695 {
 696         if (chan->device->dev->driver == &edma_driver.driver) {
 697                 struct edma_chan *echan = to_edma_chan(chan);
 698                 unsigned ch_req = *(unsigned *)param;
 699                 return ch_req == echan->ch_num;
 700         }
 701         return false;
 702 }
 703 EXPORT_SYMBOL(edma_filter_fn);
 704
 705 static struct platform_device *pdev0, *pdev1;
 706
 707 static const struct platform_device_info edma_dev_info0 = {
 708         .name = "edma-dma-engine",
 709         .id = 0,
 710         .dma_mask = DMA_BIT_MASK(32),
 711 };
 712
 713 static const struct platform_device_info edma_dev_info1 = {
 714         .name = "edma-dma-engine",
 715         .id = 1,
 716         .dma_mask = DMA_BIT_MASK(32),
 717 };
 718
 719 static int edma_init(void)
 720 {
 721         int ret = platform_driver_register(&edma_driver);
 722
 723         if (ret == 0) {
 724                 pdev0 = platform_device_register_full(&edma_dev_info0);
 725                 if (IS_ERR(pdev0)) {
 726                         platform_driver_unregister(&edma_driver);
 727                         ret = PTR_ERR(pdev0);
 728                         goto out;
 729                 }
 730         }
 731
 732         if (EDMA_CTLRS == 2) {
 733                 pdev1 = platform_device_register_full(&edma_dev_info1);
 734                 if (IS_ERR(pdev1)) {
 735                         platform_driver_unregister(&edma_driver);
 736                         platform_device_unregister(pdev0);
 737                         ret = PTR_ERR(pdev1);
 738                 }
 739         }
 740
 741 out:
 742         return ret;
 743 }
 744 subsys_initcall(edma_init);
 745
 746 static void __exit edma_exit(void)
 747 {
 748         platform_device_unregister(pdev0);
 749         if (pdev1)
 750                 platform_device_unregister(pdev1);
 751         platform_driver_unregister(&edma_driver);
 752 }
 753 module_exit(edma_exit);
 754
 755 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
 756 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
 757 MODULE_LICENSE("GPL v2");