2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/gpio.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29 #include <linux/basic_mmio_gpio.h>
30 #include <mach/hardware.h>
31 #include <asm-generic/bug.h>
33 struct mxc_gpio_port {
34 struct list_head node;
38 int virtual_irq_start;
39 struct bgpio_chip bgc;
44 * MX2 has one interrupt *for all* gpio ports. The list is used
45 * to save the references to all ports, so that mx2_gpio_irq_handler
46 * can walk through all interrupt status registers.
48 static LIST_HEAD(mxc_gpio_ports);
50 #define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
52 #define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
53 #define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
54 #define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
55 #define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
56 #define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
57 #define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
58 #define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
60 #define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
61 #define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
62 #define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
63 #define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
64 #define GPIO_INT_NONE 0x4
66 /* Note: This driver assumes 32 GPIOs are handled in one register */
68 static int gpio_set_irq_type(struct irq_data *d, u32 type)
70 u32 gpio = irq_to_gpio(d->irq);
71 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
72 struct mxc_gpio_port *port = gc->private;
75 void __iomem *reg = port->base;
77 port->both_edges &= ~(1 << (gpio & 31));
79 case IRQ_TYPE_EDGE_RISING:
80 edge = GPIO_INT_RISE_EDGE;
82 case IRQ_TYPE_EDGE_FALLING:
83 edge = GPIO_INT_FALL_EDGE;
85 case IRQ_TYPE_EDGE_BOTH:
86 val = gpio_get_value(gpio);
88 edge = GPIO_INT_LOW_LEV;
89 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
91 edge = GPIO_INT_HIGH_LEV;
92 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
94 port->both_edges |= 1 << (gpio & 31);
96 case IRQ_TYPE_LEVEL_LOW:
97 edge = GPIO_INT_LOW_LEV;
99 case IRQ_TYPE_LEVEL_HIGH:
100 edge = GPIO_INT_HIGH_LEV;
106 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
108 val = readl(reg) & ~(0x3 << (bit << 1));
109 writel(val | (edge << (bit << 1)), reg);
110 writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
115 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
117 void __iomem *reg = port->base;
121 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
124 edge = (val >> (bit << 1)) & 3;
125 val &= ~(0x3 << (bit << 1));
126 if (edge == GPIO_INT_HIGH_LEV) {
127 edge = GPIO_INT_LOW_LEV;
128 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
129 } else if (edge == GPIO_INT_LOW_LEV) {
130 edge = GPIO_INT_HIGH_LEV;
131 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
133 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
137 writel(val | (edge << (bit << 1)), reg);
140 /* handle 32 interrupts in one status register */
141 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
143 u32 gpio_irq_no_base = port->virtual_irq_start;
145 while (irq_stat != 0) {
146 int irqoffset = fls(irq_stat) - 1;
148 if (port->both_edges & (1 << irqoffset))
149 mxc_flip_edge(port, irqoffset);
151 generic_handle_irq(gpio_irq_no_base + irqoffset);
153 irq_stat &= ~(1 << irqoffset);
157 /* MX1 and MX3 has one interrupt *per* gpio port */
158 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
161 struct mxc_gpio_port *port = irq_get_handler_data(irq);
163 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
165 mxc_gpio_irq_handler(port, irq_stat);
168 /* MX2 has one interrupt *for all* gpio ports */
169 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
171 u32 irq_msk, irq_stat;
172 struct mxc_gpio_port *port;
174 /* walk through all interrupt status registers */
175 list_for_each_entry(port, &mxc_gpio_ports, node) {
176 irq_msk = readl(port->base + GPIO_IMR);
180 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
182 mxc_gpio_irq_handler(port, irq_stat);
187 * Set interrupt number "irq" in the GPIO as a wake-up source.
188 * While system is running, all registered GPIO interrupts need to have
189 * wake-up enabled. When system is suspended, only selected GPIO interrupts
190 * need to have wake-up enabled.
191 * @param irq interrupt source number
192 * @param enable enable as wake-up if equal to non-zero
193 * @return This function returns 0 on success.
195 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
197 u32 gpio = irq_to_gpio(d->irq);
198 u32 gpio_idx = gpio & 0x1F;
199 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
200 struct mxc_gpio_port *port = gc->private;
203 if (port->irq_high && (gpio_idx >= 16))
204 enable_irq_wake(port->irq_high);
206 enable_irq_wake(port->irq);
208 if (port->irq_high && (gpio_idx >= 16))
209 disable_irq_wake(port->irq_high);
211 disable_irq_wake(port->irq);
217 static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
219 struct irq_chip_generic *gc;
220 struct irq_chip_type *ct;
222 gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
223 port->base, handle_level_irq);
227 ct->chip.irq_ack = irq_gc_ack,
228 ct->chip.irq_mask = irq_gc_mask_clr_bit;
229 ct->chip.irq_unmask = irq_gc_mask_set_bit;
230 ct->chip.irq_set_type = gpio_set_irq_type;
231 ct->chip.irq_set_wake = gpio_set_wake_irq,
232 ct->regs.ack = GPIO_ISR;
233 ct->regs.mask = GPIO_IMR;
235 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
239 static int __devinit mxc_gpio_probe(struct platform_device *pdev)
241 struct mxc_gpio_port *port;
242 struct resource *iores;
245 port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
249 port->virtual_irq_start = MXC_GPIO_IRQ_START + pdev->id * 32;
251 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
257 if (!request_mem_region(iores->start, resource_size(iores),
263 port->base = ioremap(iores->start, resource_size(iores));
266 goto out_release_mem;
269 port->irq_high = platform_get_irq(pdev, 1);
270 port->irq = platform_get_irq(pdev, 0);
276 /* disable the interrupt and clear the status */
277 writel(0, port->base + GPIO_IMR);
278 writel(~0, port->base + GPIO_ISR);
280 /* gpio-mxc can be a generic irq chip */
281 mxc_gpio_init_gc(port);
284 /* setup one handler for all GPIO interrupts */
286 irq_set_chained_handler(port->irq,
287 mx2_gpio_irq_handler);
289 /* setup one handler for each entry */
290 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
291 irq_set_handler_data(port->irq, port);
292 if (port->irq_high > 0) {
293 /* setup handler for GPIO 16 to 31 */
294 irq_set_chained_handler(port->irq_high,
295 mx3_gpio_irq_handler);
296 irq_set_handler_data(port->irq_high, port);
300 err = bgpio_init(&port->bgc, &pdev->dev, 4,
301 port->base + GPIO_PSR,
302 port->base + GPIO_DR, NULL,
303 port->base + GPIO_GDIR, NULL, false);
307 port->bgc.gc.base = pdev->id * 32;
309 err = gpiochip_add(&port->bgc.gc);
311 goto out_bgpio_remove;
313 list_add_tail(&port->node, &mxc_gpio_ports);
318 bgpio_remove(&port->bgc);
322 release_mem_region(iores->start, resource_size(iores));
325 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
329 static struct platform_driver mxc_gpio_driver = {
332 .owner = THIS_MODULE,
334 .probe = mxc_gpio_probe,
337 static int __init gpio_mxc_init(void)
339 return platform_driver_register(&mxc_gpio_driver);
341 postcore_initcall(gpio_mxc_init);
343 MODULE_AUTHOR("Freescale Semiconductor, "
344 "Daniel Mack <danielncaiaq.de>, "
345 "Juergen Beisert <kernel@pengutronix.de>");
346 MODULE_DESCRIPTION("Freescale MXC GPIO");
347 MODULE_LICENSE("GPL");