drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "cikd.h"
  27 #include "cik.h"
  28 #include "gmc_v7_0.h"
  29 #include "amdgpu_ucode.h"
  30
  31 #include "bif/bif_4_1_d.h"
  32 #include "bif/bif_4_1_sh_mask.h"
  33
  34 #include "gmc/gmc_7_1_d.h"
  35 #include "gmc/gmc_7_1_sh_mask.h"
  36
  37 #include "oss/oss_2_0_d.h"
  38 #include "oss/oss_2_0_sh_mask.h"
  39
  40 #include "amdgpu_atombios.h"
  41
  42 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
  43 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  44 static int gmc_v7_0_wait_for_idle(void *handle);
  45
  46 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
  47 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
  48 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
  49
  50 static const u32 golden_settings_iceland_a11[] =
  51 {
  52         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  53         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  54         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  55         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  56 };
  57
  58 static const u32 iceland_mgcg_cgcg_init[] =
  59 {
  60         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  61 };
  62
  63 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  64 {
  65         switch (adev->asic_type) {
  66         case CHIP_TOPAZ:
  67                 amdgpu_program_register_sequence(adev,
  68                                                  iceland_mgcg_cgcg_init,
  69                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  70                 amdgpu_program_register_sequence(adev,
  71                                                  golden_settings_iceland_a11,
  72                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
  73                 break;
  74         default:
  75                 break;
  76         }
  77 }
  78
  79 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
  80                              struct amdgpu_mode_mc_save *save)
  81 {
  82         u32 blackout;
  83
  84         if (adev->mode_info.num_crtc)
  85                 amdgpu_display_stop_mc_access(adev, save);
  86
  87         gmc_v7_0_wait_for_idle((void *)adev);
  88
  89         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  90         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  91                 /* Block CPU access */
  92                 WREG32(mmBIF_FB_EN, 0);
  93                 /* blackout the MC */
  94                 blackout = REG_SET_FIELD(blackout,
  95                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  96                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  97         }
  98         /* wait for the MC to settle */
  99         udelay(100);
 100 }
 101
 102 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
 103                                struct amdgpu_mode_mc_save *save)
 104 {
 105         u32 tmp;
 106
 107         /* unblackout the MC */
 108         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 109         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 110         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 111         /* allow CPU access */
 112         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 113         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 114         WREG32(mmBIF_FB_EN, tmp);
 115
 116         if (adev->mode_info.num_crtc)
 117                 amdgpu_display_resume_mc_access(adev, save);
 118 }
 119
 120 /**
 121  * gmc_v7_0_init_microcode - load ucode images from disk
 122  *
 123  * @adev: amdgpu_device pointer
 124  *
 125  * Use the firmware interface to load the ucode images into
 126  * the driver (not loaded into hw).
 127  * Returns 0 on success, error on failure.
 128  */
 129 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 130 {
 131         const char *chip_name;
 132         char fw_name[30];
 133         int err;
 134
 135         DRM_DEBUG("\n");
 136
 137         switch (adev->asic_type) {
 138         case CHIP_BONAIRE:
 139                 chip_name = "bonaire";
 140                 break;
 141         case CHIP_HAWAII:
 142                 chip_name = "hawaii";
 143                 break;
 144         case CHIP_TOPAZ:
 145                 chip_name = "topaz";
 146                 break;
 147         case CHIP_KAVERI:
 148         case CHIP_KABINI:
 149         case CHIP_MULLINS:
 150                 return 0;
 151         default: BUG();
 152         }
 153
 154         if (adev->asic_type == CHIP_TOPAZ)
 155                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 156         else
 157                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 158
 159         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 160         if (err)
 161                 goto out;
 162         err = amdgpu_ucode_validate(adev->mc.fw);
 163
 164 out:
 165         if (err) {
 166                 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
 167                 release_firmware(adev->mc.fw);
 168                 adev->mc.fw = NULL;
 169         }
 170         return err;
 171 }
 172
 173 /**
 174  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 175  *
 176  * @adev: amdgpu_device pointer
 177  *
 178  * Load the GDDR MC ucode into the hw (CIK).
 179  * Returns 0 on success, error on failure.
 180  */
 181 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 182 {
 183         const struct mc_firmware_header_v1_0 *hdr;
 184         const __le32 *fw_data = NULL;
 185         const __le32 *io_mc_regs = NULL;
 186         u32 running;
 187         int i, ucode_size, regs_size;
 188
 189         if (!adev->mc.fw)
 190                 return -EINVAL;
 191
 192         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 193         amdgpu_ucode_print_mc_hdr(&hdr->header);
 194
 195         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 196         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 197         io_mc_regs = (const __le32 *)
 198                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 199         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 200         fw_data = (const __le32 *)
 201                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 202
 203         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 204
 205         if (running == 0) {
 206                 /* reset the engine and set to writable */
 207                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 208                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 209
 210                 /* load mc io regs */
 211                 for (i = 0; i < regs_size; i++) {
 212                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 213                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 214                 }
 215                 /* load the MC ucode */
 216                 for (i = 0; i < ucode_size; i++)
 217                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 218
 219                 /* put the engine back into the active state */
 220                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 221                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 222                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 223
 224                 /* wait for training to complete */
 225                 for (i = 0; i < adev->usec_timeout; i++) {
 226                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 227                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 228                                 break;
 229                         udelay(1);
 230                 }
 231                 for (i = 0; i < adev->usec_timeout; i++) {
 232                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 233                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 234                                 break;
 235                         udelay(1);
 236                 }
 237         }
 238
 239         return 0;
 240 }
 241
 242 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 243                                        struct amdgpu_mc *mc)
 244 {
 245         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 246                 /* leave room for at least 1024M GTT */
 247                 dev_warn(adev->dev, "limiting VRAM\n");
 248                 mc->real_vram_size = 0xFFC0000000ULL;
 249                 mc->mc_vram_size = 0xFFC0000000ULL;
 250         }
 251         amdgpu_vram_location(adev, &adev->mc, 0);
 252         adev->mc.gtt_base_align = 0;
 253         amdgpu_gtt_location(adev, mc);
 254 }
 255
 256 /**
 257  * gmc_v7_0_mc_program - program the GPU memory controller
 258  *
 259  * @adev: amdgpu_device pointer
 260  *
 261  * Set the location of vram, gart, and AGP in the GPU's
 262  * physical address space (CIK).
 263  */
 264 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 265 {
 266         struct amdgpu_mode_mc_save save;
 267         u32 tmp;
 268         int i, j;
 269
 270         /* Initialize HDP */
 271         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 272                 WREG32((0xb05 + j), 0x00000000);
 273                 WREG32((0xb06 + j), 0x00000000);
 274                 WREG32((0xb07 + j), 0x00000000);
 275                 WREG32((0xb08 + j), 0x00000000);
 276                 WREG32((0xb09 + j), 0x00000000);
 277         }
 278         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 279
 280         if (adev->mode_info.num_crtc)
 281                 amdgpu_display_set_vga_render_state(adev, false);
 282
 283         gmc_v7_0_mc_stop(adev, &save);
 284         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 285                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 286         }
 287         /* Update configuration */
 288         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 289                adev->mc.vram_start >> 12);
 290         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 291                adev->mc.vram_end >> 12);
 292         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 293                adev->vram_scratch.gpu_addr >> 12);
 294         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 295         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 296         WREG32(mmMC_VM_FB_LOCATION, tmp);
 297         /* XXX double check these! */
 298         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 299         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 300         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 301         WREG32(mmMC_VM_AGP_BASE, 0);
 302         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 303         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 304         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 305                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 306         }
 307         gmc_v7_0_mc_resume(adev, &save);
 308
 309         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 310
 311         tmp = RREG32(mmHDP_MISC_CNTL);
 312         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 313         WREG32(mmHDP_MISC_CNTL, tmp);
 314
 315         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 316         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 317 }
 318
 319 /**
 320  * gmc_v7_0_mc_init - initialize the memory controller driver params
 321  *
 322  * @adev: amdgpu_device pointer
 323  *
 324  * Look up the amount of vram, vram width, and decide how to place
 325  * vram and gart within the GPU's physical address space (CIK).
 326  * Returns 0 for success.
 327  */
 328 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 329 {
 330         adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
 331         if (!adev->mc.vram_width) {
 332                 u32 tmp;
 333                 int chansize, numchan;
 334
 335                 /* Get VRAM informations */
 336                 tmp = RREG32(mmMC_ARB_RAMCFG);
 337                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 338                         chansize = 64;
 339                 } else {
 340                         chansize = 32;
 341                 }
 342                 tmp = RREG32(mmMC_SHARED_CHMAP);
 343                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 344                 case 0:
 345                 default:
 346                         numchan = 1;
 347                         break;
 348                 case 1:
 349                         numchan = 2;
 350                         break;
 351                 case 2:
 352                         numchan = 4;
 353                         break;
 354                 case 3:
 355                         numchan = 8;
 356                         break;
 357                 case 4:
 358                         numchan = 3;
 359                         break;
 360                 case 5:
 361                         numchan = 6;
 362                         break;
 363                 case 6:
 364                         numchan = 10;
 365                         break;
 366                 case 7:
 367                         numchan = 12;
 368                         break;
 369                 case 8:
 370                         numchan = 16;
 371                         break;
 372                 }
 373                 adev->mc.vram_width = numchan * chansize;
 374         }
 375         /* Could aper size report 0 ? */
 376         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 377         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 378         /* size in MB on si */
 379         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 380         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 381
 382 #ifdef CONFIG_X86_64
 383         if (adev->flags & AMD_IS_APU) {
 384                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 385                 adev->mc.aper_size = adev->mc.real_vram_size;
 386         }
 387 #endif
 388
 389         /* In case the PCI BAR is larger than the actual amount of vram */
 390         adev->mc.visible_vram_size = adev->mc.aper_size;
 391         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 392                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 393
 394         /* unless the user had overridden it, set the gart
 395          * size equal to the 1024 or vram, whichever is larger.
 396          */
 397         if (amdgpu_gart_size == -1)
 398                 adev->mc.gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
 399                                         adev->mc.mc_vram_size);
 400         else
 401                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 402
 403         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * GART
 410  * VMID 0 is the physical GPU addresses as used by the kernel.
 411  * VMIDs 1-15 are used for userspace clients and are handled
 412  * by the amdgpu vm/hsa code.
 413  */
 414
 415 /**
 416  * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
 417  *
 418  * @adev: amdgpu_device pointer
 419  * @vmid: vm instance to flush
 420  *
 421  * Flush the TLB for the requested page table (CIK).
 422  */
 423 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 424                                         uint32_t vmid)
 425 {
 426         /* flush hdp cache */
 427         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 428
 429         /* bits 0-15 are the VM contexts0-15 */
 430         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 431 }
 432
 433 /**
 434  * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
 435  *
 436  * @adev: amdgpu_device pointer
 437  * @cpu_pt_addr: cpu address of the page table
 438  * @gpu_page_idx: entry in the page table to update
 439  * @addr: dst addr to write into pte/pde
 440  * @flags: access flags
 441  *
 442  * Update the page tables using the CPU.
 443  */
 444 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 445                                      void *cpu_pt_addr,
 446                                      uint32_t gpu_page_idx,
 447                                      uint64_t addr,
 448                                      uint64_t flags)
 449 {
 450         void __iomem *ptr = (void *)cpu_pt_addr;
 451         uint64_t value;
 452
 453         value = addr & 0xFFFFFFFFFFFFF000ULL;
 454         value |= flags;
 455         writeq(value, ptr + (gpu_page_idx * 8));
 456
 457         return 0;
 458 }
 459
 460 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev,
 461                                           uint32_t flags)
 462 {
 463         uint64_t pte_flag = 0;
 464
 465         if (flags & AMDGPU_VM_PAGE_READABLE)
 466                 pte_flag |= AMDGPU_PTE_READABLE;
 467         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 468                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 469         if (flags & AMDGPU_VM_PAGE_PRT)
 470                 pte_flag |= AMDGPU_PTE_PRT;
 471
 472         return pte_flag;
 473 }
 474
 475 /**
 476  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 477  *
 478  * @adev: amdgpu_device pointer
 479  * @value: true redirects VM faults to the default page
 480  */
 481 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 482                                               bool value)
 483 {
 484         u32 tmp;
 485
 486         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 487         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 488                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 489         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 490                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 491         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 492                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 493         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 494                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 495         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 496                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 497         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 498                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 499         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 500 }
 501
 502 /**
 503  * gmc_v7_0_set_prt - set PRT VM fault
 504  *
 505  * @adev: amdgpu_device pointer
 506  * @enable: enable/disable VM fault handling for PRT
 507  */
 508 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
 509 {
 510         uint32_t tmp;
 511
 512         if (enable && !adev->mc.prt_warning) {
 513                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 514                 adev->mc.prt_warning = true;
 515         }
 516
 517         tmp = RREG32(mmVM_PRT_CNTL);
 518         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 519                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 520         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 521                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 522         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 523                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 524         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 525                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 526         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 527                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 528         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 529                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 530         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 531                             MASK_PDE0_FAULT, enable);
 532         WREG32(mmVM_PRT_CNTL, tmp);
 533
 534         if (enable) {
 535                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 536                 uint32_t high = adev->vm_manager.max_pfn;
 537
 538                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 539                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 540                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 541                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 542                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 543                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 544                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 545                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 546         } else {
 547                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 548                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 549                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 550                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 551                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 552                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 553                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 554                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 555         }
 556 }
 557
 558 /**
 559  * gmc_v7_0_gart_enable - gart enable
 560  *
 561  * @adev: amdgpu_device pointer
 562  *
 563  * This sets up the TLBs, programs the page tables for VMID0,
 564  * sets up the hw for VMIDs 1-15 which are allocated on
 565  * demand, and sets up the global locations for the LDS, GDS,
 566  * and GPUVM for FSA64 clients (CIK).
 567  * Returns 0 for success, errors for failure.
 568  */
 569 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 570 {
 571         int r, i;
 572         u32 tmp;
 573
 574         if (adev->gart.robj == NULL) {
 575                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 576                 return -EINVAL;
 577         }
 578         r = amdgpu_gart_table_vram_pin(adev);
 579         if (r)
 580                 return r;
 581         /* Setup TLB control */
 582         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 583         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 584         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 585         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 586         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 587         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 588         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 589         /* Setup L2 cache */
 590         tmp = RREG32(mmVM_L2_CNTL);
 591         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 592         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 593         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 594         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 595         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 596         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 597         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 598         WREG32(mmVM_L2_CNTL, tmp);
 599         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 600         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 601         WREG32(mmVM_L2_CNTL2, tmp);
 602         tmp = RREG32(mmVM_L2_CNTL3);
 603         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 604         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 605         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 606         WREG32(mmVM_L2_CNTL3, tmp);
 607         /* setup context0 */
 608         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 609         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 610         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 611         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 612                         (u32)(adev->dummy_page.addr >> 12));
 613         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 614         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 615         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 616         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 617         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 618         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 619
 620         WREG32(0x575, 0);
 621         WREG32(0x576, 0);
 622         WREG32(0x577, 0);
 623
 624         /* empty context1-15 */
 625         /* FIXME start with 4G, once using 2 level pt switch to full
 626          * vm size space
 627          */
 628         /* set vm size, must be a multiple of 4 */
 629         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 630         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 631         for (i = 1; i < 16; i++) {
 632                 if (i < 8)
 633                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 634                                adev->gart.table_addr >> 12);
 635                 else
 636                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 637                                adev->gart.table_addr >> 12);
 638         }
 639
 640         /* enable context1-15 */
 641         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 642                (u32)(adev->dummy_page.addr >> 12));
 643         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 644         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 645         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 646         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 647         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 648                             adev->vm_manager.block_size - 9);
 649         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 650         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 651                 gmc_v7_0_set_fault_enable_default(adev, false);
 652         else
 653                 gmc_v7_0_set_fault_enable_default(adev, true);
 654
 655         if (adev->asic_type == CHIP_KAVERI) {
 656                 tmp = RREG32(mmCHUB_CONTROL);
 657                 tmp &= ~BYPASS_VM;
 658                 WREG32(mmCHUB_CONTROL, tmp);
 659         }
 660
 661         gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
 662         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 663                  (unsigned)(adev->mc.gtt_size >> 20),
 664                  (unsigned long long)adev->gart.table_addr);
 665         adev->gart.ready = true;
 666         return 0;
 667 }
 668
 669 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 670 {
 671         int r;
 672
 673         if (adev->gart.robj) {
 674                 WARN(1, "R600 PCIE GART already initialized\n");
 675                 return 0;
 676         }
 677         /* Initialize common gart structure */
 678         r = amdgpu_gart_init(adev);
 679         if (r)
 680                 return r;
 681         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 682         adev->gart.gart_pte_flags = 0;
 683         return amdgpu_gart_table_vram_alloc(adev);
 684 }
 685
 686 /**
 687  * gmc_v7_0_gart_disable - gart disable
 688  *
 689  * @adev: amdgpu_device pointer
 690  *
 691  * This disables all VM page table (CIK).
 692  */
 693 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 694 {
 695         u32 tmp;
 696
 697         /* Disable all tables */
 698         WREG32(mmVM_CONTEXT0_CNTL, 0);
 699         WREG32(mmVM_CONTEXT1_CNTL, 0);
 700         /* Setup TLB control */
 701         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 702         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 703         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 704         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 705         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 706         /* Setup L2 cache */
 707         tmp = RREG32(mmVM_L2_CNTL);
 708         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 709         WREG32(mmVM_L2_CNTL, tmp);
 710         WREG32(mmVM_L2_CNTL2, 0);
 711         amdgpu_gart_table_vram_unpin(adev);
 712 }
 713
 714 /**
 715  * gmc_v7_0_gart_fini - vm fini callback
 716  *
 717  * @adev: amdgpu_device pointer
 718  *
 719  * Tears down the driver GART/VM setup (CIK).
 720  */
 721 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
 722 {
 723         amdgpu_gart_table_vram_free(adev);
 724         amdgpu_gart_fini(adev);
 725 }
 726
 727 /*
 728  * vm
 729  * VMID 0 is the physical GPU addresses as used by the kernel.
 730  * VMIDs 1-15 are used for userspace clients and are handled
 731  * by the amdgpu vm/hsa code.
 732  */
 733 /**
 734  * gmc_v7_0_vm_init - cik vm init callback
 735  *
 736  * @adev: amdgpu_device pointer
 737  *
 738  * Inits cik specific vm parameters (number of VMs, base of vram for
 739  * VMIDs 1-15) (CIK).
 740  * Returns 0 for success.
 741  */
 742 static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
 743 {
 744         /*
 745          * number of VMs
 746          * VMID 0 is reserved for System
 747          * amdgpu graphics/compute will use VMIDs 1-7
 748          * amdkfd will use VMIDs 8-15
 749          */
 750         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
 751         adev->vm_manager.num_level = 1;
 752         amdgpu_vm_manager_init(adev);
 753
 754         /* base offset of vram pages */
 755         if (adev->flags & AMD_IS_APU) {
 756                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 757                 tmp <<= 22;
 758                 adev->vm_manager.vram_base_offset = tmp;
 759         } else
 760                 adev->vm_manager.vram_base_offset = 0;
 761
 762         return 0;
 763 }
 764
 765 /**
 766  * gmc_v7_0_vm_fini - cik vm fini callback
 767  *
 768  * @adev: amdgpu_device pointer
 769  *
 770  * Tear down any asic specific VM setup (CIK).
 771  */
 772 static void gmc_v7_0_vm_fini(struct amdgpu_device *adev)
 773 {
 774 }
 775
 776 /**
 777  * gmc_v7_0_vm_decode_fault - print human readable fault info
 778  *
 779  * @adev: amdgpu_device pointer
 780  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 781  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 782  *
 783  * Print human readable fault information (CIK).
 784  */
 785 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 786                                      u32 status, u32 addr, u32 mc_client)
 787 {
 788         u32 mc_id;
 789         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 790         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 791                                         PROTECTIONS);
 792         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 793                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 794
 795         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 796                               MEMORY_CLIENT_ID);
 797
 798         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 799                protections, vmid, addr,
 800                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 801                              MEMORY_CLIENT_RW) ?
 802                "write" : "read", block, mc_client, mc_id);
 803 }
 804
 805
 806 static const u32 mc_cg_registers[] = {
 807         mmMC_HUB_MISC_HUB_CG,
 808         mmMC_HUB_MISC_SIP_CG,
 809         mmMC_HUB_MISC_VM_CG,
 810         mmMC_XPB_CLK_GAT,
 811         mmATC_MISC_CG,
 812         mmMC_CITF_MISC_WR_CG,
 813         mmMC_CITF_MISC_RD_CG,
 814         mmMC_CITF_MISC_VM_CG,
 815         mmVM_L2_CG,
 816 };
 817
 818 static const u32 mc_cg_ls_en[] = {
 819         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 820         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 821         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 822         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 823         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 824         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 825         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 826         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 827         VM_L2_CG__MEM_LS_ENABLE_MASK,
 828 };
 829
 830 static const u32 mc_cg_en[] = {
 831         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 832         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 833         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 834         MC_XPB_CLK_GAT__ENABLE_MASK,
 835         ATC_MISC_CG__ENABLE_MASK,
 836         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 837         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 838         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 839         VM_L2_CG__ENABLE_MASK,
 840 };
 841
 842 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 843                                   bool enable)
 844 {
 845         int i;
 846         u32 orig, data;
 847
 848         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 849                 orig = data = RREG32(mc_cg_registers[i]);
 850                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 851                         data |= mc_cg_ls_en[i];
 852                 else
 853                         data &= ~mc_cg_ls_en[i];
 854                 if (data != orig)
 855                         WREG32(mc_cg_registers[i], data);
 856         }
 857 }
 858
 859 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 860                                     bool enable)
 861 {
 862         int i;
 863         u32 orig, data;
 864
 865         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 866                 orig = data = RREG32(mc_cg_registers[i]);
 867                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 868                         data |= mc_cg_en[i];
 869                 else
 870                         data &= ~mc_cg_en[i];
 871                 if (data != orig)
 872                         WREG32(mc_cg_registers[i], data);
 873         }
 874 }
 875
 876 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 877                                      bool enable)
 878 {
 879         u32 orig, data;
 880
 881         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 882
 883         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 884                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 885                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 886                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 887                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 888         } else {
 889                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 890                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 891                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 892                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 893         }
 894
 895         if (orig != data)
 896                 WREG32_PCIE(ixPCIE_CNTL2, data);
 897 }
 898
 899 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 900                                      bool enable)
 901 {
 902         u32 orig, data;
 903
 904         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 905
 906         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 907                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 908         else
 909                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 910
 911         if (orig != data)
 912                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 913 }
 914
 915 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 916                                    bool enable)
 917 {
 918         u32 orig, data;
 919
 920         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 921
 922         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 923                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 924         else
 925                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 926
 927         if (orig != data)
 928                 WREG32(mmHDP_MEM_POWER_LS, data);
 929 }
 930
 931 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 932 {
 933         switch (mc_seq_vram_type) {
 934         case MC_SEQ_MISC0__MT__GDDR1:
 935                 return AMDGPU_VRAM_TYPE_GDDR1;
 936         case MC_SEQ_MISC0__MT__DDR2:
 937                 return AMDGPU_VRAM_TYPE_DDR2;
 938         case MC_SEQ_MISC0__MT__GDDR3:
 939                 return AMDGPU_VRAM_TYPE_GDDR3;
 940         case MC_SEQ_MISC0__MT__GDDR4:
 941                 return AMDGPU_VRAM_TYPE_GDDR4;
 942         case MC_SEQ_MISC0__MT__GDDR5:
 943                 return AMDGPU_VRAM_TYPE_GDDR5;
 944         case MC_SEQ_MISC0__MT__HBM:
 945                 return AMDGPU_VRAM_TYPE_HBM;
 946         case MC_SEQ_MISC0__MT__DDR3:
 947                 return AMDGPU_VRAM_TYPE_DDR3;
 948         default:
 949                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 950         }
 951 }
 952
 953 static int gmc_v7_0_early_init(void *handle)
 954 {
 955         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 956
 957         gmc_v7_0_set_gart_funcs(adev);
 958         gmc_v7_0_set_irq_funcs(adev);
 959
 960         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
 961         adev->mc.shared_aperture_end =
 962                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
 963         adev->mc.private_aperture_start =
 964                 adev->mc.shared_aperture_end + 1;
 965         adev->mc.private_aperture_end =
 966                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
 967
 968         return 0;
 969 }
 970
 971 static int gmc_v7_0_late_init(void *handle)
 972 {
 973         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 974
 975         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 976                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 977         else
 978                 return 0;
 979 }
 980
 981 static int gmc_v7_0_sw_init(void *handle)
 982 {
 983         int r;
 984         int dma_bits;
 985         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 986
 987         if (adev->flags & AMD_IS_APU) {
 988                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 989         } else {
 990                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 991                 tmp &= MC_SEQ_MISC0__MT__MASK;
 992                 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 993         }
 994
 995         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
 996         if (r)
 997                 return r;
 998
 999         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
1000         if (r)
1001                 return r;
1002
1003         /* Adjust VM size here.
1004          * Currently set to 4GB ((1 << 20) 4k pages).
1005          * Max GPUVM size for cayman and SI is 40 bits.
1006          */
1007         amdgpu_vm_adjust_size(adev, 64);
1008         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
1009
1010         /* Set the internal MC address mask
1011          * This is the max address of the GPU's
1012          * internal address space.
1013          */
1014         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1015
1016         /* set DMA mask + need_dma32 flags.
1017          * PCIE - can handle 40-bits.
1018          * IGP - can handle 40-bits
1019          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1020          */
1021         adev->need_dma32 = false;
1022         dma_bits = adev->need_dma32 ? 32 : 40;
1023         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1024         if (r) {
1025                 adev->need_dma32 = true;
1026                 dma_bits = 32;
1027                 pr_warn("amdgpu: No suitable DMA available\n");
1028         }
1029         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1030         if (r) {
1031                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1032                 pr_warn("amdgpu: No coherent DMA available\n");
1033         }
1034
1035         r = gmc_v7_0_init_microcode(adev);
1036         if (r) {
1037                 DRM_ERROR("Failed to load mc firmware!\n");
1038                 return r;
1039         }
1040
1041         r = gmc_v7_0_mc_init(adev);
1042         if (r)
1043                 return r;
1044
1045         /* Memory manager */
1046         r = amdgpu_bo_init(adev);
1047         if (r)
1048                 return r;
1049
1050         r = gmc_v7_0_gart_init(adev);
1051         if (r)
1052                 return r;
1053
1054         if (!adev->vm_manager.enabled) {
1055                 r = gmc_v7_0_vm_init(adev);
1056                 if (r) {
1057                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1058                         return r;
1059                 }
1060                 adev->vm_manager.enabled = true;
1061         }
1062
1063         return r;
1064 }
1065
1066 static int gmc_v7_0_sw_fini(void *handle)
1067 {
1068         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1069
1070         if (adev->vm_manager.enabled) {
1071                 amdgpu_vm_manager_fini(adev);
1072                 gmc_v7_0_vm_fini(adev);
1073                 adev->vm_manager.enabled = false;
1074         }
1075         gmc_v7_0_gart_fini(adev);
1076         amdgpu_gem_force_release(adev);
1077         amdgpu_bo_fini(adev);
1078
1079         return 0;
1080 }
1081
1082 static int gmc_v7_0_hw_init(void *handle)
1083 {
1084         int r;
1085         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1086
1087         gmc_v7_0_init_golden_registers(adev);
1088
1089         gmc_v7_0_mc_program(adev);
1090
1091         if (!(adev->flags & AMD_IS_APU)) {
1092                 r = gmc_v7_0_mc_load_microcode(adev);
1093                 if (r) {
1094                         DRM_ERROR("Failed to load MC firmware!\n");
1095                         return r;
1096                 }
1097         }
1098
1099         r = gmc_v7_0_gart_enable(adev);
1100         if (r)
1101                 return r;
1102
1103         return r;
1104 }
1105
1106 static int gmc_v7_0_hw_fini(void *handle)
1107 {
1108         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1109
1110         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1111         gmc_v7_0_gart_disable(adev);
1112
1113         return 0;
1114 }
1115
1116 static int gmc_v7_0_suspend(void *handle)
1117 {
1118         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1119
1120         gmc_v7_0_hw_fini(adev);
1121
1122         return 0;
1123 }
1124
1125 static int gmc_v7_0_resume(void *handle)
1126 {
1127         int r;
1128         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1129
1130         r = gmc_v7_0_hw_init(adev);
1131         if (r)
1132                 return r;
1133
1134         amdgpu_vm_reset_all_ids(adev);
1135
1136         return 0;
1137 }
1138
1139 static bool gmc_v7_0_is_idle(void *handle)
1140 {
1141         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1142         u32 tmp = RREG32(mmSRBM_STATUS);
1143
1144         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1145                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1146                 return false;
1147
1148         return true;
1149 }
1150
1151 static int gmc_v7_0_wait_for_idle(void *handle)
1152 {
1153         unsigned i;
1154         u32 tmp;
1155         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1156
1157         for (i = 0; i < adev->usec_timeout; i++) {
1158                 /* read MC_STATUS */
1159                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1160                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1161                                                SRBM_STATUS__MCC_BUSY_MASK |
1162                                                SRBM_STATUS__MCD_BUSY_MASK |
1163                                                SRBM_STATUS__VMC_BUSY_MASK);
1164                 if (!tmp)
1165                         return 0;
1166                 udelay(1);
1167         }
1168         return -ETIMEDOUT;
1169
1170 }
1171
1172 static int gmc_v7_0_soft_reset(void *handle)
1173 {
1174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1175         struct amdgpu_mode_mc_save save;
1176         u32 srbm_soft_reset = 0;
1177         u32 tmp = RREG32(mmSRBM_STATUS);
1178
1179         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1180                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1181                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1182
1183         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1184                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1185                 if (!(adev->flags & AMD_IS_APU))
1186                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1187                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1188         }
1189
1190         if (srbm_soft_reset) {
1191                 gmc_v7_0_mc_stop(adev, &save);
1192                 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1193                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1194                 }
1195
1196
1197                 tmp = RREG32(mmSRBM_SOFT_RESET);
1198                 tmp |= srbm_soft_reset;
1199                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1200                 WREG32(mmSRBM_SOFT_RESET, tmp);
1201                 tmp = RREG32(mmSRBM_SOFT_RESET);
1202
1203                 udelay(50);
1204
1205                 tmp &= ~srbm_soft_reset;
1206                 WREG32(mmSRBM_SOFT_RESET, tmp);
1207                 tmp = RREG32(mmSRBM_SOFT_RESET);
1208
1209                 /* Wait a little for things to settle down */
1210                 udelay(50);
1211
1212                 gmc_v7_0_mc_resume(adev, &save);
1213                 udelay(50);
1214         }
1215
1216         return 0;
1217 }
1218
1219 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1220                                              struct amdgpu_irq_src *src,
1221                                              unsigned type,
1222                                              enum amdgpu_interrupt_state state)
1223 {
1224         u32 tmp;
1225         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1226                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1227                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1228                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1229                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1230                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1231
1232         switch (state) {
1233         case AMDGPU_IRQ_STATE_DISABLE:
1234                 /* system context */
1235                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1236                 tmp &= ~bits;
1237                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1238                 /* VMs */
1239                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1240                 tmp &= ~bits;
1241                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1242                 break;
1243         case AMDGPU_IRQ_STATE_ENABLE:
1244                 /* system context */
1245                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1246                 tmp |= bits;
1247                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1248                 /* VMs */
1249                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1250                 tmp |= bits;
1251                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1252                 break;
1253         default:
1254                 break;
1255         }
1256
1257         return 0;
1258 }
1259
1260 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1261                                       struct amdgpu_irq_src *source,
1262                                       struct amdgpu_iv_entry *entry)
1263 {
1264         u32 addr, status, mc_client;
1265
1266         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1267         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1268         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1269         /* reset addr and status */
1270         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1271
1272         if (!addr && !status)
1273                 return 0;
1274
1275         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1276                 gmc_v7_0_set_fault_enable_default(adev, false);
1277
1278         if (printk_ratelimit()) {
1279                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1280                         entry->src_id, entry->src_data[0]);
1281                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1282                         addr);
1283                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1284                         status);
1285                 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1286         }
1287
1288         return 0;
1289 }
1290
1291 static int gmc_v7_0_set_clockgating_state(void *handle,
1292                                           enum amd_clockgating_state state)
1293 {
1294         bool gate = false;
1295         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296
1297         if (state == AMD_CG_STATE_GATE)
1298                 gate = true;
1299
1300         if (!(adev->flags & AMD_IS_APU)) {
1301                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1302                 gmc_v7_0_enable_mc_ls(adev, gate);
1303         }
1304         gmc_v7_0_enable_bif_mgls(adev, gate);
1305         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1306         gmc_v7_0_enable_hdp_ls(adev, gate);
1307
1308         return 0;
1309 }
1310
1311 static int gmc_v7_0_set_powergating_state(void *handle,
1312                                           enum amd_powergating_state state)
1313 {
1314         return 0;
1315 }
1316
1317 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1318         .name = "gmc_v7_0",
1319         .early_init = gmc_v7_0_early_init,
1320         .late_init = gmc_v7_0_late_init,
1321         .sw_init = gmc_v7_0_sw_init,
1322         .sw_fini = gmc_v7_0_sw_fini,
1323         .hw_init = gmc_v7_0_hw_init,
1324         .hw_fini = gmc_v7_0_hw_fini,
1325         .suspend = gmc_v7_0_suspend,
1326         .resume = gmc_v7_0_resume,
1327         .is_idle = gmc_v7_0_is_idle,
1328         .wait_for_idle = gmc_v7_0_wait_for_idle,
1329         .soft_reset = gmc_v7_0_soft_reset,
1330         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1331         .set_powergating_state = gmc_v7_0_set_powergating_state,
1332 };
1333
1334 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1335         .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1336         .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1337         .set_prt = gmc_v7_0_set_prt,
1338         .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags
1339 };
1340
1341 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1342         .set = gmc_v7_0_vm_fault_interrupt_state,
1343         .process = gmc_v7_0_process_interrupt,
1344 };
1345
1346 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1347 {
1348         if (adev->gart.gart_funcs == NULL)
1349                 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1350 }
1351
1352 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1353 {
1354         adev->mc.vm_fault.num_types = 1;
1355         adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1356 }
1357
1358 const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1359 {
1360         .type = AMD_IP_BLOCK_TYPE_GMC,
1361         .major = 7,
1362         .minor = 0,
1363         .rev = 0,
1364         .funcs = &gmc_v7_0_ip_funcs,
1365 };
1366
1367 const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1368 {
1369         .type = AMD_IP_BLOCK_TYPE_GMC,
1370         .major = 7,
1371         .minor = 4,
1372         .rev = 0,
1373         .funcs = &gmc_v7_0_ip_funcs,
1374 };