2 * Texas Instruments SN65DSI83 DSI to LVDS converter driver
4 * Copyright (C) 2016 Lothar Waßmann <LW@KARO-electronics.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #ifndef __DRM_I2C_SN65DSI83_H__
18 #define __DRM_I2C_SN65DSI83_H__
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
23 #include <drm/drm_crtc_helper.h>
24 #include <drm/drm_mipi_dsi.h>
26 #define SN65DSI83_REG_CHIPREV(n) (0x00 + (n))
28 #define SN65DSI83_REG_RSTCTRL 0x09
29 #define RSTCTRL_SOFT_RESET BIT(0)
31 #define SN65DSI83_REG_LVDSCTRL 0x0a
32 #define LVDSCTRL_PLL_EN_STAT BIT(7)
33 #define LVDSCTRL_LVDS_CLK_RANGE_SHIFT 1
34 #define LVDSCTRL_LVDS_CLK_RANGE_MASK (0x7 << LVDSCTRL_LVDS_CLK_RANGE_SHIFT)
35 #define LVDSCTRL_LVDS_CLK_RANGE(n) (((n) << LVDSCTRL_LVDS_CLK_RANGE_SHIFT) & \
36 LVDSCTRL_LVDS_CLK_RANGE_MASK)
37 #define LVDSCTRL_HS_CLK_SRC BIT(0)
39 #define SN65DSI83_REG_DSICTRL 0x0b
40 #define DSICTRL_DSI_CLK_DIVIDER_SHIFT 3
41 #define DSICTRL_DSI_CLK_DIVIDER_MASK (0x1f << DSICTRL_DSI_CLK_DIVIDER_SHIFT)
42 #define DSICTRL_DSI_CLK_DIVIDER(n) (((n) << DSICTRL_DSI_CLK_DIVIDER_SHIFT) & \
43 DSICTRL_DSI_CLK_DIVIDER_MASK)
44 #define DSICTRL_REFCLK_MULTIPLIER_SHIFT 0
45 #define DSICTRL_REFCLK_MULTIPLIER_MASK (0x3 << DSICTRL_REFCLK_MULTIPLIER_SHIFT)
46 #define DSICTRL_REFCLK_MULTIPLIER(n) (((n) << DSICTRL_REFCLK_MULTIPLIER_SHIFT) & \
47 DSICTRL_REFCLK_MULTIPLIER_MASK)
49 #define SN65DSI83_REG_PLLCTRL 0x0d
50 #define PLLCTRL_PLL_EN BIT(0)
52 #define SN65DSI83_REG_LVDSCFG0 0x10
53 #define SN65DSI83_REG_LVDSCFG1 0x11
54 #define SN65DSI83_REG_LVDSCFG2 0x12
55 #define SN65DSI83_REG_LVDSCFG3 0x13
56 #define SN65DSI83_REG_LVDSCFG4 0x18
57 #define SN65DSI83_REG_LVDSCFG5 0x19
58 #define SN65DSI83_REG_LVDSCFG6 0x1a
59 #define SN65DSI83_REG_LVDSCFG7 0x1b
61 #define SN65DSI83_REG_LINE_LENGTH_LSB 0x20
62 #define SN65DSI83_REG_LINE_LENGTH_MSB 0x21
63 #define SN65DSI83_REG_VERT_SIZE_LSB 0x24
64 #define SN65DSI83_REG_VERT_SIZE_MSB 0x25
65 #define SN65DSI83_REG_SYNC_DELAY_LSB 0x28
66 #define SN65DSI83_REG_SYNC_DELAY_MSB 0x29
67 #define SN65DSI83_REG_HSYNC_WIDTH_LSB 0x2c
68 #define SN65DSI83_REG_HSYNC_WIDTH_MSB 0x2d
69 #define SN65DSI83_REG_VSYNC_WIDTH_LSB 0x30
70 #define SN65DSI83_REG_VSYNC_WIDTH_MSB 0x31
71 #define SN65DSI83_REG_H_BACK_PORCH 0x34
72 #define SN65DSI83_REG_V_BACK_PORCH 0x36
73 #define SN65DSI83_REG_H_FRONT_PORCH 0x38
74 #define SN65DSI83_REG_V_FRONT_PORCH 0x3a
76 #define SN65DSI83_REG_TEST_PATTERN 0x3c
77 #define TEST_PATTERN_ENABLE BIT(4)
79 #define SN65DSI83_REG_IRQCTRL 0xe0
80 #define IRQCTRL_IRQ_EN BIT(0)
82 #define SN65DSI83_REG_IRQEN 0xe1
83 #define IRQEN_SYNCH_ERR BIT(7)
84 #define IRQEN_CRC_ERR BIT(6)
85 #define IRQEN_UNC_ECC_ERR BIT(5)
86 #define IRQEN_COR_ECC_ERR BIT(4)
87 #define IRQEN_LLP_ERR BIT(3)
88 #define IRQEN_SOT_BIT_ERR BIT(2)
89 #define IRQEN_PLL_UNLOCK BIT(0)
91 #define SN65DSI83_REG_ERRSTAT 0xe5
92 #define ERRSTAT_SYNCH_ERR BIT(7)
93 #define ERRSTAT_CRC_ERR BIT(6)
94 #define ERRSTAT_UNC_ECC_ERR BIT(5)
95 #define ERRSTAT_COR_ECC_ERR BIT(4)
96 #define ERRSTAT_LLP_ERR BIT(3)
97 #define ERRSTAT_SOT_BIT_ERR BIT(2)
98 #define ERRSTAT_PLL_UNLOCK BIT(0)
100 #endif /* __DRM_I2C_SN65DSI83_H__ */