1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_uncore.h"
59 #include "intel_bios.h"
60 #include "intel_dpll_mgr.h"
62 #include "intel_lrc.h"
63 #include "intel_ringbuffer.h"
66 #include "i915_gem_context.h"
67 #include "i915_gem_fence_reg.h"
68 #include "i915_gem_object.h"
69 #include "i915_gem_gtt.h"
70 #include "i915_gem_render_state.h"
71 #include "i915_gem_request.h"
72 #include "i915_gem_timeline.h"
76 #include "intel_gvt.h"
78 /* General customization:
81 #define DRIVER_NAME "i915"
82 #define DRIVER_DESC "Intel Graphics"
83 #define DRIVER_DATE "20170515"
84 #define DRIVER_TIMESTAMP 1494832308
86 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
88 * which may not necessarily be a user visible problem. This will either
89 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
90 * enable distros and users to tailor their preferred amount of i915 abrt
93 #define I915_STATE_WARN(condition, format...) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) \
96 if (!WARN(i915.verbose_state_checks, format)) \
98 unlikely(__ret_warn_on); \
101 #define I915_STATE_WARN_ON(x) \
102 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
104 bool __i915_inject_load_failure(const char *func, int line);
105 #define i915_inject_load_failure() \
106 __i915_inject_load_failure(__func__, __LINE__)
110 } uint_fixed_16_16_t;
112 #define FP_16_16_MAX ({ \
113 uint_fixed_16_16_t fp; \
118 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
120 uint_fixed_16_16_t fp;
128 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
130 return DIV_ROUND_UP(fp.val, 1 << 16);
133 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
138 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
139 uint_fixed_16_16_t min2)
141 uint_fixed_16_16_t min;
143 min.val = min(min1.val, min2.val);
147 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
148 uint_fixed_16_16_t max2)
150 uint_fixed_16_16_t max;
152 max.val = max(max1.val, max2.val);
156 static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
159 uint_fixed_16_16_t fp, res;
161 fp = u32_to_fixed_16_16(val);
162 res.val = DIV_ROUND_UP(fp.val, d);
166 static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
169 uint_fixed_16_16_t res;
172 interm_val = (uint64_t)val << 16;
173 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
174 WARN_ON(interm_val >> 32);
175 res.val = (uint32_t) interm_val;
180 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
181 uint_fixed_16_16_t mul)
183 uint64_t intermediate_val;
184 uint_fixed_16_16_t fp;
186 intermediate_val = (uint64_t) val * mul.val;
187 WARN_ON(intermediate_val >> 32);
188 fp.val = (uint32_t) intermediate_val;
192 static inline const char *yesno(bool v)
194 return v ? "yes" : "no";
197 static inline const char *onoff(bool v)
199 return v ? "on" : "off";
202 static inline const char *enableddisabled(bool v)
204 return v ? "enabled" : "disabled";
213 I915_MAX_PIPES = _PIPE_EDP
215 #define pipe_name(p) ((p) + 'A')
227 static inline const char *transcoder_name(enum transcoder transcoder)
229 switch (transcoder) {
238 case TRANSCODER_DSI_A:
240 case TRANSCODER_DSI_C:
247 static inline bool transcoder_is_dsi(enum transcoder transcoder)
249 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
253 * Global legacy plane identifier. Valid only for primary/sprite
254 * planes on pre-g4x, and only for primary planes on g4x+.
261 #define plane_name(p) ((p) + 'A')
263 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
266 * Per-pipe plane identifier.
267 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
268 * number of planes per CRTC. Not all platforms really have this many planes,
269 * which means some arrays of size I915_MAX_PLANES may have unused entries
270 * between the topmost sprite plane and the cursor plane.
272 * This is expected to be passed to various register macros
273 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
284 #define for_each_plane_id_on_crtc(__crtc, __p) \
285 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
286 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
297 #define port_name(p) ((p) + 'A')
299 #define I915_NUM_PHYS_VLV 2
312 enum intel_display_power_domain {
316 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
317 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
318 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
319 POWER_DOMAIN_TRANSCODER_A,
320 POWER_DOMAIN_TRANSCODER_B,
321 POWER_DOMAIN_TRANSCODER_C,
322 POWER_DOMAIN_TRANSCODER_EDP,
323 POWER_DOMAIN_TRANSCODER_DSI_A,
324 POWER_DOMAIN_TRANSCODER_DSI_C,
325 POWER_DOMAIN_PORT_DDI_A_LANES,
326 POWER_DOMAIN_PORT_DDI_B_LANES,
327 POWER_DOMAIN_PORT_DDI_C_LANES,
328 POWER_DOMAIN_PORT_DDI_D_LANES,
329 POWER_DOMAIN_PORT_DDI_E_LANES,
330 POWER_DOMAIN_PORT_DDI_A_IO,
331 POWER_DOMAIN_PORT_DDI_B_IO,
332 POWER_DOMAIN_PORT_DDI_C_IO,
333 POWER_DOMAIN_PORT_DDI_D_IO,
334 POWER_DOMAIN_PORT_DDI_E_IO,
335 POWER_DOMAIN_PORT_DSI,
336 POWER_DOMAIN_PORT_CRT,
337 POWER_DOMAIN_PORT_OTHER,
346 POWER_DOMAIN_MODESET,
352 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
353 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
354 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
355 #define POWER_DOMAIN_TRANSCODER(tran) \
356 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
357 (tran) + POWER_DOMAIN_TRANSCODER_A)
361 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
373 #define for_each_hpd_pin(__pin) \
374 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
376 #define HPD_STORM_DEFAULT_THRESHOLD 5
378 struct i915_hotplug {
379 struct work_struct hotplug_work;
382 unsigned long last_jiffies;
387 HPD_MARK_DISABLED = 2
389 } stats[HPD_NUM_PINS];
391 struct delayed_work reenable_work;
393 struct intel_digital_port *irq_port[I915_MAX_PORTS];
396 struct work_struct dig_port_work;
398 struct work_struct poll_init_work;
401 unsigned int hpd_storm_threshold;
404 * if we get a HPD irq from DP and a HPD irq from non-DP
405 * the non-DP HPD could block the workqueue on a mode config
406 * mutex getting, that userspace may have taken. However
407 * userspace is waiting on the DP workqueue to run which is
408 * blocked behind the non-DP one.
410 struct workqueue_struct *dp_wq;
413 #define I915_GEM_GPU_DOMAINS \
414 (I915_GEM_DOMAIN_RENDER | \
415 I915_GEM_DOMAIN_SAMPLER | \
416 I915_GEM_DOMAIN_COMMAND | \
417 I915_GEM_DOMAIN_INSTRUCTION | \
418 I915_GEM_DOMAIN_VERTEX)
420 #define for_each_pipe(__dev_priv, __p) \
421 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
422 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
423 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
424 for_each_if ((__mask) & (1 << (__p)))
425 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
427 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
429 #define for_each_sprite(__dev_priv, __p, __s) \
431 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
434 #define for_each_port_masked(__port, __ports_mask) \
435 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
436 for_each_if ((__ports_mask) & (1 << (__port)))
438 #define for_each_crtc(dev, crtc) \
439 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
441 #define for_each_intel_plane(dev, intel_plane) \
442 list_for_each_entry(intel_plane, \
443 &(dev)->mode_config.plane_list, \
446 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
447 list_for_each_entry(intel_plane, \
448 &(dev)->mode_config.plane_list, \
450 for_each_if ((plane_mask) & \
451 (1 << drm_plane_index(&intel_plane->base)))
453 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
454 list_for_each_entry(intel_plane, \
455 &(dev)->mode_config.plane_list, \
457 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
459 #define for_each_intel_crtc(dev, intel_crtc) \
460 list_for_each_entry(intel_crtc, \
461 &(dev)->mode_config.crtc_list, \
464 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
465 list_for_each_entry(intel_crtc, \
466 &(dev)->mode_config.crtc_list, \
468 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
470 #define for_each_intel_encoder(dev, intel_encoder) \
471 list_for_each_entry(intel_encoder, \
472 &(dev)->mode_config.encoder_list, \
475 #define for_each_intel_connector_iter(intel_connector, iter) \
476 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
478 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
479 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
480 for_each_if ((intel_encoder)->base.crtc == (__crtc))
482 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
483 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
484 for_each_if ((intel_connector)->base.encoder == (__encoder))
486 #define for_each_power_domain(domain, mask) \
487 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
488 for_each_if (BIT_ULL(domain) & (mask))
490 #define for_each_power_well(__dev_priv, __power_well) \
491 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
492 (__power_well) - (__dev_priv)->power_domains.power_wells < \
493 (__dev_priv)->power_domains.power_well_count; \
496 #define for_each_power_well_rev(__dev_priv, __power_well) \
497 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
498 (__dev_priv)->power_domains.power_well_count - 1; \
499 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
502 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
503 for_each_power_well(__dev_priv, __power_well) \
504 for_each_if ((__power_well)->domains & (__domain_mask))
506 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
507 for_each_power_well_rev(__dev_priv, __power_well) \
508 for_each_if ((__power_well)->domains & (__domain_mask))
510 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
512 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
513 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
514 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
516 for_each_if (plane_state)
518 struct drm_i915_private;
519 struct i915_mm_struct;
520 struct i915_mmu_object;
522 struct drm_i915_file_private {
523 struct drm_i915_private *dev_priv;
524 struct drm_file *file;
528 struct list_head request_list;
529 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
530 * chosen to prevent the CPU getting more than a frame ahead of the GPU
531 * (when using lax throttling for the frontbuffer). We also use it to
532 * offer free GPU waitboosts for severely congested workloads.
534 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
536 struct idr context_idr;
538 struct intel_rps_client {
539 struct list_head link;
543 unsigned int bsd_engine;
545 /* Client can have a maximum of 3 contexts banned before
546 * it is denied of creating new contexts. As one context
547 * ban needs 4 consecutive hangs, and more if there is
548 * progress in between, this is a last resort stop gap measure
549 * to limit the badly behaving clients access to gpu.
551 #define I915_MAX_CLIENT_CONTEXT_BANS 3
555 /* Used by dp and fdi links */
556 struct intel_link_m_n {
564 void intel_link_compute_m_n(int bpp, int nlanes,
565 int pixel_clock, int link_clock,
566 struct intel_link_m_n *m_n);
568 /* Interface history:
571 * 1.2: Add Power Management
572 * 1.3: Add vblank support
573 * 1.4: Fix cmdbuffer path, add heap destroy
574 * 1.5: Add vblank pipe configuration
575 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
576 * - Support vertical blank on secondary display pipe
578 #define DRIVER_MAJOR 1
579 #define DRIVER_MINOR 6
580 #define DRIVER_PATCHLEVEL 0
582 struct opregion_header;
583 struct opregion_acpi;
584 struct opregion_swsci;
585 struct opregion_asle;
587 struct intel_opregion {
588 struct opregion_header *header;
589 struct opregion_acpi *acpi;
590 struct opregion_swsci *swsci;
591 u32 swsci_gbda_sub_functions;
592 u32 swsci_sbcb_sub_functions;
593 struct opregion_asle *asle;
598 struct work_struct asle_work;
600 #define OPREGION_SIZE (8*1024)
602 struct intel_overlay;
603 struct intel_overlay_error_state;
605 struct sdvo_device_mapping {
614 struct intel_connector;
615 struct intel_encoder;
616 struct intel_atomic_state;
617 struct intel_crtc_state;
618 struct intel_initial_plane_config;
622 struct intel_cdclk_state;
624 struct drm_i915_display_funcs {
625 void (*get_cdclk)(struct drm_i915_private *dev_priv,
626 struct intel_cdclk_state *cdclk_state);
627 void (*set_cdclk)(struct drm_i915_private *dev_priv,
628 const struct intel_cdclk_state *cdclk_state);
629 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
630 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
631 int (*compute_intermediate_wm)(struct drm_device *dev,
632 struct intel_crtc *intel_crtc,
633 struct intel_crtc_state *newstate);
634 void (*initial_watermarks)(struct intel_atomic_state *state,
635 struct intel_crtc_state *cstate);
636 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
637 struct intel_crtc_state *cstate);
638 void (*optimize_watermarks)(struct intel_atomic_state *state,
639 struct intel_crtc_state *cstate);
640 int (*compute_global_watermarks)(struct drm_atomic_state *state);
641 void (*update_wm)(struct intel_crtc *crtc);
642 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
643 /* Returns the active state of the crtc, and if the crtc is active,
644 * fills out the pipe-config with the hw state. */
645 bool (*get_pipe_config)(struct intel_crtc *,
646 struct intel_crtc_state *);
647 void (*get_initial_plane_config)(struct intel_crtc *,
648 struct intel_initial_plane_config *);
649 int (*crtc_compute_clock)(struct intel_crtc *crtc,
650 struct intel_crtc_state *crtc_state);
651 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
652 struct drm_atomic_state *old_state);
653 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
654 struct drm_atomic_state *old_state);
655 void (*update_crtcs)(struct drm_atomic_state *state,
656 unsigned int *crtc_vblank_mask);
657 void (*audio_codec_enable)(struct drm_connector *connector,
658 struct intel_encoder *encoder,
659 const struct drm_display_mode *adjusted_mode);
660 void (*audio_codec_disable)(struct intel_encoder *encoder);
661 void (*fdi_link_train)(struct intel_crtc *crtc,
662 const struct intel_crtc_state *crtc_state);
663 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
664 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
665 struct drm_framebuffer *fb,
666 struct drm_i915_gem_object *obj,
667 struct drm_i915_gem_request *req,
669 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
670 /* clock updates for mode set */
672 /* render clock increase/decrease */
673 /* display clock increase/decrease */
674 /* pll clock increase/decrease */
676 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
677 void (*load_luts)(struct drm_crtc_state *crtc_state);
680 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
681 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
682 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
685 struct work_struct work;
687 uint32_t *dmc_payload;
688 uint32_t dmc_fw_size;
691 i915_reg_t mmioaddr[8];
692 uint32_t mmiodata[8];
694 uint32_t allowed_dc_mask;
697 #define DEV_INFO_FOR_EACH_FLAG(func) \
700 func(is_alpha_support); \
701 /* Keep has_* in alphabetical order */ \
702 func(has_64bit_reloc); \
703 func(has_aliasing_ppgtt); \
706 func(has_decoupled_mmio); \
709 func(has_fpga_dbg); \
710 func(has_full_ppgtt); \
711 func(has_full_48bit_ppgtt); \
712 func(has_gmbus_irq); \
713 func(has_gmch_display); \
718 func(has_logical_ring_contexts); \
720 func(has_pipe_cxsr); \
721 func(has_pooled_eu); \
725 func(has_resource_streamer); \
726 func(has_runtime_pm); \
728 func(unfenced_needs_alignment); \
729 func(cursor_needs_physical); \
730 func(hws_needs_physical); \
731 func(overlay_needs_physical); \
734 struct sseu_dev_info {
740 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
743 u8 has_subslice_pg:1;
747 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
749 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
752 /* Keep in gen based order, and chronological order within a gen */
753 enum intel_platform {
754 INTEL_PLATFORM_UNINITIALIZED = 0,
783 struct intel_device_info {
784 u32 display_mmio_offset;
787 u8 num_sprites[I915_MAX_PIPES];
788 u8 num_scalers[I915_MAX_PIPES];
791 enum intel_platform platform;
792 u8 ring_mask; /* Rings supported by the HW */
794 #define DEFINE_FLAG(name) u8 name:1
795 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
797 u16 ddb_size; /* in blocks */
798 /* Register offsets for the various display pipes and transcoders */
799 int pipe_offsets[I915_MAX_TRANSCODERS];
800 int trans_offsets[I915_MAX_TRANSCODERS];
801 int palette_offsets[I915_MAX_PIPES];
802 int cursor_offsets[I915_MAX_PIPES];
804 /* Slice/subslice/EU info */
805 struct sseu_dev_info sseu;
808 u16 degamma_lut_size;
813 struct intel_display_error_state;
815 struct i915_gpu_state {
818 struct timeval boottime;
819 struct timeval uptime;
821 struct drm_i915_private *i915;
831 struct intel_device_info device_info;
832 struct i915_params params;
834 /* Generic register state */
838 u32 gtier[4], ngtier;
842 u32 error; /* gen6+ */
843 u32 err_int; /* gen7 */
844 u32 fault_data0; /* gen8, gen9 */
845 u32 fault_data1; /* gen8, gen9 */
853 u64 fence[I915_MAX_NUM_FENCES];
854 struct intel_overlay_error_state *overlay;
855 struct intel_display_error_state *display;
856 struct drm_i915_error_object *semaphore;
857 struct drm_i915_error_object *guc_log;
859 struct drm_i915_error_engine {
861 /* Software tracked state */
864 unsigned long hangcheck_timestamp;
865 bool hangcheck_stalled;
866 enum intel_engine_hangcheck_action hangcheck_action;
867 struct i915_address_space *vm;
870 /* position of active request inside the ring */
871 u32 rq_head, rq_post, rq_tail;
873 /* our own tracking of ring head and tail */
896 u32 rc_psmi; /* sleep state */
897 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
898 struct intel_instdone instdone;
900 struct drm_i915_error_context {
901 char comm[TASK_COMM_LEN];
910 struct drm_i915_error_object {
916 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
918 struct drm_i915_error_object **user_bo;
921 struct drm_i915_error_object *wa_ctx;
923 struct drm_i915_error_request {
931 } *requests, execlist[2];
933 struct drm_i915_error_waiter {
934 char comm[TASK_COMM_LEN];
946 } engine[I915_NUM_ENGINES];
948 struct drm_i915_error_buffer {
951 u32 rseqno[I915_NUM_ENGINES], wseqno;
955 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
962 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
963 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
964 struct i915_address_space *active_vm[I915_NUM_ENGINES];
967 enum i915_cache_level {
969 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
970 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
971 caches, eg sampler/render caches, and the
972 large Last-Level-Cache. LLC is coherent with
973 the CPU, but L3 is only visible to the GPU. */
974 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
977 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
988 /* This is always the inner lock when overlapping with struct_mutex and
989 * it's the outer lock when overlapping with stolen_lock. */
992 unsigned int possible_framebuffer_bits;
993 unsigned int busy_bits;
994 unsigned int visible_pipes_mask;
995 struct intel_crtc *crtc;
997 struct drm_mm_node compressed_fb;
998 struct drm_mm_node *compressed_llb;
1005 bool underrun_detected;
1006 struct work_struct underrun_work;
1008 struct intel_fbc_state_cache {
1009 struct i915_vma *vma;
1012 unsigned int mode_flags;
1013 uint32_t hsw_bdw_pixel_rate;
1017 unsigned int rotation;
1024 const struct drm_format_info *format;
1025 unsigned int stride;
1029 struct intel_fbc_reg_params {
1030 struct i915_vma *vma;
1035 unsigned int fence_y_offset;
1039 const struct drm_format_info *format;
1040 unsigned int stride;
1046 struct intel_fbc_work {
1048 u32 scheduled_vblank;
1049 struct work_struct work;
1052 const char *no_fbc_reason;
1056 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1057 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1058 * parsing for same resolution.
1060 enum drrs_refresh_rate_type {
1063 DRRS_MAX_RR, /* RR count */
1066 enum drrs_support_type {
1067 DRRS_NOT_SUPPORTED = 0,
1068 STATIC_DRRS_SUPPORT = 1,
1069 SEAMLESS_DRRS_SUPPORT = 2
1075 struct delayed_work work;
1076 struct intel_dp *dp;
1077 unsigned busy_frontbuffer_bits;
1078 enum drrs_refresh_rate_type refresh_rate_type;
1079 enum drrs_support_type type;
1086 struct intel_dp *enabled;
1088 struct delayed_work work;
1089 unsigned busy_frontbuffer_bits;
1091 bool aux_frame_sync;
1093 bool y_cord_support;
1094 bool colorimetry_support;
1099 PCH_NONE = 0, /* No PCH present */
1100 PCH_IBX, /* Ibexpeak PCH */
1101 PCH_CPT, /* Cougarpoint PCH */
1102 PCH_LPT, /* Lynxpoint PCH */
1103 PCH_SPT, /* Sunrisepoint PCH */
1104 PCH_KBP, /* Kabypoint PCH */
1108 enum intel_sbi_destination {
1113 #define QUIRK_PIPEA_FORCE (1<<0)
1114 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1115 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1116 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1117 #define QUIRK_PIPEB_FORCE (1<<4)
1118 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1121 struct intel_fbc_work;
1123 struct intel_gmbus {
1124 struct i2c_adapter adapter;
1125 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1128 i915_reg_t gpio_reg;
1129 struct i2c_algo_bit_data bit_algo;
1130 struct drm_i915_private *dev_priv;
1133 struct i915_suspend_saved_registers {
1135 u32 saveFBC_CONTROL;
1136 u32 saveCACHE_MODE_0;
1137 u32 saveMI_ARB_STATE;
1141 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1142 u32 savePCH_PORT_HOTPLUG;
1146 struct vlv_s0ix_state {
1153 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1154 u32 media_max_req_count;
1155 u32 gfx_max_req_count;
1181 u32 rp_down_timeout;
1187 /* Display 1 CZ domain */
1192 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1194 /* GT SA CZ domain */
1201 /* Display 2 CZ domain */
1205 u32 clock_gate_dis2;
1208 struct intel_rps_ei {
1214 struct intel_gen6_power_mgmt {
1216 * work, interrupts_enabled and pm_iir are protected by
1217 * dev_priv->irq_lock
1219 struct work_struct work;
1220 bool interrupts_enabled;
1223 /* PM interrupt bits that should never be masked */
1226 /* Frequencies are stored in potentially platform dependent multiples.
1227 * In other words, *_freq needs to be multiplied by X to be interesting.
1228 * Soft limits are those which are used for the dynamic reclocking done
1229 * by the driver (raise frequencies under heavy loads, and lower for
1230 * lighter loads). Hard limits are those imposed by the hardware.
1232 * A distinction is made for overclocking, which is never enabled by
1233 * default, and is considered to be above the hard limit if it's
1236 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1237 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1238 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1239 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1240 u8 min_freq; /* AKA RPn. Minimum frequency */
1241 u8 boost_freq; /* Frequency to request when wait boosting */
1242 u8 idle_freq; /* Frequency to request when we are idle */
1243 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1244 u8 rp1_freq; /* "less than" RP0 power/freqency */
1245 u8 rp0_freq; /* Non-overclocked max frequency. */
1246 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1248 u8 up_threshold; /* Current %busy required to uplock */
1249 u8 down_threshold; /* Current %busy required to downclock */
1252 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1254 spinlock_t client_lock;
1255 struct list_head clients;
1259 struct delayed_work autoenable_work;
1262 /* manual wa residency calculations */
1263 struct intel_rps_ei ei;
1266 * Protects RPS/RC6 register access and PCU communication.
1267 * Must be taken after struct_mutex if nested. Note that
1268 * this lock may be held for long periods of time when
1269 * talking to hw - so only take it when talking to hw!
1271 struct mutex hw_lock;
1274 /* defined intel_pm.c */
1275 extern spinlock_t mchdev_lock;
1277 struct intel_ilk_power_mgmt {
1285 unsigned long last_time1;
1286 unsigned long chipset_power;
1289 unsigned long gfx_power;
1296 struct drm_i915_private;
1297 struct i915_power_well;
1299 struct i915_power_well_ops {
1301 * Synchronize the well's hw state to match the current sw state, for
1302 * example enable/disable it based on the current refcount. Called
1303 * during driver init and resume time, possibly after first calling
1304 * the enable/disable handlers.
1306 void (*sync_hw)(struct drm_i915_private *dev_priv,
1307 struct i915_power_well *power_well);
1309 * Enable the well and resources that depend on it (for example
1310 * interrupts located on the well). Called after the 0->1 refcount
1313 void (*enable)(struct drm_i915_private *dev_priv,
1314 struct i915_power_well *power_well);
1316 * Disable the well and resources that depend on it. Called after
1317 * the 1->0 refcount transition.
1319 void (*disable)(struct drm_i915_private *dev_priv,
1320 struct i915_power_well *power_well);
1321 /* Returns the hw enabled state. */
1322 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1323 struct i915_power_well *power_well);
1326 /* Power well structure for haswell */
1327 struct i915_power_well {
1330 /* power well enable/disable usage count */
1332 /* cached hw enabled state */
1335 /* unique identifier for this power well */
1338 * Arbitraty data associated with this power well. Platform and power
1342 const struct i915_power_well_ops *ops;
1345 struct i915_power_domains {
1347 * Power wells needed for initialization at driver init and suspend
1348 * time are on. They are kept on until after the first modeset.
1352 int power_well_count;
1355 int domain_use_count[POWER_DOMAIN_NUM];
1356 struct i915_power_well *power_wells;
1359 #define MAX_L3_SLICES 2
1360 struct intel_l3_parity {
1361 u32 *remap_info[MAX_L3_SLICES];
1362 struct work_struct error_work;
1366 struct i915_gem_mm {
1367 /** Memory allocator for GTT stolen memory */
1368 struct drm_mm stolen;
1369 /** Protects the usage of the GTT stolen memory allocator. This is
1370 * always the inner lock when overlapping with struct_mutex. */
1371 struct mutex stolen_lock;
1373 /** List of all objects in gtt_space. Used to restore gtt
1374 * mappings on resume */
1375 struct list_head bound_list;
1377 * List of objects which are not bound to the GTT (thus
1378 * are idle and not used by the GPU). These objects may or may
1379 * not actually have any pages attached.
1381 struct list_head unbound_list;
1383 /** List of all objects in gtt_space, currently mmaped by userspace.
1384 * All objects within this list must also be on bound_list.
1386 struct list_head userfault_list;
1389 * List of objects which are pending destruction.
1391 struct llist_head free_list;
1392 struct work_struct free_work;
1394 /** Usable portion of the GTT for GEM */
1395 dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1397 /** PPGTT used for aliasing the PPGTT with the GTT */
1398 struct i915_hw_ppgtt *aliasing_ppgtt;
1400 struct notifier_block oom_notifier;
1401 struct notifier_block vmap_notifier;
1402 struct shrinker shrinker;
1404 /** LRU list of objects with fence regs on them. */
1405 struct list_head fence_list;
1407 u64 unordered_timeline;
1409 /* the indicator for dispatch video commands on two BSD rings */
1410 atomic_t bsd_engine_dispatch_index;
1412 /** Bit 6 swizzling required for X tiling */
1413 uint32_t bit_6_swizzle_x;
1414 /** Bit 6 swizzling required for Y tiling */
1415 uint32_t bit_6_swizzle_y;
1417 /* accounting, useful for userland debugging */
1418 spinlock_t object_stat_lock;
1423 struct drm_i915_error_state_buf {
1424 struct drm_i915_private *i915;
1433 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1434 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1436 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1437 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1439 struct i915_gpu_error {
1440 /* For hangcheck timer */
1441 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1442 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1444 struct delayed_work hangcheck_work;
1446 /* For reset and error_state handling. */
1448 /* Protected by the above dev->gpu_error.lock. */
1449 struct i915_gpu_state *first_error;
1451 unsigned long missed_irq_rings;
1454 * State variable controlling the reset flow and count
1456 * This is a counter which gets incremented when reset is triggered,
1458 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1459 * meaning that any waiters holding onto the struct_mutex should
1460 * relinquish the lock immediately in order for the reset to start.
1462 * If reset is not completed succesfully, the I915_WEDGE bit is
1463 * set meaning that hardware is terminally sour and there is no
1464 * recovery. All waiters on the reset_queue will be woken when
1467 * This counter is used by the wait_seqno code to notice that reset
1468 * event happened and it needs to restart the entire ioctl (since most
1469 * likely the seqno it waited for won't ever signal anytime soon).
1471 * This is important for lock-free wait paths, where no contended lock
1472 * naturally enforces the correct ordering between the bail-out of the
1473 * waiter and the gpu reset work code.
1475 unsigned long reset_count;
1478 * flags: Control various stages of the GPU reset
1480 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1481 * other users acquiring the struct_mutex. To do this we set the
1482 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1483 * and then check for that bit before acquiring the struct_mutex (in
1484 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1485 * secondary role in preventing two concurrent global reset attempts.
1487 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1488 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1489 * but it may be held by some long running waiter (that we cannot
1490 * interrupt without causing trouble). Once we are ready to do the GPU
1491 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1492 * they already hold the struct_mutex and want to participate they can
1493 * inspect the bit and do the reset directly, otherwise the worker
1494 * waits for the struct_mutex.
1496 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1497 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1498 * i915_gem_request_alloc(), this bit is checked and the sequence
1499 * aborted (with -EIO reported to userspace) if set.
1501 unsigned long flags;
1502 #define I915_RESET_BACKOFF 0
1503 #define I915_RESET_HANDOFF 1
1504 #define I915_WEDGED (BITS_PER_LONG - 1)
1507 * Waitqueue to signal when a hang is detected. Used to for waiters
1508 * to release the struct_mutex for the reset to procede.
1510 wait_queue_head_t wait_queue;
1513 * Waitqueue to signal when the reset has completed. Used by clients
1514 * that wait for dev_priv->mm.wedged to settle.
1516 wait_queue_head_t reset_queue;
1518 /* For missed irq/seqno simulation. */
1519 unsigned long test_irq_rings;
1522 enum modeset_restore {
1523 MODESET_ON_LID_OPEN,
1528 #define DP_AUX_A 0x40
1529 #define DP_AUX_B 0x10
1530 #define DP_AUX_C 0x20
1531 #define DP_AUX_D 0x30
1533 #define DDC_PIN_B 0x05
1534 #define DDC_PIN_C 0x04
1535 #define DDC_PIN_D 0x06
1537 struct ddi_vbt_port_info {
1539 * This is an index in the HDMI/DVI DDI buffer translation table.
1540 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1541 * populate this field.
1543 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1544 uint8_t hdmi_level_shift;
1546 uint8_t supports_dvi:1;
1547 uint8_t supports_hdmi:1;
1548 uint8_t supports_dp:1;
1549 uint8_t supports_edp:1;
1551 uint8_t alternate_aux_channel;
1552 uint8_t alternate_ddc_pin;
1554 uint8_t dp_boost_level;
1555 uint8_t hdmi_boost_level;
1558 enum psr_lines_to_wait {
1559 PSR_0_LINES_TO_WAIT = 0,
1561 PSR_4_LINES_TO_WAIT,
1565 struct intel_vbt_data {
1566 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1567 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1570 unsigned int int_tv_support:1;
1571 unsigned int lvds_dither:1;
1572 unsigned int lvds_vbt:1;
1573 unsigned int int_crt_support:1;
1574 unsigned int lvds_use_ssc:1;
1575 unsigned int display_clock_mode:1;
1576 unsigned int fdi_rx_polarity_inverted:1;
1577 unsigned int panel_type:4;
1579 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1581 enum drrs_support_type drrs_type;
1592 struct edp_power_seq pps;
1597 bool require_aux_wakeup;
1599 enum psr_lines_to_wait lines_to_wait;
1600 int tp1_wakeup_time;
1601 int tp2_tp3_wakeup_time;
1607 bool active_low_pwm;
1608 u8 min_brightness; /* min_brightness/255 of max */
1609 u8 controller; /* brightness controller number */
1610 enum intel_backlight_type type;
1616 struct mipi_config *config;
1617 struct mipi_pps_data *pps;
1621 const u8 *sequence[MIPI_SEQ_MAX];
1627 union child_device_config *child_dev;
1629 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1630 struct sdvo_device_mapping sdvo_mappings[2];
1633 enum intel_ddb_partitioning {
1635 INTEL_DDB_PART_5_6, /* IVB+ */
1638 struct intel_wm_level {
1646 struct ilk_wm_values {
1647 uint32_t wm_pipe[3];
1649 uint32_t wm_lp_spr[3];
1650 uint32_t wm_linetime[3];
1652 enum intel_ddb_partitioning partitioning;
1655 struct g4x_pipe_wm {
1656 uint16_t plane[I915_MAX_PLANES];
1666 struct vlv_wm_ddl_values {
1667 uint8_t plane[I915_MAX_PLANES];
1670 struct vlv_wm_values {
1671 struct g4x_pipe_wm pipe[3];
1672 struct g4x_sr_wm sr;
1673 struct vlv_wm_ddl_values ddl[3];
1678 struct g4x_wm_values {
1679 struct g4x_pipe_wm pipe[2];
1680 struct g4x_sr_wm sr;
1681 struct g4x_sr_wm hpll;
1687 struct skl_ddb_entry {
1688 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1691 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1693 return entry->end - entry->start;
1696 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1697 const struct skl_ddb_entry *e2)
1699 if (e1->start == e2->start && e1->end == e2->end)
1705 struct skl_ddb_allocation {
1706 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1707 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1710 struct skl_wm_values {
1711 unsigned dirty_pipes;
1712 struct skl_ddb_allocation ddb;
1715 struct skl_wm_level {
1717 uint16_t plane_res_b;
1718 uint8_t plane_res_l;
1722 * This struct helps tracking the state needed for runtime PM, which puts the
1723 * device in PCI D3 state. Notice that when this happens, nothing on the
1724 * graphics device works, even register access, so we don't get interrupts nor
1727 * Every piece of our code that needs to actually touch the hardware needs to
1728 * either call intel_runtime_pm_get or call intel_display_power_get with the
1729 * appropriate power domain.
1731 * Our driver uses the autosuspend delay feature, which means we'll only really
1732 * suspend if we stay with zero refcount for a certain amount of time. The
1733 * default value is currently very conservative (see intel_runtime_pm_enable), but
1734 * it can be changed with the standard runtime PM files from sysfs.
1736 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1737 * goes back to false exactly before we reenable the IRQs. We use this variable
1738 * to check if someone is trying to enable/disable IRQs while they're supposed
1739 * to be disabled. This shouldn't happen and we'll print some error messages in
1742 * For more, read the Documentation/power/runtime_pm.txt.
1744 struct i915_runtime_pm {
1745 atomic_t wakeref_count;
1750 enum intel_pipe_crc_source {
1751 INTEL_PIPE_CRC_SOURCE_NONE,
1752 INTEL_PIPE_CRC_SOURCE_PLANE1,
1753 INTEL_PIPE_CRC_SOURCE_PLANE2,
1754 INTEL_PIPE_CRC_SOURCE_PF,
1755 INTEL_PIPE_CRC_SOURCE_PIPE,
1756 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1757 INTEL_PIPE_CRC_SOURCE_TV,
1758 INTEL_PIPE_CRC_SOURCE_DP_B,
1759 INTEL_PIPE_CRC_SOURCE_DP_C,
1760 INTEL_PIPE_CRC_SOURCE_DP_D,
1761 INTEL_PIPE_CRC_SOURCE_AUTO,
1762 INTEL_PIPE_CRC_SOURCE_MAX,
1765 struct intel_pipe_crc_entry {
1770 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1771 struct intel_pipe_crc {
1773 bool opened; /* exclusive access to the result file */
1774 struct intel_pipe_crc_entry *entries;
1775 enum intel_pipe_crc_source source;
1777 wait_queue_head_t wq;
1781 struct i915_frontbuffer_tracking {
1785 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1792 struct i915_wa_reg {
1795 /* bitmask representing WA bits */
1800 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1801 * allowing it for RCS as we don't foresee any requirement of having
1802 * a whitelist for other engines. When it is really required for
1803 * other engines then the limit need to be increased.
1805 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1807 struct i915_workarounds {
1808 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1810 u32 hw_whitelist_count[I915_NUM_ENGINES];
1813 struct i915_virtual_gpu {
1817 /* used in computing the new watermarks state */
1818 struct intel_wm_config {
1819 unsigned int num_pipes_active;
1820 bool sprites_enabled;
1821 bool sprites_scaled;
1824 struct i915_oa_format {
1829 struct i915_oa_reg {
1834 struct i915_perf_stream;
1837 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1839 struct i915_perf_stream_ops {
1841 * @enable: Enables the collection of HW samples, either in response to
1842 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1843 * without `I915_PERF_FLAG_DISABLED`.
1845 void (*enable)(struct i915_perf_stream *stream);
1848 * @disable: Disables the collection of HW samples, either in response
1849 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1852 void (*disable)(struct i915_perf_stream *stream);
1855 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1856 * once there is something ready to read() for the stream
1858 void (*poll_wait)(struct i915_perf_stream *stream,
1863 * @wait_unlocked: For handling a blocking read, wait until there is
1864 * something to ready to read() for the stream. E.g. wait on the same
1865 * wait queue that would be passed to poll_wait().
1867 int (*wait_unlocked)(struct i915_perf_stream *stream);
1870 * @read: Copy buffered metrics as records to userspace
1871 * **buf**: the userspace, destination buffer
1872 * **count**: the number of bytes to copy, requested by userspace
1873 * **offset**: zero at the start of the read, updated as the read
1874 * proceeds, it represents how many bytes have been copied so far and
1875 * the buffer offset for copying the next record.
1877 * Copy as many buffered i915 perf samples and records for this stream
1878 * to userspace as will fit in the given buffer.
1880 * Only write complete records; returning -%ENOSPC if there isn't room
1881 * for a complete record.
1883 * Return any error condition that results in a short read such as
1884 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1885 * returning to userspace.
1887 int (*read)(struct i915_perf_stream *stream,
1893 * @destroy: Cleanup any stream specific resources.
1895 * The stream will always be disabled before this is called.
1897 void (*destroy)(struct i915_perf_stream *stream);
1901 * struct i915_perf_stream - state for a single open stream FD
1903 struct i915_perf_stream {
1905 * @dev_priv: i915 drm device
1907 struct drm_i915_private *dev_priv;
1910 * @link: Links the stream into ``&drm_i915_private->streams``
1912 struct list_head link;
1915 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1916 * properties given when opening a stream, representing the contents
1917 * of a single sample as read() by userspace.
1922 * @sample_size: Considering the configured contents of a sample
1923 * combined with the required header size, this is the total size
1924 * of a single sample record.
1929 * @ctx: %NULL if measuring system-wide across all contexts or a
1930 * specific context that is being monitored.
1932 struct i915_gem_context *ctx;
1935 * @enabled: Whether the stream is currently enabled, considering
1936 * whether the stream was opened in a disabled state and based
1937 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1942 * @ops: The callbacks providing the implementation of this specific
1943 * type of configured stream.
1945 const struct i915_perf_stream_ops *ops;
1949 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1951 struct i915_oa_ops {
1953 * @init_oa_buffer: Resets the head and tail pointers of the
1954 * circular buffer for periodic OA reports.
1956 * Called when first opening a stream for OA metrics, but also may be
1957 * called in response to an OA buffer overflow or other error
1960 * Note it may be necessary to clear the full OA buffer here as part of
1961 * maintaining the invariable that new reports must be written to
1962 * zeroed memory for us to be able to reliable detect if an expected
1963 * report has not yet landed in memory. (At least on Haswell the OA
1964 * buffer tail pointer is not synchronized with reports being visible
1967 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1970 * @enable_metric_set: Applies any MUX configuration to set up the
1971 * Boolean and Custom (B/C) counters that are part of the counter
1972 * reports being sampled. May apply system constraints such as
1973 * disabling EU clock gating as required.
1975 int (*enable_metric_set)(struct drm_i915_private *dev_priv);
1978 * @disable_metric_set: Remove system constraints associated with using
1981 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1984 * @oa_enable: Enable periodic sampling
1986 void (*oa_enable)(struct drm_i915_private *dev_priv);
1989 * @oa_disable: Disable periodic sampling
1991 void (*oa_disable)(struct drm_i915_private *dev_priv);
1994 * @read: Copy data from the circular OA buffer into a given userspace
1997 int (*read)(struct i915_perf_stream *stream,
2003 * @oa_buffer_check: Check for OA buffer data + update tail
2005 * This is either called via fops or the poll check hrtimer (atomic
2006 * ctx) without any locks taken.
2008 * It's safe to read OA config state here unlocked, assuming that this
2009 * is only called while the stream is enabled, while the global OA
2010 * configuration can't be modified.
2012 * Efficiency is more important than avoiding some false positives
2013 * here, which will be handled gracefully - likely resulting in an
2014 * %EAGAIN error for userspace.
2016 bool (*oa_buffer_check)(struct drm_i915_private *dev_priv);
2019 struct intel_cdclk_state {
2020 unsigned int cdclk, vco, ref;
2023 struct drm_i915_private {
2024 struct drm_device drm;
2026 struct kmem_cache *objects;
2027 struct kmem_cache *vmas;
2028 struct kmem_cache *requests;
2029 struct kmem_cache *dependencies;
2030 struct kmem_cache *priorities;
2032 const struct intel_device_info info;
2036 struct intel_uncore uncore;
2038 struct i915_virtual_gpu vgpu;
2040 struct intel_gvt *gvt;
2042 struct intel_huc huc;
2043 struct intel_guc guc;
2045 struct intel_csr csr;
2047 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2049 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2050 * controller on different i2c buses. */
2051 struct mutex gmbus_mutex;
2054 * Base address of the gmbus and gpio block.
2056 uint32_t gpio_mmio_base;
2058 /* MMIO base address for MIPI regs */
2059 uint32_t mipi_mmio_base;
2061 uint32_t psr_mmio_base;
2063 uint32_t pps_mmio_base;
2065 wait_queue_head_t gmbus_wait_queue;
2067 struct pci_dev *bridge_dev;
2068 struct i915_gem_context *kernel_context;
2069 struct intel_engine_cs *engine[I915_NUM_ENGINES];
2070 struct i915_vma *semaphore;
2072 struct drm_dma_handle *status_page_dmah;
2073 struct resource mch_res;
2075 /* protects the irq masks */
2076 spinlock_t irq_lock;
2078 /* protects the mmio flip data */
2079 spinlock_t mmio_flip_lock;
2081 bool display_irqs_enabled;
2083 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2084 struct pm_qos_request pm_qos;
2086 /* Sideband mailbox protection */
2087 struct mutex sb_lock;
2089 /** Cached value of IMR to avoid reads in updating the bitfield */
2092 u32 de_irq_mask[I915_MAX_PIPES];
2099 u32 pipestat_irq_mask[I915_MAX_PIPES];
2101 struct i915_hotplug hotplug;
2102 struct intel_fbc fbc;
2103 struct i915_drrs drrs;
2104 struct intel_opregion opregion;
2105 struct intel_vbt_data vbt;
2107 bool preserve_bios_swizzle;
2110 struct intel_overlay *overlay;
2112 /* backlight registers and fields in struct intel_panel */
2113 struct mutex backlight_lock;
2116 bool no_aux_handshake;
2118 /* protects panel power sequencer state */
2119 struct mutex pps_mutex;
2121 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2122 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2124 unsigned int fsb_freq, mem_freq, is_ddr3;
2125 unsigned int skl_preferred_vco_freq;
2126 unsigned int max_cdclk_freq;
2128 unsigned int max_dotclk_freq;
2129 unsigned int rawclk_freq;
2130 unsigned int hpll_freq;
2131 unsigned int czclk_freq;
2135 * The current logical cdclk state.
2136 * See intel_atomic_state.cdclk.logical
2138 * For reading holding any crtc lock is sufficient,
2139 * for writing must hold all of them.
2141 struct intel_cdclk_state logical;
2143 * The current actual cdclk state.
2144 * See intel_atomic_state.cdclk.actual
2146 struct intel_cdclk_state actual;
2147 /* The current hardware cdclk state */
2148 struct intel_cdclk_state hw;
2152 * wq - Driver workqueue for GEM.
2154 * NOTE: Work items scheduled here are not allowed to grab any modeset
2155 * locks, for otherwise the flushing done in the pageflip code will
2156 * result in deadlocks.
2158 struct workqueue_struct *wq;
2160 /* Display functions */
2161 struct drm_i915_display_funcs display;
2163 /* PCH chipset type */
2164 enum intel_pch pch_type;
2165 unsigned short pch_id;
2167 unsigned long quirks;
2169 enum modeset_restore modeset_restore;
2170 struct mutex modeset_restore_lock;
2171 struct drm_atomic_state *modeset_restore_state;
2172 struct drm_modeset_acquire_ctx reset_ctx;
2174 struct list_head vm_list; /* Global list of all address spaces */
2175 struct i915_ggtt ggtt; /* VM representing the global address space */
2177 struct i915_gem_mm mm;
2178 DECLARE_HASHTABLE(mm_structs, 7);
2179 struct mutex mm_lock;
2181 /* The hw wants to have a stable context identifier for the lifetime
2182 * of the context (for OA, PASID, faults, etc). This is limited
2183 * in execlists to 21 bits.
2185 struct ida context_hw_ida;
2186 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2188 /* Kernel Modesetting */
2190 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2191 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2192 wait_queue_head_t pending_flip_queue;
2194 #ifdef CONFIG_DEBUG_FS
2195 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2198 /* dpll and cdclk state is protected by connection_mutex */
2199 int num_shared_dpll;
2200 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2201 const struct intel_dpll_mgr *dpll_mgr;
2204 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2205 * Must be global rather than per dpll, because on some platforms
2206 * plls share registers.
2208 struct mutex dpll_lock;
2210 unsigned int active_crtcs;
2211 unsigned int min_pixclk[I915_MAX_PIPES];
2213 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2215 struct i915_workarounds workarounds;
2217 struct i915_frontbuffer_tracking fb_tracking;
2219 struct intel_atomic_helper {
2220 struct llist_head free_list;
2221 struct work_struct free_work;
2226 bool mchbar_need_disable;
2228 struct intel_l3_parity l3_parity;
2230 /* Cannot be determined by PCIID. You must always read a register. */
2233 /* gen6+ rps state */
2234 struct intel_gen6_power_mgmt rps;
2236 /* ilk-only ips/rps state. Everything in here is protected by the global
2237 * mchdev_lock in intel_pm.c */
2238 struct intel_ilk_power_mgmt ips;
2240 struct i915_power_domains power_domains;
2242 struct i915_psr psr;
2244 struct i915_gpu_error gpu_error;
2246 struct drm_i915_gem_object *vlv_pctx;
2248 #ifdef CONFIG_DRM_FBDEV_EMULATION
2249 /* list of fbdev register on this device */
2250 struct intel_fbdev *fbdev;
2251 struct work_struct fbdev_suspend_work;
2254 struct drm_property *broadcast_rgb_property;
2255 struct drm_property *force_audio_property;
2257 /* hda/i915 audio component */
2258 struct i915_audio_component *audio_component;
2259 bool audio_component_registered;
2261 * av_mutex - mutex for audio/video sync
2264 struct mutex av_mutex;
2266 struct list_head context_list;
2270 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2271 u32 chv_phy_control;
2273 * Shadows for CHV DPLL_MD regs to keep the state
2274 * checker somewhat working in the presence hardware
2275 * crappiness (can't read out DPLL_MD for pipes B & C).
2277 u32 chv_dpll_md[I915_MAX_PIPES];
2281 bool suspended_to_idle;
2282 struct i915_suspend_saved_registers regfile;
2283 struct vlv_s0ix_state vlv_s0ix_state;
2286 I915_SAGV_UNKNOWN = 0,
2289 I915_SAGV_NOT_CONTROLLED
2294 * Raw watermark latency values:
2295 * in 0.1us units for WM0,
2296 * in 0.5us units for WM1+.
2299 uint16_t pri_latency[5];
2301 uint16_t spr_latency[5];
2303 uint16_t cur_latency[5];
2305 * Raw watermark memory latency values
2306 * for SKL for all 8 levels
2309 uint16_t skl_latency[8];
2311 /* current hardware state */
2313 struct ilk_wm_values hw;
2314 struct skl_wm_values skl_hw;
2315 struct vlv_wm_values vlv;
2316 struct g4x_wm_values g4x;
2322 * Should be held around atomic WM register writing; also
2323 * protects * intel_crtc->wm.active and
2324 * cstate->wm.need_postvbl_update.
2326 struct mutex wm_mutex;
2329 * Set during HW readout of watermarks/DDB. Some platforms
2330 * need to know when we're still using BIOS-provided values
2331 * (which we don't fully trust).
2333 bool distrust_bios_wm;
2336 struct i915_runtime_pm pm;
2341 struct kobject *metrics_kobj;
2342 struct ctl_table_header *sysctl_header;
2345 struct list_head streams;
2347 spinlock_t hook_lock;
2350 struct i915_perf_stream *exclusive_stream;
2352 u32 specific_ctx_id;
2354 struct hrtimer poll_check_timer;
2355 wait_queue_head_t poll_wq;
2359 * For rate limiting any notifications of spurious
2360 * invalid OA reports
2362 struct ratelimit_state spurious_report_rs;
2365 int period_exponent;
2369 const struct i915_oa_reg *mux_regs;
2371 const struct i915_oa_reg *b_counter_regs;
2372 int b_counter_regs_len;
2375 struct i915_vma *vma;
2381 * Locks reads and writes to all head/tail state
2383 * Consider: the head and tail pointer state
2384 * needs to be read consistently from a hrtimer
2385 * callback (atomic context) and read() fop
2386 * (user context) with tail pointer updates
2387 * happening in atomic context and head updates
2388 * in user context and the (unlikely)
2389 * possibility of read() errors needing to
2390 * reset all head/tail state.
2392 * Note: Contention or performance aren't
2393 * currently a significant concern here
2394 * considering the relatively low frequency of
2395 * hrtimer callbacks (5ms period) and that
2396 * reads typically only happen in response to a
2397 * hrtimer event and likely complete before the
2400 * Note: This lock is not held *while* reading
2401 * and copying data to userspace so the value
2402 * of head observed in htrimer callbacks won't
2403 * represent any partial consumption of data.
2405 spinlock_t ptr_lock;
2408 * One 'aging' tail pointer and one 'aged'
2409 * tail pointer ready to used for reading.
2411 * Initial values of 0xffffffff are invalid
2412 * and imply that an update is required
2413 * (and should be ignored by an attempted
2421 * Index for the aged tail ready to read()
2424 unsigned int aged_tail_idx;
2427 * A monotonic timestamp for when the current
2428 * aging tail pointer was read; used to
2429 * determine when it is old enough to trust.
2431 u64 aging_timestamp;
2434 * Although we can always read back the head
2435 * pointer register, we prefer to avoid
2436 * trusting the HW state, just to avoid any
2437 * risk that some hardware condition could
2438 * somehow bump the head pointer unpredictably
2439 * and cause us to forward the wrong OA buffer
2440 * data to userspace.
2445 u32 gen7_latched_oastatus1;
2447 struct i915_oa_ops ops;
2448 const struct i915_oa_format *oa_formats;
2453 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2455 void (*resume)(struct drm_i915_private *);
2456 void (*cleanup_engine)(struct intel_engine_cs *engine);
2458 struct list_head timelines;
2459 struct i915_gem_timeline global_timeline;
2460 u32 active_requests;
2463 * Is the GPU currently considered idle, or busy executing
2464 * userspace requests? Whilst idle, we allow runtime power
2465 * management to power down the hardware and display clocks.
2466 * In order to reduce the effect on performance, there
2467 * is a slight delay before we do so.
2472 * We leave the user IRQ off as much as possible,
2473 * but this means that requests will finish and never
2474 * be retired once the system goes idle. Set a timer to
2475 * fire periodically while the ring is running. When it
2476 * fires, go retire requests.
2478 struct delayed_work retire_work;
2481 * When we detect an idle GPU, we want to turn on
2482 * powersaving features. So once we see that there
2483 * are no more requests outstanding and no more
2484 * arrive within a small period of time, we fire
2485 * off the idle_work.
2487 struct delayed_work idle_work;
2489 ktime_t last_init_time;
2492 /* perform PHY state sanity checks? */
2493 bool chv_phy_assert[2];
2497 /* Used to save the pipe-to-encoder mapping for audio */
2498 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2500 /* necessary resource sharing with HDMI LPE audio driver. */
2502 struct platform_device *platdev;
2507 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2508 * will be rejected. Instead look for a better place.
2512 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2514 return container_of(dev, struct drm_i915_private, drm);
2517 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2519 return to_i915(dev_get_drvdata(kdev));
2522 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2524 return container_of(guc, struct drm_i915_private, guc);
2527 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2529 return container_of(huc, struct drm_i915_private, huc);
2532 /* Simple iterator over all initialised engines */
2533 #define for_each_engine(engine__, dev_priv__, id__) \
2535 (id__) < I915_NUM_ENGINES; \
2537 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2539 /* Iterator over subset of engines selected by mask */
2540 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2541 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2542 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2544 enum hdmi_force_audio {
2545 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2546 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2547 HDMI_AUDIO_AUTO, /* trust EDID */
2548 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2551 #define I915_GTT_OFFSET_NONE ((u32)-1)
2554 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2555 * considered to be the frontbuffer for the given plane interface-wise. This
2556 * doesn't mean that the hw necessarily already scans it out, but that any
2557 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2559 * We have one bit per pipe and per scanout plane type.
2561 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2562 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2563 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2564 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2565 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2566 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2567 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2568 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2569 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2570 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2571 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2572 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2575 * Optimised SGL iterator for GEM objects
2577 static __always_inline struct sgt_iter {
2578 struct scatterlist *sgp;
2585 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2586 struct sgt_iter s = { .sgp = sgl };
2589 s.max = s.curr = s.sgp->offset;
2590 s.max += s.sgp->length;
2592 s.dma = sg_dma_address(s.sgp);
2594 s.pfn = page_to_pfn(sg_page(s.sgp));
2600 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2603 if (unlikely(sg_is_chain(sg)))
2604 sg = sg_chain_ptr(sg);
2609 * __sg_next - return the next scatterlist entry in a list
2610 * @sg: The current sg entry
2613 * If the entry is the last, return NULL; otherwise, step to the next
2614 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2615 * otherwise just return the pointer to the current element.
2617 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2619 #ifdef CONFIG_DEBUG_SG
2620 BUG_ON(sg->sg_magic != SG_MAGIC);
2622 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2626 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2627 * @__dmap: DMA address (output)
2628 * @__iter: 'struct sgt_iter' (iterator state, internal)
2629 * @__sgt: sg_table to iterate over (input)
2631 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2632 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2633 ((__dmap) = (__iter).dma + (__iter).curr); \
2634 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2635 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2638 * for_each_sgt_page - iterate over the pages of the given sg_table
2639 * @__pp: page pointer (output)
2640 * @__iter: 'struct sgt_iter' (iterator state, internal)
2641 * @__sgt: sg_table to iterate over (input)
2643 #define for_each_sgt_page(__pp, __iter, __sgt) \
2644 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2645 ((__pp) = (__iter).pfn == 0 ? NULL : \
2646 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2647 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2648 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2650 static inline const struct intel_device_info *
2651 intel_info(const struct drm_i915_private *dev_priv)
2653 return &dev_priv->info;
2656 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2658 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2659 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2661 #define REVID_FOREVER 0xff
2662 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2664 #define GEN_FOREVER (0)
2666 * Returns true if Gen is in inclusive range [Start, End].
2668 * Use GEN_FOREVER for unbound start and or end.
2670 #define IS_GEN(dev_priv, s, e) ({ \
2671 unsigned int __s = (s), __e = (e); \
2672 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2673 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2674 if ((__s) != GEN_FOREVER) \
2676 if ((__e) == GEN_FOREVER) \
2677 __e = BITS_PER_LONG - 1; \
2680 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2684 * Return true if revision is in range [since,until] inclusive.
2686 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2688 #define IS_REVID(p, since, until) \
2689 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2691 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2692 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2693 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2694 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2695 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2696 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2697 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2698 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2699 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2700 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2701 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2702 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2703 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2704 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2705 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2706 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2707 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2708 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2709 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2710 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2711 INTEL_DEVID(dev_priv) == 0x0152 || \
2712 INTEL_DEVID(dev_priv) == 0x015a)
2713 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2714 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2715 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2716 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2717 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2718 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2719 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2720 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2721 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2722 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2723 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2724 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2725 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2726 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2727 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2728 /* ULX machines are also considered ULT. */
2729 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2730 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2731 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2732 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2733 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2734 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2735 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2736 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2737 /* ULX machines are also considered ULT. */
2738 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2739 INTEL_DEVID(dev_priv) == 0x0A1E)
2740 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2741 INTEL_DEVID(dev_priv) == 0x1913 || \
2742 INTEL_DEVID(dev_priv) == 0x1916 || \
2743 INTEL_DEVID(dev_priv) == 0x1921 || \
2744 INTEL_DEVID(dev_priv) == 0x1926)
2745 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2746 INTEL_DEVID(dev_priv) == 0x1915 || \
2747 INTEL_DEVID(dev_priv) == 0x191E)
2748 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2749 INTEL_DEVID(dev_priv) == 0x5913 || \
2750 INTEL_DEVID(dev_priv) == 0x5916 || \
2751 INTEL_DEVID(dev_priv) == 0x5921 || \
2752 INTEL_DEVID(dev_priv) == 0x5926)
2753 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2754 INTEL_DEVID(dev_priv) == 0x5915 || \
2755 INTEL_DEVID(dev_priv) == 0x591E)
2756 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2757 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2758 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2759 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2761 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2763 #define SKL_REVID_A0 0x0
2764 #define SKL_REVID_B0 0x1
2765 #define SKL_REVID_C0 0x2
2766 #define SKL_REVID_D0 0x3
2767 #define SKL_REVID_E0 0x4
2768 #define SKL_REVID_F0 0x5
2769 #define SKL_REVID_G0 0x6
2770 #define SKL_REVID_H0 0x7
2772 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2774 #define BXT_REVID_A0 0x0
2775 #define BXT_REVID_A1 0x1
2776 #define BXT_REVID_B0 0x3
2777 #define BXT_REVID_B_LAST 0x8
2778 #define BXT_REVID_C0 0x9
2780 #define IS_BXT_REVID(dev_priv, since, until) \
2781 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2783 #define KBL_REVID_A0 0x0
2784 #define KBL_REVID_B0 0x1
2785 #define KBL_REVID_C0 0x2
2786 #define KBL_REVID_D0 0x3
2787 #define KBL_REVID_E0 0x4
2789 #define IS_KBL_REVID(dev_priv, since, until) \
2790 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2792 #define GLK_REVID_A0 0x0
2793 #define GLK_REVID_A1 0x1
2795 #define IS_GLK_REVID(dev_priv, since, until) \
2796 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2799 * The genX designation typically refers to the render engine, so render
2800 * capability related checks should use IS_GEN, while display and other checks
2801 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2804 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2805 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2806 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2807 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2808 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2809 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2810 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2811 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2813 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2814 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2815 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2817 #define ENGINE_MASK(id) BIT(id)
2818 #define RENDER_RING ENGINE_MASK(RCS)
2819 #define BSD_RING ENGINE_MASK(VCS)
2820 #define BLT_RING ENGINE_MASK(BCS)
2821 #define VEBOX_RING ENGINE_MASK(VECS)
2822 #define BSD2_RING ENGINE_MASK(VCS2)
2823 #define ALL_ENGINES (~0)
2825 #define HAS_ENGINE(dev_priv, id) \
2826 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2828 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2829 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2830 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2831 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2833 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2834 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2835 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2836 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2837 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2839 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2841 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2842 ((dev_priv)->info.has_logical_ring_contexts)
2843 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2844 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2845 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2847 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2848 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2849 ((dev_priv)->info.overlay_needs_physical)
2851 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2852 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2854 /* WaRsDisableCoarsePowerGating:skl,bxt */
2855 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2856 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2859 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2860 * even when in MSI mode. This results in spurious interrupt warnings if the
2861 * legacy irq no. is shared with another device. The kernel then disables that
2862 * interrupt source and so prevents the other device from working properly.
2864 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2865 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2867 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2868 * rows, which changed the alignment requirements and fence programming.
2870 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2871 !(IS_I915G(dev_priv) || \
2872 IS_I915GM(dev_priv)))
2873 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2874 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2876 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2877 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2878 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2879 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
2881 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2883 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2885 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2886 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2887 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2888 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2889 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2891 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2893 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2894 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2897 * For now, anything with a GuC requires uCode loading, and then supports
2898 * command submission once loaded. But these are logically independent
2899 * properties, so we have separate macros to test them.
2901 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2902 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2903 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2904 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2906 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2908 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2910 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2911 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2912 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2913 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2914 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2915 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2916 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2917 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2918 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2919 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2920 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2921 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2923 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2924 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2925 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2926 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2927 #define HAS_PCH_LPT_LP(dev_priv) \
2928 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2929 #define HAS_PCH_LPT_H(dev_priv) \
2930 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2931 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2932 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2933 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2934 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2936 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2938 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2940 /* DPF == dynamic parity feature */
2941 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2942 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2943 2 : HAS_L3_DPF(dev_priv))
2945 #define GT_FREQUENCY_MULTIPLIER 50
2946 #define GEN9_FREQ_SCALER 3
2948 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2950 #include "i915_trace.h"
2952 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2954 #ifdef CONFIG_INTEL_IOMMU
2955 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2961 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2964 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2968 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2969 const char *fmt, ...);
2971 #define i915_report_error(dev_priv, fmt, ...) \
2972 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2974 #ifdef CONFIG_COMPAT
2975 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2978 #define i915_compat_ioctl NULL
2980 extern const struct dev_pm_ops i915_pm_ops;
2982 extern int i915_driver_load(struct pci_dev *pdev,
2983 const struct pci_device_id *ent);
2984 extern void i915_driver_unload(struct drm_device *dev);
2985 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2986 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2987 extern void i915_reset(struct drm_i915_private *dev_priv);
2988 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2989 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2990 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2991 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2992 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2993 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2994 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2995 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2997 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2998 int intel_engines_init(struct drm_i915_private *dev_priv);
3000 /* intel_hotplug.c */
3001 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3002 u32 pin_mask, u32 long_mask);
3003 void intel_hpd_init(struct drm_i915_private *dev_priv);
3004 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3005 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3006 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3007 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3008 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3011 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3013 unsigned long delay;
3015 if (unlikely(!i915.enable_hangcheck))
3018 /* Don't continually defer the hangcheck so that it is always run at
3019 * least once after work has been scheduled on any ring. Otherwise,
3020 * we will ignore a hung ring if a second ring is kept busy.
3023 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3024 queue_delayed_work(system_long_wq,
3025 &dev_priv->gpu_error.hangcheck_work, delay);
3029 void i915_handle_error(struct drm_i915_private *dev_priv,
3031 const char *fmt, ...);
3033 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3034 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
3035 int intel_irq_install(struct drm_i915_private *dev_priv);
3036 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3038 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3040 return dev_priv->gvt;
3043 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3045 return dev_priv->vgpu.active;
3049 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3053 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3056 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3057 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3058 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3061 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3062 uint32_t interrupt_mask,
3063 uint32_t enabled_irq_mask);
3065 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3067 ilk_update_display_irq(dev_priv, bits, bits);
3070 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3072 ilk_update_display_irq(dev_priv, bits, 0);
3074 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3076 uint32_t interrupt_mask,
3077 uint32_t enabled_irq_mask);
3078 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3079 enum pipe pipe, uint32_t bits)
3081 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3083 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3084 enum pipe pipe, uint32_t bits)
3086 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3088 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3089 uint32_t interrupt_mask,
3090 uint32_t enabled_irq_mask);
3092 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3094 ibx_display_interrupt_update(dev_priv, bits, bits);
3097 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3099 ibx_display_interrupt_update(dev_priv, bits, 0);
3103 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3104 struct drm_file *file_priv);
3105 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3106 struct drm_file *file_priv);
3107 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3108 struct drm_file *file_priv);
3109 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3110 struct drm_file *file_priv);
3111 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3112 struct drm_file *file_priv);
3113 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3114 struct drm_file *file_priv);
3115 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3116 struct drm_file *file_priv);
3117 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3118 struct drm_file *file_priv);
3119 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3120 struct drm_file *file_priv);
3121 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3122 struct drm_file *file_priv);
3123 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3124 struct drm_file *file);
3125 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3126 struct drm_file *file);
3127 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3128 struct drm_file *file_priv);
3129 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3130 struct drm_file *file_priv);
3131 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3132 struct drm_file *file_priv);
3133 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3134 struct drm_file *file_priv);
3135 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3136 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3137 struct drm_file *file);
3138 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3139 struct drm_file *file_priv);
3140 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3141 struct drm_file *file_priv);
3142 void i915_gem_sanitize(struct drm_i915_private *i915);
3143 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3144 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3145 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3146 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3147 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3149 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3150 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3151 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3152 const struct drm_i915_gem_object_ops *ops);
3153 struct drm_i915_gem_object *
3154 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3155 struct drm_i915_gem_object *
3156 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3157 const void *data, size_t size);
3158 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3159 void i915_gem_free_object(struct drm_gem_object *obj);
3161 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3163 /* A single pass should suffice to release all the freed objects (along
3164 * most call paths) , but be a little more paranoid in that freeing
3165 * the objects does take a little amount of time, during which the rcu
3166 * callbacks could have added new objects into the freed list, and
3167 * armed the work again.
3171 } while (flush_work(&i915->mm.free_work));
3174 struct i915_vma * __must_check
3175 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3176 const struct i915_ggtt_view *view,
3181 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3182 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3184 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3186 static inline int __sg_page_count(const struct scatterlist *sg)
3188 return sg->length >> PAGE_SHIFT;
3191 struct scatterlist *
3192 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3193 unsigned int n, unsigned int *offset);
3196 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3200 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3204 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3207 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3208 struct sg_table *pages);
3209 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3211 static inline int __must_check
3212 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3214 might_lock(&obj->mm.lock);
3216 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3219 return __i915_gem_object_get_pages(obj);
3223 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3225 GEM_BUG_ON(!obj->mm.pages);
3227 atomic_inc(&obj->mm.pages_pin_count);
3231 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3233 return atomic_read(&obj->mm.pages_pin_count);
3237 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3239 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3240 GEM_BUG_ON(!obj->mm.pages);
3242 atomic_dec(&obj->mm.pages_pin_count);
3246 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3248 __i915_gem_object_unpin_pages(obj);
3251 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3256 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3257 enum i915_mm_subclass subclass);
3258 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3260 enum i915_map_type {
3266 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3267 * @obj: the object to map into kernel address space
3268 * @type: the type of mapping, used to select pgprot_t
3270 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3271 * pages and then returns a contiguous mapping of the backing storage into
3272 * the kernel address space. Based on the @type of mapping, the PTE will be
3273 * set to either WriteBack or WriteCombine (via pgprot_t).
3275 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3276 * mapping is no longer required.
3278 * Returns the pointer through which to access the mapped object, or an
3279 * ERR_PTR() on error.
3281 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3282 enum i915_map_type type);
3285 * i915_gem_object_unpin_map - releases an earlier mapping
3286 * @obj: the object to unmap
3288 * After pinning the object and mapping its pages, once you are finished
3289 * with your access, call i915_gem_object_unpin_map() to release the pin
3290 * upon the mapping. Once the pin count reaches zero, that mapping may be
3293 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3295 i915_gem_object_unpin_pages(obj);
3298 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3299 unsigned int *needs_clflush);
3300 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3301 unsigned int *needs_clflush);
3302 #define CLFLUSH_BEFORE BIT(0)
3303 #define CLFLUSH_AFTER BIT(1)
3304 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3307 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3309 i915_gem_object_unpin_pages(obj);
3312 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3313 void i915_vma_move_to_active(struct i915_vma *vma,
3314 struct drm_i915_gem_request *req,
3315 unsigned int flags);
3316 int i915_gem_dumb_create(struct drm_file *file_priv,
3317 struct drm_device *dev,
3318 struct drm_mode_create_dumb *args);
3319 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3320 uint32_t handle, uint64_t *offset);
3321 int i915_gem_mmap_gtt_version(void);
3323 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3324 struct drm_i915_gem_object *new,
3325 unsigned frontbuffer_bits);
3327 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3329 struct drm_i915_gem_request *
3330 i915_gem_find_active_request(struct intel_engine_cs *engine);
3332 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3334 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3336 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3339 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3341 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3344 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3346 return unlikely(test_bit(I915_WEDGED, &error->flags));
3349 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3351 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3354 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3356 return READ_ONCE(error->reset_count);
3359 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3360 void i915_gem_reset(struct drm_i915_private *dev_priv);
3361 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3362 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3363 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3365 void i915_gem_init_mmio(struct drm_i915_private *i915);
3366 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3367 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3368 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3369 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3370 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3371 unsigned int flags);
3372 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3373 void i915_gem_resume(struct drm_i915_private *dev_priv);
3374 int i915_gem_fault(struct vm_fault *vmf);
3375 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3378 struct intel_rps_client *rps);
3379 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3382 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3385 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3387 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3389 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3390 struct i915_vma * __must_check
3391 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3393 const struct i915_ggtt_view *view);
3394 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3395 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3397 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3398 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3400 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3401 enum i915_cache_level cache_level);
3403 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3404 struct dma_buf *dma_buf);
3406 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3407 struct drm_gem_object *gem_obj, int flags);
3409 static inline struct i915_hw_ppgtt *
3410 i915_vm_to_ppgtt(struct i915_address_space *vm)
3412 return container_of(vm, struct i915_hw_ppgtt, base);
3415 /* i915_gem_fence_reg.c */
3416 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3417 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3419 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3420 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3422 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3423 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3424 struct sg_table *pages);
3425 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3426 struct sg_table *pages);
3428 static inline struct i915_gem_context *
3429 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3431 struct i915_gem_context *ctx;
3433 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3435 ctx = idr_find(&file_priv->context_idr, id);
3437 return ERR_PTR(-ENOENT);
3442 static inline struct i915_gem_context *
3443 i915_gem_context_get(struct i915_gem_context *ctx)
3445 kref_get(&ctx->ref);
3449 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3451 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3452 kref_put(&ctx->ref, i915_gem_context_free);
3455 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3457 struct mutex *lock = &ctx->i915->drm.struct_mutex;
3459 if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
3463 static inline struct intel_timeline *
3464 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3465 struct intel_engine_cs *engine)
3467 struct i915_address_space *vm;
3469 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3470 return &vm->timeline.engine[engine->id];
3473 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3474 struct drm_file *file);
3476 /* i915_gem_evict.c */
3477 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3478 u64 min_size, u64 alignment,
3479 unsigned cache_level,
3482 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3483 struct drm_mm_node *node,
3484 unsigned int flags);
3485 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3487 /* belongs in i915_gem_gtt.h */
3488 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3491 if (INTEL_GEN(dev_priv) < 6)
3492 intel_gtt_chipset_flush();
3495 /* i915_gem_stolen.c */
3496 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3497 struct drm_mm_node *node, u64 size,
3498 unsigned alignment);
3499 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3500 struct drm_mm_node *node, u64 size,
3501 unsigned alignment, u64 start,
3503 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3504 struct drm_mm_node *node);
3505 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3506 void i915_gem_cleanup_stolen(struct drm_device *dev);
3507 struct drm_i915_gem_object *
3508 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3509 struct drm_i915_gem_object *
3510 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3515 /* i915_gem_internal.c */
3516 struct drm_i915_gem_object *
3517 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3520 /* i915_gem_shrinker.c */
3521 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3522 unsigned long target,
3524 #define I915_SHRINK_PURGEABLE 0x1
3525 #define I915_SHRINK_UNBOUND 0x2
3526 #define I915_SHRINK_BOUND 0x4
3527 #define I915_SHRINK_ACTIVE 0x8
3528 #define I915_SHRINK_VMAPS 0x10
3529 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3530 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3531 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3534 /* i915_gem_tiling.c */
3535 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3537 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3539 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3540 i915_gem_object_is_tiled(obj);
3543 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3544 unsigned int tiling, unsigned int stride);
3545 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3546 unsigned int tiling, unsigned int stride);
3548 /* i915_debugfs.c */
3549 #ifdef CONFIG_DEBUG_FS
3550 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3551 int i915_debugfs_connector_add(struct drm_connector *connector);
3552 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3554 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3555 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3557 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3560 /* i915_gpu_error.c */
3561 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3564 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3565 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3566 const struct i915_gpu_state *gpu);
3567 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3568 struct drm_i915_private *i915,
3569 size_t count, loff_t pos);
3570 static inline void i915_error_state_buf_release(
3571 struct drm_i915_error_state_buf *eb)
3576 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3577 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3579 const char *error_msg);
3581 static inline struct i915_gpu_state *
3582 i915_gpu_state_get(struct i915_gpu_state *gpu)
3584 kref_get(&gpu->ref);
3588 void __i915_gpu_state_free(struct kref *kref);
3589 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3592 kref_put(&gpu->ref, __i915_gpu_state_free);
3595 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3596 void i915_reset_error_state(struct drm_i915_private *i915);
3600 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3602 const char *error_msg)
3606 static inline struct i915_gpu_state *
3607 i915_first_error_state(struct drm_i915_private *i915)
3612 static inline void i915_reset_error_state(struct drm_i915_private *i915)
3618 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3620 /* i915_cmd_parser.c */
3621 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3622 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3623 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3624 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3625 struct drm_i915_gem_object *batch_obj,
3626 struct drm_i915_gem_object *shadow_batch_obj,
3627 u32 batch_start_offset,
3632 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3633 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3634 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3635 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3637 /* i915_suspend.c */
3638 extern int i915_save_state(struct drm_i915_private *dev_priv);
3639 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3642 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3643 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3645 /* intel_lpe_audio.c */
3646 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3647 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3648 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3649 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3650 enum pipe pipe, enum port port,
3651 const void *eld, int ls_clock, bool dp_output);
3654 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3655 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3656 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3659 extern struct i2c_adapter *
3660 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3661 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3662 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3663 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3665 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3667 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3670 void intel_bios_init(struct drm_i915_private *dev_priv);
3671 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3672 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3673 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3674 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3675 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3676 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3677 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3678 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3680 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3684 /* intel_opregion.c */
3686 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3687 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3688 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3689 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3690 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3692 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3694 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3696 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3697 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3698 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3699 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3703 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3708 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3712 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3720 extern void intel_register_dsm_handler(void);
3721 extern void intel_unregister_dsm_handler(void);
3723 static inline void intel_register_dsm_handler(void) { return; }
3724 static inline void intel_unregister_dsm_handler(void) { return; }
3725 #endif /* CONFIG_ACPI */
3727 /* intel_device_info.c */
3728 static inline struct intel_device_info *
3729 mkwrite_device_info(struct drm_i915_private *dev_priv)
3731 return (struct intel_device_info *)&dev_priv->info;
3734 const char *intel_platform_name(enum intel_platform platform);
3735 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3736 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3739 extern void intel_modeset_init_hw(struct drm_device *dev);
3740 extern int intel_modeset_init(struct drm_device *dev);
3741 extern void intel_modeset_gem_init(struct drm_device *dev);
3742 extern void intel_modeset_cleanup(struct drm_device *dev);
3743 extern int intel_connector_register(struct drm_connector *);
3744 extern void intel_connector_unregister(struct drm_connector *);
3745 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3747 extern void intel_display_resume(struct drm_device *dev);
3748 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3749 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3750 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3751 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3752 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3753 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3756 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3757 struct drm_file *file);
3760 extern struct intel_overlay_error_state *
3761 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3762 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3763 struct intel_overlay_error_state *error);
3765 extern struct intel_display_error_state *
3766 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3767 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3768 struct intel_display_error_state *error);
3770 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3771 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3772 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3773 u32 reply_mask, u32 reply, int timeout_base_ms);
3775 /* intel_sideband.c */
3776 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3777 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3778 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3779 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3780 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3781 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3782 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3783 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3784 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3785 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3786 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3787 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3788 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3789 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3790 enum intel_sbi_destination destination);
3791 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3792 enum intel_sbi_destination destination);
3793 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3794 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3796 /* intel_dpio_phy.c */
3797 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3798 enum dpio_phy *phy, enum dpio_channel *ch);
3799 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3800 enum port port, u32 margin, u32 scale,
3801 u32 enable, u32 deemphasis);
3802 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3803 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3804 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3806 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3808 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3809 uint8_t lane_count);
3810 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3811 uint8_t lane_lat_optim_mask);
3812 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3814 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3815 u32 deemph_reg_value, u32 margin_reg_value,
3816 bool uniq_trans_scale);
3817 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3819 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3820 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3821 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3822 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3824 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3825 u32 demph_reg_value, u32 preemph_reg_value,
3826 u32 uniqtranscale_reg_value, u32 tx3_demph);
3827 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3828 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3829 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3831 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3832 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3833 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3834 const i915_reg_t reg);
3836 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3837 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3839 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3840 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3841 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3842 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3844 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3845 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3846 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3847 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3849 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3850 * will be implemented using 2 32-bit writes in an arbitrary order with
3851 * an arbitrary delay between them. This can cause the hardware to
3852 * act upon the intermediate value, possibly leading to corruption and
3853 * machine death. For this reason we do not support I915_WRITE64, or
3854 * dev_priv->uncore.funcs.mmio_writeq.
3856 * When reading a 64-bit value as two 32-bit values, the delay may cause
3857 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3858 * occasionally a 64-bit register does not actualy support a full readq
3859 * and must be read using two 32-bit reads.
3861 * You have been warned.
3863 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3865 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3866 u32 upper, lower, old_upper, loop = 0; \
3867 upper = I915_READ(upper_reg); \
3869 old_upper = upper; \
3870 lower = I915_READ(lower_reg); \
3871 upper = I915_READ(upper_reg); \
3872 } while (upper != old_upper && loop++ < 2); \
3873 (u64)upper << 32 | lower; })
3875 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3876 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3878 #define __raw_read(x, s) \
3879 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3882 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3885 #define __raw_write(x, s) \
3886 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3887 i915_reg_t reg, uint##x##_t val) \
3889 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3904 /* These are untraced mmio-accessors that are only valid to be used inside
3905 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3908 * Think twice, and think again, before using these.
3910 * As an example, these accessors can possibly be used between:
3912 * spin_lock_irq(&dev_priv->uncore.lock);
3913 * intel_uncore_forcewake_get__locked();
3917 * intel_uncore_forcewake_put__locked();
3918 * spin_unlock_irq(&dev_priv->uncore.lock);
3921 * Note: some registers may not need forcewake held, so
3922 * intel_uncore_forcewake_{get,put} can be omitted, see
3923 * intel_uncore_forcewake_for_reg().
3925 * Certain architectures will die if the same cacheline is concurrently accessed
3926 * by different clients (e.g. on Ivybridge). Access to registers should
3927 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3928 * a more localised lock guarding all access to that bank of registers.
3930 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3931 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3932 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3933 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3935 /* "Broadcast RGB" property */
3936 #define INTEL_BROADCAST_RGB_AUTO 0
3937 #define INTEL_BROADCAST_RGB_FULL 1
3938 #define INTEL_BROADCAST_RGB_LIMITED 2
3940 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3942 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3943 return VLV_VGACNTRL;
3944 else if (INTEL_GEN(dev_priv) >= 5)
3945 return CPU_VGACNTRL;
3950 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3952 unsigned long j = msecs_to_jiffies(m);
3954 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3957 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3959 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3962 static inline unsigned long
3963 timespec_to_jiffies_timeout(const struct timespec *value)
3965 unsigned long j = timespec_to_jiffies(value);
3967 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3971 * If you need to wait X milliseconds between events A and B, but event B
3972 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3973 * when event A happened, then just before event B you call this function and
3974 * pass the timestamp as the first argument, and X as the second argument.
3977 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3979 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3982 * Don't re-read the value of "jiffies" every time since it may change
3983 * behind our back and break the math.
3985 tmp_jiffies = jiffies;
3986 target_jiffies = timestamp_jiffies +
3987 msecs_to_jiffies_timeout(to_wait_ms);
3989 if (time_after(target_jiffies, tmp_jiffies)) {
3990 remaining_jiffies = target_jiffies - tmp_jiffies;
3991 while (remaining_jiffies)
3993 schedule_timeout_uninterruptible(remaining_jiffies);
3998 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
4000 struct intel_engine_cs *engine = req->engine;
4003 /* Note that the engine may have wrapped around the seqno, and
4004 * so our request->global_seqno will be ahead of the hardware,
4005 * even though it completed the request before wrapping. We catch
4006 * this by kicking all the waiters before resetting the seqno
4007 * in hardware, and also signal the fence.
4009 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
4012 /* The request was dequeued before we were awoken. We check after
4013 * inspecting the hw to confirm that this was the same request
4014 * that generated the HWS update. The memory barriers within
4015 * the request execution are sufficient to ensure that a check
4016 * after reading the value from hw matches this request.
4018 seqno = i915_gem_request_global_seqno(req);
4022 /* Before we do the heavier coherent read of the seqno,
4023 * check the value (hopefully) in the CPU cacheline.
4025 if (__i915_gem_request_completed(req, seqno))
4028 /* Ensure our read of the seqno is coherent so that we
4029 * do not "miss an interrupt" (i.e. if this is the last
4030 * request and the seqno write from the GPU is not visible
4031 * by the time the interrupt fires, we will see that the
4032 * request is incomplete and go back to sleep awaiting
4033 * another interrupt that will never come.)
4035 * Strictly, we only need to do this once after an interrupt,
4036 * but it is easier and safer to do it every time the waiter
4039 if (engine->irq_seqno_barrier &&
4040 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4041 struct intel_breadcrumbs *b = &engine->breadcrumbs;
4043 /* The ordering of irq_posted versus applying the barrier
4044 * is crucial. The clearing of the current irq_posted must
4045 * be visible before we perform the barrier operation,
4046 * such that if a subsequent interrupt arrives, irq_posted
4047 * is reasserted and our task rewoken (which causes us to
4048 * do another __i915_request_irq_complete() immediately
4049 * and reapply the barrier). Conversely, if the clear
4050 * occurs after the barrier, then an interrupt that arrived
4051 * whilst we waited on the barrier would not trigger a
4052 * barrier on the next pass, and the read may not see the
4055 engine->irq_seqno_barrier(engine);
4057 /* If we consume the irq, but we are no longer the bottom-half,
4058 * the real bottom-half may not have serialised their own
4059 * seqno check with the irq-barrier (i.e. may have inspected
4060 * the seqno before we believe it coherent since they see
4061 * irq_posted == false but we are still running).
4063 spin_lock_irq(&b->irq_lock);
4064 if (b->irq_wait && b->irq_wait->tsk != current)
4065 /* Note that if the bottom-half is changed as we
4066 * are sending the wake-up, the new bottom-half will
4067 * be woken by whomever made the change. We only have
4068 * to worry about when we steal the irq-posted for
4071 wake_up_process(b->irq_wait->tsk);
4072 spin_unlock_irq(&b->irq_lock);
4074 if (__i915_gem_request_completed(req, seqno))
4081 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4082 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4084 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4085 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4086 * perform the operation. To check beforehand, pass in the parameters to
4087 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4088 * you only need to pass in the minor offsets, page-aligned pointers are
4091 * For just checking for SSE4.1, in the foreknowledge that the future use
4092 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4094 #define i915_can_memcpy_from_wc(dst, src, len) \
4095 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4097 #define i915_has_memcpy_from_wc() \
4098 i915_memcpy_from_wc(NULL, NULL, 0)
4101 int remap_io_mapping(struct vm_area_struct *vma,
4102 unsigned long addr, unsigned long pfn, unsigned long size,
4103 struct io_mapping *iomap);
4105 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
4107 return (obj->cache_level != I915_CACHE_NONE ||
4108 HAS_LLC(to_i915(obj->base.dev)));