drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33 #include <linux/shmem_fs.h>
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-buf.h>
  38
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  42                                                     unsigned alignment,
  43                                                     bool map_and_fenceable,
  44                                                     bool nonblocking);
  45 static int i915_gem_phys_pwrite(struct drm_device *dev,
  46                                 struct drm_i915_gem_object *obj,
  47                                 struct drm_i915_gem_pwrite *args,
  48                                 struct drm_file *file);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  57                                     struct shrink_control *sc);
  58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  61
  62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  63 {
  64         if (obj->tiling_mode)
  65                 i915_gem_release_mmap(obj);
  66
  67         /* As we do not have an associated fence register, we will force
  68          * a tiling change if we ever need to acquire one.
  69          */
  70         obj->fence_dirty = false;
  71         obj->fence_reg = I915_FENCE_REG_NONE;
  72 }
  73
  74 /* some bookkeeping */
  75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  76                                   size_t size)
  77 {
  78         dev_priv->mm.object_count++;
  79         dev_priv->mm.object_memory += size;
  80 }
  81
  82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  83                                      size_t size)
  84 {
  85         dev_priv->mm.object_count--;
  86         dev_priv->mm.object_memory -= size;
  87 }
  88
  89 static int
  90 i915_gem_wait_for_error(struct i915_gpu_error *error)
  91 {
  92         int ret;
  93
  94 #define EXIT_COND (!i915_reset_in_progress(error) || \
  95                    i915_terminally_wedged(error))
  96         if (EXIT_COND)
  97                 return 0;
  98
  99         /*
 100          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 101          * userspace. If it takes that long something really bad is going on and
 102          * we should simply try to bail out and fail as gracefully as possible.
 103          */
 104         ret = wait_event_interruptible_timeout(error->reset_queue,
 105                                                EXIT_COND,
 106                                                10*HZ);
 107         if (ret == 0) {
 108                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 109                 return -EIO;
 110         } else if (ret < 0) {
 111                 return ret;
 112         }
 113 #undef EXIT_COND
 114
 115         return 0;
 116 }
 117
 118 int i915_mutex_lock_interruptible(struct drm_device *dev)
 119 {
 120         struct drm_i915_private *dev_priv = dev->dev_private;
 121         int ret;
 122
 123         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 124         if (ret)
 125                 return ret;
 126
 127         ret = mutex_lock_interruptible(&dev->struct_mutex);
 128         if (ret)
 129                 return ret;
 130
 131         WARN_ON(i915_verify_lists(dev));
 132         return 0;
 133 }
 134
 135 static inline bool
 136 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 137 {
 138         return obj->gtt_space && !obj->active;
 139 }
 140
 141 int
 142 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 143                     struct drm_file *file)
 144 {
 145         struct drm_i915_private *dev_priv = dev->dev_private;
 146         struct drm_i915_gem_init *args = data;
 147
 148         if (drm_core_check_feature(dev, DRIVER_MODESET))
 149                 return -ENODEV;
 150
 151         if (args->gtt_start >= args->gtt_end ||
 152             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 153                 return -EINVAL;
 154
 155         /* GEM with user mode setting was never supported on ilk and later. */
 156         if (INTEL_INFO(dev)->gen >= 5)
 157                 return -ENODEV;
 158
 159         mutex_lock(&dev->struct_mutex);
 160         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 161                                   args->gtt_end);
 162         dev_priv->gtt.mappable_end = args->gtt_end;
 163         mutex_unlock(&dev->struct_mutex);
 164
 165         return 0;
 166 }
 167
 168 int
 169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 170                             struct drm_file *file)
 171 {
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct drm_i915_gem_get_aperture *args = data;
 174         struct drm_i915_gem_object *obj;
 175         size_t pinned;
 176
 177         pinned = 0;
 178         mutex_lock(&dev->struct_mutex);
 179         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 180                 if (obj->pin_count)
 181                         pinned += obj->gtt_space->size;
 182         mutex_unlock(&dev->struct_mutex);
 183
 184         args->aper_size = dev_priv->gtt.total;
 185         args->aper_available_size = args->aper_size - pinned;
 186
 187         return 0;
 188 }
 189
 190 void *i915_gem_object_alloc(struct drm_device *dev)
 191 {
 192         struct drm_i915_private *dev_priv = dev->dev_private;
 193         return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
 194 }
 195
 196 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 197 {
 198         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 199         kmem_cache_free(dev_priv->slab, obj);
 200 }
 201
 202 static int
 203 i915_gem_create(struct drm_file *file,
 204                 struct drm_device *dev,
 205                 uint64_t size,
 206                 uint32_t *handle_p)
 207 {
 208         struct drm_i915_gem_object *obj;
 209         int ret;
 210         u32 handle;
 211
 212         size = roundup(size, PAGE_SIZE);
 213         if (size == 0)
 214                 return -EINVAL;
 215
 216         /* Allocate the new object */
 217         obj = i915_gem_alloc_object(dev, size);
 218         if (obj == NULL)
 219                 return -ENOMEM;
 220
 221         ret = drm_gem_handle_create(file, &obj->base, &handle);
 222         if (ret) {
 223                 drm_gem_object_release(&obj->base);
 224                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 225                 i915_gem_object_free(obj);
 226                 return ret;
 227         }
 228
 229         /* drop reference from allocate - handle holds it now */
 230         drm_gem_object_unreference(&obj->base);
 231         trace_i915_gem_object_create(obj);
 232
 233         *handle_p = handle;
 234         return 0;
 235 }
 236
 237 int
 238 i915_gem_dumb_create(struct drm_file *file,
 239                      struct drm_device *dev,
 240                      struct drm_mode_create_dumb *args)
 241 {
 242         /* have to work out size/pitch and return them */
 243         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 244         args->size = args->pitch * args->height;
 245         return i915_gem_create(file, dev,
 246                                args->size, &args->handle);
 247 }
 248
 249 int i915_gem_dumb_destroy(struct drm_file *file,
 250                           struct drm_device *dev,
 251                           uint32_t handle)
 252 {
 253         return drm_gem_handle_delete(file, handle);
 254 }
 255
 256 /**
 257  * Creates a new mm object and returns a handle to it.
 258  */
 259 int
 260 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 261                       struct drm_file *file)
 262 {
 263         struct drm_i915_gem_create *args = data;
 264
 265         return i915_gem_create(file, dev,
 266                                args->size, &args->handle);
 267 }
 268
 269 static inline int
 270 __copy_to_user_swizzled(char __user *cpu_vaddr,
 271                         const char *gpu_vaddr, int gpu_offset,
 272                         int length)
 273 {
 274         int ret, cpu_offset = 0;
 275
 276         while (length > 0) {
 277                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 278                 int this_length = min(cacheline_end - gpu_offset, length);
 279                 int swizzled_gpu_offset = gpu_offset ^ 64;
 280
 281                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 282                                      gpu_vaddr + swizzled_gpu_offset,
 283                                      this_length);
 284                 if (ret)
 285                         return ret + length;
 286
 287                 cpu_offset += this_length;
 288                 gpu_offset += this_length;
 289                 length -= this_length;
 290         }
 291
 292         return 0;
 293 }
 294
 295 static inline int
 296 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 297                           const char __user *cpu_vaddr,
 298                           int length)
 299 {
 300         int ret, cpu_offset = 0;
 301
 302         while (length > 0) {
 303                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 304                 int this_length = min(cacheline_end - gpu_offset, length);
 305                 int swizzled_gpu_offset = gpu_offset ^ 64;
 306
 307                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 308                                        cpu_vaddr + cpu_offset,
 309                                        this_length);
 310                 if (ret)
 311                         return ret + length;
 312
 313                 cpu_offset += this_length;
 314                 gpu_offset += this_length;
 315                 length -= this_length;
 316         }
 317
 318         return 0;
 319 }
 320
 321 /* Per-page copy function for the shmem pread fastpath.
 322  * Flushes invalid cachelines before reading the target if
 323  * needs_clflush is set. */
 324 static int
 325 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 326                  char __user *user_data,
 327                  bool page_do_bit17_swizzling, bool needs_clflush)
 328 {
 329         char *vaddr;
 330         int ret;
 331
 332         if (unlikely(page_do_bit17_swizzling))
 333                 return -EINVAL;
 334
 335         vaddr = kmap_atomic(page);
 336         if (needs_clflush)
 337                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 338                                        page_length);
 339         ret = __copy_to_user_inatomic(user_data,
 340                                       vaddr + shmem_page_offset,
 341                                       page_length);
 342         kunmap_atomic(vaddr);
 343
 344         return ret ? -EFAULT : 0;
 345 }
 346
 347 static void
 348 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 349                              bool swizzled)
 350 {
 351         if (unlikely(swizzled)) {
 352                 unsigned long start = (unsigned long) addr;
 353                 unsigned long end = (unsigned long) addr + length;
 354
 355                 /* For swizzling simply ensure that we always flush both
 356                  * channels. Lame, but simple and it works. Swizzled
 357                  * pwrite/pread is far from a hotpath - current userspace
 358                  * doesn't use it at all. */
 359                 start = round_down(start, 128);
 360                 end = round_up(end, 128);
 361
 362                 drm_clflush_virt_range((void *)start, end - start);
 363         } else {
 364                 drm_clflush_virt_range(addr, length);
 365         }
 366
 367 }
 368
 369 /* Only difference to the fast-path function is that this can handle bit17
 370  * and uses non-atomic copy and kmap functions. */
 371 static int
 372 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 373                  char __user *user_data,
 374                  bool page_do_bit17_swizzling, bool needs_clflush)
 375 {
 376         char *vaddr;
 377         int ret;
 378
 379         vaddr = kmap(page);
 380         if (needs_clflush)
 381                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 382                                              page_length,
 383                                              page_do_bit17_swizzling);
 384
 385         if (page_do_bit17_swizzling)
 386                 ret = __copy_to_user_swizzled(user_data,
 387                                               vaddr, shmem_page_offset,
 388                                               page_length);
 389         else
 390                 ret = __copy_to_user(user_data,
 391                                      vaddr + shmem_page_offset,
 392                                      page_length);
 393         kunmap(page);
 394
 395         return ret ? - EFAULT : 0;
 396 }
 397
 398 static int
 399 i915_gem_shmem_pread(struct drm_device *dev,
 400                      struct drm_i915_gem_object *obj,
 401                      struct drm_i915_gem_pread *args,
 402                      struct drm_file *file)
 403 {
 404         char __user *user_data;
 405         ssize_t remain;
 406         loff_t offset;
 407         int shmem_page_offset, page_length, ret = 0;
 408         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 409         int prefaulted = 0;
 410         int needs_clflush = 0;
 411         struct sg_page_iter sg_iter;
 412
 413         user_data = to_user_ptr(args->data_ptr);
 414         remain = args->size;
 415
 416         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 417
 418         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 419                 /* If we're not in the cpu read domain, set ourself into the gtt
 420                  * read domain and manually flush cachelines (if required). This
 421                  * optimizes for the case when the gpu will dirty the data
 422                  * anyway again before the next pread happens. */
 423                 if (obj->cache_level == I915_CACHE_NONE)
 424                         needs_clflush = 1;
 425                 if (obj->gtt_space) {
 426                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
 427                         if (ret)
 428                                 return ret;
 429                 }
 430         }
 431
 432         ret = i915_gem_object_get_pages(obj);
 433         if (ret)
 434                 return ret;
 435
 436         i915_gem_object_pin_pages(obj);
 437
 438         offset = args->offset;
 439
 440         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 441                          offset >> PAGE_SHIFT) {
 442                 struct page *page = sg_page_iter_page(&sg_iter);
 443
 444                 if (remain <= 0)
 445                         break;
 446
 447                 /* Operation in this page
 448                  *
 449                  * shmem_page_offset = offset within page in shmem file
 450                  * page_length = bytes to copy for this page
 451                  */
 452                 shmem_page_offset = offset_in_page(offset);
 453                 page_length = remain;
 454                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 455                         page_length = PAGE_SIZE - shmem_page_offset;
 456
 457                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 458                         (page_to_phys(page) & (1 << 17)) != 0;
 459
 460                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 461                                        user_data, page_do_bit17_swizzling,
 462                                        needs_clflush);
 463                 if (ret == 0)
 464                         goto next_page;
 465
 466                 mutex_unlock(&dev->struct_mutex);
 467
 468                 if (!prefaulted) {
 469                         ret = fault_in_multipages_writeable(user_data, remain);
 470                         /* Userspace is tricking us, but we've already clobbered
 471                          * its pages with the prefault and promised to write the
 472                          * data up to the first fault. Hence ignore any errors
 473                          * and just continue. */
 474                         (void)ret;
 475                         prefaulted = 1;
 476                 }
 477
 478                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 479                                        user_data, page_do_bit17_swizzling,
 480                                        needs_clflush);
 481
 482                 mutex_lock(&dev->struct_mutex);
 483
 484 next_page:
 485                 mark_page_accessed(page);
 486
 487                 if (ret)
 488                         goto out;
 489
 490                 remain -= page_length;
 491                 user_data += page_length;
 492                 offset += page_length;
 493         }
 494
 495 out:
 496         i915_gem_object_unpin_pages(obj);
 497
 498         return ret;
 499 }
 500
 501 /**
 502  * Reads data from the object referenced by handle.
 503  *
 504  * On error, the contents of *data are undefined.
 505  */
 506 int
 507 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 508                      struct drm_file *file)
 509 {
 510         struct drm_i915_gem_pread *args = data;
 511         struct drm_i915_gem_object *obj;
 512         int ret = 0;
 513
 514         if (args->size == 0)
 515                 return 0;
 516
 517         if (!access_ok(VERIFY_WRITE,
 518                        to_user_ptr(args->data_ptr),
 519                        args->size))
 520                 return -EFAULT;
 521
 522         ret = i915_mutex_lock_interruptible(dev);
 523         if (ret)
 524                 return ret;
 525
 526         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 527         if (&obj->base == NULL) {
 528                 ret = -ENOENT;
 529                 goto unlock;
 530         }
 531
 532         /* Bounds check source.  */
 533         if (args->offset > obj->base.size ||
 534             args->size > obj->base.size - args->offset) {
 535                 ret = -EINVAL;
 536                 goto out;
 537         }
 538
 539         /* prime objects have no backing filp to GEM pread/pwrite
 540          * pages from.
 541          */
 542         if (!obj->base.filp) {
 543                 ret = -EINVAL;
 544                 goto out;
 545         }
 546
 547         trace_i915_gem_object_pread(obj, args->offset, args->size);
 548
 549         ret = i915_gem_shmem_pread(dev, obj, args, file);
 550
 551 out:
 552         drm_gem_object_unreference(&obj->base);
 553 unlock:
 554         mutex_unlock(&dev->struct_mutex);
 555         return ret;
 556 }
 557
 558 /* This is the fast write path which cannot handle
 559  * page faults in the source data
 560  */
 561
 562 static inline int
 563 fast_user_write(struct io_mapping *mapping,
 564                 loff_t page_base, int page_offset,
 565                 char __user *user_data,
 566                 int length)
 567 {
 568         void __iomem *vaddr_atomic;
 569         void *vaddr;
 570         unsigned long unwritten;
 571
 572         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 573         /* We can use the cpu mem copy function because this is X86. */
 574         vaddr = (void __force*)vaddr_atomic + page_offset;
 575         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 576                                                       user_data, length);
 577         io_mapping_unmap_atomic(vaddr_atomic);
 578         return unwritten;
 579 }
 580
 581 /**
 582  * This is the fast pwrite path, where we copy the data directly from the
 583  * user into the GTT, uncached.
 584  */
 585 static int
 586 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 587                          struct drm_i915_gem_object *obj,
 588                          struct drm_i915_gem_pwrite *args,
 589                          struct drm_file *file)
 590 {
 591         drm_i915_private_t *dev_priv = dev->dev_private;
 592         ssize_t remain;
 593         loff_t offset, page_base;
 594         char __user *user_data;
 595         int page_offset, page_length, ret;
 596
 597         ret = i915_gem_object_pin(obj, 0, true, true);
 598         if (ret)
 599                 goto out;
 600
 601         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 602         if (ret)
 603                 goto out_unpin;
 604
 605         ret = i915_gem_object_put_fence(obj);
 606         if (ret)
 607                 goto out_unpin;
 608
 609         user_data = to_user_ptr(args->data_ptr);
 610         remain = args->size;
 611
 612         offset = obj->gtt_offset + args->offset;
 613
 614         while (remain > 0) {
 615                 /* Operation in this page
 616                  *
 617                  * page_base = page offset within aperture
 618                  * page_offset = offset within page
 619                  * page_length = bytes to copy for this page
 620                  */
 621                 page_base = offset & PAGE_MASK;
 622                 page_offset = offset_in_page(offset);
 623                 page_length = remain;
 624                 if ((page_offset + remain) > PAGE_SIZE)
 625                         page_length = PAGE_SIZE - page_offset;
 626
 627                 /* If we get a fault while copying data, then (presumably) our
 628                  * source page isn't available.  Return the error and we'll
 629                  * retry in the slow path.
 630                  */
 631                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 632                                     page_offset, user_data, page_length)) {
 633                         ret = -EFAULT;
 634                         goto out_unpin;
 635                 }
 636
 637                 remain -= page_length;
 638                 user_data += page_length;
 639                 offset += page_length;
 640         }
 641
 642 out_unpin:
 643         i915_gem_object_unpin(obj);
 644 out:
 645         return ret;
 646 }
 647
 648 /* Per-page copy function for the shmem pwrite fastpath.
 649  * Flushes invalid cachelines before writing to the target if
 650  * needs_clflush_before is set and flushes out any written cachelines after
 651  * writing if needs_clflush is set. */
 652 static int
 653 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 654                   char __user *user_data,
 655                   bool page_do_bit17_swizzling,
 656                   bool needs_clflush_before,
 657                   bool needs_clflush_after)
 658 {
 659         char *vaddr;
 660         int ret;
 661
 662         if (unlikely(page_do_bit17_swizzling))
 663                 return -EINVAL;
 664
 665         vaddr = kmap_atomic(page);
 666         if (needs_clflush_before)
 667                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 668                                        page_length);
 669         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
 670                                                 user_data,
 671                                                 page_length);
 672         if (needs_clflush_after)
 673                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 674                                        page_length);
 675         kunmap_atomic(vaddr);
 676
 677         return ret ? -EFAULT : 0;
 678 }
 679
 680 /* Only difference to the fast-path function is that this can handle bit17
 681  * and uses non-atomic copy and kmap functions. */
 682 static int
 683 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 684                   char __user *user_data,
 685                   bool page_do_bit17_swizzling,
 686                   bool needs_clflush_before,
 687                   bool needs_clflush_after)
 688 {
 689         char *vaddr;
 690         int ret;
 691
 692         vaddr = kmap(page);
 693         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 694                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 695                                              page_length,
 696                                              page_do_bit17_swizzling);
 697         if (page_do_bit17_swizzling)
 698                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 699                                                 user_data,
 700                                                 page_length);
 701         else
 702                 ret = __copy_from_user(vaddr + shmem_page_offset,
 703                                        user_data,
 704                                        page_length);
 705         if (needs_clflush_after)
 706                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 707                                              page_length,
 708                                              page_do_bit17_swizzling);
 709         kunmap(page);
 710
 711         return ret ? -EFAULT : 0;
 712 }
 713
 714 static int
 715 i915_gem_shmem_pwrite(struct drm_device *dev,
 716                       struct drm_i915_gem_object *obj,
 717                       struct drm_i915_gem_pwrite *args,
 718                       struct drm_file *file)
 719 {
 720         ssize_t remain;
 721         loff_t offset;
 722         char __user *user_data;
 723         int shmem_page_offset, page_length, ret = 0;
 724         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 725         int hit_slowpath = 0;
 726         int needs_clflush_after = 0;
 727         int needs_clflush_before = 0;
 728         struct sg_page_iter sg_iter;
 729
 730         user_data = to_user_ptr(args->data_ptr);
 731         remain = args->size;
 732
 733         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 734
 735         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 736                 /* If we're not in the cpu write domain, set ourself into the gtt
 737                  * write domain and manually flush cachelines (if required). This
 738                  * optimizes for the case when the gpu will use the data
 739                  * right away and we therefore have to clflush anyway. */
 740                 if (obj->cache_level == I915_CACHE_NONE)
 741                         needs_clflush_after = 1;
 742                 if (obj->gtt_space) {
 743                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 744                         if (ret)
 745                                 return ret;
 746                 }
 747         }
 748         /* Same trick applies for invalidate partially written cachelines before
 749          * writing.  */
 750         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
 751             && obj->cache_level == I915_CACHE_NONE)
 752                 needs_clflush_before = 1;
 753
 754         ret = i915_gem_object_get_pages(obj);
 755         if (ret)
 756                 return ret;
 757
 758         i915_gem_object_pin_pages(obj);
 759
 760         offset = args->offset;
 761         obj->dirty = 1;
 762
 763         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 764                          offset >> PAGE_SHIFT) {
 765                 struct page *page = sg_page_iter_page(&sg_iter);
 766                 int partial_cacheline_write;
 767
 768                 if (remain <= 0)
 769                         break;
 770
 771                 /* Operation in this page
 772                  *
 773                  * shmem_page_offset = offset within page in shmem file
 774                  * page_length = bytes to copy for this page
 775                  */
 776                 shmem_page_offset = offset_in_page(offset);
 777
 778                 page_length = remain;
 779                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 780                         page_length = PAGE_SIZE - shmem_page_offset;
 781
 782                 /* If we don't overwrite a cacheline completely we need to be
 783                  * careful to have up-to-date data by first clflushing. Don't
 784                  * overcomplicate things and flush the entire patch. */
 785                 partial_cacheline_write = needs_clflush_before &&
 786                         ((shmem_page_offset | page_length)
 787                                 & (boot_cpu_data.x86_clflush_size - 1));
 788
 789                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 790                         (page_to_phys(page) & (1 << 17)) != 0;
 791
 792                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 793                                         user_data, page_do_bit17_swizzling,
 794                                         partial_cacheline_write,
 795                                         needs_clflush_after);
 796                 if (ret == 0)
 797                         goto next_page;
 798
 799                 hit_slowpath = 1;
 800                 mutex_unlock(&dev->struct_mutex);
 801                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 802                                         user_data, page_do_bit17_swizzling,
 803                                         partial_cacheline_write,
 804                                         needs_clflush_after);
 805
 806                 mutex_lock(&dev->struct_mutex);
 807
 808 next_page:
 809                 set_page_dirty(page);
 810                 mark_page_accessed(page);
 811
 812                 if (ret)
 813                         goto out;
 814
 815                 remain -= page_length;
 816                 user_data += page_length;
 817                 offset += page_length;
 818         }
 819
 820 out:
 821         i915_gem_object_unpin_pages(obj);
 822
 823         if (hit_slowpath) {
 824                 /*
 825                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 826                  * cachelines in-line while writing and the object moved
 827                  * out of the cpu write domain while we've dropped the lock.
 828                  */
 829                 if (!needs_clflush_after &&
 830                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 831                         i915_gem_clflush_object(obj);
 832                         i915_gem_chipset_flush(dev);
 833                 }
 834         }
 835
 836         if (needs_clflush_after)
 837                 i915_gem_chipset_flush(dev);
 838
 839         return ret;
 840 }
 841
 842 /**
 843  * Writes data to the object referenced by handle.
 844  *
 845  * On error, the contents of the buffer that were to be modified are undefined.
 846  */
 847 int
 848 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 849                       struct drm_file *file)
 850 {
 851         struct drm_i915_gem_pwrite *args = data;
 852         struct drm_i915_gem_object *obj;
 853         int ret;
 854
 855         if (args->size == 0)
 856                 return 0;
 857
 858         if (!access_ok(VERIFY_READ,
 859                        to_user_ptr(args->data_ptr),
 860                        args->size))
 861                 return -EFAULT;
 862
 863         ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
 864                                            args->size);
 865         if (ret)
 866                 return -EFAULT;
 867
 868         ret = i915_mutex_lock_interruptible(dev);
 869         if (ret)
 870                 return ret;
 871
 872         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 873         if (&obj->base == NULL) {
 874                 ret = -ENOENT;
 875                 goto unlock;
 876         }
 877
 878         /* Bounds check destination. */
 879         if (args->offset > obj->base.size ||
 880             args->size > obj->base.size - args->offset) {
 881                 ret = -EINVAL;
 882                 goto out;
 883         }
 884
 885         /* prime objects have no backing filp to GEM pread/pwrite
 886          * pages from.
 887          */
 888         if (!obj->base.filp) {
 889                 ret = -EINVAL;
 890                 goto out;
 891         }
 892
 893         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 894
 895         ret = -EFAULT;
 896         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 897          * it would end up going through the fenced access, and we'll get
 898          * different detiling behavior between reading and writing.
 899          * pread/pwrite currently are reading and writing from the CPU
 900          * perspective, requiring manual detiling by the client.
 901          */
 902         if (obj->phys_obj) {
 903                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 904                 goto out;
 905         }
 906
 907         if (obj->cache_level == I915_CACHE_NONE &&
 908             obj->tiling_mode == I915_TILING_NONE &&
 909             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 910                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 911                 /* Note that the gtt paths might fail with non-page-backed user
 912                  * pointers (e.g. gtt mappings when moving data between
 913                  * textures). Fallback to the shmem path in that case. */
 914         }
 915
 916         if (ret == -EFAULT || ret == -ENOSPC)
 917                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
 918
 919 out:
 920         drm_gem_object_unreference(&obj->base);
 921 unlock:
 922         mutex_unlock(&dev->struct_mutex);
 923         return ret;
 924 }
 925
 926 int
 927 i915_gem_check_wedge(struct i915_gpu_error *error,
 928                      bool interruptible)
 929 {
 930         if (i915_reset_in_progress(error)) {
 931                 /* Non-interruptible callers can't handle -EAGAIN, hence return
 932                  * -EIO unconditionally for these. */
 933                 if (!interruptible)
 934                         return -EIO;
 935
 936                 /* Recovery complete, but the reset failed ... */
 937                 if (i915_terminally_wedged(error))
 938                         return -EIO;
 939
 940                 return -EAGAIN;
 941         }
 942
 943         return 0;
 944 }
 945
 946 /*
 947  * Compare seqno against outstanding lazy request. Emit a request if they are
 948  * equal.
 949  */
 950 static int
 951 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
 952 {
 953         int ret;
 954
 955         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 956
 957         ret = 0;
 958         if (seqno == ring->outstanding_lazy_request)
 959                 ret = i915_add_request(ring, NULL);
 960
 961         return ret;
 962 }
 963
 964 /**
 965  * __wait_seqno - wait until execution of seqno has finished
 966  * @ring: the ring expected to report seqno
 967  * @seqno: duh!
 968  * @reset_counter: reset sequence associated with the given seqno
 969  * @interruptible: do an interruptible wait (normally yes)
 970  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 971  *
 972  * Note: It is of utmost importance that the passed in seqno and reset_counter
 973  * values have been read by the caller in an smp safe manner. Where read-side
 974  * locks are involved, it is sufficient to read the reset_counter before
 975  * unlocking the lock that protects the seqno. For lockless tricks, the
 976  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
 977  * inserted.
 978  *
 979  * Returns 0 if the seqno was found within the alloted time. Else returns the
 980  * errno with remaining time filled in timeout argument.
 981  */
 982 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
 983                         unsigned reset_counter,
 984                         bool interruptible, struct timespec *timeout)
 985 {
 986         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 987         struct timespec before, now, wait_time={1,0};
 988         unsigned long timeout_jiffies;
 989         long end;
 990         bool wait_forever = true;
 991         int ret;
 992
 993         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
 994                 return 0;
 995
 996         trace_i915_gem_request_wait_begin(ring, seqno);
 997
 998         if (timeout != NULL) {
 999                 wait_time = *timeout;
1000                 wait_forever = false;
1001         }
1002
1003         timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1004
1005         if (WARN_ON(!ring->irq_get(ring)))
1006                 return -ENODEV;
1007
1008         /* Record current time in case interrupted by signal, or wedged * */
1009         getrawmonotonic(&before);
1010
1011 #define EXIT_COND \
1012         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1013          i915_reset_in_progress(&dev_priv->gpu_error) || \
1014          reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1015         do {
1016                 if (interruptible)
1017                         end = wait_event_interruptible_timeout(ring->irq_queue,
1018                                                                EXIT_COND,
1019                                                                timeout_jiffies);
1020                 else
1021                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1022                                                  timeout_jiffies);
1023
1024                 /* We need to check whether any gpu reset happened in between
1025                  * the caller grabbing the seqno and now ... */
1026                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1027                         end = -EAGAIN;
1028
1029                 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1030                  * gone. */
1031                 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1032                 if (ret)
1033                         end = ret;
1034         } while (end == 0 && wait_forever);
1035
1036         getrawmonotonic(&now);
1037
1038         ring->irq_put(ring);
1039         trace_i915_gem_request_wait_end(ring, seqno);
1040 #undef EXIT_COND
1041
1042         if (timeout) {
1043                 struct timespec sleep_time = timespec_sub(now, before);
1044                 *timeout = timespec_sub(*timeout, sleep_time);
1045                 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1046                         set_normalized_timespec(timeout, 0, 0);
1047         }
1048
1049         switch (end) {
1050         case -EIO:
1051         case -EAGAIN: /* Wedged */
1052         case -ERESTARTSYS: /* Signal */
1053                 return (int)end;
1054         case 0: /* Timeout */
1055                 return -ETIME;
1056         default: /* Completed */
1057                 WARN_ON(end < 0); /* We're not aware of other errors */
1058                 return 0;
1059         }
1060 }
1061
1062 /**
1063  * Waits for a sequence number to be signaled, and cleans up the
1064  * request and object lists appropriately for that event.
1065  */
1066 int
1067 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1068 {
1069         struct drm_device *dev = ring->dev;
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         bool interruptible = dev_priv->mm.interruptible;
1072         int ret;
1073
1074         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1075         BUG_ON(seqno == 0);
1076
1077         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1078         if (ret)
1079                 return ret;
1080
1081         ret = i915_gem_check_olr(ring, seqno);
1082         if (ret)
1083                 return ret;
1084
1085         return __wait_seqno(ring, seqno,
1086                             atomic_read(&dev_priv->gpu_error.reset_counter),
1087                             interruptible, NULL);
1088 }
1089
1090 static int
1091 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1092                                      struct intel_ring_buffer *ring)
1093 {
1094         i915_gem_retire_requests_ring(ring);
1095
1096         /* Manually manage the write flush as we may have not yet
1097          * retired the buffer.
1098          *
1099          * Note that the last_write_seqno is always the earlier of
1100          * the two (read/write) seqno, so if we haved successfully waited,
1101          * we know we have passed the last write.
1102          */
1103         obj->last_write_seqno = 0;
1104         obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1105
1106         return 0;
1107 }
1108
1109 /**
1110  * Ensures that all rendering to the object has completed and the object is
1111  * safe to unbind from the GTT or access from the CPU.
1112  */
1113 static __must_check int
1114 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1115                                bool readonly)
1116 {
1117         struct intel_ring_buffer *ring = obj->ring;
1118         u32 seqno;
1119         int ret;
1120
1121         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1122         if (seqno == 0)
1123                 return 0;
1124
1125         ret = i915_wait_seqno(ring, seqno);
1126         if (ret)
1127                 return ret;
1128
1129         return i915_gem_object_wait_rendering__tail(obj, ring);
1130 }
1131
1132 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1133  * as the object state may change during this call.
1134  */
1135 static __must_check int
1136 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1137                                             bool readonly)
1138 {
1139         struct drm_device *dev = obj->base.dev;
1140         struct drm_i915_private *dev_priv = dev->dev_private;
1141         struct intel_ring_buffer *ring = obj->ring;
1142         unsigned reset_counter;
1143         u32 seqno;
1144         int ret;
1145
1146         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1147         BUG_ON(!dev_priv->mm.interruptible);
1148
1149         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1150         if (seqno == 0)
1151                 return 0;
1152
1153         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1154         if (ret)
1155                 return ret;
1156
1157         ret = i915_gem_check_olr(ring, seqno);
1158         if (ret)
1159                 return ret;
1160
1161         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1162         mutex_unlock(&dev->struct_mutex);
1163         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1164         mutex_lock(&dev->struct_mutex);
1165         if (ret)
1166                 return ret;
1167
1168         return i915_gem_object_wait_rendering__tail(obj, ring);
1169 }
1170
1171 /**
1172  * Called when user space prepares to use an object with the CPU, either
1173  * through the mmap ioctl's mapping or a GTT mapping.
1174  */
1175 int
1176 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1177                           struct drm_file *file)
1178 {
1179         struct drm_i915_gem_set_domain *args = data;
1180         struct drm_i915_gem_object *obj;
1181         uint32_t read_domains = args->read_domains;
1182         uint32_t write_domain = args->write_domain;
1183         int ret;
1184
1185         /* Only handle setting domains to types used by the CPU. */
1186         if (write_domain & I915_GEM_GPU_DOMAINS)
1187                 return -EINVAL;
1188
1189         if (read_domains & I915_GEM_GPU_DOMAINS)
1190                 return -EINVAL;
1191
1192         /* Having something in the write domain implies it's in the read
1193          * domain, and only that read domain.  Enforce that in the request.
1194          */
1195         if (write_domain != 0 && read_domains != write_domain)
1196                 return -EINVAL;
1197
1198         ret = i915_mutex_lock_interruptible(dev);
1199         if (ret)
1200                 return ret;
1201
1202         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1203         if (&obj->base == NULL) {
1204                 ret = -ENOENT;
1205                 goto unlock;
1206         }
1207
1208         /* Try to flush the object off the GPU without holding the lock.
1209          * We will repeat the flush holding the lock in the normal manner
1210          * to catch cases where we are gazumped.
1211          */
1212         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1213         if (ret)
1214                 goto unref;
1215
1216         if (read_domains & I915_GEM_DOMAIN_GTT) {
1217                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1218
1219                 /* Silently promote "you're not bound, there was nothing to do"
1220                  * to success, since the client was just asking us to
1221                  * make sure everything was done.
1222                  */
1223                 if (ret == -EINVAL)
1224                         ret = 0;
1225         } else {
1226                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1227         }
1228
1229 unref:
1230         drm_gem_object_unreference(&obj->base);
1231 unlock:
1232         mutex_unlock(&dev->struct_mutex);
1233         return ret;
1234 }
1235
1236 /**
1237  * Called when user space has done writes to this buffer
1238  */
1239 int
1240 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1241                          struct drm_file *file)
1242 {
1243         struct drm_i915_gem_sw_finish *args = data;
1244         struct drm_i915_gem_object *obj;
1245         int ret = 0;
1246
1247         ret = i915_mutex_lock_interruptible(dev);
1248         if (ret)
1249                 return ret;
1250
1251         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1252         if (&obj->base == NULL) {
1253                 ret = -ENOENT;
1254                 goto unlock;
1255         }
1256
1257         /* Pinned buffers may be scanout, so flush the cache */
1258         if (obj->pin_count)
1259                 i915_gem_object_flush_cpu_write_domain(obj);
1260
1261         drm_gem_object_unreference(&obj->base);
1262 unlock:
1263         mutex_unlock(&dev->struct_mutex);
1264         return ret;
1265 }
1266
1267 /**
1268  * Maps the contents of an object, returning the address it is mapped
1269  * into.
1270  *
1271  * While the mapping holds a reference on the contents of the object, it doesn't
1272  * imply a ref on the object itself.
1273  */
1274 int
1275 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1276                     struct drm_file *file)
1277 {
1278         struct drm_i915_gem_mmap *args = data;
1279         struct drm_gem_object *obj;
1280         unsigned long addr;
1281
1282         obj = drm_gem_object_lookup(dev, file, args->handle);
1283         if (obj == NULL)
1284                 return -ENOENT;
1285
1286         /* prime objects have no backing filp to GEM mmap
1287          * pages from.
1288          */
1289         if (!obj->filp) {
1290                 drm_gem_object_unreference_unlocked(obj);
1291                 return -EINVAL;
1292         }
1293
1294         addr = vm_mmap(obj->filp, 0, args->size,
1295                        PROT_READ | PROT_WRITE, MAP_SHARED,
1296                        args->offset);
1297         drm_gem_object_unreference_unlocked(obj);
1298         if (IS_ERR((void *)addr))
1299                 return addr;
1300
1301         args->addr_ptr = (uint64_t) addr;
1302
1303         return 0;
1304 }
1305
1306 /**
1307  * i915_gem_fault - fault a page into the GTT
1308  * vma: VMA in question
1309  * vmf: fault info
1310  *
1311  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1312  * from userspace.  The fault handler takes care of binding the object to
1313  * the GTT (if needed), allocating and programming a fence register (again,
1314  * only if needed based on whether the old reg is still valid or the object
1315  * is tiled) and inserting a new PTE into the faulting process.
1316  *
1317  * Note that the faulting process may involve evicting existing objects
1318  * from the GTT and/or fence registers to make room.  So performance may
1319  * suffer if the GTT working set is large or there are few fence registers
1320  * left.
1321  */
1322 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1323 {
1324         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1325         struct drm_device *dev = obj->base.dev;
1326         drm_i915_private_t *dev_priv = dev->dev_private;
1327         pgoff_t page_offset;
1328         unsigned long pfn;
1329         int ret = 0;
1330         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1331
1332         /* We don't use vmf->pgoff since that has the fake offset */
1333         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1334                 PAGE_SHIFT;
1335
1336         ret = i915_mutex_lock_interruptible(dev);
1337         if (ret)
1338                 goto out;
1339
1340         trace_i915_gem_object_fault(obj, page_offset, true, write);
1341
1342         /* Access to snoopable pages through the GTT is incoherent. */
1343         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1344                 ret = -EINVAL;
1345                 goto unlock;
1346         }
1347
1348         /* Now bind it into the GTT if needed */
1349         ret = i915_gem_object_pin(obj, 0, true, false);
1350         if (ret)
1351                 goto unlock;
1352
1353         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1354         if (ret)
1355                 goto unpin;
1356
1357         ret = i915_gem_object_get_fence(obj);
1358         if (ret)
1359                 goto unpin;
1360
1361         obj->fault_mappable = true;
1362
1363         pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) +
1364                 page_offset;
1365
1366         /* Finally, remap it using the new GTT offset */
1367         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1368 unpin:
1369         i915_gem_object_unpin(obj);
1370 unlock:
1371         mutex_unlock(&dev->struct_mutex);
1372 out:
1373         switch (ret) {
1374         case -EIO:
1375                 /* If this -EIO is due to a gpu hang, give the reset code a
1376                  * chance to clean up the mess. Otherwise return the proper
1377                  * SIGBUS. */
1378                 if (i915_terminally_wedged(&dev_priv->gpu_error))
1379                         return VM_FAULT_SIGBUS;
1380         case -EAGAIN:
1381                 /* Give the error handler a chance to run and move the
1382                  * objects off the GPU active list. Next time we service the
1383                  * fault, we should be able to transition the page into the
1384                  * GTT without touching the GPU (and so avoid further
1385                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1386                  * with coherency, just lost writes.
1387                  */
1388                 set_need_resched();
1389         case 0:
1390         case -ERESTARTSYS:
1391         case -EINTR:
1392         case -EBUSY:
1393                 /*
1394                  * EBUSY is ok: this just means that another thread
1395                  * already did the job.
1396                  */
1397                 return VM_FAULT_NOPAGE;
1398         case -ENOMEM:
1399                 return VM_FAULT_OOM;
1400         case -ENOSPC:
1401                 return VM_FAULT_SIGBUS;
1402         default:
1403                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1404                 return VM_FAULT_SIGBUS;
1405         }
1406 }
1407
1408 /**
1409  * i915_gem_release_mmap - remove physical page mappings
1410  * @obj: obj in question
1411  *
1412  * Preserve the reservation of the mmapping with the DRM core code, but
1413  * relinquish ownership of the pages back to the system.
1414  *
1415  * It is vital that we remove the page mapping if we have mapped a tiled
1416  * object through the GTT and then lose the fence register due to
1417  * resource pressure. Similarly if the object has been moved out of the
1418  * aperture, than pages mapped into userspace must be revoked. Removing the
1419  * mapping will then trigger a page fault on the next user access, allowing
1420  * fixup by i915_gem_fault().
1421  */
1422 void
1423 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1424 {
1425         if (!obj->fault_mappable)
1426                 return;
1427
1428         if (obj->base.dev->dev_mapping)
1429                 unmap_mapping_range(obj->base.dev->dev_mapping,
1430                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1431                                     obj->base.size, 1);
1432
1433         obj->fault_mappable = false;
1434 }
1435
1436 uint32_t
1437 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1438 {
1439         uint32_t gtt_size;
1440
1441         if (INTEL_INFO(dev)->gen >= 4 ||
1442             tiling_mode == I915_TILING_NONE)
1443                 return size;
1444
1445         /* Previous chips need a power-of-two fence region when tiling */
1446         if (INTEL_INFO(dev)->gen == 3)
1447                 gtt_size = 1024*1024;
1448         else
1449                 gtt_size = 512*1024;
1450
1451         while (gtt_size < size)
1452                 gtt_size <<= 1;
1453
1454         return gtt_size;
1455 }
1456
1457 /**
1458  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1459  * @obj: object to check
1460  *
1461  * Return the required GTT alignment for an object, taking into account
1462  * potential fence register mapping.
1463  */
1464 uint32_t
1465 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1466                            int tiling_mode, bool fenced)
1467 {
1468         /*
1469          * Minimum alignment is 4k (GTT page size), but might be greater
1470          * if a fence register is needed for the object.
1471          */
1472         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1473             tiling_mode == I915_TILING_NONE)
1474                 return 4096;
1475
1476         /*
1477          * Previous chips need to be aligned to the size of the smallest
1478          * fence register that can contain the object.
1479          */
1480         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1481 }
1482
1483 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1484 {
1485         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1486         int ret;
1487
1488         if (obj->base.map_list.map)
1489                 return 0;
1490
1491         dev_priv->mm.shrinker_no_lock_stealing = true;
1492
1493         ret = drm_gem_create_mmap_offset(&obj->base);
1494         if (ret != -ENOSPC)
1495                 goto out;
1496
1497         /* Badly fragmented mmap space? The only way we can recover
1498          * space is by destroying unwanted objects. We can't randomly release
1499          * mmap_offsets as userspace expects them to be persistent for the
1500          * lifetime of the objects. The closest we can is to release the
1501          * offsets on purgeable objects by truncating it and marking it purged,
1502          * which prevents userspace from ever using that object again.
1503          */
1504         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1505         ret = drm_gem_create_mmap_offset(&obj->base);
1506         if (ret != -ENOSPC)
1507                 goto out;
1508
1509         i915_gem_shrink_all(dev_priv);
1510         ret = drm_gem_create_mmap_offset(&obj->base);
1511 out:
1512         dev_priv->mm.shrinker_no_lock_stealing = false;
1513
1514         return ret;
1515 }
1516
1517 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1518 {
1519         if (!obj->base.map_list.map)
1520                 return;
1521
1522         drm_gem_free_mmap_offset(&obj->base);
1523 }
1524
1525 int
1526 i915_gem_mmap_gtt(struct drm_file *file,
1527                   struct drm_device *dev,
1528                   uint32_t handle,
1529                   uint64_t *offset)
1530 {
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         struct drm_i915_gem_object *obj;
1533         int ret;
1534
1535         ret = i915_mutex_lock_interruptible(dev);
1536         if (ret)
1537                 return ret;
1538
1539         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1540         if (&obj->base == NULL) {
1541                 ret = -ENOENT;
1542                 goto unlock;
1543         }
1544
1545         if (obj->base.size > dev_priv->gtt.mappable_end) {
1546                 ret = -E2BIG;
1547                 goto out;
1548         }
1549
1550         if (obj->madv != I915_MADV_WILLNEED) {
1551                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1552                 ret = -EINVAL;
1553                 goto out;
1554         }
1555
1556         ret = i915_gem_object_create_mmap_offset(obj);
1557         if (ret)
1558                 goto out;
1559
1560         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1561
1562 out:
1563         drm_gem_object_unreference(&obj->base);
1564 unlock:
1565         mutex_unlock(&dev->struct_mutex);
1566         return ret;
1567 }
1568
1569 /**
1570  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1571  * @dev: DRM device
1572  * @data: GTT mapping ioctl data
1573  * @file: GEM object info
1574  *
1575  * Simply returns the fake offset to userspace so it can mmap it.
1576  * The mmap call will end up in drm_gem_mmap(), which will set things
1577  * up so we can get faults in the handler above.
1578  *
1579  * The fault handler will take care of binding the object into the GTT
1580  * (since it may have been evicted to make room for something), allocating
1581  * a fence register, and mapping the appropriate aperture address into
1582  * userspace.
1583  */
1584 int
1585 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1586                         struct drm_file *file)
1587 {
1588         struct drm_i915_gem_mmap_gtt *args = data;
1589
1590         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1591 }
1592
1593 /* Immediately discard the backing storage */
1594 static void
1595 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1596 {
1597         struct inode *inode;
1598
1599         i915_gem_object_free_mmap_offset(obj);
1600
1601         if (obj->base.filp == NULL)
1602                 return;
1603
1604         /* Our goal here is to return as much of the memory as
1605          * is possible back to the system as we are called from OOM.
1606          * To do this we must instruct the shmfs to drop all of its
1607          * backing pages, *now*.
1608          */
1609         inode = file_inode(obj->base.filp);
1610         shmem_truncate_range(inode, 0, (loff_t)-1);
1611
1612         obj->madv = __I915_MADV_PURGED;
1613 }
1614
1615 static inline int
1616 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1617 {
1618         return obj->madv == I915_MADV_DONTNEED;
1619 }
1620
1621 static void
1622 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1623 {
1624         struct sg_page_iter sg_iter;
1625         int ret;
1626
1627         BUG_ON(obj->madv == __I915_MADV_PURGED);
1628
1629         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1630         if (ret) {
1631                 /* In the event of a disaster, abandon all caches and
1632                  * hope for the best.
1633                  */
1634                 WARN_ON(ret != -EIO);
1635                 i915_gem_clflush_object(obj);
1636                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1637         }
1638
1639         if (i915_gem_object_needs_bit17_swizzle(obj))
1640                 i915_gem_object_save_bit_17_swizzle(obj);
1641
1642         if (obj->madv == I915_MADV_DONTNEED)
1643                 obj->dirty = 0;
1644
1645         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1646                 struct page *page = sg_page_iter_page(&sg_iter);
1647
1648                 if (obj->dirty)
1649                         set_page_dirty(page);
1650
1651                 if (obj->madv == I915_MADV_WILLNEED)
1652                         mark_page_accessed(page);
1653
1654                 page_cache_release(page);
1655         }
1656         obj->dirty = 0;
1657
1658         sg_free_table(obj->pages);
1659         kfree(obj->pages);
1660 }
1661
1662 int
1663 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1664 {
1665         const struct drm_i915_gem_object_ops *ops = obj->ops;
1666
1667         if (obj->pages == NULL)
1668                 return 0;
1669
1670         BUG_ON(obj->gtt_space);
1671
1672         if (obj->pages_pin_count)
1673                 return -EBUSY;
1674
1675         /* ->put_pages might need to allocate memory for the bit17 swizzle
1676          * array, hence protect them from being reaped by removing them from gtt
1677          * lists early. */
1678         list_del(&obj->global_list);
1679
1680         ops->put_pages(obj);
1681         obj->pages = NULL;
1682
1683         if (i915_gem_object_is_purgeable(obj))
1684                 i915_gem_object_truncate(obj);
1685
1686         return 0;
1687 }
1688
1689 static long
1690 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1691                   bool purgeable_only)
1692 {
1693         struct drm_i915_gem_object *obj, *next;
1694         long count = 0;
1695
1696         list_for_each_entry_safe(obj, next,
1697                                  &dev_priv->mm.unbound_list,
1698                                  global_list) {
1699                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1700                     i915_gem_object_put_pages(obj) == 0) {
1701                         count += obj->base.size >> PAGE_SHIFT;
1702                         if (count >= target)
1703                                 return count;
1704                 }
1705         }
1706
1707         list_for_each_entry_safe(obj, next,
1708                                  &dev_priv->mm.inactive_list,
1709                                  mm_list) {
1710                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1711                     i915_gem_object_unbind(obj) == 0 &&
1712                     i915_gem_object_put_pages(obj) == 0) {
1713                         count += obj->base.size >> PAGE_SHIFT;
1714                         if (count >= target)
1715                                 return count;
1716                 }
1717         }
1718
1719         return count;
1720 }
1721
1722 static long
1723 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1724 {
1725         return __i915_gem_shrink(dev_priv, target, true);
1726 }
1727
1728 static void
1729 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1730 {
1731         struct drm_i915_gem_object *obj, *next;
1732
1733         i915_gem_evict_everything(dev_priv->dev);
1734
1735         list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1736                                  global_list)
1737                 i915_gem_object_put_pages(obj);
1738 }
1739
1740 static int
1741 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1742 {
1743         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1744         int page_count, i;
1745         struct address_space *mapping;
1746         struct sg_table *st;
1747         struct scatterlist *sg;
1748         struct sg_page_iter sg_iter;
1749         struct page *page;
1750         unsigned long last_pfn = 0;     /* suppress gcc warning */
1751         gfp_t gfp;
1752
1753         /* Assert that the object is not currently in any GPU domain. As it
1754          * wasn't in the GTT, there shouldn't be any way it could have been in
1755          * a GPU cache
1756          */
1757         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1758         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1759
1760         st = kmalloc(sizeof(*st), GFP_KERNEL);
1761         if (st == NULL)
1762                 return -ENOMEM;
1763
1764         page_count = obj->base.size / PAGE_SIZE;
1765         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1766                 sg_free_table(st);
1767                 kfree(st);
1768                 return -ENOMEM;
1769         }
1770
1771         /* Get the list of pages out of our struct file.  They'll be pinned
1772          * at this point until we release them.
1773          *
1774          * Fail silently without starting the shrinker
1775          */
1776         mapping = file_inode(obj->base.filp)->i_mapping;
1777         gfp = mapping_gfp_mask(mapping);
1778         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1779         gfp &= ~(__GFP_IO | __GFP_WAIT);
1780         sg = st->sgl;
1781         st->nents = 0;
1782         for (i = 0; i < page_count; i++) {
1783                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1784                 if (IS_ERR(page)) {
1785                         i915_gem_purge(dev_priv, page_count);
1786                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1787                 }
1788                 if (IS_ERR(page)) {
1789                         /* We've tried hard to allocate the memory by reaping
1790                          * our own buffer, now let the real VM do its job and
1791                          * go down in flames if truly OOM.
1792                          */
1793                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1794                         gfp |= __GFP_IO | __GFP_WAIT;
1795
1796                         i915_gem_shrink_all(dev_priv);
1797                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1798                         if (IS_ERR(page))
1799                                 goto err_pages;
1800
1801                         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1802                         gfp &= ~(__GFP_IO | __GFP_WAIT);
1803                 }
1804 #ifdef CONFIG_SWIOTLB
1805                 if (swiotlb_nr_tbl()) {
1806                         st->nents++;
1807                         sg_set_page(sg, page, PAGE_SIZE, 0);
1808                         sg = sg_next(sg);
1809                         continue;
1810                 }
1811 #endif
1812                 if (!i || page_to_pfn(page) != last_pfn + 1) {
1813                         if (i)
1814                                 sg = sg_next(sg);
1815                         st->nents++;
1816                         sg_set_page(sg, page, PAGE_SIZE, 0);
1817                 } else {
1818                         sg->length += PAGE_SIZE;
1819                 }
1820                 last_pfn = page_to_pfn(page);
1821         }
1822 #ifdef CONFIG_SWIOTLB
1823         if (!swiotlb_nr_tbl())
1824 #endif
1825                 sg_mark_end(sg);
1826         obj->pages = st;
1827
1828         if (i915_gem_object_needs_bit17_swizzle(obj))
1829                 i915_gem_object_do_bit_17_swizzle(obj);
1830
1831         return 0;
1832
1833 err_pages:
1834         sg_mark_end(sg);
1835         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1836                 page_cache_release(sg_page_iter_page(&sg_iter));
1837         sg_free_table(st);
1838         kfree(st);
1839         return PTR_ERR(page);
1840 }
1841
1842 /* Ensure that the associated pages are gathered from the backing storage
1843  * and pinned into our object. i915_gem_object_get_pages() may be called
1844  * multiple times before they are released by a single call to
1845  * i915_gem_object_put_pages() - once the pages are no longer referenced
1846  * either as a result of memory pressure (reaping pages under the shrinker)
1847  * or as the object is itself released.
1848  */
1849 int
1850 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1851 {
1852         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1853         const struct drm_i915_gem_object_ops *ops = obj->ops;
1854         int ret;
1855
1856         if (obj->pages)
1857                 return 0;
1858
1859         if (obj->madv != I915_MADV_WILLNEED) {
1860                 DRM_ERROR("Attempting to obtain a purgeable object\n");
1861                 return -EINVAL;
1862         }
1863
1864         BUG_ON(obj->pages_pin_count);
1865
1866         ret = ops->get_pages(obj);
1867         if (ret)
1868                 return ret;
1869
1870         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1871         return 0;
1872 }
1873
1874 void
1875 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1876                                struct intel_ring_buffer *ring)
1877 {
1878         struct drm_device *dev = obj->base.dev;
1879         struct drm_i915_private *dev_priv = dev->dev_private;
1880         u32 seqno = intel_ring_get_seqno(ring);
1881
1882         BUG_ON(ring == NULL);
1883         if (obj->ring != ring && obj->last_write_seqno) {
1884                 /* Keep the seqno relative to the current ring */
1885                 obj->last_write_seqno = seqno;
1886         }
1887         obj->ring = ring;
1888
1889         /* Add a reference if we're newly entering the active list. */
1890         if (!obj->active) {
1891                 drm_gem_object_reference(&obj->base);
1892                 obj->active = 1;
1893         }
1894
1895         /* Move from whatever list we were on to the tail of execution. */
1896         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1897         list_move_tail(&obj->ring_list, &ring->active_list);
1898
1899         obj->last_read_seqno = seqno;
1900
1901         if (obj->fenced_gpu_access) {
1902                 obj->last_fenced_seqno = seqno;
1903
1904                 /* Bump MRU to take account of the delayed flush */
1905                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1906                         struct drm_i915_fence_reg *reg;
1907
1908                         reg = &dev_priv->fence_regs[obj->fence_reg];
1909                         list_move_tail(&reg->lru_list,
1910                                        &dev_priv->mm.fence_list);
1911                 }
1912         }
1913 }
1914
1915 static void
1916 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1917 {
1918         struct drm_device *dev = obj->base.dev;
1919         struct drm_i915_private *dev_priv = dev->dev_private;
1920
1921         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1922         BUG_ON(!obj->active);
1923
1924         list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1925
1926         list_del_init(&obj->ring_list);
1927         obj->ring = NULL;
1928
1929         obj->last_read_seqno = 0;
1930         obj->last_write_seqno = 0;
1931         obj->base.write_domain = 0;
1932
1933         obj->last_fenced_seqno = 0;
1934         obj->fenced_gpu_access = false;
1935
1936         obj->active = 0;
1937         drm_gem_object_unreference(&obj->base);
1938
1939         WARN_ON(i915_verify_lists(dev));
1940 }
1941
1942 static int
1943 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1944 {
1945         struct drm_i915_private *dev_priv = dev->dev_private;
1946         struct intel_ring_buffer *ring;
1947         int ret, i, j;
1948
1949         /* Carefully retire all requests without writing to the rings */
1950         for_each_ring(ring, dev_priv, i) {
1951                 ret = intel_ring_idle(ring);
1952                 if (ret)
1953                         return ret;
1954         }
1955         i915_gem_retire_requests(dev);
1956
1957         /* Finally reset hw state */
1958         for_each_ring(ring, dev_priv, i) {
1959                 intel_ring_init_seqno(ring, seqno);
1960
1961                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1962                         ring->sync_seqno[j] = 0;
1963         }
1964
1965         return 0;
1966 }
1967
1968 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1969 {
1970         struct drm_i915_private *dev_priv = dev->dev_private;
1971         int ret;
1972
1973         if (seqno == 0)
1974                 return -EINVAL;
1975
1976         /* HWS page needs to be set less than what we
1977          * will inject to ring
1978          */
1979         ret = i915_gem_init_seqno(dev, seqno - 1);
1980         if (ret)
1981                 return ret;
1982
1983         /* Carefully set the last_seqno value so that wrap
1984          * detection still works
1985          */
1986         dev_priv->next_seqno = seqno;
1987         dev_priv->last_seqno = seqno - 1;
1988         if (dev_priv->last_seqno == 0)
1989                 dev_priv->last_seqno--;
1990
1991         return 0;
1992 }
1993
1994 int
1995 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1996 {
1997         struct drm_i915_private *dev_priv = dev->dev_private;
1998
1999         /* reserve 0 for non-seqno */
2000         if (dev_priv->next_seqno == 0) {
2001                 int ret = i915_gem_init_seqno(dev, 0);
2002                 if (ret)
2003                         return ret;
2004
2005                 dev_priv->next_seqno = 1;
2006         }
2007
2008         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2009         return 0;
2010 }
2011
2012 int __i915_add_request(struct intel_ring_buffer *ring,
2013                        struct drm_file *file,
2014                        struct drm_i915_gem_object *obj,
2015                        u32 *out_seqno)
2016 {
2017         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2018         struct drm_i915_gem_request *request;
2019         u32 request_ring_position, request_start;
2020         int was_empty;
2021         int ret;
2022
2023         request_start = intel_ring_get_tail(ring);
2024         /*
2025          * Emit any outstanding flushes - execbuf can fail to emit the flush
2026          * after having emitted the batchbuffer command. Hence we need to fix
2027          * things up similar to emitting the lazy request. The difference here
2028          * is that the flush _must_ happen before the next request, no matter
2029          * what.
2030          */
2031         ret = intel_ring_flush_all_caches(ring);
2032         if (ret)
2033                 return ret;
2034
2035         request = kmalloc(sizeof(*request), GFP_KERNEL);
2036         if (request == NULL)
2037                 return -ENOMEM;
2038
2039
2040         /* Record the position of the start of the request so that
2041          * should we detect the updated seqno part-way through the
2042          * GPU processing the request, we never over-estimate the
2043          * position of the head.
2044          */
2045         request_ring_position = intel_ring_get_tail(ring);
2046
2047         ret = ring->add_request(ring);
2048         if (ret) {
2049                 kfree(request);
2050                 return ret;
2051         }
2052
2053         request->seqno = intel_ring_get_seqno(ring);
2054         request->ring = ring;
2055         request->head = request_start;
2056         request->tail = request_ring_position;
2057         request->ctx = ring->last_context;
2058         request->batch_obj = obj;
2059
2060         /* Whilst this request exists, batch_obj will be on the
2061          * active_list, and so will hold the active reference. Only when this
2062          * request is retired will the the batch_obj be moved onto the
2063          * inactive_list and lose its active reference. Hence we do not need
2064          * to explicitly hold another reference here.
2065          */
2066
2067         if (request->ctx)
2068                 i915_gem_context_reference(request->ctx);
2069
2070         request->emitted_jiffies = jiffies;
2071         was_empty = list_empty(&ring->request_list);
2072         list_add_tail(&request->list, &ring->request_list);
2073         request->file_priv = NULL;
2074
2075         if (file) {
2076                 struct drm_i915_file_private *file_priv = file->driver_priv;
2077
2078                 spin_lock(&file_priv->mm.lock);
2079                 request->file_priv = file_priv;
2080                 list_add_tail(&request->client_list,
2081                               &file_priv->mm.request_list);
2082                 spin_unlock(&file_priv->mm.lock);
2083         }
2084
2085         trace_i915_gem_request_add(ring, request->seqno);
2086         ring->outstanding_lazy_request = 0;
2087
2088         if (!dev_priv->mm.suspended) {
2089                 if (i915_enable_hangcheck) {
2090                         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2091                                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2092                 }
2093                 if (was_empty) {
2094                         queue_delayed_work(dev_priv->wq,
2095                                            &dev_priv->mm.retire_work,
2096                                            round_jiffies_up_relative(HZ));
2097                         intel_mark_busy(dev_priv->dev);
2098                 }
2099         }
2100
2101         if (out_seqno)
2102                 *out_seqno = request->seqno;
2103         return 0;
2104 }
2105
2106 static inline void
2107 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2108 {
2109         struct drm_i915_file_private *file_priv = request->file_priv;
2110
2111         if (!file_priv)
2112                 return;
2113
2114         spin_lock(&file_priv->mm.lock);
2115         if (request->file_priv) {
2116                 list_del(&request->client_list);
2117                 request->file_priv = NULL;
2118         }
2119         spin_unlock(&file_priv->mm.lock);
2120 }
2121
2122 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2123 {
2124         if (acthd >= obj->gtt_offset &&
2125             acthd < obj->gtt_offset + obj->base.size)
2126                 return true;
2127
2128         return false;
2129 }
2130
2131 static bool i915_head_inside_request(const u32 acthd_unmasked,
2132                                      const u32 request_start,
2133                                      const u32 request_end)
2134 {
2135         const u32 acthd = acthd_unmasked & HEAD_ADDR;
2136
2137         if (request_start < request_end) {
2138                 if (acthd >= request_start && acthd < request_end)
2139                         return true;
2140         } else if (request_start > request_end) {
2141                 if (acthd >= request_start || acthd < request_end)
2142                         return true;
2143         }
2144
2145         return false;
2146 }
2147
2148 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2149                                 const u32 acthd, bool *inside)
2150 {
2151         /* There is a possibility that unmasked head address
2152          * pointing inside the ring, matches the batch_obj address range.
2153          * However this is extremely unlikely.
2154          */
2155
2156         if (request->batch_obj) {
2157                 if (i915_head_inside_object(acthd, request->batch_obj)) {
2158                         *inside = true;
2159                         return true;
2160                 }
2161         }
2162
2163         if (i915_head_inside_request(acthd, request->head, request->tail)) {
2164                 *inside = false;
2165                 return true;
2166         }
2167
2168         return false;
2169 }
2170
2171 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2172                                   struct drm_i915_gem_request *request,
2173                                   u32 acthd)
2174 {
2175         struct i915_ctx_hang_stats *hs = NULL;
2176         bool inside, guilty;
2177
2178         /* Innocent until proven guilty */
2179         guilty = false;
2180
2181         if (ring->hangcheck.action != wait &&
2182             i915_request_guilty(request, acthd, &inside)) {
2183                 DRM_ERROR("%s hung %s bo (0x%x ctx %d) at 0x%x\n",
2184                           ring->name,
2185                           inside ? "inside" : "flushing",
2186                           request->batch_obj ?
2187                           request->batch_obj->gtt_offset : 0,
2188                           request->ctx ? request->ctx->id : 0,
2189                           acthd);
2190
2191                 guilty = true;
2192         }
2193
2194         /* If contexts are disabled or this is the default context, use
2195          * file_priv->reset_state
2196          */
2197         if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2198                 hs = &request->ctx->hang_stats;
2199         else if (request->file_priv)
2200                 hs = &request->file_priv->hang_stats;
2201
2202         if (hs) {
2203                 if (guilty)
2204                         hs->batch_active++;
2205                 else
2206                         hs->batch_pending++;
2207         }
2208 }
2209
2210 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2211 {
2212         list_del(&request->list);
2213         i915_gem_request_remove_from_client(request);
2214
2215         if (request->ctx)
2216                 i915_gem_context_unreference(request->ctx);
2217
2218         kfree(request);
2219 }
2220
2221 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2222                                       struct intel_ring_buffer *ring)
2223 {
2224         u32 completed_seqno;
2225         u32 acthd;
2226
2227         acthd = intel_ring_get_active_head(ring);
2228         completed_seqno = ring->get_seqno(ring, false);
2229
2230         while (!list_empty(&ring->request_list)) {
2231                 struct drm_i915_gem_request *request;
2232
2233                 request = list_first_entry(&ring->request_list,
2234                                            struct drm_i915_gem_request,
2235                                            list);
2236
2237                 if (request->seqno > completed_seqno)
2238                         i915_set_reset_status(ring, request, acthd);
2239
2240                 i915_gem_free_request(request);
2241         }
2242
2243         while (!list_empty(&ring->active_list)) {
2244                 struct drm_i915_gem_object *obj;
2245
2246                 obj = list_first_entry(&ring->active_list,
2247                                        struct drm_i915_gem_object,
2248                                        ring_list);
2249
2250                 i915_gem_object_move_to_inactive(obj);
2251         }
2252 }
2253
2254 void i915_gem_restore_fences(struct drm_device *dev)
2255 {
2256         struct drm_i915_private *dev_priv = dev->dev_private;
2257         int i;
2258
2259         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2260                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2261
2262                 /*
2263                  * Commit delayed tiling changes if we have an object still
2264                  * attached to the fence, otherwise just clear the fence.
2265                  */
2266                 if (reg->obj) {
2267                         i915_gem_object_update_fence(reg->obj, reg,
2268                                                      reg->obj->tiling_mode);
2269                 } else {
2270                         i915_gem_write_fence(dev, i, NULL);
2271                 }
2272         }
2273 }
2274
2275 void i915_gem_reset(struct drm_device *dev)
2276 {
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct drm_i915_gem_object *obj;
2279         struct intel_ring_buffer *ring;
2280         int i;
2281
2282         for_each_ring(ring, dev_priv, i)
2283                 i915_gem_reset_ring_lists(dev_priv, ring);
2284
2285         /* Move everything out of the GPU domains to ensure we do any
2286          * necessary invalidation upon reuse.
2287          */
2288         list_for_each_entry(obj,
2289                             &dev_priv->mm.inactive_list,
2290                             mm_list)
2291         {
2292                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2293         }
2294
2295         i915_gem_restore_fences(dev);
2296 }
2297
2298 /**
2299  * This function clears the request list as sequence numbers are passed.
2300  */
2301 void
2302 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2303 {
2304         uint32_t seqno;
2305
2306         if (list_empty(&ring->request_list))
2307                 return;
2308
2309         WARN_ON(i915_verify_lists(ring->dev));
2310
2311         seqno = ring->get_seqno(ring, true);
2312
2313         while (!list_empty(&ring->request_list)) {
2314                 struct drm_i915_gem_request *request;
2315
2316                 request = list_first_entry(&ring->request_list,
2317                                            struct drm_i915_gem_request,
2318                                            list);
2319
2320                 if (!i915_seqno_passed(seqno, request->seqno))
2321                         break;
2322
2323                 trace_i915_gem_request_retire(ring, request->seqno);
2324                 /* We know the GPU must have read the request to have
2325                  * sent us the seqno + interrupt, so use the position
2326                  * of tail of the request to update the last known position
2327                  * of the GPU head.
2328                  */
2329                 ring->last_retired_head = request->tail;
2330
2331                 i915_gem_free_request(request);
2332         }
2333
2334         /* Move any buffers on the active list that are no longer referenced
2335          * by the ringbuffer to the flushing/inactive lists as appropriate.
2336          */
2337         while (!list_empty(&ring->active_list)) {
2338                 struct drm_i915_gem_object *obj;
2339
2340                 obj = list_first_entry(&ring->active_list,
2341                                       struct drm_i915_gem_object,
2342                                       ring_list);
2343
2344                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2345                         break;
2346
2347                 i915_gem_object_move_to_inactive(obj);
2348         }
2349
2350         if (unlikely(ring->trace_irq_seqno &&
2351                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2352                 ring->irq_put(ring);
2353                 ring->trace_irq_seqno = 0;
2354         }
2355
2356         WARN_ON(i915_verify_lists(ring->dev));
2357 }
2358
2359 void
2360 i915_gem_retire_requests(struct drm_device *dev)
2361 {
2362         drm_i915_private_t *dev_priv = dev->dev_private;
2363         struct intel_ring_buffer *ring;
2364         int i;
2365
2366         for_each_ring(ring, dev_priv, i)
2367                 i915_gem_retire_requests_ring(ring);
2368 }
2369
2370 static void
2371 i915_gem_retire_work_handler(struct work_struct *work)
2372 {
2373         drm_i915_private_t *dev_priv;
2374         struct drm_device *dev;
2375         struct intel_ring_buffer *ring;
2376         bool idle;
2377         int i;
2378
2379         dev_priv = container_of(work, drm_i915_private_t,
2380                                 mm.retire_work.work);
2381         dev = dev_priv->dev;
2382
2383         /* Come back later if the device is busy... */
2384         if (!mutex_trylock(&dev->struct_mutex)) {
2385                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2386                                    round_jiffies_up_relative(HZ));
2387                 return;
2388         }
2389
2390         i915_gem_retire_requests(dev);
2391
2392         /* Send a periodic flush down the ring so we don't hold onto GEM
2393          * objects indefinitely.
2394          */
2395         idle = true;
2396         for_each_ring(ring, dev_priv, i) {
2397                 if (ring->gpu_caches_dirty)
2398                         i915_add_request(ring, NULL);
2399
2400                 idle &= list_empty(&ring->request_list);
2401         }
2402
2403         if (!dev_priv->mm.suspended && !idle)
2404                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2405                                    round_jiffies_up_relative(HZ));
2406         if (idle)
2407                 intel_mark_idle(dev);
2408
2409         mutex_unlock(&dev->struct_mutex);
2410 }
2411
2412 /**
2413  * Ensures that an object will eventually get non-busy by flushing any required
2414  * write domains, emitting any outstanding lazy request and retiring and
2415  * completed requests.
2416  */
2417 static int
2418 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2419 {
2420         int ret;
2421
2422         if (obj->active) {
2423                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2424                 if (ret)
2425                         return ret;
2426
2427                 i915_gem_retire_requests_ring(obj->ring);
2428         }
2429
2430         return 0;
2431 }
2432
2433 /**
2434  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2435  * @DRM_IOCTL_ARGS: standard ioctl arguments
2436  *
2437  * Returns 0 if successful, else an error is returned with the remaining time in
2438  * the timeout parameter.
2439  *  -ETIME: object is still busy after timeout
2440  *  -ERESTARTSYS: signal interrupted the wait
2441  *  -ENONENT: object doesn't exist
2442  * Also possible, but rare:
2443  *  -EAGAIN: GPU wedged
2444  *  -ENOMEM: damn
2445  *  -ENODEV: Internal IRQ fail
2446  *  -E?: The add request failed
2447  *
2448  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2449  * non-zero timeout parameter the wait ioctl will wait for the given number of
2450  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2451  * without holding struct_mutex the object may become re-busied before this
2452  * function completes. A similar but shorter * race condition exists in the busy
2453  * ioctl
2454  */
2455 int
2456 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2457 {
2458         drm_i915_private_t *dev_priv = dev->dev_private;
2459         struct drm_i915_gem_wait *args = data;
2460         struct drm_i915_gem_object *obj;
2461         struct intel_ring_buffer *ring = NULL;
2462         struct timespec timeout_stack, *timeout = NULL;
2463         unsigned reset_counter;
2464         u32 seqno = 0;
2465         int ret = 0;
2466
2467         if (args->timeout_ns >= 0) {
2468                 timeout_stack = ns_to_timespec(args->timeout_ns);
2469                 timeout = &timeout_stack;
2470         }
2471
2472         ret = i915_mutex_lock_interruptible(dev);
2473         if (ret)
2474                 return ret;
2475
2476         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2477         if (&obj->base == NULL) {
2478                 mutex_unlock(&dev->struct_mutex);
2479                 return -ENOENT;
2480         }
2481
2482         /* Need to make sure the object gets inactive eventually. */
2483         ret = i915_gem_object_flush_active(obj);
2484         if (ret)
2485                 goto out;
2486
2487         if (obj->active) {
2488                 seqno = obj->last_read_seqno;
2489                 ring = obj->ring;
2490         }
2491
2492         if (seqno == 0)
2493                  goto out;
2494
2495         /* Do this after OLR check to make sure we make forward progress polling
2496          * on this IOCTL with a 0 timeout (like busy ioctl)
2497          */
2498         if (!args->timeout_ns) {
2499                 ret = -ETIME;
2500                 goto out;
2501         }
2502
2503         drm_gem_object_unreference(&obj->base);
2504         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2505         mutex_unlock(&dev->struct_mutex);
2506
2507         ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2508         if (timeout)
2509                 args->timeout_ns = timespec_to_ns(timeout);
2510         return ret;
2511
2512 out:
2513         drm_gem_object_unreference(&obj->base);
2514         mutex_unlock(&dev->struct_mutex);
2515         return ret;
2516 }
2517
2518 /**
2519  * i915_gem_object_sync - sync an object to a ring.
2520  *
2521  * @obj: object which may be in use on another ring.
2522  * @to: ring we wish to use the object on. May be NULL.
2523  *
2524  * This code is meant to abstract object synchronization with the GPU.
2525  * Calling with NULL implies synchronizing the object with the CPU
2526  * rather than a particular GPU ring.
2527  *
2528  * Returns 0 if successful, else propagates up the lower layer error.
2529  */
2530 int
2531 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2532                      struct intel_ring_buffer *to)
2533 {
2534         struct intel_ring_buffer *from = obj->ring;
2535         u32 seqno;
2536         int ret, idx;
2537
2538         if (from == NULL || to == from)
2539                 return 0;
2540
2541         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2542                 return i915_gem_object_wait_rendering(obj, false);
2543
2544         idx = intel_ring_sync_index(from, to);
2545
2546         seqno = obj->last_read_seqno;
2547         if (seqno <= from->sync_seqno[idx])
2548                 return 0;
2549
2550         ret = i915_gem_check_olr(obj->ring, seqno);
2551         if (ret)
2552                 return ret;
2553
2554         ret = to->sync_to(to, from, seqno);
2555         if (!ret)
2556                 /* We use last_read_seqno because sync_to()
2557                  * might have just caused seqno wrap under
2558                  * the radar.
2559                  */
2560                 from->sync_seqno[idx] = obj->last_read_seqno;
2561
2562         return ret;
2563 }
2564
2565 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2566 {
2567         u32 old_write_domain, old_read_domains;
2568
2569         /* Force a pagefault for domain tracking on next user access */
2570         i915_gem_release_mmap(obj);
2571
2572         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2573                 return;
2574
2575         /* Wait for any direct GTT access to complete */
2576         mb();
2577
2578         old_read_domains = obj->base.read_domains;
2579         old_write_domain = obj->base.write_domain;
2580
2581         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2582         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2583
2584         trace_i915_gem_object_change_domain(obj,
2585                                             old_read_domains,
2586                                             old_write_domain);
2587 }
2588
2589 /**
2590  * Unbinds an object from the GTT aperture.
2591  */
2592 int
2593 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2594 {
2595         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2596         int ret;
2597
2598         if (obj->gtt_space == NULL)
2599                 return 0;
2600
2601         if (obj->pin_count)
2602                 return -EBUSY;
2603
2604         BUG_ON(obj->pages == NULL);
2605
2606         ret = i915_gem_object_finish_gpu(obj);
2607         if (ret)
2608                 return ret;
2609         /* Continue on if we fail due to EIO, the GPU is hung so we
2610          * should be safe and we need to cleanup or else we might
2611          * cause memory corruption through use-after-free.
2612          */
2613
2614         i915_gem_object_finish_gtt(obj);
2615
2616         /* release the fence reg _after_ flushing */
2617         ret = i915_gem_object_put_fence(obj);
2618         if (ret)
2619                 return ret;
2620
2621         trace_i915_gem_object_unbind(obj);
2622
2623         if (obj->has_global_gtt_mapping)
2624                 i915_gem_gtt_unbind_object(obj);
2625         if (obj->has_aliasing_ppgtt_mapping) {
2626                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2627                 obj->has_aliasing_ppgtt_mapping = 0;
2628         }
2629         i915_gem_gtt_finish_object(obj);
2630         i915_gem_object_unpin_pages(obj);
2631
2632         list_del(&obj->mm_list);
2633         list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2634         /* Avoid an unnecessary call to unbind on rebind. */
2635         obj->map_and_fenceable = true;
2636
2637         drm_mm_put_block(obj->gtt_space);
2638         obj->gtt_space = NULL;
2639         obj->gtt_offset = 0;
2640
2641         return 0;
2642 }
2643
2644 int i915_gpu_idle(struct drm_device *dev)
2645 {
2646         drm_i915_private_t *dev_priv = dev->dev_private;
2647         struct intel_ring_buffer *ring;
2648         int ret, i;
2649
2650         /* Flush everything onto the inactive list. */
2651         for_each_ring(ring, dev_priv, i) {
2652                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2653                 if (ret)
2654                         return ret;
2655
2656                 ret = intel_ring_idle(ring);
2657                 if (ret)
2658                         return ret;
2659         }
2660
2661         return 0;
2662 }
2663
2664 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2665                                  struct drm_i915_gem_object *obj)
2666 {
2667         drm_i915_private_t *dev_priv = dev->dev_private;
2668         int fence_reg;
2669         int fence_pitch_shift;
2670
2671         if (INTEL_INFO(dev)->gen >= 6) {
2672                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2673                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2674         } else {
2675                 fence_reg = FENCE_REG_965_0;
2676                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2677         }
2678
2679         fence_reg += reg * 8;
2680
2681         /* To w/a incoherency with non-atomic 64-bit register updates,
2682          * we split the 64-bit update into two 32-bit writes. In order
2683          * for a partial fence not to be evaluated between writes, we
2684          * precede the update with write to turn off the fence register,
2685          * and only enable the fence as the last step.
2686          *
2687          * For extra levels of paranoia, we make sure each step lands
2688          * before applying the next step.
2689          */
2690         I915_WRITE(fence_reg, 0);
2691         POSTING_READ(fence_reg);
2692
2693         if (obj) {
2694                 u32 size = obj->gtt_space->size;
2695                 uint64_t val;
2696
2697                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2698                                  0xfffff000) << 32;
2699                 val |= obj->gtt_offset & 0xfffff000;
2700                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2701                 if (obj->tiling_mode == I915_TILING_Y)
2702                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2703                 val |= I965_FENCE_REG_VALID;
2704
2705                 I915_WRITE(fence_reg + 4, val >> 32);
2706                 POSTING_READ(fence_reg + 4);
2707
2708                 I915_WRITE(fence_reg + 0, val);
2709                 POSTING_READ(fence_reg);
2710         } else {
2711                 I915_WRITE(fence_reg + 4, 0);
2712                 POSTING_READ(fence_reg + 4);
2713         }
2714 }
2715
2716 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2717                                  struct drm_i915_gem_object *obj)
2718 {
2719         drm_i915_private_t *dev_priv = dev->dev_private;
2720         u32 val;
2721
2722         if (obj) {
2723                 u32 size = obj->gtt_space->size;
2724                 int pitch_val;
2725                 int tile_width;
2726
2727                 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2728                      (size & -size) != size ||
2729                      (obj->gtt_offset & (size - 1)),
2730                      "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2731                      obj->gtt_offset, obj->map_and_fenceable, size);
2732
2733                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2734                         tile_width = 128;
2735                 else
2736                         tile_width = 512;
2737
2738                 /* Note: pitch better be a power of two tile widths */
2739                 pitch_val = obj->stride / tile_width;
2740                 pitch_val = ffs(pitch_val) - 1;
2741
2742                 val = obj->gtt_offset;
2743                 if (obj->tiling_mode == I915_TILING_Y)
2744                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2745                 val |= I915_FENCE_SIZE_BITS(size);
2746                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2747                 val |= I830_FENCE_REG_VALID;
2748         } else
2749                 val = 0;
2750
2751         if (reg < 8)
2752                 reg = FENCE_REG_830_0 + reg * 4;
2753         else
2754                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2755
2756         I915_WRITE(reg, val);
2757         POSTING_READ(reg);
2758 }
2759
2760 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2761                                 struct drm_i915_gem_object *obj)
2762 {
2763         drm_i915_private_t *dev_priv = dev->dev_private;
2764         uint32_t val;
2765
2766         if (obj) {
2767                 u32 size = obj->gtt_space->size;
2768                 uint32_t pitch_val;
2769
2770                 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2771                      (size & -size) != size ||
2772                      (obj->gtt_offset & (size - 1)),
2773                      "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2774                      obj->gtt_offset, size);
2775
2776                 pitch_val = obj->stride / 128;
2777                 pitch_val = ffs(pitch_val) - 1;
2778
2779                 val = obj->gtt_offset;
2780                 if (obj->tiling_mode == I915_TILING_Y)
2781                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2782                 val |= I830_FENCE_SIZE_BITS(size);
2783                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2784                 val |= I830_FENCE_REG_VALID;
2785         } else
2786                 val = 0;
2787
2788         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2789         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2790 }
2791
2792 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2793 {
2794         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2795 }
2796
2797 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2798                                  struct drm_i915_gem_object *obj)
2799 {
2800         struct drm_i915_private *dev_priv = dev->dev_private;
2801
2802         /* Ensure that all CPU reads are completed before installing a fence
2803          * and all writes before removing the fence.
2804          */
2805         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2806                 mb();
2807
2808         WARN(obj && (!obj->stride || !obj->tiling_mode),
2809              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2810              obj->stride, obj->tiling_mode);
2811
2812         switch (INTEL_INFO(dev)->gen) {
2813         case 7:
2814         case 6:
2815         case 5:
2816         case 4: i965_write_fence_reg(dev, reg, obj); break;
2817         case 3: i915_write_fence_reg(dev, reg, obj); break;
2818         case 2: i830_write_fence_reg(dev, reg, obj); break;
2819         default: BUG();
2820         }
2821
2822         /* And similarly be paranoid that no direct access to this region
2823          * is reordered to before the fence is installed.
2824          */
2825         if (i915_gem_object_needs_mb(obj))
2826                 mb();
2827 }
2828
2829 static inline int fence_number(struct drm_i915_private *dev_priv,
2830                                struct drm_i915_fence_reg *fence)
2831 {
2832         return fence - dev_priv->fence_regs;
2833 }
2834
2835 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2836                                          struct drm_i915_fence_reg *fence,
2837                                          bool enable)
2838 {
2839         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2840         int reg = fence_number(dev_priv, fence);
2841
2842         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2843
2844         if (enable) {
2845                 obj->fence_reg = reg;
2846                 fence->obj = obj;
2847                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2848         } else {
2849                 obj->fence_reg = I915_FENCE_REG_NONE;
2850                 fence->obj = NULL;
2851                 list_del_init(&fence->lru_list);
2852         }
2853         obj->fence_dirty = false;
2854 }
2855
2856 static int
2857 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2858 {
2859         if (obj->last_fenced_seqno) {
2860                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2861                 if (ret)
2862                         return ret;
2863
2864                 obj->last_fenced_seqno = 0;
2865         }
2866
2867         obj->fenced_gpu_access = false;
2868         return 0;
2869 }
2870
2871 int
2872 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2873 {
2874         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2875         struct drm_i915_fence_reg *fence;
2876         int ret;
2877
2878         ret = i915_gem_object_wait_fence(obj);
2879         if (ret)
2880                 return ret;
2881
2882         if (obj->fence_reg == I915_FENCE_REG_NONE)
2883                 return 0;
2884
2885         fence = &dev_priv->fence_regs[obj->fence_reg];
2886
2887         i915_gem_object_fence_lost(obj);
2888         i915_gem_object_update_fence(obj, fence, false);
2889
2890         return 0;
2891 }
2892
2893 static struct drm_i915_fence_reg *
2894 i915_find_fence_reg(struct drm_device *dev)
2895 {
2896         struct drm_i915_private *dev_priv = dev->dev_private;
2897         struct drm_i915_fence_reg *reg, *avail;
2898         int i;
2899
2900         /* First try to find a free reg */
2901         avail = NULL;
2902         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2903                 reg = &dev_priv->fence_regs[i];
2904                 if (!reg->obj)
2905                         return reg;
2906
2907                 if (!reg->pin_count)
2908                         avail = reg;
2909         }
2910
2911         if (avail == NULL)
2912                 return NULL;
2913
2914         /* None available, try to steal one or wait for a user to finish */
2915         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2916                 if (reg->pin_count)
2917                         continue;
2918
2919                 return reg;
2920         }
2921
2922         return NULL;
2923 }
2924
2925 /**
2926  * i915_gem_object_get_fence - set up fencing for an object
2927  * @obj: object to map through a fence reg
2928  *
2929  * When mapping objects through the GTT, userspace wants to be able to write
2930  * to them without having to worry about swizzling if the object is tiled.
2931  * This function walks the fence regs looking for a free one for @obj,
2932  * stealing one if it can't find any.
2933  *
2934  * It then sets up the reg based on the object's properties: address, pitch
2935  * and tiling format.
2936  *
2937  * For an untiled surface, this removes any existing fence.
2938  */
2939 int
2940 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2941 {
2942         struct drm_device *dev = obj->base.dev;
2943         struct drm_i915_private *dev_priv = dev->dev_private;
2944         bool enable = obj->tiling_mode != I915_TILING_NONE;
2945         struct drm_i915_fence_reg *reg;
2946         int ret;
2947
2948         /* Have we updated the tiling parameters upon the object and so
2949          * will need to serialise the write to the associated fence register?
2950          */
2951         if (obj->fence_dirty) {
2952                 ret = i915_gem_object_wait_fence(obj);
2953                 if (ret)
2954                         return ret;
2955         }
2956
2957         /* Just update our place in the LRU if our fence is getting reused. */
2958         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2959                 reg = &dev_priv->fence_regs[obj->fence_reg];
2960                 if (!obj->fence_dirty) {
2961                         list_move_tail(&reg->lru_list,
2962                                        &dev_priv->mm.fence_list);
2963                         return 0;
2964                 }
2965         } else if (enable) {
2966                 reg = i915_find_fence_reg(dev);
2967                 if (reg == NULL)
2968                         return -EDEADLK;
2969
2970                 if (reg->obj) {
2971                         struct drm_i915_gem_object *old = reg->obj;
2972
2973                         ret = i915_gem_object_wait_fence(old);
2974                         if (ret)
2975                                 return ret;
2976
2977                         i915_gem_object_fence_lost(old);
2978                 }
2979         } else
2980                 return 0;
2981
2982         i915_gem_object_update_fence(obj, reg, enable);
2983
2984         return 0;
2985 }
2986
2987 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2988                                      struct drm_mm_node *gtt_space,
2989                                      unsigned long cache_level)
2990 {
2991         struct drm_mm_node *other;
2992
2993         /* On non-LLC machines we have to be careful when putting differing
2994          * types of snoopable memory together to avoid the prefetcher
2995          * crossing memory domains and dying.
2996          */
2997         if (HAS_LLC(dev))
2998                 return true;
2999
3000         if (gtt_space == NULL)
3001                 return true;
3002
3003         if (list_empty(&gtt_space->node_list))
3004                 return true;
3005
3006         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3007         if (other->allocated && !other->hole_follows && other->color != cache_level)
3008                 return false;
3009
3010         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3011         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3012                 return false;
3013
3014         return true;
3015 }
3016
3017 static void i915_gem_verify_gtt(struct drm_device *dev)
3018 {
3019 #if WATCH_GTT
3020         struct drm_i915_private *dev_priv = dev->dev_private;
3021         struct drm_i915_gem_object *obj;
3022         int err = 0;
3023
3024         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3025                 if (obj->gtt_space == NULL) {
3026                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3027                         err++;
3028                         continue;
3029                 }
3030
3031                 if (obj->cache_level != obj->gtt_space->color) {
3032                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3033                                obj->gtt_space->start,
3034                                obj->gtt_space->start + obj->gtt_space->size,
3035                                obj->cache_level,
3036                                obj->gtt_space->color);
3037                         err++;
3038                         continue;
3039                 }
3040
3041                 if (!i915_gem_valid_gtt_space(dev,
3042                                               obj->gtt_space,
3043                                               obj->cache_level)) {
3044                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3045                                obj->gtt_space->start,
3046                                obj->gtt_space->start + obj->gtt_space->size,
3047                                obj->cache_level);
3048                         err++;
3049                         continue;
3050                 }
3051         }
3052
3053         WARN_ON(err);
3054 #endif
3055 }
3056
3057 /**
3058  * Finds free space in the GTT aperture and binds the object there.
3059  */
3060 static int
3061 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3062                             unsigned alignment,
3063                             bool map_and_fenceable,
3064                             bool nonblocking)
3065 {
3066         struct drm_device *dev = obj->base.dev;
3067         drm_i915_private_t *dev_priv = dev->dev_private;
3068         struct drm_mm_node *node;
3069         u32 size, fence_size, fence_alignment, unfenced_alignment;
3070         bool mappable, fenceable;
3071         size_t gtt_max = map_and_fenceable ?
3072                 dev_priv->gtt.mappable_end : dev_priv->gtt.total;
3073         int ret;
3074
3075         fence_size = i915_gem_get_gtt_size(dev,
3076                                            obj->base.size,
3077                                            obj->tiling_mode);
3078         fence_alignment = i915_gem_get_gtt_alignment(dev,
3079                                                      obj->base.size,
3080                                                      obj->tiling_mode, true);
3081         unfenced_alignment =
3082                 i915_gem_get_gtt_alignment(dev,
3083                                                     obj->base.size,
3084                                                     obj->tiling_mode, false);
3085
3086         if (alignment == 0)
3087                 alignment = map_and_fenceable ? fence_alignment :
3088                                                 unfenced_alignment;
3089         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3090                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3091                 return -EINVAL;
3092         }
3093
3094         size = map_and_fenceable ? fence_size : obj->base.size;
3095
3096         /* If the object is bigger than the entire aperture, reject it early
3097          * before evicting everything in a vain attempt to find space.
3098          */
3099         if (obj->base.size > gtt_max) {
3100                 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3101                           obj->base.size,
3102                           map_and_fenceable ? "mappable" : "total",
3103                           gtt_max);
3104                 return -E2BIG;
3105         }
3106
3107         ret = i915_gem_object_get_pages(obj);
3108         if (ret)
3109                 return ret;
3110
3111         i915_gem_object_pin_pages(obj);
3112
3113         node = kzalloc(sizeof(*node), GFP_KERNEL);
3114         if (node == NULL) {
3115                 i915_gem_object_unpin_pages(obj);
3116                 return -ENOMEM;
3117         }
3118
3119 search_free:
3120         ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
3121                                                   size, alignment,
3122                                                   obj->cache_level, 0, gtt_max);
3123         if (ret) {
3124                 ret = i915_gem_evict_something(dev, size, alignment,
3125                                                obj->cache_level,
3126                                                map_and_fenceable,
3127                                                nonblocking);
3128                 if (ret == 0)
3129                         goto search_free;
3130
3131                 i915_gem_object_unpin_pages(obj);
3132                 kfree(node);
3133                 return ret;
3134         }
3135         if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
3136                 i915_gem_object_unpin_pages(obj);
3137                 drm_mm_put_block(node);
3138                 return -EINVAL;
3139         }
3140
3141         ret = i915_gem_gtt_prepare_object(obj);
3142         if (ret) {
3143                 i915_gem_object_unpin_pages(obj);
3144                 drm_mm_put_block(node);
3145                 return ret;
3146         }
3147
3148         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3149         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3150
3151         obj->gtt_space = node;
3152         obj->gtt_offset = node->start;
3153
3154         fenceable =
3155                 node->size == fence_size &&
3156                 (node->start & (fence_alignment - 1)) == 0;
3157
3158         mappable =
3159                 obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
3160
3161         obj->map_and_fenceable = mappable && fenceable;
3162
3163         trace_i915_gem_object_bind(obj, map_and_fenceable);
3164         i915_gem_verify_gtt(dev);
3165         return 0;
3166 }
3167
3168 void
3169 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3170 {
3171         /* If we don't have a page list set up, then we're not pinned
3172          * to GPU, and we can ignore the cache flush because it'll happen
3173          * again at bind time.
3174          */
3175         if (obj->pages == NULL)
3176                 return;
3177
3178         /*
3179          * Stolen memory is always coherent with the GPU as it is explicitly
3180          * marked as wc by the system, or the system is cache-coherent.
3181          */
3182         if (obj->stolen)
3183                 return;
3184
3185         /* If the GPU is snooping the contents of the CPU cache,
3186          * we do not need to manually clear the CPU cache lines.  However,
3187          * the caches are only snooped when the render cache is
3188          * flushed/invalidated.  As we always have to emit invalidations
3189          * and flushes when moving into and out of the RENDER domain, correct
3190          * snooping behaviour occurs naturally as the result of our domain
3191          * tracking.
3192          */
3193         if (obj->cache_level != I915_CACHE_NONE)
3194                 return;
3195
3196         trace_i915_gem_object_clflush(obj);
3197
3198         drm_clflush_sg(obj->pages);
3199 }
3200
3201 /** Flushes the GTT write domain for the object if it's dirty. */
3202 static void
3203 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3204 {
3205         uint32_t old_write_domain;
3206
3207         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3208                 return;
3209
3210         /* No actual flushing is required for the GTT write domain.  Writes
3211          * to it immediately go to main memory as far as we know, so there's
3212          * no chipset flush.  It also doesn't land in render cache.
3213          *
3214          * However, we do have to enforce the order so that all writes through
3215          * the GTT land before any writes to the device, such as updates to
3216          * the GATT itself.
3217          */
3218         wmb();
3219
3220         old_write_domain = obj->base.write_domain;
3221         obj->base.write_domain = 0;
3222
3223         trace_i915_gem_object_change_domain(obj,
3224                                             obj->base.read_domains,
3225                                             old_write_domain);
3226 }
3227
3228 /** Flushes the CPU write domain for the object if it's dirty. */
3229 static void
3230 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3231 {
3232         uint32_t old_write_domain;
3233
3234         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3235                 return;
3236
3237         i915_gem_clflush_object(obj);
3238         i915_gem_chipset_flush(obj->base.dev);
3239         old_write_domain = obj->base.write_domain;
3240         obj->base.write_domain = 0;
3241
3242         trace_i915_gem_object_change_domain(obj,
3243                                             obj->base.read_domains,
3244                                             old_write_domain);
3245 }
3246
3247 /**
3248  * Moves a single object to the GTT read, and possibly write domain.
3249  *
3250  * This function returns when the move is complete, including waiting on
3251  * flushes to occur.
3252  */
3253 int
3254 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3255 {
3256         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3257         uint32_t old_write_domain, old_read_domains;
3258         int ret;
3259
3260         /* Not valid to be called on unbound objects. */
3261         if (obj->gtt_space == NULL)
3262                 return -EINVAL;
3263
3264         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3265                 return 0;
3266
3267         ret = i915_gem_object_wait_rendering(obj, !write);
3268         if (ret)
3269                 return ret;
3270
3271         i915_gem_object_flush_cpu_write_domain(obj);
3272
3273         /* Serialise direct access to this object with the barriers for
3274          * coherent writes from the GPU, by effectively invalidating the
3275          * GTT domain upon first access.
3276          */
3277         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3278                 mb();
3279
3280         old_write_domain = obj->base.write_domain;
3281         old_read_domains = obj->base.read_domains;
3282
3283         /* It should now be out of any other write domains, and we can update
3284          * the domain values for our changes.
3285          */
3286         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3287         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3288         if (write) {
3289                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3290                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3291                 obj->dirty = 1;
3292         }
3293
3294         trace_i915_gem_object_change_domain(obj,
3295                                             old_read_domains,
3296                                             old_write_domain);
3297
3298         /* And bump the LRU for this access */
3299         if (i915_gem_object_is_inactive(obj))
3300                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3301
3302         return 0;
3303 }
3304
3305 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3306                                     enum i915_cache_level cache_level)
3307 {
3308         struct drm_device *dev = obj->base.dev;
3309         drm_i915_private_t *dev_priv = dev->dev_private;
3310         int ret;
3311
3312         if (obj->cache_level == cache_level)
3313                 return 0;
3314
3315         if (obj->pin_count) {
3316                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3317                 return -EBUSY;
3318         }
3319
3320         if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3321                 ret = i915_gem_object_unbind(obj);
3322                 if (ret)
3323                         return ret;
3324         }
3325
3326         if (obj->gtt_space) {
3327                 ret = i915_gem_object_finish_gpu(obj);
3328                 if (ret)
3329                         return ret;
3330
3331                 i915_gem_object_finish_gtt(obj);
3332
3333                 /* Before SandyBridge, you could not use tiling or fence
3334                  * registers with snooped memory, so relinquish any fences
3335                  * currently pointing to our region in the aperture.
3336                  */
3337                 if (INTEL_INFO(dev)->gen < 6) {
3338                         ret = i915_gem_object_put_fence(obj);
3339                         if (ret)
3340                                 return ret;
3341                 }
3342
3343                 if (obj->has_global_gtt_mapping)
3344                         i915_gem_gtt_bind_object(obj, cache_level);
3345                 if (obj->has_aliasing_ppgtt_mapping)
3346                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3347                                                obj, cache_level);
3348
3349                 obj->gtt_space->color = cache_level;
3350         }
3351
3352         if (cache_level == I915_CACHE_NONE) {
3353                 u32 old_read_domains, old_write_domain;
3354
3355                 /* If we're coming from LLC cached, then we haven't
3356                  * actually been tracking whether the data is in the
3357                  * CPU cache or not, since we only allow one bit set
3358                  * in obj->write_domain and have been skipping the clflushes.
3359                  * Just set it to the CPU cache for now.
3360                  */
3361                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3362                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3363
3364                 old_read_domains = obj->base.read_domains;
3365                 old_write_domain = obj->base.write_domain;
3366
3367                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3368                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3369
3370                 trace_i915_gem_object_change_domain(obj,
3371                                                     old_read_domains,
3372                                                     old_write_domain);
3373         }
3374
3375         obj->cache_level = cache_level;
3376         i915_gem_verify_gtt(dev);
3377         return 0;
3378 }
3379
3380 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3381                                struct drm_file *file)
3382 {
3383         struct drm_i915_gem_caching *args = data;
3384         struct drm_i915_gem_object *obj;
3385         int ret;
3386
3387         ret = i915_mutex_lock_interruptible(dev);
3388         if (ret)
3389                 return ret;
3390
3391         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3392         if (&obj->base == NULL) {
3393                 ret = -ENOENT;
3394                 goto unlock;
3395         }
3396
3397         args->caching = obj->cache_level != I915_CACHE_NONE;
3398
3399         drm_gem_object_unreference(&obj->base);
3400 unlock:
3401         mutex_unlock(&dev->struct_mutex);
3402         return ret;
3403 }
3404
3405 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3406                                struct drm_file *file)
3407 {
3408         struct drm_i915_gem_caching *args = data;
3409         struct drm_i915_gem_object *obj;
3410         enum i915_cache_level level;
3411         int ret;
3412
3413         switch (args->caching) {
3414         case I915_CACHING_NONE:
3415                 level = I915_CACHE_NONE;
3416                 break;
3417         case I915_CACHING_CACHED:
3418                 level = I915_CACHE_LLC;
3419                 break;
3420         default:
3421                 return -EINVAL;
3422         }
3423
3424         ret = i915_mutex_lock_interruptible(dev);
3425         if (ret)
3426                 return ret;
3427
3428         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3429         if (&obj->base == NULL) {
3430                 ret = -ENOENT;
3431                 goto unlock;
3432         }
3433
3434         ret = i915_gem_object_set_cache_level(obj, level);
3435
3436         drm_gem_object_unreference(&obj->base);
3437 unlock:
3438         mutex_unlock(&dev->struct_mutex);
3439         return ret;
3440 }
3441
3442 /*
3443  * Prepare buffer for display plane (scanout, cursors, etc).
3444  * Can be called from an uninterruptible phase (modesetting) and allows
3445  * any flushes to be pipelined (for pageflips).
3446  */
3447 int
3448 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3449                                      u32 alignment,
3450                                      struct intel_ring_buffer *pipelined)
3451 {
3452         u32 old_read_domains, old_write_domain;
3453         int ret;
3454
3455         if (pipelined != obj->ring) {
3456                 ret = i915_gem_object_sync(obj, pipelined);
3457                 if (ret)
3458                         return ret;
3459         }
3460
3461         /* The display engine is not coherent with the LLC cache on gen6.  As
3462          * a result, we make sure that the pinning that is about to occur is
3463          * done with uncached PTEs. This is lowest common denominator for all
3464          * chipsets.
3465          *
3466          * However for gen6+, we could do better by using the GFDT bit instead
3467          * of uncaching, which would allow us to flush all the LLC-cached data
3468          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3469          */
3470         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3471         if (ret)
3472                 return ret;
3473
3474         /* As the user may map the buffer once pinned in the display plane
3475          * (e.g. libkms for the bootup splash), we have to ensure that we
3476          * always use map_and_fenceable for all scanout buffers.
3477          */
3478         ret = i915_gem_object_pin(obj, alignment, true, false);
3479         if (ret)
3480                 return ret;
3481
3482         i915_gem_object_flush_cpu_write_domain(obj);
3483
3484         old_write_domain = obj->base.write_domain;
3485         old_read_domains = obj->base.read_domains;
3486
3487         /* It should now be out of any other write domains, and we can update
3488          * the domain values for our changes.
3489          */
3490         obj->base.write_domain = 0;
3491         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3492
3493         trace_i915_gem_object_change_domain(obj,
3494                                             old_read_domains,
3495                                             old_write_domain);
3496
3497         return 0;
3498 }
3499
3500 int
3501 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3502 {
3503         int ret;
3504
3505         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3506                 return 0;
3507
3508         ret = i915_gem_object_wait_rendering(obj, false);
3509         if (ret)
3510                 return ret;
3511
3512         /* Ensure that we invalidate the GPU's caches and TLBs. */
3513         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3514         return 0;
3515 }
3516
3517 /**
3518  * Moves a single object to the CPU read, and possibly write domain.
3519  *
3520  * This function returns when the move is complete, including waiting on
3521  * flushes to occur.
3522  */
3523 int
3524 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3525 {
3526         uint32_t old_write_domain, old_read_domains;
3527         int ret;
3528
3529         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3530                 return 0;
3531
3532         ret = i915_gem_object_wait_rendering(obj, !write);
3533         if (ret)
3534                 return ret;
3535
3536         i915_gem_object_flush_gtt_write_domain(obj);
3537
3538         old_write_domain = obj->base.write_domain;
3539         old_read_domains = obj->base.read_domains;
3540
3541         /* Flush the CPU cache if it's still invalid. */
3542         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3543                 i915_gem_clflush_object(obj);
3544
3545                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3546         }
3547
3548         /* It should now be out of any other write domains, and we can update
3549          * the domain values for our changes.
3550          */
3551         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3552
3553         /* If we're writing through the CPU, then the GPU read domains will
3554          * need to be invalidated at next use.
3555          */
3556         if (write) {
3557                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3558                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3559         }
3560
3561         trace_i915_gem_object_change_domain(obj,
3562                                             old_read_domains,
3563                                             old_write_domain);
3564
3565         return 0;
3566 }
3567
3568 /* Throttle our rendering by waiting until the ring has completed our requests
3569  * emitted over 20 msec ago.
3570  *
3571  * Note that if we were to use the current jiffies each time around the loop,
3572  * we wouldn't escape the function with any frames outstanding if the time to
3573  * render a frame was over 20ms.
3574  *
3575  * This should get us reasonable parallelism between CPU and GPU but also
3576  * relatively low latency when blocking on a particular request to finish.
3577  */
3578 static int
3579 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3580 {
3581         struct drm_i915_private *dev_priv = dev->dev_private;
3582         struct drm_i915_file_private *file_priv = file->driver_priv;
3583         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3584         struct drm_i915_gem_request *request;
3585         struct intel_ring_buffer *ring = NULL;
3586         unsigned reset_counter;
3587         u32 seqno = 0;
3588         int ret;
3589
3590         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3591         if (ret)
3592                 return ret;
3593
3594         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3595         if (ret)
3596                 return ret;
3597
3598         spin_lock(&file_priv->mm.lock);
3599         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3600                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3601                         break;
3602
3603                 ring = request->ring;
3604                 seqno = request->seqno;
3605         }
3606         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3607         spin_unlock(&file_priv->mm.lock);
3608
3609         if (seqno == 0)
3610                 return 0;
3611
3612         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3613         if (ret == 0)
3614                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3615
3616         return ret;
3617 }
3618
3619 int
3620 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3621                     uint32_t alignment,
3622                     bool map_and_fenceable,
3623                     bool nonblocking)
3624 {
3625         int ret;
3626
3627         if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3628                 return -EBUSY;
3629
3630         if (obj->gtt_space != NULL) {
3631                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3632                     (map_and_fenceable && !obj->map_and_fenceable)) {
3633                         WARN(obj->pin_count,
3634                              "bo is already pinned with incorrect alignment:"
3635                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3636                              " obj->map_and_fenceable=%d\n",
3637                              obj->gtt_offset, alignment,
3638                              map_and_fenceable,
3639                              obj->map_and_fenceable);
3640                         ret = i915_gem_object_unbind(obj);
3641                         if (ret)
3642                                 return ret;
3643                 }
3644         }
3645
3646         if (obj->gtt_space == NULL) {
3647                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3648
3649                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3650                                                   map_and_fenceable,
3651                                                   nonblocking);
3652                 if (ret)
3653                         return ret;
3654
3655                 if (!dev_priv->mm.aliasing_ppgtt)
3656                         i915_gem_gtt_bind_object(obj, obj->cache_level);
3657         }
3658
3659         if (!obj->has_global_gtt_mapping && map_and_fenceable)
3660                 i915_gem_gtt_bind_object(obj, obj->cache_level);
3661
3662         obj->pin_count++;
3663         obj->pin_mappable |= map_and_fenceable;
3664
3665         return 0;
3666 }
3667
3668 void
3669 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3670 {
3671         BUG_ON(obj->pin_count == 0);
3672         BUG_ON(obj->gtt_space == NULL);
3673
3674         if (--obj->pin_count == 0)
3675                 obj->pin_mappable = false;
3676 }
3677
3678 int
3679 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3680                    struct drm_file *file)
3681 {
3682         struct drm_i915_gem_pin *args = data;
3683         struct drm_i915_gem_object *obj;
3684         int ret;
3685
3686         ret = i915_mutex_lock_interruptible(dev);
3687         if (ret)
3688                 return ret;
3689
3690         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3691         if (&obj->base == NULL) {
3692                 ret = -ENOENT;
3693                 goto unlock;
3694         }
3695
3696         if (obj->madv != I915_MADV_WILLNEED) {
3697                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3698                 ret = -EINVAL;
3699                 goto out;
3700         }
3701
3702         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3703                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3704                           args->handle);
3705                 ret = -EINVAL;
3706                 goto out;
3707         }
3708
3709         if (obj->user_pin_count == 0) {
3710                 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3711                 if (ret)
3712                         goto out;
3713         }
3714
3715         obj->user_pin_count++;
3716         obj->pin_filp = file;
3717
3718         /* XXX - flush the CPU caches for pinned objects
3719          * as the X server doesn't manage domains yet
3720          */
3721         i915_gem_object_flush_cpu_write_domain(obj);
3722         args->offset = obj->gtt_offset;
3723 out:
3724         drm_gem_object_unreference(&obj->base);
3725 unlock:
3726         mutex_unlock(&dev->struct_mutex);
3727         return ret;
3728 }
3729
3730 int
3731 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3732                      struct drm_file *file)
3733 {
3734         struct drm_i915_gem_pin *args = data;
3735         struct drm_i915_gem_object *obj;
3736         int ret;
3737
3738         ret = i915_mutex_lock_interruptible(dev);
3739         if (ret)
3740                 return ret;
3741
3742         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3743         if (&obj->base == NULL) {
3744                 ret = -ENOENT;
3745                 goto unlock;
3746         }
3747
3748         if (obj->pin_filp != file) {
3749                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3750                           args->handle);
3751                 ret = -EINVAL;
3752                 goto out;
3753         }
3754         obj->user_pin_count--;
3755         if (obj->user_pin_count == 0) {
3756                 obj->pin_filp = NULL;
3757                 i915_gem_object_unpin(obj);
3758         }
3759
3760 out:
3761         drm_gem_object_unreference(&obj->base);
3762 unlock:
3763         mutex_unlock(&dev->struct_mutex);
3764         return ret;
3765 }
3766
3767 int
3768 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3769                     struct drm_file *file)
3770 {
3771         struct drm_i915_gem_busy *args = data;
3772         struct drm_i915_gem_object *obj;
3773         int ret;
3774
3775         ret = i915_mutex_lock_interruptible(dev);
3776         if (ret)
3777                 return ret;
3778
3779         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3780         if (&obj->base == NULL) {
3781                 ret = -ENOENT;
3782                 goto unlock;
3783         }
3784
3785         /* Count all active objects as busy, even if they are currently not used
3786          * by the gpu. Users of this interface expect objects to eventually
3787          * become non-busy without any further actions, therefore emit any
3788          * necessary flushes here.
3789          */
3790         ret = i915_gem_object_flush_active(obj);
3791
3792         args->busy = obj->active;
3793         if (obj->ring) {
3794                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3795                 args->busy |= intel_ring_flag(obj->ring) << 16;
3796         }
3797
3798         drm_gem_object_unreference(&obj->base);
3799 unlock:
3800         mutex_unlock(&dev->struct_mutex);
3801         return ret;
3802 }
3803
3804 int
3805 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3806                         struct drm_file *file_priv)
3807 {
3808         return i915_gem_ring_throttle(dev, file_priv);
3809 }
3810
3811 int
3812 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3813                        struct drm_file *file_priv)
3814 {
3815         struct drm_i915_gem_madvise *args = data;
3816         struct drm_i915_gem_object *obj;
3817         int ret;
3818
3819         switch (args->madv) {
3820         case I915_MADV_DONTNEED:
3821         case I915_MADV_WILLNEED:
3822             break;
3823         default:
3824             return -EINVAL;
3825         }
3826
3827         ret = i915_mutex_lock_interruptible(dev);
3828         if (ret)
3829                 return ret;
3830
3831         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3832         if (&obj->base == NULL) {
3833                 ret = -ENOENT;
3834                 goto unlock;
3835         }
3836
3837         if (obj->pin_count) {
3838                 ret = -EINVAL;
3839                 goto out;
3840         }
3841
3842         if (obj->madv != __I915_MADV_PURGED)
3843                 obj->madv = args->madv;
3844
3845         /* if the object is no longer attached, discard its backing storage */
3846         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3847                 i915_gem_object_truncate(obj);
3848
3849         args->retained = obj->madv != __I915_MADV_PURGED;
3850
3851 out:
3852         drm_gem_object_unreference(&obj->base);
3853 unlock:
3854         mutex_unlock(&dev->struct_mutex);
3855         return ret;
3856 }
3857
3858 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3859                           const struct drm_i915_gem_object_ops *ops)
3860 {
3861         INIT_LIST_HEAD(&obj->mm_list);
3862         INIT_LIST_HEAD(&obj->global_list);
3863         INIT_LIST_HEAD(&obj->ring_list);
3864         INIT_LIST_HEAD(&obj->exec_list);
3865
3866         obj->ops = ops;
3867
3868         obj->fence_reg = I915_FENCE_REG_NONE;
3869         obj->madv = I915_MADV_WILLNEED;
3870         /* Avoid an unnecessary call to unbind on the first bind. */
3871         obj->map_and_fenceable = true;
3872
3873         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3874 }
3875
3876 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3877         .get_pages = i915_gem_object_get_pages_gtt,
3878         .put_pages = i915_gem_object_put_pages_gtt,
3879 };
3880
3881 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3882                                                   size_t size)
3883 {
3884         struct drm_i915_gem_object *obj;
3885         struct address_space *mapping;
3886         gfp_t mask;
3887
3888         obj = i915_gem_object_alloc(dev);
3889         if (obj == NULL)
3890                 return NULL;
3891
3892         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3893                 i915_gem_object_free(obj);
3894                 return NULL;
3895         }
3896
3897         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3898         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3899                 /* 965gm cannot relocate objects above 4GiB. */
3900                 mask &= ~__GFP_HIGHMEM;
3901                 mask |= __GFP_DMA32;
3902         }
3903
3904         mapping = file_inode(obj->base.filp)->i_mapping;
3905         mapping_set_gfp_mask(mapping, mask);
3906
3907         i915_gem_object_init(obj, &i915_gem_object_ops);
3908
3909         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3910         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3911
3912         if (HAS_LLC(dev)) {
3913                 /* On some devices, we can have the GPU use the LLC (the CPU
3914                  * cache) for about a 10% performance improvement
3915                  * compared to uncached.  Graphics requests other than
3916                  * display scanout are coherent with the CPU in
3917                  * accessing this cache.  This means in this mode we
3918                  * don't need to clflush on the CPU side, and on the
3919                  * GPU side we only need to flush internal caches to
3920                  * get data visible to the CPU.
3921                  *
3922                  * However, we maintain the display planes as UC, and so
3923                  * need to rebind when first used as such.
3924                  */
3925                 obj->cache_level = I915_CACHE_LLC;
3926         } else
3927                 obj->cache_level = I915_CACHE_NONE;
3928
3929         return obj;
3930 }
3931
3932 int i915_gem_init_object(struct drm_gem_object *obj)
3933 {
3934         BUG();
3935
3936         return 0;
3937 }
3938
3939 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3940 {
3941         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3942         struct drm_device *dev = obj->base.dev;
3943         drm_i915_private_t *dev_priv = dev->dev_private;
3944
3945         trace_i915_gem_object_destroy(obj);
3946
3947         if (obj->phys_obj)
3948                 i915_gem_detach_phys_object(dev, obj);
3949
3950         obj->pin_count = 0;
3951         if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3952                 bool was_interruptible;
3953
3954                 was_interruptible = dev_priv->mm.interruptible;
3955                 dev_priv->mm.interruptible = false;
3956
3957                 WARN_ON(i915_gem_object_unbind(obj));
3958
3959                 dev_priv->mm.interruptible = was_interruptible;
3960         }
3961
3962         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3963          * before progressing. */
3964         if (obj->stolen)
3965                 i915_gem_object_unpin_pages(obj);
3966
3967         if (WARN_ON(obj->pages_pin_count))
3968                 obj->pages_pin_count = 0;
3969         i915_gem_object_put_pages(obj);
3970         i915_gem_object_free_mmap_offset(obj);
3971         i915_gem_object_release_stolen(obj);
3972
3973         BUG_ON(obj->pages);
3974
3975         if (obj->base.import_attach)
3976                 drm_prime_gem_destroy(&obj->base, NULL);
3977
3978         drm_gem_object_release(&obj->base);
3979         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3980
3981         kfree(obj->bit_17);
3982         i915_gem_object_free(obj);
3983 }
3984
3985 int
3986 i915_gem_idle(struct drm_device *dev)
3987 {
3988         drm_i915_private_t *dev_priv = dev->dev_private;
3989         int ret;
3990
3991         mutex_lock(&dev->struct_mutex);
3992
3993         if (dev_priv->mm.suspended) {
3994                 mutex_unlock(&dev->struct_mutex);
3995                 return 0;
3996         }
3997
3998         ret = i915_gpu_idle(dev);
3999         if (ret) {
4000                 mutex_unlock(&dev->struct_mutex);
4001                 return ret;
4002         }
4003         i915_gem_retire_requests(dev);
4004
4005         /* Under UMS, be paranoid and evict. */
4006         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4007                 i915_gem_evict_everything(dev);
4008
4009         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4010          * We need to replace this with a semaphore, or something.
4011          * And not confound mm.suspended!
4012          */
4013         dev_priv->mm.suspended = 1;
4014         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4015
4016         i915_kernel_lost_context(dev);
4017         i915_gem_cleanup_ringbuffer(dev);
4018
4019         mutex_unlock(&dev->struct_mutex);
4020
4021         /* Cancel the retire work handler, which should be idle now. */
4022         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4023
4024         return 0;
4025 }
4026
4027 void i915_gem_l3_remap(struct drm_device *dev)
4028 {
4029         drm_i915_private_t *dev_priv = dev->dev_private;
4030         u32 misccpctl;
4031         int i;
4032
4033         if (!HAS_L3_GPU_CACHE(dev))
4034                 return;
4035
4036         if (!dev_priv->l3_parity.remap_info)
4037                 return;
4038
4039         misccpctl = I915_READ(GEN7_MISCCPCTL);
4040         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4041         POSTING_READ(GEN7_MISCCPCTL);
4042
4043         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4044                 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4045                 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4046                         DRM_DEBUG("0x%x was already programmed to %x\n",
4047                                   GEN7_L3LOG_BASE + i, remap);
4048                 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4049                         DRM_DEBUG_DRIVER("Clearing remapped register\n");
4050                 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4051         }
4052
4053         /* Make sure all the writes land before disabling dop clock gating */
4054         POSTING_READ(GEN7_L3LOG_BASE);
4055
4056         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4057 }
4058
4059 void i915_gem_init_swizzling(struct drm_device *dev)
4060 {
4061         drm_i915_private_t *dev_priv = dev->dev_private;
4062
4063         if (INTEL_INFO(dev)->gen < 5 ||
4064             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4065                 return;
4066
4067         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4068                                  DISP_TILE_SURFACE_SWIZZLING);
4069
4070         if (IS_GEN5(dev))
4071                 return;
4072
4073         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4074         if (IS_GEN6(dev))
4075                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4076         else if (IS_GEN7(dev))
4077                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4078         else
4079                 BUG();
4080 }
4081
4082 static bool
4083 intel_enable_blt(struct drm_device *dev)
4084 {
4085         if (!HAS_BLT(dev))
4086                 return false;
4087
4088         /* The blitter was dysfunctional on early prototypes */
4089         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4090                 DRM_INFO("BLT not supported on this pre-production hardware;"
4091                          " graphics performance will be degraded.\n");
4092                 return false;
4093         }
4094
4095         return true;
4096 }
4097
4098 static int i915_gem_init_rings(struct drm_device *dev)
4099 {
4100         struct drm_i915_private *dev_priv = dev->dev_private;
4101         int ret;
4102
4103         ret = intel_init_render_ring_buffer(dev);
4104         if (ret)
4105                 return ret;
4106
4107         if (HAS_BSD(dev)) {
4108                 ret = intel_init_bsd_ring_buffer(dev);
4109                 if (ret)
4110                         goto cleanup_render_ring;
4111         }
4112
4113         if (intel_enable_blt(dev)) {
4114                 ret = intel_init_blt_ring_buffer(dev);
4115                 if (ret)
4116                         goto cleanup_bsd_ring;
4117         }
4118
4119         if (HAS_VEBOX(dev)) {
4120                 ret = intel_init_vebox_ring_buffer(dev);
4121                 if (ret)
4122                         goto cleanup_blt_ring;
4123         }
4124
4125
4126         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4127         if (ret)
4128                 goto cleanup_vebox_ring;
4129
4130         return 0;
4131
4132 cleanup_vebox_ring:
4133         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4134 cleanup_blt_ring:
4135         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4136 cleanup_bsd_ring:
4137         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4138 cleanup_render_ring:
4139         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4140
4141         return ret;
4142 }
4143
4144 int
4145 i915_gem_init_hw(struct drm_device *dev)
4146 {
4147         drm_i915_private_t *dev_priv = dev->dev_private;
4148         int ret;
4149
4150         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4151                 return -EIO;
4152
4153         if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4154                 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4155
4156         if (HAS_PCH_NOP(dev)) {
4157                 u32 temp = I915_READ(GEN7_MSG_CTL);
4158                 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4159                 I915_WRITE(GEN7_MSG_CTL, temp);
4160         }
4161
4162         i915_gem_l3_remap(dev);
4163
4164         i915_gem_init_swizzling(dev);
4165
4166         ret = i915_gem_init_rings(dev);
4167         if (ret)
4168                 return ret;
4169
4170         /*
4171          * XXX: There was some w/a described somewhere suggesting loading
4172          * contexts before PPGTT.
4173          */
4174         i915_gem_context_init(dev);
4175         if (dev_priv->mm.aliasing_ppgtt) {
4176                 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4177                 if (ret) {
4178                         i915_gem_cleanup_aliasing_ppgtt(dev);
4179                         DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4180                 }
4181         }
4182
4183         return 0;
4184 }
4185
4186 int i915_gem_init(struct drm_device *dev)
4187 {
4188         struct drm_i915_private *dev_priv = dev->dev_private;
4189         int ret;
4190
4191         mutex_lock(&dev->struct_mutex);
4192
4193         if (IS_VALLEYVIEW(dev)) {
4194                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4195                 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4196                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4197                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4198         }
4199
4200         i915_gem_init_global_gtt(dev);
4201
4202         ret = i915_gem_init_hw(dev);
4203         mutex_unlock(&dev->struct_mutex);
4204         if (ret) {
4205                 i915_gem_cleanup_aliasing_ppgtt(dev);
4206                 return ret;
4207         }
4208
4209         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4210         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4211                 dev_priv->dri1.allow_batchbuffer = 1;
4212         return 0;
4213 }
4214
4215 void
4216 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4217 {
4218         drm_i915_private_t *dev_priv = dev->dev_private;
4219         struct intel_ring_buffer *ring;
4220         int i;
4221
4222         for_each_ring(ring, dev_priv, i)
4223                 intel_cleanup_ring_buffer(ring);
4224 }
4225
4226 int
4227 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4228                        struct drm_file *file_priv)
4229 {
4230         drm_i915_private_t *dev_priv = dev->dev_private;
4231         int ret;
4232
4233         if (drm_core_check_feature(dev, DRIVER_MODESET))
4234                 return 0;
4235
4236         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4237                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4238                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4239         }
4240
4241         mutex_lock(&dev->struct_mutex);
4242         dev_priv->mm.suspended = 0;
4243
4244         ret = i915_gem_init_hw(dev);
4245         if (ret != 0) {
4246                 mutex_unlock(&dev->struct_mutex);
4247                 return ret;
4248         }
4249
4250         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4251         mutex_unlock(&dev->struct_mutex);
4252
4253         ret = drm_irq_install(dev);
4254         if (ret)
4255                 goto cleanup_ringbuffer;
4256
4257         return 0;
4258
4259 cleanup_ringbuffer:
4260         mutex_lock(&dev->struct_mutex);
4261         i915_gem_cleanup_ringbuffer(dev);
4262         dev_priv->mm.suspended = 1;
4263         mutex_unlock(&dev->struct_mutex);
4264
4265         return ret;
4266 }
4267
4268 int
4269 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4270                        struct drm_file *file_priv)
4271 {
4272         if (drm_core_check_feature(dev, DRIVER_MODESET))
4273                 return 0;
4274
4275         drm_irq_uninstall(dev);
4276         return i915_gem_idle(dev);
4277 }
4278
4279 void
4280 i915_gem_lastclose(struct drm_device *dev)
4281 {
4282         int ret;
4283
4284         if (drm_core_check_feature(dev, DRIVER_MODESET))
4285                 return;
4286
4287         ret = i915_gem_idle(dev);
4288         if (ret)
4289                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4290 }
4291
4292 static void
4293 init_ring_lists(struct intel_ring_buffer *ring)
4294 {
4295         INIT_LIST_HEAD(&ring->active_list);
4296         INIT_LIST_HEAD(&ring->request_list);
4297 }
4298
4299 void
4300 i915_gem_load(struct drm_device *dev)
4301 {
4302         drm_i915_private_t *dev_priv = dev->dev_private;
4303         int i;
4304
4305         dev_priv->slab =
4306                 kmem_cache_create("i915_gem_object",
4307                                   sizeof(struct drm_i915_gem_object), 0,
4308                                   SLAB_HWCACHE_ALIGN,
4309                                   NULL);
4310
4311         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4312         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4313         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4314         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4315         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4316         for (i = 0; i < I915_NUM_RINGS; i++)
4317                 init_ring_lists(&dev_priv->ring[i]);
4318         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4319                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4320         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4321                           i915_gem_retire_work_handler);
4322         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4323
4324         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4325         if (IS_GEN3(dev)) {
4326                 I915_WRITE(MI_ARB_STATE,
4327                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4328         }
4329
4330         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4331
4332         /* Old X drivers will take 0-2 for front, back, depth buffers */
4333         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4334                 dev_priv->fence_reg_start = 3;
4335
4336         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4337                 dev_priv->num_fence_regs = 32;
4338         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4339                 dev_priv->num_fence_regs = 16;
4340         else
4341                 dev_priv->num_fence_regs = 8;
4342
4343         /* Initialize fence registers to zero */
4344         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4345         i915_gem_restore_fences(dev);
4346
4347         i915_gem_detect_bit_6_swizzle(dev);
4348         init_waitqueue_head(&dev_priv->pending_flip_queue);
4349
4350         dev_priv->mm.interruptible = true;
4351
4352         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4353         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4354         register_shrinker(&dev_priv->mm.inactive_shrinker);
4355 }
4356
4357 /*
4358  * Create a physically contiguous memory object for this object
4359  * e.g. for cursor + overlay regs
4360  */
4361 static int i915_gem_init_phys_object(struct drm_device *dev,
4362                                      int id, int size, int align)
4363 {
4364         drm_i915_private_t *dev_priv = dev->dev_private;
4365         struct drm_i915_gem_phys_object *phys_obj;
4366         int ret;
4367
4368         if (dev_priv->mm.phys_objs[id - 1] || !size)
4369                 return 0;
4370
4371         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4372         if (!phys_obj)
4373                 return -ENOMEM;
4374
4375         phys_obj->id = id;
4376
4377         phys_obj->handle = drm_pci_alloc(dev, size, align);
4378         if (!phys_obj->handle) {
4379                 ret = -ENOMEM;
4380                 goto kfree_obj;
4381         }
4382 #ifdef CONFIG_X86
4383         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4384 #endif
4385
4386         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4387
4388         return 0;
4389 kfree_obj:
4390         kfree(phys_obj);
4391         return ret;
4392 }
4393
4394 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4395 {
4396         drm_i915_private_t *dev_priv = dev->dev_private;
4397         struct drm_i915_gem_phys_object *phys_obj;
4398
4399         if (!dev_priv->mm.phys_objs[id - 1])
4400                 return;
4401
4402         phys_obj = dev_priv->mm.phys_objs[id - 1];
4403         if (phys_obj->cur_obj) {
4404                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4405         }
4406
4407 #ifdef CONFIG_X86
4408         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4409 #endif
4410         drm_pci_free(dev, phys_obj->handle);
4411         kfree(phys_obj);
4412         dev_priv->mm.phys_objs[id - 1] = NULL;
4413 }
4414
4415 void i915_gem_free_all_phys_object(struct drm_device *dev)
4416 {
4417         int i;
4418
4419         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4420                 i915_gem_free_phys_object(dev, i);
4421 }
4422
4423 void i915_gem_detach_phys_object(struct drm_device *dev,
4424                                  struct drm_i915_gem_object *obj)
4425 {
4426         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4427         char *vaddr;
4428         int i;
4429         int page_count;
4430
4431         if (!obj->phys_obj)
4432                 return;
4433         vaddr = obj->phys_obj->handle->vaddr;
4434
4435         page_count = obj->base.size / PAGE_SIZE;
4436         for (i = 0; i < page_count; i++) {
4437                 struct page *page = shmem_read_mapping_page(mapping, i);
4438                 if (!IS_ERR(page)) {
4439                         char *dst = kmap_atomic(page);
4440                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4441                         kunmap_atomic(dst);
4442
4443                         drm_clflush_pages(&page, 1);
4444
4445                         set_page_dirty(page);
4446                         mark_page_accessed(page);
4447                         page_cache_release(page);
4448                 }
4449         }
4450         i915_gem_chipset_flush(dev);
4451
4452         obj->phys_obj->cur_obj = NULL;
4453         obj->phys_obj = NULL;
4454 }
4455
4456 int
4457 i915_gem_attach_phys_object(struct drm_device *dev,
4458                             struct drm_i915_gem_object *obj,
4459                             int id,
4460                             int align)
4461 {
4462         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4463         drm_i915_private_t *dev_priv = dev->dev_private;
4464         int ret = 0;
4465         int page_count;
4466         int i;
4467
4468         if (id > I915_MAX_PHYS_OBJECT)
4469                 return -EINVAL;
4470
4471         if (obj->phys_obj) {
4472                 if (obj->phys_obj->id == id)
4473                         return 0;
4474                 i915_gem_detach_phys_object(dev, obj);
4475         }
4476
4477         /* create a new object */
4478         if (!dev_priv->mm.phys_objs[id - 1]) {
4479                 ret = i915_gem_init_phys_object(dev, id,
4480                                                 obj->base.size, align);
4481                 if (ret) {
4482                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4483                                   id, obj->base.size);
4484                         return ret;
4485                 }
4486         }
4487
4488         /* bind to the object */
4489         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4490         obj->phys_obj->cur_obj = obj;
4491
4492         page_count = obj->base.size / PAGE_SIZE;
4493
4494         for (i = 0; i < page_count; i++) {
4495                 struct page *page;
4496                 char *dst, *src;
4497
4498                 page = shmem_read_mapping_page(mapping, i);
4499                 if (IS_ERR(page))
4500                         return PTR_ERR(page);
4501
4502                 src = kmap_atomic(page);
4503                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4504                 memcpy(dst, src, PAGE_SIZE);
4505                 kunmap_atomic(src);
4506
4507                 mark_page_accessed(page);
4508                 page_cache_release(page);
4509         }
4510
4511         return 0;
4512 }
4513
4514 static int
4515 i915_gem_phys_pwrite(struct drm_device *dev,
4516                      struct drm_i915_gem_object *obj,
4517                      struct drm_i915_gem_pwrite *args,
4518                      struct drm_file *file_priv)
4519 {
4520         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4521         char __user *user_data = to_user_ptr(args->data_ptr);
4522
4523         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4524                 unsigned long unwritten;
4525
4526                 /* The physical object once assigned is fixed for the lifetime
4527                  * of the obj, so we can safely drop the lock and continue
4528                  * to access vaddr.
4529                  */
4530                 mutex_unlock(&dev->struct_mutex);
4531                 unwritten = copy_from_user(vaddr, user_data, args->size);
4532                 mutex_lock(&dev->struct_mutex);
4533                 if (unwritten)
4534                         return -EFAULT;
4535         }
4536
4537         i915_gem_chipset_flush(dev);
4538         return 0;
4539 }
4540
4541 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4542 {
4543         struct drm_i915_file_private *file_priv = file->driver_priv;
4544
4545         /* Clean up our request list when the client is going away, so that
4546          * later retire_requests won't dereference our soon-to-be-gone
4547          * file_priv.
4548          */
4549         spin_lock(&file_priv->mm.lock);
4550         while (!list_empty(&file_priv->mm.request_list)) {
4551                 struct drm_i915_gem_request *request;
4552
4553                 request = list_first_entry(&file_priv->mm.request_list,
4554                                            struct drm_i915_gem_request,
4555                                            client_list);
4556                 list_del(&request->client_list);
4557                 request->file_priv = NULL;
4558         }
4559         spin_unlock(&file_priv->mm.lock);
4560 }
4561
4562 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4563 {
4564         if (!mutex_is_locked(mutex))
4565                 return false;
4566
4567 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4568         return mutex->owner == task;
4569 #else
4570         /* Since UP may be pre-empted, we cannot assume that we own the lock */
4571         return false;
4572 #endif
4573 }
4574
4575 static int
4576 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4577 {
4578         struct drm_i915_private *dev_priv =
4579                 container_of(shrinker,
4580                              struct drm_i915_private,
4581                              mm.inactive_shrinker);
4582         struct drm_device *dev = dev_priv->dev;
4583         struct drm_i915_gem_object *obj;
4584         int nr_to_scan = sc->nr_to_scan;
4585         bool unlock = true;
4586         int cnt;
4587
4588         if (!mutex_trylock(&dev->struct_mutex)) {
4589                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4590                         return 0;
4591
4592                 if (dev_priv->mm.shrinker_no_lock_stealing)
4593                         return 0;
4594
4595                 unlock = false;
4596         }
4597
4598         if (nr_to_scan) {
4599                 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4600                 if (nr_to_scan > 0)
4601                         nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4602                                                         false);
4603                 if (nr_to_scan > 0)
4604                         i915_gem_shrink_all(dev_priv);
4605         }
4606
4607         cnt = 0;
4608         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4609                 if (obj->pages_pin_count == 0)
4610                         cnt += obj->base.size >> PAGE_SHIFT;
4611         list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list)
4612                 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4613                         cnt += obj->base.size >> PAGE_SHIFT;
4614
4615         if (unlock)
4616                 mutex_unlock(&dev->struct_mutex);
4617         return cnt;
4618 }