drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv_dac = {
 313         .dot = { .min = 25000, .max = 270000 },
 314         .vco = { .min = 4000000, .max = 6000000 },
 315         .n = { .min = 1, .max = 7 },
 316         .m = { .min = 22, .max = 450 }, /* guess */
 317         .m1 = { .min = 2, .max = 3 },
 318         .m2 = { .min = 11, .max = 156 },
 319         .p = { .min = 10, .max = 30 },
 320         .p1 = { .min = 1, .max = 3 },
 321         .p2 = { .dot_limit = 270000,
 322                 .p2_slow = 2, .p2_fast = 20 },
 323 };
 324
 325 static const intel_limit_t intel_limits_vlv_hdmi = {
 326         .dot = { .min = 25000, .max = 270000 },
 327         .vco = { .min = 4000000, .max = 6000000 },
 328         .n = { .min = 1, .max = 7 },
 329         .m = { .min = 60, .max = 300 }, /* guess */
 330         .m1 = { .min = 2, .max = 3 },
 331         .m2 = { .min = 11, .max = 156 },
 332         .p = { .min = 10, .max = 30 },
 333         .p1 = { .min = 2, .max = 3 },
 334         .p2 = { .dot_limit = 270000,
 335                 .p2_slow = 2, .p2_fast = 20 },
 336 };
 337
 338 /**
 339  * Returns whether any output on the specified pipe is of the specified type
 340  */
 341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 342 {
 343         struct drm_device *dev = crtc->dev;
 344         struct intel_encoder *encoder;
 345
 346         for_each_encoder_on_crtc(dev, crtc, encoder)
 347                 if (encoder->type == type)
 348                         return true;
 349
 350         return false;
 351 }
 352
 353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 354                                                 int refclk)
 355 {
 356         struct drm_device *dev = crtc->dev;
 357         const intel_limit_t *limit;
 358
 359         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 360                 if (intel_is_dual_link_lvds(dev)) {
 361                         if (refclk == 100000)
 362                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 363                         else
 364                                 limit = &intel_limits_ironlake_dual_lvds;
 365                 } else {
 366                         if (refclk == 100000)
 367                                 limit = &intel_limits_ironlake_single_lvds_100m;
 368                         else
 369                                 limit = &intel_limits_ironlake_single_lvds;
 370                 }
 371         } else
 372                 limit = &intel_limits_ironlake_dac;
 373
 374         return limit;
 375 }
 376
 377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 378 {
 379         struct drm_device *dev = crtc->dev;
 380         const intel_limit_t *limit;
 381
 382         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 383                 if (intel_is_dual_link_lvds(dev))
 384                         limit = &intel_limits_g4x_dual_channel_lvds;
 385                 else
 386                         limit = &intel_limits_g4x_single_channel_lvds;
 387         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 388                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 389                 limit = &intel_limits_g4x_hdmi;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 391                 limit = &intel_limits_g4x_sdvo;
 392         } else /* The option is for other outputs */
 393                 limit = &intel_limits_i9xx_sdvo;
 394
 395         return limit;
 396 }
 397
 398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 399 {
 400         struct drm_device *dev = crtc->dev;
 401         const intel_limit_t *limit;
 402
 403         if (HAS_PCH_SPLIT(dev))
 404                 limit = intel_ironlake_limit(crtc, refclk);
 405         else if (IS_G4X(dev)) {
 406                 limit = intel_g4x_limit(crtc);
 407         } else if (IS_PINEVIEW(dev)) {
 408                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 409                         limit = &intel_limits_pineview_lvds;
 410                 else
 411                         limit = &intel_limits_pineview_sdvo;
 412         } else if (IS_VALLEYVIEW(dev)) {
 413                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 414                         limit = &intel_limits_vlv_dac;
 415                 else
 416                         limit = &intel_limits_vlv_hdmi;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         clock->vco = refclk * clock->m / clock->n;
 439         clock->dot = clock->vco / clock->p;
 440 }
 441
 442 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 443 {
 444         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 445 }
 446
 447 static void i9xx_clock(int refclk, intel_clock_t *clock)
 448 {
 449         clock->m = i9xx_dpll_compute_m(clock);
 450         clock->p = clock->p1 * clock->p2;
 451         clock->vco = refclk * clock->m / (clock->n + 2);
 452         clock->dot = clock->vco / clock->p;
 453 }
 454
 455 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 456 /**
 457  * Returns whether the given set of divisors are valid for a given refclk with
 458  * the given connectors.
 459  */
 460
 461 static bool intel_PLL_is_valid(struct drm_device *dev,
 462                                const intel_limit_t *limit,
 463                                const intel_clock_t *clock)
 464 {
 465         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 466                 INTELPllInvalid("p1 out of range\n");
 467         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 468                 INTELPllInvalid("p out of range\n");
 469         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 470                 INTELPllInvalid("m2 out of range\n");
 471         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 472                 INTELPllInvalid("m1 out of range\n");
 473         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 474                 INTELPllInvalid("m1 <= m2\n");
 475         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 476                 INTELPllInvalid("m out of range\n");
 477         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 478                 INTELPllInvalid("n out of range\n");
 479         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 480                 INTELPllInvalid("vco out of range\n");
 481         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 482          * connector, etc., rather than just a single range.
 483          */
 484         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 485                 INTELPllInvalid("dot out of range\n");
 486
 487         return true;
 488 }
 489
 490 static bool
 491 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 492                     int target, int refclk, intel_clock_t *match_clock,
 493                     intel_clock_t *best_clock)
 494 {
 495         struct drm_device *dev = crtc->dev;
 496         intel_clock_t clock;
 497         int err = target;
 498
 499         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 500                 /*
 501                  * For LVDS just rely on its current settings for dual-channel.
 502                  * We haven't figured out how to reliably set up different
 503                  * single/dual channel state, if we even can.
 504                  */
 505                 if (intel_is_dual_link_lvds(dev))
 506                         clock.p2 = limit->p2.p2_fast;
 507                 else
 508                         clock.p2 = limit->p2.p2_slow;
 509         } else {
 510                 if (target < limit->p2.dot_limit)
 511                         clock.p2 = limit->p2.p2_slow;
 512                 else
 513                         clock.p2 = limit->p2.p2_fast;
 514         }
 515
 516         memset(best_clock, 0, sizeof(*best_clock));
 517
 518         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 519              clock.m1++) {
 520                 for (clock.m2 = limit->m2.min;
 521                      clock.m2 <= limit->m2.max; clock.m2++) {
 522                         if (clock.m2 >= clock.m1)
 523                                 break;
 524                         for (clock.n = limit->n.min;
 525                              clock.n <= limit->n.max; clock.n++) {
 526                                 for (clock.p1 = limit->p1.min;
 527                                         clock.p1 <= limit->p1.max; clock.p1++) {
 528                                         int this_err;
 529
 530                                         i9xx_clock(refclk, &clock);
 531                                         if (!intel_PLL_is_valid(dev, limit,
 532                                                                 &clock))
 533                                                 continue;
 534                                         if (match_clock &&
 535                                             clock.p != match_clock->p)
 536                                                 continue;
 537
 538                                         this_err = abs(clock.dot - target);
 539                                         if (this_err < err) {
 540                                                 *best_clock = clock;
 541                                                 err = this_err;
 542                                         }
 543                                 }
 544                         }
 545                 }
 546         }
 547
 548         return (err != target);
 549 }
 550
 551 static bool
 552 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 553                    int target, int refclk, intel_clock_t *match_clock,
 554                    intel_clock_t *best_clock)
 555 {
 556         struct drm_device *dev = crtc->dev;
 557         intel_clock_t clock;
 558         int err = target;
 559
 560         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 561                 /*
 562                  * For LVDS just rely on its current settings for dual-channel.
 563                  * We haven't figured out how to reliably set up different
 564                  * single/dual channel state, if we even can.
 565                  */
 566                 if (intel_is_dual_link_lvds(dev))
 567                         clock.p2 = limit->p2.p2_fast;
 568                 else
 569                         clock.p2 = limit->p2.p2_slow;
 570         } else {
 571                 if (target < limit->p2.dot_limit)
 572                         clock.p2 = limit->p2.p2_slow;
 573                 else
 574                         clock.p2 = limit->p2.p2_fast;
 575         }
 576
 577         memset(best_clock, 0, sizeof(*best_clock));
 578
 579         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 580              clock.m1++) {
 581                 for (clock.m2 = limit->m2.min;
 582                      clock.m2 <= limit->m2.max; clock.m2++) {
 583                         for (clock.n = limit->n.min;
 584                              clock.n <= limit->n.max; clock.n++) {
 585                                 for (clock.p1 = limit->p1.min;
 586                                         clock.p1 <= limit->p1.max; clock.p1++) {
 587                                         int this_err;
 588
 589                                         pineview_clock(refclk, &clock);
 590                                         if (!intel_PLL_is_valid(dev, limit,
 591                                                                 &clock))
 592                                                 continue;
 593                                         if (match_clock &&
 594                                             clock.p != match_clock->p)
 595                                                 continue;
 596
 597                                         this_err = abs(clock.dot - target);
 598                                         if (this_err < err) {
 599                                                 *best_clock = clock;
 600                                                 err = this_err;
 601                                         }
 602                                 }
 603                         }
 604                 }
 605         }
 606
 607         return (err != target);
 608 }
 609
 610 static bool
 611 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 612                    int target, int refclk, intel_clock_t *match_clock,
 613                    intel_clock_t *best_clock)
 614 {
 615         struct drm_device *dev = crtc->dev;
 616         intel_clock_t clock;
 617         int max_n;
 618         bool found;
 619         /* approximately equals target * 0.00585 */
 620         int err_most = (target >> 8) + (target >> 9);
 621         found = false;
 622
 623         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 624                 if (intel_is_dual_link_lvds(dev))
 625                         clock.p2 = limit->p2.p2_fast;
 626                 else
 627                         clock.p2 = limit->p2.p2_slow;
 628         } else {
 629                 if (target < limit->p2.dot_limit)
 630                         clock.p2 = limit->p2.p2_slow;
 631                 else
 632                         clock.p2 = limit->p2.p2_fast;
 633         }
 634
 635         memset(best_clock, 0, sizeof(*best_clock));
 636         max_n = limit->n.max;
 637         /* based on hardware requirement, prefer smaller n to precision */
 638         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 639                 /* based on hardware requirement, prefere larger m1,m2 */
 640                 for (clock.m1 = limit->m1.max;
 641                      clock.m1 >= limit->m1.min; clock.m1--) {
 642                         for (clock.m2 = limit->m2.max;
 643                              clock.m2 >= limit->m2.min; clock.m2--) {
 644                                 for (clock.p1 = limit->p1.max;
 645                                      clock.p1 >= limit->p1.min; clock.p1--) {
 646                                         int this_err;
 647
 648                                         i9xx_clock(refclk, &clock);
 649                                         if (!intel_PLL_is_valid(dev, limit,
 650                                                                 &clock))
 651                                                 continue;
 652
 653                                         this_err = abs(clock.dot - target);
 654                                         if (this_err < err_most) {
 655                                                 *best_clock = clock;
 656                                                 err_most = this_err;
 657                                                 max_n = clock.n;
 658                                                 found = true;
 659                                         }
 660                                 }
 661                         }
 662                 }
 663         }
 664         return found;
 665 }
 666
 667 static bool
 668 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 669                    int target, int refclk, intel_clock_t *match_clock,
 670                    intel_clock_t *best_clock)
 671 {
 672         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 673         u32 m, n, fastclk;
 674         u32 updrate, minupdate, p;
 675         unsigned long bestppm, ppm, absppm;
 676         int dotclk, flag;
 677
 678         flag = 0;
 679         dotclk = target * 1000;
 680         bestppm = 1000000;
 681         ppm = absppm = 0;
 682         fastclk = dotclk / (2*100);
 683         updrate = 0;
 684         minupdate = 19200;
 685         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 686         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 687
 688         /* based on hardware requirement, prefer smaller n to precision */
 689         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 690                 updrate = refclk / n;
 691                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 692                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 693                                 if (p2 > 10)
 694                                         p2 = p2 - 1;
 695                                 p = p1 * p2;
 696                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 697                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 698                                         m2 = DIV_ROUND_CLOSEST(fastclk * p * n, refclk * m1);
 699                                         m = m1 * m2;
 700                                         vco = updrate * m;
 701
 702                                         if (vco < limit->vco.min || vco >= limit->vco.max)
 703                                                 continue;
 704
 705                                         ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 706                                         absppm = (ppm > 0) ? ppm : (-ppm);
 707                                         if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 708                                                 bestppm = 0;
 709                                                 flag = 1;
 710                                         }
 711                                         if (absppm < bestppm - 10) {
 712                                                 bestppm = absppm;
 713                                                 flag = 1;
 714                                         }
 715                                         if (flag) {
 716                                                 bestn = n;
 717                                                 bestm1 = m1;
 718                                                 bestm2 = m2;
 719                                                 bestp1 = p1;
 720                                                 bestp2 = p2;
 721                                                 flag = 0;
 722                                         }
 723                                 }
 724                         }
 725                 }
 726         }
 727         best_clock->n = bestn;
 728         best_clock->m1 = bestm1;
 729         best_clock->m2 = bestm2;
 730         best_clock->p1 = bestp1;
 731         best_clock->p2 = bestp2;
 732
 733         return true;
 734 }
 735
 736 bool intel_crtc_active(struct drm_crtc *crtc)
 737 {
 738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 739
 740         /* Be paranoid as we can arrive here with only partial
 741          * state retrieved from the hardware during setup.
 742          *
 743          * We can ditch the adjusted_mode.crtc_clock check as soon
 744          * as Haswell has gained clock readout/fastboot support.
 745          *
 746          * We can ditch the crtc->fb check as soon as we can
 747          * properly reconstruct framebuffers.
 748          */
 749         return intel_crtc->active && crtc->fb &&
 750                 intel_crtc->config.adjusted_mode.crtc_clock;
 751 }
 752
 753 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 754                                              enum pipe pipe)
 755 {
 756         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 758
 759         return intel_crtc->config.cpu_transcoder;
 760 }
 761
 762 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 763 {
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765         u32 frame, frame_reg = PIPEFRAME(pipe);
 766
 767         frame = I915_READ(frame_reg);
 768
 769         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 770                 DRM_DEBUG_KMS("vblank wait timed out\n");
 771 }
 772
 773 /**
 774  * intel_wait_for_vblank - wait for vblank on a given pipe
 775  * @dev: drm device
 776  * @pipe: pipe to wait for
 777  *
 778  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 779  * mode setting code.
 780  */
 781 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 782 {
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         int pipestat_reg = PIPESTAT(pipe);
 785
 786         if (INTEL_INFO(dev)->gen >= 5) {
 787                 ironlake_wait_for_vblank(dev, pipe);
 788                 return;
 789         }
 790
 791         /* Clear existing vblank status. Note this will clear any other
 792          * sticky status fields as well.
 793          *
 794          * This races with i915_driver_irq_handler() with the result
 795          * that either function could miss a vblank event.  Here it is not
 796          * fatal, as we will either wait upon the next vblank interrupt or
 797          * timeout.  Generally speaking intel_wait_for_vblank() is only
 798          * called during modeset at which time the GPU should be idle and
 799          * should *not* be performing page flips and thus not waiting on
 800          * vblanks...
 801          * Currently, the result of us stealing a vblank from the irq
 802          * handler is that a single frame will be skipped during swapbuffers.
 803          */
 804         I915_WRITE(pipestat_reg,
 805                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 806
 807         /* Wait for vblank interrupt bit to set */
 808         if (wait_for(I915_READ(pipestat_reg) &
 809                      PIPE_VBLANK_INTERRUPT_STATUS,
 810                      50))
 811                 DRM_DEBUG_KMS("vblank wait timed out\n");
 812 }
 813
 814 /*
 815  * intel_wait_for_pipe_off - wait for pipe to turn off
 816  * @dev: drm device
 817  * @pipe: pipe to wait for
 818  *
 819  * After disabling a pipe, we can't wait for vblank in the usual way,
 820  * spinning on the vblank interrupt status bit, since we won't actually
 821  * see an interrupt when the pipe is disabled.
 822  *
 823  * On Gen4 and above:
 824  *   wait for the pipe register state bit to turn off
 825  *
 826  * Otherwise:
 827  *   wait for the display line value to settle (it usually
 828  *   ends up stopping at the start of the next frame).
 829  *
 830  */
 831 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 832 {
 833         struct drm_i915_private *dev_priv = dev->dev_private;
 834         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 835                                                                       pipe);
 836
 837         if (INTEL_INFO(dev)->gen >= 4) {
 838                 int reg = PIPECONF(cpu_transcoder);
 839
 840                 /* Wait for the Pipe State to go off */
 841                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 842                              100))
 843                         WARN(1, "pipe_off wait timed out\n");
 844         } else {
 845                 u32 last_line, line_mask;
 846                 int reg = PIPEDSL(pipe);
 847                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 848
 849                 if (IS_GEN2(dev))
 850                         line_mask = DSL_LINEMASK_GEN2;
 851                 else
 852                         line_mask = DSL_LINEMASK_GEN3;
 853
 854                 /* Wait for the display line to settle */
 855                 do {
 856                         last_line = I915_READ(reg) & line_mask;
 857                         mdelay(5);
 858                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 859                          time_after(timeout, jiffies));
 860                 if (time_after(jiffies, timeout))
 861                         WARN(1, "pipe_off wait timed out\n");
 862         }
 863 }
 864
 865 /*
 866  * ibx_digital_port_connected - is the specified port connected?
 867  * @dev_priv: i915 private structure
 868  * @port: the port to test
 869  *
 870  * Returns true if @port is connected, false otherwise.
 871  */
 872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 873                                 struct intel_digital_port *port)
 874 {
 875         u32 bit;
 876
 877         if (HAS_PCH_IBX(dev_priv->dev)) {
 878                 switch(port->port) {
 879                 case PORT_B:
 880                         bit = SDE_PORTB_HOTPLUG;
 881                         break;
 882                 case PORT_C:
 883                         bit = SDE_PORTC_HOTPLUG;
 884                         break;
 885                 case PORT_D:
 886                         bit = SDE_PORTD_HOTPLUG;
 887                         break;
 888                 default:
 889                         return true;
 890                 }
 891         } else {
 892                 switch(port->port) {
 893                 case PORT_B:
 894                         bit = SDE_PORTB_HOTPLUG_CPT;
 895                         break;
 896                 case PORT_C:
 897                         bit = SDE_PORTC_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_D:
 900                         bit = SDE_PORTD_HOTPLUG_CPT;
 901                         break;
 902                 default:
 903                         return true;
 904                 }
 905         }
 906
 907         return I915_READ(SDEISR) & bit;
 908 }
 909
 910 static const char *state_string(bool enabled)
 911 {
 912         return enabled ? "on" : "off";
 913 }
 914
 915 /* Only for pre-ILK configs */
 916 void assert_pll(struct drm_i915_private *dev_priv,
 917                 enum pipe pipe, bool state)
 918 {
 919         int reg;
 920         u32 val;
 921         bool cur_state;
 922
 923         reg = DPLL(pipe);
 924         val = I915_READ(reg);
 925         cur_state = !!(val & DPLL_VCO_ENABLE);
 926         WARN(cur_state != state,
 927              "PLL state assertion failure (expected %s, current %s)\n",
 928              state_string(state), state_string(cur_state));
 929 }
 930
 931 /* XXX: the dsi pll is shared between MIPI DSI ports */
 932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 933 {
 934         u32 val;
 935         bool cur_state;
 936
 937         mutex_lock(&dev_priv->dpio_lock);
 938         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 939         mutex_unlock(&dev_priv->dpio_lock);
 940
 941         cur_state = val & DSI_PLL_VCO_EN;
 942         WARN(cur_state != state,
 943              "DSI PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 948
 949 struct intel_shared_dpll *
 950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953
 954         if (crtc->config.shared_dpll < 0)
 955                 return NULL;
 956
 957         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 958 }
 959
 960 /* For ILK+ */
 961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 962                         struct intel_shared_dpll *pll,
 963                         bool state)
 964 {
 965         bool cur_state;
 966         struct intel_dpll_hw_state hw_state;
 967
 968         if (HAS_PCH_LPT(dev_priv->dev)) {
 969                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 970                 return;
 971         }
 972
 973         if (WARN (!pll,
 974                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 975                 return;
 976
 977         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 978         WARN(cur_state != state,
 979              "%s assertion failure (expected %s, current %s)\n",
 980              pll->name, state_string(state), state_string(cur_state));
 981 }
 982
 983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 984                           enum pipe pipe, bool state)
 985 {
 986         int reg;
 987         u32 val;
 988         bool cur_state;
 989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 990                                                                       pipe);
 991
 992         if (HAS_DDI(dev_priv->dev)) {
 993                 /* DDI does not have a specific FDI_TX register */
 994                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 995                 val = I915_READ(reg);
 996                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 997         } else {
 998                 reg = FDI_TX_CTL(pipe);
 999                 val = I915_READ(reg);
1000                 cur_state = !!(val & FDI_TX_ENABLE);
1001         }
1002         WARN(cur_state != state,
1003              "FDI TX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010                           enum pipe pipe, bool state)
1011 {
1012         int reg;
1013         u32 val;
1014         bool cur_state;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         cur_state = !!(val & FDI_RX_ENABLE);
1019         WARN(cur_state != state,
1020              "FDI RX state assertion failure (expected %s, current %s)\n",
1021              state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027                                       enum pipe pipe)
1028 {
1029         int reg;
1030         u32 val;
1031
1032         /* ILK FDI PLL is always enabled */
1033         if (dev_priv->info->gen == 5)
1034                 return;
1035
1036         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037         if (HAS_DDI(dev_priv->dev))
1038                 return;
1039
1040         reg = FDI_TX_CTL(pipe);
1041         val = I915_READ(reg);
1042         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046                        enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051
1052         reg = FDI_RX_CTL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055         WARN(cur_state != state,
1056              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061                                   enum pipe pipe)
1062 {
1063         int pp_reg, lvds_reg;
1064         u32 val;
1065         enum pipe panel_pipe = PIPE_A;
1066         bool locked = true;
1067
1068         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069                 pp_reg = PCH_PP_CONTROL;
1070                 lvds_reg = PCH_LVDS;
1071         } else {
1072                 pp_reg = PP_CONTROL;
1073                 lvds_reg = LVDS;
1074         }
1075
1076         val = I915_READ(pp_reg);
1077         if (!(val & PANEL_POWER_ON) ||
1078             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079                 locked = false;
1080
1081         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082                 panel_pipe = PIPE_B;
1083
1084         WARN(panel_pipe == pipe && locked,
1085              "panel assertion failure, pipe %c regs locked\n",
1086              pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090                           enum pipe pipe, bool state)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093         bool cur_state;
1094
1095         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097         else if (IS_845G(dev) || IS_I865G(dev))
1098                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099         else
1100                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102         WARN(cur_state != state,
1103              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104              pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110                  enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116                                                                       pipe);
1117
1118         /* if we need the pipe A quirk it must be always on */
1119         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120                 state = true;
1121
1122         if (!intel_display_power_enabled(dev_priv->dev,
1123                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124                 cur_state = false;
1125         } else {
1126                 reg = PIPECONF(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & PIPECONF_ENABLE);
1129         }
1130
1131         WARN(cur_state != state,
1132              "pipe %c assertion failure (expected %s, current %s)\n",
1133              pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137                          enum plane plane, bool state)
1138 {
1139         int reg;
1140         u32 val;
1141         bool cur_state;
1142
1143         reg = DSPCNTR(plane);
1144         val = I915_READ(reg);
1145         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146         WARN(cur_state != state,
1147              "plane %c assertion failure (expected %s, current %s)\n",
1148              plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155                                    enum pipe pipe)
1156 {
1157         struct drm_device *dev = dev_priv->dev;
1158         int reg, i;
1159         u32 val;
1160         int cur_pipe;
1161
1162         /* Primary planes are fixed to pipes on gen4+ */
1163         if (INTEL_INFO(dev)->gen >= 4) {
1164                 reg = DSPCNTR(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & DISPLAY_PLANE_ENABLE),
1167                      "plane %c assertion failure, should be disabled but not\n",
1168                      plane_name(pipe));
1169                 return;
1170         }
1171
1172         /* Need to check both planes against the pipe */
1173         for_each_pipe(i) {
1174                 reg = DSPCNTR(i);
1175                 val = I915_READ(reg);
1176                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177                         DISPPLANE_SEL_PIPE_SHIFT;
1178                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180                      plane_name(i), pipe_name(pipe));
1181         }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185                                     enum pipe pipe)
1186 {
1187         struct drm_device *dev = dev_priv->dev;
1188         int reg, i;
1189         u32 val;
1190
1191         if (IS_VALLEYVIEW(dev)) {
1192                 for (i = 0; i < dev_priv->num_plane; i++) {
1193                         reg = SPCNTR(pipe, i);
1194                         val = I915_READ(reg);
1195                         WARN((val & SP_ENABLE),
1196                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197                              sprite_name(pipe, i), pipe_name(pipe));
1198                 }
1199         } else if (INTEL_INFO(dev)->gen >= 7) {
1200                 reg = SPRCTL(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & SPRITE_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         } else if (INTEL_INFO(dev)->gen >= 5) {
1206                 reg = DVSCNTR(pipe);
1207                 val = I915_READ(reg);
1208                 WARN((val & DVS_ENABLE),
1209                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210                      plane_name(pipe), pipe_name(pipe));
1211         }
1212 }
1213
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216         u32 val;
1217         bool enabled;
1218
1219         if (HAS_PCH_LPT(dev_priv->dev)) {
1220                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221                 return;
1222         }
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         /*
1371          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1372          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1373          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1374          *   b. The other bits such as sfr settings / modesel may all be set
1375          *      to 0.
1376          *
1377          * This should only be done on init and resume from S3 with both
1378          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1379          */
1380         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1381 }
1382
1383 static void vlv_enable_pll(struct intel_crtc *crtc)
1384 {
1385         struct drm_device *dev = crtc->base.dev;
1386         struct drm_i915_private *dev_priv = dev->dev_private;
1387         int reg = DPLL(crtc->pipe);
1388         u32 dpll = crtc->config.dpll_hw_state.dpll;
1389
1390         assert_pipe_disabled(dev_priv, crtc->pipe);
1391
1392         /* No really, not for ILK+ */
1393         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1394
1395         /* PLL is protected by panel, make sure we can write it */
1396         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1397                 assert_panel_unlocked(dev_priv, crtc->pipe);
1398
1399         I915_WRITE(reg, dpll);
1400         POSTING_READ(reg);
1401         udelay(150);
1402
1403         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1404                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1405
1406         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1407         POSTING_READ(DPLL_MD(crtc->pipe));
1408
1409         /* We do this three times for luck */
1410         I915_WRITE(reg, dpll);
1411         POSTING_READ(reg);
1412         udelay(150); /* wait for warmup */
1413         I915_WRITE(reg, dpll);
1414         POSTING_READ(reg);
1415         udelay(150); /* wait for warmup */
1416         I915_WRITE(reg, dpll);
1417         POSTING_READ(reg);
1418         udelay(150); /* wait for warmup */
1419 }
1420
1421 static void i9xx_enable_pll(struct intel_crtc *crtc)
1422 {
1423         struct drm_device *dev = crtc->base.dev;
1424         struct drm_i915_private *dev_priv = dev->dev_private;
1425         int reg = DPLL(crtc->pipe);
1426         u32 dpll = crtc->config.dpll_hw_state.dpll;
1427
1428         assert_pipe_disabled(dev_priv, crtc->pipe);
1429
1430         /* No really, not for ILK+ */
1431         BUG_ON(dev_priv->info->gen >= 5);
1432
1433         /* PLL is protected by panel, make sure we can write it */
1434         if (IS_MOBILE(dev) && !IS_I830(dev))
1435                 assert_panel_unlocked(dev_priv, crtc->pipe);
1436
1437         I915_WRITE(reg, dpll);
1438
1439         /* Wait for the clocks to stabilize. */
1440         POSTING_READ(reg);
1441         udelay(150);
1442
1443         if (INTEL_INFO(dev)->gen >= 4) {
1444                 I915_WRITE(DPLL_MD(crtc->pipe),
1445                            crtc->config.dpll_hw_state.dpll_md);
1446         } else {
1447                 /* The pixel multiplier can only be updated once the
1448                  * DPLL is enabled and the clocks are stable.
1449                  *
1450                  * So write it again.
1451                  */
1452                 I915_WRITE(reg, dpll);
1453         }
1454
1455         /* We do this three times for luck */
1456         I915_WRITE(reg, dpll);
1457         POSTING_READ(reg);
1458         udelay(150); /* wait for warmup */
1459         I915_WRITE(reg, dpll);
1460         POSTING_READ(reg);
1461         udelay(150); /* wait for warmup */
1462         I915_WRITE(reg, dpll);
1463         POSTING_READ(reg);
1464         udelay(150); /* wait for warmup */
1465 }
1466
1467 /**
1468  * i9xx_disable_pll - disable a PLL
1469  * @dev_priv: i915 private structure
1470  * @pipe: pipe PLL to disable
1471  *
1472  * Disable the PLL for @pipe, making sure the pipe is off first.
1473  *
1474  * Note!  This is for pre-ILK only.
1475  */
1476 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1477 {
1478         /* Don't disable pipe A or pipe A PLLs if needed */
1479         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1480                 return;
1481
1482         /* Make sure the pipe isn't still relying on us */
1483         assert_pipe_disabled(dev_priv, pipe);
1484
1485         I915_WRITE(DPLL(pipe), 0);
1486         POSTING_READ(DPLL(pipe));
1487 }
1488
1489 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1490 {
1491         u32 val = 0;
1492
1493         /* Make sure the pipe isn't still relying on us */
1494         assert_pipe_disabled(dev_priv, pipe);
1495
1496         /* Leave integrated clock source enabled */
1497         if (pipe == PIPE_B)
1498                 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1499         I915_WRITE(DPLL(pipe), val);
1500         POSTING_READ(DPLL(pipe));
1501 }
1502
1503 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1504 {
1505         u32 port_mask;
1506
1507         if (!port)
1508                 port_mask = DPLL_PORTB_READY_MASK;
1509         else
1510                 port_mask = DPLL_PORTC_READY_MASK;
1511
1512         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1513                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1514                      'B' + port, I915_READ(DPLL(0)));
1515 }
1516
1517 /**
1518  * ironlake_enable_shared_dpll - enable PCH PLL
1519  * @dev_priv: i915 private structure
1520  * @pipe: pipe PLL to enable
1521  *
1522  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1523  * drives the transcoder clock.
1524  */
1525 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1526 {
1527         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1528         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1529
1530         /* PCH PLLs only available on ILK, SNB and IVB */
1531         BUG_ON(dev_priv->info->gen < 5);
1532         if (WARN_ON(pll == NULL))
1533                 return;
1534
1535         if (WARN_ON(pll->refcount == 0))
1536                 return;
1537
1538         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1539                       pll->name, pll->active, pll->on,
1540                       crtc->base.base.id);
1541
1542         if (pll->active++) {
1543                 WARN_ON(!pll->on);
1544                 assert_shared_dpll_enabled(dev_priv, pll);
1545                 return;
1546         }
1547         WARN_ON(pll->on);
1548
1549         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1550         pll->enable(dev_priv, pll);
1551         pll->on = true;
1552 }
1553
1554 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1555 {
1556         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1557         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1558
1559         /* PCH only available on ILK+ */
1560         BUG_ON(dev_priv->info->gen < 5);
1561         if (WARN_ON(pll == NULL))
1562                return;
1563
1564         if (WARN_ON(pll->refcount == 0))
1565                 return;
1566
1567         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1568                       pll->name, pll->active, pll->on,
1569                       crtc->base.base.id);
1570
1571         if (WARN_ON(pll->active == 0)) {
1572                 assert_shared_dpll_disabled(dev_priv, pll);
1573                 return;
1574         }
1575
1576         assert_shared_dpll_enabled(dev_priv, pll);
1577         WARN_ON(!pll->on);
1578         if (--pll->active)
1579                 return;
1580
1581         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1582         pll->disable(dev_priv, pll);
1583         pll->on = false;
1584 }
1585
1586 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1587                                            enum pipe pipe)
1588 {
1589         struct drm_device *dev = dev_priv->dev;
1590         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1592         uint32_t reg, val, pipeconf_val;
1593
1594         /* PCH only available on ILK+ */
1595         BUG_ON(dev_priv->info->gen < 5);
1596
1597         /* Make sure PCH DPLL is enabled */
1598         assert_shared_dpll_enabled(dev_priv,
1599                                    intel_crtc_to_shared_dpll(intel_crtc));
1600
1601         /* FDI must be feeding us bits for PCH ports */
1602         assert_fdi_tx_enabled(dev_priv, pipe);
1603         assert_fdi_rx_enabled(dev_priv, pipe);
1604
1605         if (HAS_PCH_CPT(dev)) {
1606                 /* Workaround: Set the timing override bit before enabling the
1607                  * pch transcoder. */
1608                 reg = TRANS_CHICKEN2(pipe);
1609                 val = I915_READ(reg);
1610                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1611                 I915_WRITE(reg, val);
1612         }
1613
1614         reg = PCH_TRANSCONF(pipe);
1615         val = I915_READ(reg);
1616         pipeconf_val = I915_READ(PIPECONF(pipe));
1617
1618         if (HAS_PCH_IBX(dev_priv->dev)) {
1619                 /*
1620                  * make the BPC in transcoder be consistent with
1621                  * that in pipeconf reg.
1622                  */
1623                 val &= ~PIPECONF_BPC_MASK;
1624                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1625         }
1626
1627         val &= ~TRANS_INTERLACE_MASK;
1628         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1629                 if (HAS_PCH_IBX(dev_priv->dev) &&
1630                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1631                         val |= TRANS_LEGACY_INTERLACED_ILK;
1632                 else
1633                         val |= TRANS_INTERLACED;
1634         else
1635                 val |= TRANS_PROGRESSIVE;
1636
1637         I915_WRITE(reg, val | TRANS_ENABLE);
1638         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1639                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1640 }
1641
1642 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1643                                       enum transcoder cpu_transcoder)
1644 {
1645         u32 val, pipeconf_val;
1646
1647         /* PCH only available on ILK+ */
1648         BUG_ON(dev_priv->info->gen < 5);
1649
1650         /* FDI must be feeding us bits for PCH ports */
1651         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1652         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1653
1654         /* Workaround: set timing override bit. */
1655         val = I915_READ(_TRANSA_CHICKEN2);
1656         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1657         I915_WRITE(_TRANSA_CHICKEN2, val);
1658
1659         val = TRANS_ENABLE;
1660         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1661
1662         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1663             PIPECONF_INTERLACED_ILK)
1664                 val |= TRANS_INTERLACED;
1665         else
1666                 val |= TRANS_PROGRESSIVE;
1667
1668         I915_WRITE(LPT_TRANSCONF, val);
1669         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1670                 DRM_ERROR("Failed to enable PCH transcoder\n");
1671 }
1672
1673 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1674                                             enum pipe pipe)
1675 {
1676         struct drm_device *dev = dev_priv->dev;
1677         uint32_t reg, val;
1678
1679         /* FDI relies on the transcoder */
1680         assert_fdi_tx_disabled(dev_priv, pipe);
1681         assert_fdi_rx_disabled(dev_priv, pipe);
1682
1683         /* Ports must be off as well */
1684         assert_pch_ports_disabled(dev_priv, pipe);
1685
1686         reg = PCH_TRANSCONF(pipe);
1687         val = I915_READ(reg);
1688         val &= ~TRANS_ENABLE;
1689         I915_WRITE(reg, val);
1690         /* wait for PCH transcoder off, transcoder state */
1691         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1692                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1693
1694         if (!HAS_PCH_IBX(dev)) {
1695                 /* Workaround: Clear the timing override chicken bit again. */
1696                 reg = TRANS_CHICKEN2(pipe);
1697                 val = I915_READ(reg);
1698                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1699                 I915_WRITE(reg, val);
1700         }
1701 }
1702
1703 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1704 {
1705         u32 val;
1706
1707         val = I915_READ(LPT_TRANSCONF);
1708         val &= ~TRANS_ENABLE;
1709         I915_WRITE(LPT_TRANSCONF, val);
1710         /* wait for PCH transcoder off, transcoder state */
1711         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1712                 DRM_ERROR("Failed to disable PCH transcoder\n");
1713
1714         /* Workaround: clear timing override bit. */
1715         val = I915_READ(_TRANSA_CHICKEN2);
1716         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1717         I915_WRITE(_TRANSA_CHICKEN2, val);
1718 }
1719
1720 /**
1721  * intel_enable_pipe - enable a pipe, asserting requirements
1722  * @dev_priv: i915 private structure
1723  * @pipe: pipe to enable
1724  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1725  *
1726  * Enable @pipe, making sure that various hardware specific requirements
1727  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1728  *
1729  * @pipe should be %PIPE_A or %PIPE_B.
1730  *
1731  * Will wait until the pipe is actually running (i.e. first vblank) before
1732  * returning.
1733  */
1734 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1735                               bool pch_port, bool dsi)
1736 {
1737         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1738                                                                       pipe);
1739         enum pipe pch_transcoder;
1740         int reg;
1741         u32 val;
1742
1743         assert_planes_disabled(dev_priv, pipe);
1744         assert_cursor_disabled(dev_priv, pipe);
1745         assert_sprites_disabled(dev_priv, pipe);
1746
1747         if (HAS_PCH_LPT(dev_priv->dev))
1748                 pch_transcoder = TRANSCODER_A;
1749         else
1750                 pch_transcoder = pipe;
1751
1752         /*
1753          * A pipe without a PLL won't actually be able to drive bits from
1754          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1755          * need the check.
1756          */
1757         if (!HAS_PCH_SPLIT(dev_priv->dev))
1758                 if (dsi)
1759                         assert_dsi_pll_enabled(dev_priv);
1760                 else
1761                         assert_pll_enabled(dev_priv, pipe);
1762         else {
1763                 if (pch_port) {
1764                         /* if driving the PCH, we need FDI enabled */
1765                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1766                         assert_fdi_tx_pll_enabled(dev_priv,
1767                                                   (enum pipe) cpu_transcoder);
1768                 }
1769                 /* FIXME: assert CPU port conditions for SNB+ */
1770         }
1771
1772         reg = PIPECONF(cpu_transcoder);
1773         val = I915_READ(reg);
1774         if (val & PIPECONF_ENABLE)
1775                 return;
1776
1777         I915_WRITE(reg, val | PIPECONF_ENABLE);
1778         intel_wait_for_vblank(dev_priv->dev, pipe);
1779 }
1780
1781 /**
1782  * intel_disable_pipe - disable a pipe, asserting requirements
1783  * @dev_priv: i915 private structure
1784  * @pipe: pipe to disable
1785  *
1786  * Disable @pipe, making sure that various hardware specific requirements
1787  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1788  *
1789  * @pipe should be %PIPE_A or %PIPE_B.
1790  *
1791  * Will wait until the pipe has shut down before returning.
1792  */
1793 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1794                                enum pipe pipe)
1795 {
1796         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1797                                                                       pipe);
1798         int reg;
1799         u32 val;
1800
1801         /*
1802          * Make sure planes won't keep trying to pump pixels to us,
1803          * or we might hang the display.
1804          */
1805         assert_planes_disabled(dev_priv, pipe);
1806         assert_cursor_disabled(dev_priv, pipe);
1807         assert_sprites_disabled(dev_priv, pipe);
1808
1809         /* Don't disable pipe A or pipe A PLLs if needed */
1810         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1811                 return;
1812
1813         reg = PIPECONF(cpu_transcoder);
1814         val = I915_READ(reg);
1815         if ((val & PIPECONF_ENABLE) == 0)
1816                 return;
1817
1818         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1819         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1820 }
1821
1822 /*
1823  * Plane regs are double buffered, going from enabled->disabled needs a
1824  * trigger in order to latch.  The display address reg provides this.
1825  */
1826 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1827                                       enum plane plane)
1828 {
1829         if (dev_priv->info->gen >= 4)
1830                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1831         else
1832                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1833 }
1834
1835 /**
1836  * intel_enable_plane - enable a display plane on a given pipe
1837  * @dev_priv: i915 private structure
1838  * @plane: plane to enable
1839  * @pipe: pipe being fed
1840  *
1841  * Enable @plane on @pipe, making sure that @pipe is running first.
1842  */
1843 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1844                                enum plane plane, enum pipe pipe)
1845 {
1846         int reg;
1847         u32 val;
1848
1849         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1850         assert_pipe_enabled(dev_priv, pipe);
1851
1852         reg = DSPCNTR(plane);
1853         val = I915_READ(reg);
1854         if (val & DISPLAY_PLANE_ENABLE)
1855                 return;
1856
1857         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1858         intel_flush_display_plane(dev_priv, plane);
1859         intel_wait_for_vblank(dev_priv->dev, pipe);
1860 }
1861
1862 /**
1863  * intel_disable_plane - disable a display plane
1864  * @dev_priv: i915 private structure
1865  * @plane: plane to disable
1866  * @pipe: pipe consuming the data
1867  *
1868  * Disable @plane; should be an independent operation.
1869  */
1870 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1871                                 enum plane plane, enum pipe pipe)
1872 {
1873         int reg;
1874         u32 val;
1875
1876         reg = DSPCNTR(plane);
1877         val = I915_READ(reg);
1878         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1879                 return;
1880
1881         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1882         intel_flush_display_plane(dev_priv, plane);
1883         intel_wait_for_vblank(dev_priv->dev, pipe);
1884 }
1885
1886 static bool need_vtd_wa(struct drm_device *dev)
1887 {
1888 #ifdef CONFIG_INTEL_IOMMU
1889         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1890                 return true;
1891 #endif
1892         return false;
1893 }
1894
1895 int
1896 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1897                            struct drm_i915_gem_object *obj,
1898                            struct intel_ring_buffer *pipelined)
1899 {
1900         struct drm_i915_private *dev_priv = dev->dev_private;
1901         u32 alignment;
1902         int ret;
1903
1904         switch (obj->tiling_mode) {
1905         case I915_TILING_NONE:
1906                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1907                         alignment = 128 * 1024;
1908                 else if (INTEL_INFO(dev)->gen >= 4)
1909                         alignment = 4 * 1024;
1910                 else
1911                         alignment = 64 * 1024;
1912                 break;
1913         case I915_TILING_X:
1914                 /* pin() will align the object as required by fence */
1915                 alignment = 0;
1916                 break;
1917         case I915_TILING_Y:
1918                 /* Despite that we check this in framebuffer_init userspace can
1919                  * screw us over and change the tiling after the fact. Only
1920                  * pinned buffers can't change their tiling. */
1921                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1922                 return -EINVAL;
1923         default:
1924                 BUG();
1925         }
1926
1927         /* Note that the w/a also requires 64 PTE of padding following the
1928          * bo. We currently fill all unused PTE with the shadow page and so
1929          * we should always have valid PTE following the scanout preventing
1930          * the VT-d warning.
1931          */
1932         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1933                 alignment = 256 * 1024;
1934
1935         dev_priv->mm.interruptible = false;
1936         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1937         if (ret)
1938                 goto err_interruptible;
1939
1940         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1941          * fence, whereas 965+ only requires a fence if using
1942          * framebuffer compression.  For simplicity, we always install
1943          * a fence as the cost is not that onerous.
1944          */
1945         ret = i915_gem_object_get_fence(obj);
1946         if (ret)
1947                 goto err_unpin;
1948
1949         i915_gem_object_pin_fence(obj);
1950
1951         dev_priv->mm.interruptible = true;
1952         return 0;
1953
1954 err_unpin:
1955         i915_gem_object_unpin_from_display_plane(obj);
1956 err_interruptible:
1957         dev_priv->mm.interruptible = true;
1958         return ret;
1959 }
1960
1961 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1962 {
1963         i915_gem_object_unpin_fence(obj);
1964         i915_gem_object_unpin_from_display_plane(obj);
1965 }
1966
1967 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1968  * is assumed to be a power-of-two. */
1969 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1970                                              unsigned int tiling_mode,
1971                                              unsigned int cpp,
1972                                              unsigned int pitch)
1973 {
1974         if (tiling_mode != I915_TILING_NONE) {
1975                 unsigned int tile_rows, tiles;
1976
1977                 tile_rows = *y / 8;
1978                 *y %= 8;
1979
1980                 tiles = *x / (512/cpp);
1981                 *x %= 512/cpp;
1982
1983                 return tile_rows * pitch * 8 + tiles * 4096;
1984         } else {
1985                 unsigned int offset;
1986
1987                 offset = *y * pitch + *x * cpp;
1988                 *y = 0;
1989                 *x = (offset & 4095) / cpp;
1990                 return offset & -4096;
1991         }
1992 }
1993
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995                              int x, int y)
1996 {
1997         struct drm_device *dev = crtc->dev;
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000         struct intel_framebuffer *intel_fb;
2001         struct drm_i915_gem_object *obj;
2002         int plane = intel_crtc->plane;
2003         unsigned long linear_offset;
2004         u32 dspcntr;
2005         u32 reg;
2006
2007         switch (plane) {
2008         case 0:
2009         case 1:
2010                 break;
2011         default:
2012                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2013                 return -EINVAL;
2014         }
2015
2016         intel_fb = to_intel_framebuffer(fb);
2017         obj = intel_fb->obj;
2018
2019         reg = DSPCNTR(plane);
2020         dspcntr = I915_READ(reg);
2021         /* Mask out pixel format bits in case we change it */
2022         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023         switch (fb->pixel_format) {
2024         case DRM_FORMAT_C8:
2025                 dspcntr |= DISPPLANE_8BPP;
2026                 break;
2027         case DRM_FORMAT_XRGB1555:
2028         case DRM_FORMAT_ARGB1555:
2029                 dspcntr |= DISPPLANE_BGRX555;
2030                 break;
2031         case DRM_FORMAT_RGB565:
2032                 dspcntr |= DISPPLANE_BGRX565;
2033                 break;
2034         case DRM_FORMAT_XRGB8888:
2035         case DRM_FORMAT_ARGB8888:
2036                 dspcntr |= DISPPLANE_BGRX888;
2037                 break;
2038         case DRM_FORMAT_XBGR8888:
2039         case DRM_FORMAT_ABGR8888:
2040                 dspcntr |= DISPPLANE_RGBX888;
2041                 break;
2042         case DRM_FORMAT_XRGB2101010:
2043         case DRM_FORMAT_ARGB2101010:
2044                 dspcntr |= DISPPLANE_BGRX101010;
2045                 break;
2046         case DRM_FORMAT_XBGR2101010:
2047         case DRM_FORMAT_ABGR2101010:
2048                 dspcntr |= DISPPLANE_RGBX101010;
2049                 break;
2050         default:
2051                 BUG();
2052         }
2053
2054         if (INTEL_INFO(dev)->gen >= 4) {
2055                 if (obj->tiling_mode != I915_TILING_NONE)
2056                         dspcntr |= DISPPLANE_TILED;
2057                 else
2058                         dspcntr &= ~DISPPLANE_TILED;
2059         }
2060
2061         if (IS_G4X(dev))
2062                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2063
2064         I915_WRITE(reg, dspcntr);
2065
2066         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2067
2068         if (INTEL_INFO(dev)->gen >= 4) {
2069                 intel_crtc->dspaddr_offset =
2070                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2071                                                        fb->bits_per_pixel / 8,
2072                                                        fb->pitches[0]);
2073                 linear_offset -= intel_crtc->dspaddr_offset;
2074         } else {
2075                 intel_crtc->dspaddr_offset = linear_offset;
2076         }
2077
2078         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2080                       fb->pitches[0]);
2081         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2082         if (INTEL_INFO(dev)->gen >= 4) {
2083                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2084                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2085                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2086                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2087         } else
2088                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2089         POSTING_READ(reg);
2090
2091         return 0;
2092 }
2093
2094 static int ironlake_update_plane(struct drm_crtc *crtc,
2095                                  struct drm_framebuffer *fb, int x, int y)
2096 {
2097         struct drm_device *dev = crtc->dev;
2098         struct drm_i915_private *dev_priv = dev->dev_private;
2099         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2100         struct intel_framebuffer *intel_fb;
2101         struct drm_i915_gem_object *obj;
2102         int plane = intel_crtc->plane;
2103         unsigned long linear_offset;
2104         u32 dspcntr;
2105         u32 reg;
2106
2107         switch (plane) {
2108         case 0:
2109         case 1:
2110         case 2:
2111                 break;
2112         default:
2113                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2114                 return -EINVAL;
2115         }
2116
2117         intel_fb = to_intel_framebuffer(fb);
2118         obj = intel_fb->obj;
2119
2120         reg = DSPCNTR(plane);
2121         dspcntr = I915_READ(reg);
2122         /* Mask out pixel format bits in case we change it */
2123         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2124         switch (fb->pixel_format) {
2125         case DRM_FORMAT_C8:
2126                 dspcntr |= DISPPLANE_8BPP;
2127                 break;
2128         case DRM_FORMAT_RGB565:
2129                 dspcntr |= DISPPLANE_BGRX565;
2130                 break;
2131         case DRM_FORMAT_XRGB8888:
2132         case DRM_FORMAT_ARGB8888:
2133                 dspcntr |= DISPPLANE_BGRX888;
2134                 break;
2135         case DRM_FORMAT_XBGR8888:
2136         case DRM_FORMAT_ABGR8888:
2137                 dspcntr |= DISPPLANE_RGBX888;
2138                 break;
2139         case DRM_FORMAT_XRGB2101010:
2140         case DRM_FORMAT_ARGB2101010:
2141                 dspcntr |= DISPPLANE_BGRX101010;
2142                 break;
2143         case DRM_FORMAT_XBGR2101010:
2144         case DRM_FORMAT_ABGR2101010:
2145                 dspcntr |= DISPPLANE_RGBX101010;
2146                 break;
2147         default:
2148                 BUG();
2149         }
2150
2151         if (obj->tiling_mode != I915_TILING_NONE)
2152                 dspcntr |= DISPPLANE_TILED;
2153         else
2154                 dspcntr &= ~DISPPLANE_TILED;
2155
2156         if (IS_HASWELL(dev))
2157                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2158         else
2159                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2160
2161         I915_WRITE(reg, dspcntr);
2162
2163         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2164         intel_crtc->dspaddr_offset =
2165                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2166                                                fb->bits_per_pixel / 8,
2167                                                fb->pitches[0]);
2168         linear_offset -= intel_crtc->dspaddr_offset;
2169
2170         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2171                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2172                       fb->pitches[0]);
2173         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2174         I915_MODIFY_DISPBASE(DSPSURF(plane),
2175                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2176         if (IS_HASWELL(dev)) {
2177                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2178         } else {
2179                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2180                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2181         }
2182         POSTING_READ(reg);
2183
2184         return 0;
2185 }
2186
2187 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2188 static int
2189 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2190                            int x, int y, enum mode_set_atomic state)
2191 {
2192         struct drm_device *dev = crtc->dev;
2193         struct drm_i915_private *dev_priv = dev->dev_private;
2194
2195         if (dev_priv->display.disable_fbc)
2196                 dev_priv->display.disable_fbc(dev);
2197         intel_increase_pllclock(crtc);
2198
2199         return dev_priv->display.update_plane(crtc, fb, x, y);
2200 }
2201
2202 void intel_display_handle_reset(struct drm_device *dev)
2203 {
2204         struct drm_i915_private *dev_priv = dev->dev_private;
2205         struct drm_crtc *crtc;
2206
2207         /*
2208          * Flips in the rings have been nuked by the reset,
2209          * so complete all pending flips so that user space
2210          * will get its events and not get stuck.
2211          *
2212          * Also update the base address of all primary
2213          * planes to the the last fb to make sure we're
2214          * showing the correct fb after a reset.
2215          *
2216          * Need to make two loops over the crtcs so that we
2217          * don't try to grab a crtc mutex before the
2218          * pending_flip_queue really got woken up.
2219          */
2220
2221         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2222                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2223                 enum plane plane = intel_crtc->plane;
2224
2225                 intel_prepare_page_flip(dev, plane);
2226                 intel_finish_page_flip_plane(dev, plane);
2227         }
2228
2229         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2230                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2231
2232                 mutex_lock(&crtc->mutex);
2233                 if (intel_crtc->active)
2234                         dev_priv->display.update_plane(crtc, crtc->fb,
2235                                                        crtc->x, crtc->y);
2236                 mutex_unlock(&crtc->mutex);
2237         }
2238 }
2239
2240 static int
2241 intel_finish_fb(struct drm_framebuffer *old_fb)
2242 {
2243         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2244         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2245         bool was_interruptible = dev_priv->mm.interruptible;
2246         int ret;
2247
2248         /* Big Hammer, we also need to ensure that any pending
2249          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2250          * current scanout is retired before unpinning the old
2251          * framebuffer.
2252          *
2253          * This should only fail upon a hung GPU, in which case we
2254          * can safely continue.
2255          */
2256         dev_priv->mm.interruptible = false;
2257         ret = i915_gem_object_finish_gpu(obj);
2258         dev_priv->mm.interruptible = was_interruptible;
2259
2260         return ret;
2261 }
2262
2263 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2264 {
2265         struct drm_device *dev = crtc->dev;
2266         struct drm_i915_master_private *master_priv;
2267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2268
2269         if (!dev->primary->master)
2270                 return;
2271
2272         master_priv = dev->primary->master->driver_priv;
2273         if (!master_priv->sarea_priv)
2274                 return;
2275
2276         switch (intel_crtc->pipe) {
2277         case 0:
2278                 master_priv->sarea_priv->pipeA_x = x;
2279                 master_priv->sarea_priv->pipeA_y = y;
2280                 break;
2281         case 1:
2282                 master_priv->sarea_priv->pipeB_x = x;
2283                 master_priv->sarea_priv->pipeB_y = y;
2284                 break;
2285         default:
2286                 break;
2287         }
2288 }
2289
2290 static int
2291 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2292                     struct drm_framebuffer *fb)
2293 {
2294         struct drm_device *dev = crtc->dev;
2295         struct drm_i915_private *dev_priv = dev->dev_private;
2296         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2297         struct drm_framebuffer *old_fb;
2298         int ret;
2299
2300         /* no fb bound */
2301         if (!fb) {
2302                 DRM_ERROR("No FB bound\n");
2303                 return 0;
2304         }
2305
2306         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2307                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2308                           plane_name(intel_crtc->plane),
2309                           INTEL_INFO(dev)->num_pipes);
2310                 return -EINVAL;
2311         }
2312
2313         mutex_lock(&dev->struct_mutex);
2314         ret = intel_pin_and_fence_fb_obj(dev,
2315                                          to_intel_framebuffer(fb)->obj,
2316                                          NULL);
2317         if (ret != 0) {
2318                 mutex_unlock(&dev->struct_mutex);
2319                 DRM_ERROR("pin & fence failed\n");
2320                 return ret;
2321         }
2322
2323         /*
2324          * Update pipe size and adjust fitter if needed: the reason for this is
2325          * that in compute_mode_changes we check the native mode (not the pfit
2326          * mode) to see if we can flip rather than do a full mode set. In the
2327          * fastboot case, we'll flip, but if we don't update the pipesrc and
2328          * pfit state, we'll end up with a big fb scanned out into the wrong
2329          * sized surface.
2330          *
2331          * To fix this properly, we need to hoist the checks up into
2332          * compute_mode_changes (or above), check the actual pfit state and
2333          * whether the platform allows pfit disable with pipe active, and only
2334          * then update the pipesrc and pfit state, even on the flip path.
2335          */
2336         if (i915_fastboot) {
2337                 const struct drm_display_mode *adjusted_mode =
2338                         &intel_crtc->config.adjusted_mode;
2339
2340                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2341                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2342                            (adjusted_mode->crtc_vdisplay - 1));
2343                 if (!intel_crtc->config.pch_pfit.enabled &&
2344                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2345                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2346                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2347                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2348                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2349                 }
2350         }
2351
2352         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2353         if (ret) {
2354                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2355                 mutex_unlock(&dev->struct_mutex);
2356                 DRM_ERROR("failed to update base address\n");
2357                 return ret;
2358         }
2359
2360         old_fb = crtc->fb;
2361         crtc->fb = fb;
2362         crtc->x = x;
2363         crtc->y = y;
2364
2365         if (old_fb) {
2366                 if (intel_crtc->active && old_fb != fb)
2367                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2368                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2369         }
2370
2371         intel_update_fbc(dev);
2372         intel_edp_psr_update(dev);
2373         mutex_unlock(&dev->struct_mutex);
2374
2375         intel_crtc_update_sarea_pos(crtc, x, y);
2376
2377         return 0;
2378 }
2379
2380 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2381 {
2382         struct drm_device *dev = crtc->dev;
2383         struct drm_i915_private *dev_priv = dev->dev_private;
2384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2385         int pipe = intel_crtc->pipe;
2386         u32 reg, temp;
2387
2388         /* enable normal train */
2389         reg = FDI_TX_CTL(pipe);
2390         temp = I915_READ(reg);
2391         if (IS_IVYBRIDGE(dev)) {
2392                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2393                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2394         } else {
2395                 temp &= ~FDI_LINK_TRAIN_NONE;
2396                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2397         }
2398         I915_WRITE(reg, temp);
2399
2400         reg = FDI_RX_CTL(pipe);
2401         temp = I915_READ(reg);
2402         if (HAS_PCH_CPT(dev)) {
2403                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2404                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2405         } else {
2406                 temp &= ~FDI_LINK_TRAIN_NONE;
2407                 temp |= FDI_LINK_TRAIN_NONE;
2408         }
2409         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2410
2411         /* wait one idle pattern time */
2412         POSTING_READ(reg);
2413         udelay(1000);
2414
2415         /* IVB wants error correction enabled */
2416         if (IS_IVYBRIDGE(dev))
2417                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2418                            FDI_FE_ERRC_ENABLE);
2419 }
2420
2421 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2422 {
2423         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2424 }
2425
2426 static void ivb_modeset_global_resources(struct drm_device *dev)
2427 {
2428         struct drm_i915_private *dev_priv = dev->dev_private;
2429         struct intel_crtc *pipe_B_crtc =
2430                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2431         struct intel_crtc *pipe_C_crtc =
2432                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2433         uint32_t temp;
2434
2435         /*
2436          * When everything is off disable fdi C so that we could enable fdi B
2437          * with all lanes. Note that we don't care about enabled pipes without
2438          * an enabled pch encoder.
2439          */
2440         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2441             !pipe_has_enabled_pch(pipe_C_crtc)) {
2442                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2443                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2444
2445                 temp = I915_READ(SOUTH_CHICKEN1);
2446                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2447                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2448                 I915_WRITE(SOUTH_CHICKEN1, temp);
2449         }
2450 }
2451
2452 /* The FDI link training functions for ILK/Ibexpeak. */
2453 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2454 {
2455         struct drm_device *dev = crtc->dev;
2456         struct drm_i915_private *dev_priv = dev->dev_private;
2457         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2458         int pipe = intel_crtc->pipe;
2459         int plane = intel_crtc->plane;
2460         u32 reg, temp, tries;
2461
2462         /* FDI needs bits from pipe & plane first */
2463         assert_pipe_enabled(dev_priv, pipe);
2464         assert_plane_enabled(dev_priv, plane);
2465
2466         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2467            for train result */
2468         reg = FDI_RX_IMR(pipe);
2469         temp = I915_READ(reg);
2470         temp &= ~FDI_RX_SYMBOL_LOCK;
2471         temp &= ~FDI_RX_BIT_LOCK;
2472         I915_WRITE(reg, temp);
2473         I915_READ(reg);
2474         udelay(150);
2475
2476         /* enable CPU FDI TX and PCH FDI RX */
2477         reg = FDI_TX_CTL(pipe);
2478         temp = I915_READ(reg);
2479         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2480         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2481         temp &= ~FDI_LINK_TRAIN_NONE;
2482         temp |= FDI_LINK_TRAIN_PATTERN_1;
2483         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2484
2485         reg = FDI_RX_CTL(pipe);
2486         temp = I915_READ(reg);
2487         temp &= ~FDI_LINK_TRAIN_NONE;
2488         temp |= FDI_LINK_TRAIN_PATTERN_1;
2489         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2490
2491         POSTING_READ(reg);
2492         udelay(150);
2493
2494         /* Ironlake workaround, enable clock pointer after FDI enable*/
2495         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2496         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2497                    FDI_RX_PHASE_SYNC_POINTER_EN);
2498
2499         reg = FDI_RX_IIR(pipe);
2500         for (tries = 0; tries < 5; tries++) {
2501                 temp = I915_READ(reg);
2502                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503
2504                 if ((temp & FDI_RX_BIT_LOCK)) {
2505                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2506                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2507                         break;
2508                 }
2509         }
2510         if (tries == 5)
2511                 DRM_ERROR("FDI train 1 fail!\n");
2512
2513         /* Train 2 */
2514         reg = FDI_TX_CTL(pipe);
2515         temp = I915_READ(reg);
2516         temp &= ~FDI_LINK_TRAIN_NONE;
2517         temp |= FDI_LINK_TRAIN_PATTERN_2;
2518         I915_WRITE(reg, temp);
2519
2520         reg = FDI_RX_CTL(pipe);
2521         temp = I915_READ(reg);
2522         temp &= ~FDI_LINK_TRAIN_NONE;
2523         temp |= FDI_LINK_TRAIN_PATTERN_2;
2524         I915_WRITE(reg, temp);
2525
2526         POSTING_READ(reg);
2527         udelay(150);
2528
2529         reg = FDI_RX_IIR(pipe);
2530         for (tries = 0; tries < 5; tries++) {
2531                 temp = I915_READ(reg);
2532                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533
2534                 if (temp & FDI_RX_SYMBOL_LOCK) {
2535                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2536                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2537                         break;
2538                 }
2539         }
2540         if (tries == 5)
2541                 DRM_ERROR("FDI train 2 fail!\n");
2542
2543         DRM_DEBUG_KMS("FDI train done\n");
2544
2545 }
2546
2547 static const int snb_b_fdi_train_param[] = {
2548         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2549         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2550         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2551         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2552 };
2553
2554 /* The FDI link training functions for SNB/Cougarpoint. */
2555 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2556 {
2557         struct drm_device *dev = crtc->dev;
2558         struct drm_i915_private *dev_priv = dev->dev_private;
2559         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2560         int pipe = intel_crtc->pipe;
2561         u32 reg, temp, i, retry;
2562
2563         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2564            for train result */
2565         reg = FDI_RX_IMR(pipe);
2566         temp = I915_READ(reg);
2567         temp &= ~FDI_RX_SYMBOL_LOCK;
2568         temp &= ~FDI_RX_BIT_LOCK;
2569         I915_WRITE(reg, temp);
2570
2571         POSTING_READ(reg);
2572         udelay(150);
2573
2574         /* enable CPU FDI TX and PCH FDI RX */
2575         reg = FDI_TX_CTL(pipe);
2576         temp = I915_READ(reg);
2577         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2578         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2579         temp &= ~FDI_LINK_TRAIN_NONE;
2580         temp |= FDI_LINK_TRAIN_PATTERN_1;
2581         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582         /* SNB-B */
2583         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2585
2586         I915_WRITE(FDI_RX_MISC(pipe),
2587                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2588
2589         reg = FDI_RX_CTL(pipe);
2590         temp = I915_READ(reg);
2591         if (HAS_PCH_CPT(dev)) {
2592                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2593                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2594         } else {
2595                 temp &= ~FDI_LINK_TRAIN_NONE;
2596                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2597         }
2598         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2599
2600         POSTING_READ(reg);
2601         udelay(150);
2602
2603         for (i = 0; i < 4; i++) {
2604                 reg = FDI_TX_CTL(pipe);
2605                 temp = I915_READ(reg);
2606                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2607                 temp |= snb_b_fdi_train_param[i];
2608                 I915_WRITE(reg, temp);
2609
2610                 POSTING_READ(reg);
2611                 udelay(500);
2612
2613                 for (retry = 0; retry < 5; retry++) {
2614                         reg = FDI_RX_IIR(pipe);
2615                         temp = I915_READ(reg);
2616                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2617                         if (temp & FDI_RX_BIT_LOCK) {
2618                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2619                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2620                                 break;
2621                         }
2622                         udelay(50);
2623                 }
2624                 if (retry < 5)
2625                         break;
2626         }
2627         if (i == 4)
2628                 DRM_ERROR("FDI train 1 fail!\n");
2629
2630         /* Train 2 */
2631         reg = FDI_TX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         temp &= ~FDI_LINK_TRAIN_NONE;
2634         temp |= FDI_LINK_TRAIN_PATTERN_2;
2635         if (IS_GEN6(dev)) {
2636                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2637                 /* SNB-B */
2638                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2639         }
2640         I915_WRITE(reg, temp);
2641
2642         reg = FDI_RX_CTL(pipe);
2643         temp = I915_READ(reg);
2644         if (HAS_PCH_CPT(dev)) {
2645                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2647         } else {
2648                 temp &= ~FDI_LINK_TRAIN_NONE;
2649                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2650         }
2651         I915_WRITE(reg, temp);
2652
2653         POSTING_READ(reg);
2654         udelay(150);
2655
2656         for (i = 0; i < 4; i++) {
2657                 reg = FDI_TX_CTL(pipe);
2658                 temp = I915_READ(reg);
2659                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660                 temp |= snb_b_fdi_train_param[i];
2661                 I915_WRITE(reg, temp);
2662
2663                 POSTING_READ(reg);
2664                 udelay(500);
2665
2666                 for (retry = 0; retry < 5; retry++) {
2667                         reg = FDI_RX_IIR(pipe);
2668                         temp = I915_READ(reg);
2669                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2670                         if (temp & FDI_RX_SYMBOL_LOCK) {
2671                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2672                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2673                                 break;
2674                         }
2675                         udelay(50);
2676                 }
2677                 if (retry < 5)
2678                         break;
2679         }
2680         if (i == 4)
2681                 DRM_ERROR("FDI train 2 fail!\n");
2682
2683         DRM_DEBUG_KMS("FDI train done.\n");
2684 }
2685
2686 /* Manual link training for Ivy Bridge A0 parts */
2687 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2688 {
2689         struct drm_device *dev = crtc->dev;
2690         struct drm_i915_private *dev_priv = dev->dev_private;
2691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2692         int pipe = intel_crtc->pipe;
2693         u32 reg, temp, i, j;
2694
2695         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2696            for train result */
2697         reg = FDI_RX_IMR(pipe);
2698         temp = I915_READ(reg);
2699         temp &= ~FDI_RX_SYMBOL_LOCK;
2700         temp &= ~FDI_RX_BIT_LOCK;
2701         I915_WRITE(reg, temp);
2702
2703         POSTING_READ(reg);
2704         udelay(150);
2705
2706         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2707                       I915_READ(FDI_RX_IIR(pipe)));
2708
2709         /* Try each vswing and preemphasis setting twice before moving on */
2710         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2711                 /* disable first in case we need to retry */
2712                 reg = FDI_TX_CTL(pipe);
2713                 temp = I915_READ(reg);
2714                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2715                 temp &= ~FDI_TX_ENABLE;
2716                 I915_WRITE(reg, temp);
2717
2718                 reg = FDI_RX_CTL(pipe);
2719                 temp = I915_READ(reg);
2720                 temp &= ~FDI_LINK_TRAIN_AUTO;
2721                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722                 temp &= ~FDI_RX_ENABLE;
2723                 I915_WRITE(reg, temp);
2724
2725                 /* enable CPU FDI TX and PCH FDI RX */
2726                 reg = FDI_TX_CTL(pipe);
2727                 temp = I915_READ(reg);
2728                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2729                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2730                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2731                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732                 temp |= snb_b_fdi_train_param[j/2];
2733                 temp |= FDI_COMPOSITE_SYNC;
2734                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2735
2736                 I915_WRITE(FDI_RX_MISC(pipe),
2737                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2738
2739                 reg = FDI_RX_CTL(pipe);
2740                 temp = I915_READ(reg);
2741                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2742                 temp |= FDI_COMPOSITE_SYNC;
2743                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2744
2745                 POSTING_READ(reg);
2746                 udelay(1); /* should be 0.5us */
2747
2748                 for (i = 0; i < 4; i++) {
2749                         reg = FDI_RX_IIR(pipe);
2750                         temp = I915_READ(reg);
2751                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2752
2753                         if (temp & FDI_RX_BIT_LOCK ||
2754                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2755                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2756                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2757                                               i);
2758                                 break;
2759                         }
2760                         udelay(1); /* should be 0.5us */
2761                 }
2762                 if (i == 4) {
2763                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2764                         continue;
2765                 }
2766
2767                 /* Train 2 */
2768                 reg = FDI_TX_CTL(pipe);
2769                 temp = I915_READ(reg);
2770                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2771                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2772                 I915_WRITE(reg, temp);
2773
2774                 reg = FDI_RX_CTL(pipe);
2775                 temp = I915_READ(reg);
2776                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2777                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2778                 I915_WRITE(reg, temp);
2779
2780                 POSTING_READ(reg);
2781                 udelay(2); /* should be 1.5us */
2782
2783                 for (i = 0; i < 4; i++) {
2784                         reg = FDI_RX_IIR(pipe);
2785                         temp = I915_READ(reg);
2786                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2787
2788                         if (temp & FDI_RX_SYMBOL_LOCK ||
2789                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2790                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2791                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2792                                               i);
2793                                 goto train_done;
2794                         }
2795                         udelay(2); /* should be 1.5us */
2796                 }
2797                 if (i == 4)
2798                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2799         }
2800
2801 train_done:
2802         DRM_DEBUG_KMS("FDI train done.\n");
2803 }
2804
2805 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2806 {
2807         struct drm_device *dev = intel_crtc->base.dev;
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809         int pipe = intel_crtc->pipe;
2810         u32 reg, temp;
2811
2812
2813         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2817         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2818         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2819         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821         POSTING_READ(reg);
2822         udelay(200);
2823
2824         /* Switch from Rawclk to PCDclk */
2825         temp = I915_READ(reg);
2826         I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828         POSTING_READ(reg);
2829         udelay(200);
2830
2831         /* Enable CPU FDI TX PLL, always on for Ironlake */
2832         reg = FDI_TX_CTL(pipe);
2833         temp = I915_READ(reg);
2834         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2835                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2836
2837                 POSTING_READ(reg);
2838                 udelay(100);
2839         }
2840 }
2841
2842 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2843 {
2844         struct drm_device *dev = intel_crtc->base.dev;
2845         struct drm_i915_private *dev_priv = dev->dev_private;
2846         int pipe = intel_crtc->pipe;
2847         u32 reg, temp;
2848
2849         /* Switch from PCDclk to Rawclk */
2850         reg = FDI_RX_CTL(pipe);
2851         temp = I915_READ(reg);
2852         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2853
2854         /* Disable CPU FDI TX PLL */
2855         reg = FDI_TX_CTL(pipe);
2856         temp = I915_READ(reg);
2857         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2858
2859         POSTING_READ(reg);
2860         udelay(100);
2861
2862         reg = FDI_RX_CTL(pipe);
2863         temp = I915_READ(reg);
2864         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2865
2866         /* Wait for the clocks to turn off. */
2867         POSTING_READ(reg);
2868         udelay(100);
2869 }
2870
2871 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2872 {
2873         struct drm_device *dev = crtc->dev;
2874         struct drm_i915_private *dev_priv = dev->dev_private;
2875         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2876         int pipe = intel_crtc->pipe;
2877         u32 reg, temp;
2878
2879         /* disable CPU FDI tx and PCH FDI rx */
2880         reg = FDI_TX_CTL(pipe);
2881         temp = I915_READ(reg);
2882         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2883         POSTING_READ(reg);
2884
2885         reg = FDI_RX_CTL(pipe);
2886         temp = I915_READ(reg);
2887         temp &= ~(0x7 << 16);
2888         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2889         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2890
2891         POSTING_READ(reg);
2892         udelay(100);
2893
2894         /* Ironlake workaround, disable clock pointer after downing FDI */
2895         if (HAS_PCH_IBX(dev)) {
2896                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2897         }
2898
2899         /* still set train pattern 1 */
2900         reg = FDI_TX_CTL(pipe);
2901         temp = I915_READ(reg);
2902         temp &= ~FDI_LINK_TRAIN_NONE;
2903         temp |= FDI_LINK_TRAIN_PATTERN_1;
2904         I915_WRITE(reg, temp);
2905
2906         reg = FDI_RX_CTL(pipe);
2907         temp = I915_READ(reg);
2908         if (HAS_PCH_CPT(dev)) {
2909                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2910                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2911         } else {
2912                 temp &= ~FDI_LINK_TRAIN_NONE;
2913                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2914         }
2915         /* BPC in FDI rx is consistent with that in PIPECONF */
2916         temp &= ~(0x07 << 16);
2917         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2918         I915_WRITE(reg, temp);
2919
2920         POSTING_READ(reg);
2921         udelay(100);
2922 }
2923
2924 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2925 {
2926         struct drm_device *dev = crtc->dev;
2927         struct drm_i915_private *dev_priv = dev->dev_private;
2928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2929         unsigned long flags;
2930         bool pending;
2931
2932         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2933             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2934                 return false;
2935
2936         spin_lock_irqsave(&dev->event_lock, flags);
2937         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2938         spin_unlock_irqrestore(&dev->event_lock, flags);
2939
2940         return pending;
2941 }
2942
2943 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2944 {
2945         struct drm_device *dev = crtc->dev;
2946         struct drm_i915_private *dev_priv = dev->dev_private;
2947
2948         if (crtc->fb == NULL)
2949                 return;
2950
2951         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2952
2953         wait_event(dev_priv->pending_flip_queue,
2954                    !intel_crtc_has_pending_flip(crtc));
2955
2956         mutex_lock(&dev->struct_mutex);
2957         intel_finish_fb(crtc->fb);
2958         mutex_unlock(&dev->struct_mutex);
2959 }
2960
2961 /* Program iCLKIP clock to the desired frequency */
2962 static void lpt_program_iclkip(struct drm_crtc *crtc)
2963 {
2964         struct drm_device *dev = crtc->dev;
2965         struct drm_i915_private *dev_priv = dev->dev_private;
2966         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2967         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2968         u32 temp;
2969
2970         mutex_lock(&dev_priv->dpio_lock);
2971
2972         /* It is necessary to ungate the pixclk gate prior to programming
2973          * the divisors, and gate it back when it is done.
2974          */
2975         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2976
2977         /* Disable SSCCTL */
2978         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2979                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2980                                 SBI_SSCCTL_DISABLE,
2981                         SBI_ICLK);
2982
2983         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2984         if (clock == 20000) {
2985                 auxdiv = 1;
2986                 divsel = 0x41;
2987                 phaseinc = 0x20;
2988         } else {
2989                 /* The iCLK virtual clock root frequency is in MHz,
2990                  * but the adjusted_mode->crtc_clock in in KHz. To get the
2991                  * divisors, it is necessary to divide one by another, so we
2992                  * convert the virtual clock precision to KHz here for higher
2993                  * precision.
2994                  */
2995                 u32 iclk_virtual_root_freq = 172800 * 1000;
2996                 u32 iclk_pi_range = 64;
2997                 u32 desired_divisor, msb_divisor_value, pi_value;
2998
2999                 desired_divisor = (iclk_virtual_root_freq / clock);
3000                 msb_divisor_value = desired_divisor / iclk_pi_range;
3001                 pi_value = desired_divisor % iclk_pi_range;
3002
3003                 auxdiv = 0;
3004                 divsel = msb_divisor_value - 2;
3005                 phaseinc = pi_value;
3006         }
3007
3008         /* This should not happen with any sane values */
3009         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3010                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3011         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3012                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3013
3014         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3015                         clock,
3016                         auxdiv,
3017                         divsel,
3018                         phasedir,
3019                         phaseinc);
3020
3021         /* Program SSCDIVINTPHASE6 */
3022         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3023         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3024         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3025         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3026         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3027         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3028         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3029         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3030
3031         /* Program SSCAUXDIV */
3032         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3033         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3034         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3035         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3036
3037         /* Enable modulator and associated divider */
3038         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3039         temp &= ~SBI_SSCCTL_DISABLE;
3040         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3041
3042         /* Wait for initialization time */
3043         udelay(24);
3044
3045         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3046
3047         mutex_unlock(&dev_priv->dpio_lock);
3048 }
3049
3050 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3051                                                 enum pipe pch_transcoder)
3052 {
3053         struct drm_device *dev = crtc->base.dev;
3054         struct drm_i915_private *dev_priv = dev->dev_private;
3055         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3056
3057         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3058                    I915_READ(HTOTAL(cpu_transcoder)));
3059         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3060                    I915_READ(HBLANK(cpu_transcoder)));
3061         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3062                    I915_READ(HSYNC(cpu_transcoder)));
3063
3064         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3065                    I915_READ(VTOTAL(cpu_transcoder)));
3066         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3067                    I915_READ(VBLANK(cpu_transcoder)));
3068         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3069                    I915_READ(VSYNC(cpu_transcoder)));
3070         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3071                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3072 }
3073
3074 /*
3075  * Enable PCH resources required for PCH ports:
3076  *   - PCH PLLs
3077  *   - FDI training & RX/TX
3078  *   - update transcoder timings
3079  *   - DP transcoding bits
3080  *   - transcoder
3081  */
3082 static void ironlake_pch_enable(struct drm_crtc *crtc)
3083 {
3084         struct drm_device *dev = crtc->dev;
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087         int pipe = intel_crtc->pipe;
3088         u32 reg, temp;
3089
3090         assert_pch_transcoder_disabled(dev_priv, pipe);
3091
3092         /* Write the TU size bits before fdi link training, so that error
3093          * detection works. */
3094         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3095                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3096
3097         /* For PCH output, training FDI link */
3098         dev_priv->display.fdi_link_train(crtc);
3099
3100         /* We need to program the right clock selection before writing the pixel
3101          * mutliplier into the DPLL. */
3102         if (HAS_PCH_CPT(dev)) {
3103                 u32 sel;
3104
3105                 temp = I915_READ(PCH_DPLL_SEL);
3106                 temp |= TRANS_DPLL_ENABLE(pipe);
3107                 sel = TRANS_DPLLB_SEL(pipe);
3108                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3109                         temp |= sel;
3110                 else
3111                         temp &= ~sel;
3112                 I915_WRITE(PCH_DPLL_SEL, temp);
3113         }
3114
3115         /* XXX: pch pll's can be enabled any time before we enable the PCH
3116          * transcoder, and we actually should do this to not upset any PCH
3117          * transcoder that already use the clock when we share it.
3118          *
3119          * Note that enable_shared_dpll tries to do the right thing, but
3120          * get_shared_dpll unconditionally resets the pll - we need that to have
3121          * the right LVDS enable sequence. */
3122         ironlake_enable_shared_dpll(intel_crtc);
3123
3124         /* set transcoder timing, panel must allow it */
3125         assert_panel_unlocked(dev_priv, pipe);
3126         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3127
3128         intel_fdi_normal_train(crtc);
3129
3130         /* For PCH DP, enable TRANS_DP_CTL */
3131         if (HAS_PCH_CPT(dev) &&
3132             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3133              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3134                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3135                 reg = TRANS_DP_CTL(pipe);
3136                 temp = I915_READ(reg);
3137                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3138                           TRANS_DP_SYNC_MASK |
3139                           TRANS_DP_BPC_MASK);
3140                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3141                          TRANS_DP_ENH_FRAMING);
3142                 temp |= bpc << 9; /* same format but at 11:9 */
3143
3144                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3145                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3146                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3147                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3148
3149                 switch (intel_trans_dp_port_sel(crtc)) {
3150                 case PCH_DP_B:
3151                         temp |= TRANS_DP_PORT_SEL_B;
3152                         break;
3153                 case PCH_DP_C:
3154                         temp |= TRANS_DP_PORT_SEL_C;
3155                         break;
3156                 case PCH_DP_D:
3157                         temp |= TRANS_DP_PORT_SEL_D;
3158                         break;
3159                 default:
3160                         BUG();
3161                 }
3162
3163                 I915_WRITE(reg, temp);
3164         }
3165
3166         ironlake_enable_pch_transcoder(dev_priv, pipe);
3167 }
3168
3169 static void lpt_pch_enable(struct drm_crtc *crtc)
3170 {
3171         struct drm_device *dev = crtc->dev;
3172         struct drm_i915_private *dev_priv = dev->dev_private;
3173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3174         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3175
3176         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3177
3178         lpt_program_iclkip(crtc);
3179
3180         /* Set transcoder timing. */
3181         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3182
3183         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3184 }
3185
3186 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3187 {
3188         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3189
3190         if (pll == NULL)
3191                 return;
3192
3193         if (pll->refcount == 0) {
3194                 WARN(1, "bad %s refcount\n", pll->name);
3195                 return;
3196         }
3197
3198         if (--pll->refcount == 0) {
3199                 WARN_ON(pll->on);
3200                 WARN_ON(pll->active);
3201         }
3202
3203         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3204 }
3205
3206 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3207 {
3208         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3209         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3210         enum intel_dpll_id i;
3211
3212         if (pll) {
3213                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3214                               crtc->base.base.id, pll->name);
3215                 intel_put_shared_dpll(crtc);
3216         }
3217
3218         if (HAS_PCH_IBX(dev_priv->dev)) {
3219                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3220                 i = (enum intel_dpll_id) crtc->pipe;
3221                 pll = &dev_priv->shared_dplls[i];
3222
3223                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3224                               crtc->base.base.id, pll->name);
3225
3226                 goto found;
3227         }
3228
3229         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3230                 pll = &dev_priv->shared_dplls[i];
3231
3232                 /* Only want to check enabled timings first */
3233                 if (pll->refcount == 0)
3234                         continue;
3235
3236                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3237                            sizeof(pll->hw_state)) == 0) {
3238                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3239                                       crtc->base.base.id,
3240                                       pll->name, pll->refcount, pll->active);
3241
3242                         goto found;
3243                 }
3244         }
3245
3246         /* Ok no matching timings, maybe there's a free one? */
3247         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3248                 pll = &dev_priv->shared_dplls[i];
3249                 if (pll->refcount == 0) {
3250                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3251                                       crtc->base.base.id, pll->name);
3252                         goto found;
3253                 }
3254         }
3255
3256         return NULL;
3257
3258 found:
3259         crtc->config.shared_dpll = i;
3260         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3261                          pipe_name(crtc->pipe));
3262
3263         if (pll->active == 0) {
3264                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3265                        sizeof(pll->hw_state));
3266
3267                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3268                 WARN_ON(pll->on);
3269                 assert_shared_dpll_disabled(dev_priv, pll);
3270
3271                 pll->mode_set(dev_priv, pll);
3272         }
3273         pll->refcount++;
3274
3275         return pll;
3276 }
3277
3278 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3279 {
3280         struct drm_i915_private *dev_priv = dev->dev_private;
3281         int dslreg = PIPEDSL(pipe);
3282         u32 temp;
3283
3284         temp = I915_READ(dslreg);
3285         udelay(500);
3286         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3287                 if (wait_for(I915_READ(dslreg) != temp, 5))
3288                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3289         }
3290 }
3291
3292 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3293 {
3294         struct drm_device *dev = crtc->base.dev;
3295         struct drm_i915_private *dev_priv = dev->dev_private;
3296         int pipe = crtc->pipe;
3297
3298         if (crtc->config.pch_pfit.enabled) {
3299                 /* Force use of hard-coded filter coefficients
3300                  * as some pre-programmed values are broken,
3301                  * e.g. x201.
3302                  */
3303                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3304                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3305                                                  PF_PIPE_SEL_IVB(pipe));
3306                 else
3307                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3308                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3309                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3310         }
3311 }
3312
3313 static void intel_enable_planes(struct drm_crtc *crtc)
3314 {
3315         struct drm_device *dev = crtc->dev;
3316         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3317         struct intel_plane *intel_plane;
3318
3319         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3320                 if (intel_plane->pipe == pipe)
3321                         intel_plane_restore(&intel_plane->base);
3322 }
3323
3324 static void intel_disable_planes(struct drm_crtc *crtc)
3325 {
3326         struct drm_device *dev = crtc->dev;
3327         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3328         struct intel_plane *intel_plane;
3329
3330         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3331                 if (intel_plane->pipe == pipe)
3332                         intel_plane_disable(&intel_plane->base);
3333 }
3334
3335 static void hsw_enable_ips(struct intel_crtc *crtc)
3336 {
3337         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3338
3339         if (!crtc->config.ips_enabled)
3340                 return;
3341
3342         /* We can only enable IPS after we enable a plane and wait for a vblank.
3343          * We guarantee that the plane is enabled by calling intel_enable_ips
3344          * only after intel_enable_plane. And intel_enable_plane already waits
3345          * for a vblank, so all we need to do here is to enable the IPS bit. */
3346         assert_plane_enabled(dev_priv, crtc->plane);
3347         I915_WRITE(IPS_CTL, IPS_ENABLE);
3348 }
3349
3350 static void hsw_disable_ips(struct intel_crtc *crtc)
3351 {
3352         struct drm_device *dev = crtc->base.dev;
3353         struct drm_i915_private *dev_priv = dev->dev_private;
3354
3355         if (!crtc->config.ips_enabled)
3356                 return;
3357
3358         assert_plane_enabled(dev_priv, crtc->plane);
3359         I915_WRITE(IPS_CTL, 0);
3360         POSTING_READ(IPS_CTL);
3361
3362         /* We need to wait for a vblank before we can disable the plane. */
3363         intel_wait_for_vblank(dev, crtc->pipe);
3364 }
3365
3366 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3367 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3368 {
3369         struct drm_device *dev = crtc->dev;
3370         struct drm_i915_private *dev_priv = dev->dev_private;
3371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3372         enum pipe pipe = intel_crtc->pipe;
3373         int palreg = PALETTE(pipe);
3374         int i;
3375         bool reenable_ips = false;
3376
3377         /* The clocks have to be on to load the palette. */
3378         if (!crtc->enabled || !intel_crtc->active)
3379                 return;
3380
3381         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3382                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3383                         assert_dsi_pll_enabled(dev_priv);
3384                 else
3385                         assert_pll_enabled(dev_priv, pipe);
3386         }
3387
3388         /* use legacy palette for Ironlake */
3389         if (HAS_PCH_SPLIT(dev))
3390                 palreg = LGC_PALETTE(pipe);
3391
3392         /* Workaround : Do not read or write the pipe palette/gamma data while
3393          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3394          */
3395         if (intel_crtc->config.ips_enabled &&
3396             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3397              GAMMA_MODE_MODE_SPLIT)) {
3398                 hsw_disable_ips(intel_crtc);
3399                 reenable_ips = true;
3400         }
3401
3402         for (i = 0; i < 256; i++) {
3403                 I915_WRITE(palreg + 4 * i,
3404                            (intel_crtc->lut_r[i] << 16) |
3405                            (intel_crtc->lut_g[i] << 8) |
3406                            intel_crtc->lut_b[i]);
3407         }
3408
3409         if (reenable_ips)
3410                 hsw_enable_ips(intel_crtc);
3411 }
3412
3413 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3414 {
3415         struct drm_device *dev = crtc->dev;
3416         struct drm_i915_private *dev_priv = dev->dev_private;
3417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3418         struct intel_encoder *encoder;
3419         int pipe = intel_crtc->pipe;
3420         int plane = intel_crtc->plane;
3421
3422         WARN_ON(!crtc->enabled);
3423
3424         if (intel_crtc->active)
3425                 return;
3426
3427         intel_crtc->active = true;
3428
3429         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3430         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3431
3432         for_each_encoder_on_crtc(dev, crtc, encoder)
3433                 if (encoder->pre_enable)
3434                         encoder->pre_enable(encoder);
3435
3436         if (intel_crtc->config.has_pch_encoder) {
3437                 /* Note: FDI PLL enabling _must_ be done before we enable the
3438                  * cpu pipes, hence this is separate from all the other fdi/pch
3439                  * enabling. */
3440                 ironlake_fdi_pll_enable(intel_crtc);
3441         } else {
3442                 assert_fdi_tx_disabled(dev_priv, pipe);
3443                 assert_fdi_rx_disabled(dev_priv, pipe);
3444         }
3445
3446         ironlake_pfit_enable(intel_crtc);
3447
3448         /*
3449          * On ILK+ LUT must be loaded before the pipe is running but with
3450          * clocks enabled
3451          */
3452         intel_crtc_load_lut(crtc);
3453
3454         intel_update_watermarks(crtc);
3455         intel_enable_pipe(dev_priv, pipe,
3456                           intel_crtc->config.has_pch_encoder, false);
3457         intel_enable_plane(dev_priv, plane, pipe);
3458         intel_enable_planes(crtc);
3459         intel_crtc_update_cursor(crtc, true);
3460
3461         if (intel_crtc->config.has_pch_encoder)
3462                 ironlake_pch_enable(crtc);
3463
3464         mutex_lock(&dev->struct_mutex);
3465         intel_update_fbc(dev);
3466         mutex_unlock(&dev->struct_mutex);
3467
3468         for_each_encoder_on_crtc(dev, crtc, encoder)
3469                 encoder->enable(encoder);
3470
3471         if (HAS_PCH_CPT(dev))
3472                 cpt_verify_modeset(dev, intel_crtc->pipe);
3473
3474         /*
3475          * There seems to be a race in PCH platform hw (at least on some
3476          * outputs) where an enabled pipe still completes any pageflip right
3477          * away (as if the pipe is off) instead of waiting for vblank. As soon
3478          * as the first vblank happend, everything works as expected. Hence just
3479          * wait for one vblank before returning to avoid strange things
3480          * happening.
3481          */
3482         intel_wait_for_vblank(dev, intel_crtc->pipe);
3483 }
3484
3485 /* IPS only exists on ULT machines and is tied to pipe A. */
3486 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3487 {
3488         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3489 }
3490
3491 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3492 {
3493         struct drm_device *dev = crtc->dev;
3494         struct drm_i915_private *dev_priv = dev->dev_private;
3495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3496         int pipe = intel_crtc->pipe;
3497         int plane = intel_crtc->plane;
3498
3499         intel_enable_plane(dev_priv, plane, pipe);
3500         intel_enable_planes(crtc);
3501         intel_crtc_update_cursor(crtc, true);
3502
3503         hsw_enable_ips(intel_crtc);
3504
3505         mutex_lock(&dev->struct_mutex);
3506         intel_update_fbc(dev);
3507         mutex_unlock(&dev->struct_mutex);
3508 }
3509
3510 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3511 {
3512         struct drm_device *dev = crtc->dev;
3513         struct drm_i915_private *dev_priv = dev->dev_private;
3514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3515         int pipe = intel_crtc->pipe;
3516         int plane = intel_crtc->plane;
3517
3518         intel_crtc_wait_for_pending_flips(crtc);
3519         drm_vblank_off(dev, pipe);
3520
3521         /* FBC must be disabled before disabling the plane on HSW. */
3522         if (dev_priv->fbc.plane == plane)
3523                 intel_disable_fbc(dev);
3524
3525         hsw_disable_ips(intel_crtc);
3526
3527         intel_crtc_update_cursor(crtc, false);
3528         intel_disable_planes(crtc);
3529         intel_disable_plane(dev_priv, plane, pipe);
3530 }
3531
3532 /*
3533  * This implements the workaround described in the "notes" section of the mode
3534  * set sequence documentation. When going from no pipes or single pipe to
3535  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3536  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3537  */
3538 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3539 {
3540         struct drm_device *dev = crtc->base.dev;
3541         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3542
3543         /* We want to get the other_active_crtc only if there's only 1 other
3544          * active crtc. */
3545         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3546                 if (!crtc_it->active || crtc_it == crtc)
3547                         continue;
3548
3549                 if (other_active_crtc)
3550                         return;
3551
3552                 other_active_crtc = crtc_it;
3553         }
3554         if (!other_active_crtc)
3555                 return;
3556
3557         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3558         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3559 }
3560
3561 static void haswell_crtc_enable(struct drm_crtc *crtc)
3562 {
3563         struct drm_device *dev = crtc->dev;
3564         struct drm_i915_private *dev_priv = dev->dev_private;
3565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3566         struct intel_encoder *encoder;
3567         int pipe = intel_crtc->pipe;
3568
3569         WARN_ON(!crtc->enabled);
3570
3571         if (intel_crtc->active)
3572                 return;
3573
3574         intel_crtc->active = true;
3575
3576         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3577         if (intel_crtc->config.has_pch_encoder)
3578                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3579
3580         if (intel_crtc->config.has_pch_encoder)
3581                 dev_priv->display.fdi_link_train(crtc);
3582
3583         for_each_encoder_on_crtc(dev, crtc, encoder)
3584                 if (encoder->pre_enable)
3585                         encoder->pre_enable(encoder);
3586
3587         intel_ddi_enable_pipe_clock(intel_crtc);
3588
3589         ironlake_pfit_enable(intel_crtc);
3590
3591         /*
3592          * On ILK+ LUT must be loaded before the pipe is running but with
3593          * clocks enabled
3594          */
3595         intel_crtc_load_lut(crtc);
3596
3597         intel_ddi_set_pipe_settings(crtc);
3598         intel_ddi_enable_transcoder_func(crtc);
3599
3600         intel_update_watermarks(crtc);
3601         intel_enable_pipe(dev_priv, pipe,
3602                           intel_crtc->config.has_pch_encoder, false);
3603
3604         if (intel_crtc->config.has_pch_encoder)
3605                 lpt_pch_enable(crtc);
3606
3607         for_each_encoder_on_crtc(dev, crtc, encoder) {
3608                 encoder->enable(encoder);
3609                 intel_opregion_notify_encoder(encoder, true);
3610         }
3611
3612         /* If we change the relative order between pipe/planes enabling, we need
3613          * to change the workaround. */
3614         haswell_mode_set_planes_workaround(intel_crtc);
3615         haswell_crtc_enable_planes(crtc);
3616
3617         /*
3618          * There seems to be a race in PCH platform hw (at least on some
3619          * outputs) where an enabled pipe still completes any pageflip right
3620          * away (as if the pipe is off) instead of waiting for vblank. As soon
3621          * as the first vblank happend, everything works as expected. Hence just
3622          * wait for one vblank before returning to avoid strange things
3623          * happening.
3624          */
3625         intel_wait_for_vblank(dev, intel_crtc->pipe);
3626 }
3627
3628 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3629 {
3630         struct drm_device *dev = crtc->base.dev;
3631         struct drm_i915_private *dev_priv = dev->dev_private;
3632         int pipe = crtc->pipe;
3633
3634         /* To avoid upsetting the power well on haswell only disable the pfit if
3635          * it's in use. The hw state code will make sure we get this right. */
3636         if (crtc->config.pch_pfit.enabled) {
3637                 I915_WRITE(PF_CTL(pipe), 0);
3638                 I915_WRITE(PF_WIN_POS(pipe), 0);
3639                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3640         }
3641 }
3642
3643 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3644 {
3645         struct drm_device *dev = crtc->dev;
3646         struct drm_i915_private *dev_priv = dev->dev_private;
3647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3648         struct intel_encoder *encoder;
3649         int pipe = intel_crtc->pipe;
3650         int plane = intel_crtc->plane;
3651         u32 reg, temp;
3652
3653
3654         if (!intel_crtc->active)
3655                 return;
3656
3657         for_each_encoder_on_crtc(dev, crtc, encoder)
3658                 encoder->disable(encoder);
3659
3660         intel_crtc_wait_for_pending_flips(crtc);
3661         drm_vblank_off(dev, pipe);
3662
3663         if (dev_priv->fbc.plane == plane)
3664                 intel_disable_fbc(dev);
3665
3666         intel_crtc_update_cursor(crtc, false);
3667         intel_disable_planes(crtc);
3668         intel_disable_plane(dev_priv, plane, pipe);
3669
3670         if (intel_crtc->config.has_pch_encoder)
3671                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3672
3673         intel_disable_pipe(dev_priv, pipe);
3674
3675         ironlake_pfit_disable(intel_crtc);
3676
3677         for_each_encoder_on_crtc(dev, crtc, encoder)
3678                 if (encoder->post_disable)
3679                         encoder->post_disable(encoder);
3680
3681         if (intel_crtc->config.has_pch_encoder) {
3682                 ironlake_fdi_disable(crtc);
3683
3684                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3685                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3686
3687                 if (HAS_PCH_CPT(dev)) {
3688                         /* disable TRANS_DP_CTL */
3689                         reg = TRANS_DP_CTL(pipe);
3690                         temp = I915_READ(reg);
3691                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3692                                   TRANS_DP_PORT_SEL_MASK);
3693                         temp |= TRANS_DP_PORT_SEL_NONE;
3694                         I915_WRITE(reg, temp);
3695
3696                         /* disable DPLL_SEL */
3697                         temp = I915_READ(PCH_DPLL_SEL);
3698                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3699                         I915_WRITE(PCH_DPLL_SEL, temp);
3700                 }
3701
3702                 /* disable PCH DPLL */
3703                 intel_disable_shared_dpll(intel_crtc);
3704
3705                 ironlake_fdi_pll_disable(intel_crtc);
3706         }
3707
3708         intel_crtc->active = false;
3709         intel_update_watermarks(crtc);
3710
3711         mutex_lock(&dev->struct_mutex);
3712         intel_update_fbc(dev);
3713         mutex_unlock(&dev->struct_mutex);
3714 }
3715
3716 static void haswell_crtc_disable(struct drm_crtc *crtc)
3717 {
3718         struct drm_device *dev = crtc->dev;
3719         struct drm_i915_private *dev_priv = dev->dev_private;
3720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3721         struct intel_encoder *encoder;
3722         int pipe = intel_crtc->pipe;
3723         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3724
3725         if (!intel_crtc->active)
3726                 return;
3727
3728         haswell_crtc_disable_planes(crtc);
3729
3730         for_each_encoder_on_crtc(dev, crtc, encoder) {
3731                 intel_opregion_notify_encoder(encoder, false);
3732                 encoder->disable(encoder);
3733         }
3734
3735         if (intel_crtc->config.has_pch_encoder)
3736                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3737         intel_disable_pipe(dev_priv, pipe);
3738
3739         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3740
3741         ironlake_pfit_disable(intel_crtc);
3742
3743         intel_ddi_disable_pipe_clock(intel_crtc);
3744
3745         for_each_encoder_on_crtc(dev, crtc, encoder)
3746                 if (encoder->post_disable)
3747                         encoder->post_disable(encoder);
3748
3749         if (intel_crtc->config.has_pch_encoder) {
3750                 lpt_disable_pch_transcoder(dev_priv);
3751                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3752                 intel_ddi_fdi_disable(crtc);
3753         }
3754
3755         intel_crtc->active = false;
3756         intel_update_watermarks(crtc);
3757
3758         mutex_lock(&dev->struct_mutex);
3759         intel_update_fbc(dev);
3760         mutex_unlock(&dev->struct_mutex);
3761 }
3762
3763 static void ironlake_crtc_off(struct drm_crtc *crtc)
3764 {
3765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3766         intel_put_shared_dpll(intel_crtc);
3767 }
3768
3769 static void haswell_crtc_off(struct drm_crtc *crtc)
3770 {
3771         intel_ddi_put_crtc_pll(crtc);
3772 }
3773
3774 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3775 {
3776         if (!enable && intel_crtc->overlay) {
3777                 struct drm_device *dev = intel_crtc->base.dev;
3778                 struct drm_i915_private *dev_priv = dev->dev_private;
3779
3780                 mutex_lock(&dev->struct_mutex);
3781                 dev_priv->mm.interruptible = false;
3782                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3783                 dev_priv->mm.interruptible = true;
3784                 mutex_unlock(&dev->struct_mutex);
3785         }
3786
3787         /* Let userspace switch the overlay on again. In most cases userspace
3788          * has to recompute where to put it anyway.
3789          */
3790 }
3791
3792 /**
3793  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3794  * cursor plane briefly if not already running after enabling the display
3795  * plane.
3796  * This workaround avoids occasional blank screens when self refresh is
3797  * enabled.
3798  */
3799 static void
3800 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3801 {
3802         u32 cntl = I915_READ(CURCNTR(pipe));
3803
3804         if ((cntl & CURSOR_MODE) == 0) {
3805                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3806
3807                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3808                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3809                 intel_wait_for_vblank(dev_priv->dev, pipe);
3810                 I915_WRITE(CURCNTR(pipe), cntl);
3811                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3812                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3813         }
3814 }
3815
3816 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3817 {
3818         struct drm_device *dev = crtc->base.dev;
3819         struct drm_i915_private *dev_priv = dev->dev_private;
3820         struct intel_crtc_config *pipe_config = &crtc->config;
3821
3822         if (!crtc->config.gmch_pfit.control)
3823                 return;
3824
3825         /*
3826          * The panel fitter should only be adjusted whilst the pipe is disabled,
3827          * according to register description and PRM.
3828          */
3829         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3830         assert_pipe_disabled(dev_priv, crtc->pipe);
3831
3832         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3833         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3834
3835         /* Border color in case we don't scale up to the full screen. Black by
3836          * default, change to something else for debugging. */
3837         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3838 }
3839
3840 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3841 {
3842         struct drm_device *dev = crtc->dev;
3843         struct drm_i915_private *dev_priv = dev->dev_private;
3844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3845         struct intel_encoder *encoder;
3846         int pipe = intel_crtc->pipe;
3847         int plane = intel_crtc->plane;
3848         bool is_dsi;
3849
3850         WARN_ON(!crtc->enabled);
3851
3852         if (intel_crtc->active)
3853                 return;
3854
3855         intel_crtc->active = true;
3856
3857         for_each_encoder_on_crtc(dev, crtc, encoder)
3858                 if (encoder->pre_pll_enable)
3859                         encoder->pre_pll_enable(encoder);
3860
3861         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3862
3863         if (!is_dsi)
3864                 vlv_enable_pll(intel_crtc);
3865
3866         for_each_encoder_on_crtc(dev, crtc, encoder)
3867                 if (encoder->pre_enable)
3868                         encoder->pre_enable(encoder);
3869
3870         i9xx_pfit_enable(intel_crtc);
3871
3872         intel_crtc_load_lut(crtc);
3873
3874         intel_update_watermarks(crtc);
3875         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3876         intel_enable_plane(dev_priv, plane, pipe);
3877         intel_enable_planes(crtc);
3878         intel_crtc_update_cursor(crtc, true);
3879
3880         intel_update_fbc(dev);
3881
3882         for_each_encoder_on_crtc(dev, crtc, encoder)
3883                 encoder->enable(encoder);
3884 }
3885
3886 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3887 {
3888         struct drm_device *dev = crtc->dev;
3889         struct drm_i915_private *dev_priv = dev->dev_private;
3890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3891         struct intel_encoder *encoder;
3892         int pipe = intel_crtc->pipe;
3893         int plane = intel_crtc->plane;
3894
3895         WARN_ON(!crtc->enabled);
3896
3897         if (intel_crtc->active)
3898                 return;
3899
3900         intel_crtc->active = true;
3901
3902         for_each_encoder_on_crtc(dev, crtc, encoder)
3903                 if (encoder->pre_enable)
3904                         encoder->pre_enable(encoder);
3905
3906         i9xx_enable_pll(intel_crtc);
3907
3908         i9xx_pfit_enable(intel_crtc);
3909
3910         intel_crtc_load_lut(crtc);
3911
3912         intel_update_watermarks(crtc);
3913         intel_enable_pipe(dev_priv, pipe, false, false);
3914         intel_enable_plane(dev_priv, plane, pipe);
3915         intel_enable_planes(crtc);
3916         /* The fixup needs to happen before cursor is enabled */
3917         if (IS_G4X(dev))
3918                 g4x_fixup_plane(dev_priv, pipe);
3919         intel_crtc_update_cursor(crtc, true);
3920
3921         /* Give the overlay scaler a chance to enable if it's on this pipe */
3922         intel_crtc_dpms_overlay(intel_crtc, true);
3923
3924         intel_update_fbc(dev);
3925
3926         for_each_encoder_on_crtc(dev, crtc, encoder)
3927                 encoder->enable(encoder);
3928 }
3929
3930 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3931 {
3932         struct drm_device *dev = crtc->base.dev;
3933         struct drm_i915_private *dev_priv = dev->dev_private;
3934
3935         if (!crtc->config.gmch_pfit.control)
3936                 return;
3937
3938         assert_pipe_disabled(dev_priv, crtc->pipe);
3939
3940         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3941                          I915_READ(PFIT_CONTROL));
3942         I915_WRITE(PFIT_CONTROL, 0);
3943 }
3944
3945 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3946 {
3947         struct drm_device *dev = crtc->dev;
3948         struct drm_i915_private *dev_priv = dev->dev_private;
3949         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3950         struct intel_encoder *encoder;
3951         int pipe = intel_crtc->pipe;
3952         int plane = intel_crtc->plane;
3953
3954         if (!intel_crtc->active)
3955                 return;
3956
3957         for_each_encoder_on_crtc(dev, crtc, encoder)
3958                 encoder->disable(encoder);
3959
3960         /* Give the overlay scaler a chance to disable if it's on this pipe */
3961         intel_crtc_wait_for_pending_flips(crtc);
3962         drm_vblank_off(dev, pipe);
3963
3964         if (dev_priv->fbc.plane == plane)
3965                 intel_disable_fbc(dev);
3966
3967         intel_crtc_dpms_overlay(intel_crtc, false);
3968         intel_crtc_update_cursor(crtc, false);
3969         intel_disable_planes(crtc);
3970         intel_disable_plane(dev_priv, plane, pipe);
3971
3972         intel_disable_pipe(dev_priv, pipe);
3973
3974         i9xx_pfit_disable(intel_crtc);
3975
3976         for_each_encoder_on_crtc(dev, crtc, encoder)
3977                 if (encoder->post_disable)
3978                         encoder->post_disable(encoder);
3979
3980         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3981                 vlv_disable_pll(dev_priv, pipe);
3982         else if (!IS_VALLEYVIEW(dev))
3983                 i9xx_disable_pll(dev_priv, pipe);
3984
3985         intel_crtc->active = false;
3986         intel_update_watermarks(crtc);
3987
3988         intel_update_fbc(dev);
3989 }
3990
3991 static void i9xx_crtc_off(struct drm_crtc *crtc)
3992 {
3993 }
3994
3995 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3996                                     bool enabled)
3997 {
3998         struct drm_device *dev = crtc->dev;
3999         struct drm_i915_master_private *master_priv;
4000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4001         int pipe = intel_crtc->pipe;
4002
4003         if (!dev->primary->master)
4004                 return;
4005
4006         master_priv = dev->primary->master->driver_priv;
4007         if (!master_priv->sarea_priv)
4008                 return;
4009
4010         switch (pipe) {
4011         case 0:
4012                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4013                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4014                 break;
4015         case 1:
4016                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4017                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4018                 break;
4019         default:
4020                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4021                 break;
4022         }
4023 }
4024
4025 /**
4026  * Sets the power management mode of the pipe and plane.
4027  */
4028 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4029 {
4030         struct drm_device *dev = crtc->dev;
4031         struct drm_i915_private *dev_priv = dev->dev_private;
4032         struct intel_encoder *intel_encoder;
4033         bool enable = false;
4034
4035         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4036                 enable |= intel_encoder->connectors_active;
4037
4038         if (enable)
4039                 dev_priv->display.crtc_enable(crtc);
4040         else
4041                 dev_priv->display.crtc_disable(crtc);
4042
4043         intel_crtc_update_sarea(crtc, enable);
4044 }
4045
4046 static void intel_crtc_disable(struct drm_crtc *crtc)
4047 {
4048         struct drm_device *dev = crtc->dev;
4049         struct drm_connector *connector;
4050         struct drm_i915_private *dev_priv = dev->dev_private;
4051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4052
4053         /* crtc should still be enabled when we disable it. */
4054         WARN_ON(!crtc->enabled);
4055
4056         dev_priv->display.crtc_disable(crtc);
4057         intel_crtc->eld_vld = false;
4058         intel_crtc_update_sarea(crtc, false);
4059         dev_priv->display.off(crtc);
4060
4061         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4062         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4063         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4064
4065         if (crtc->fb) {
4066                 mutex_lock(&dev->struct_mutex);
4067                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4068                 mutex_unlock(&dev->struct_mutex);
4069                 crtc->fb = NULL;
4070         }
4071
4072         /* Update computed state. */
4073         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4074                 if (!connector->encoder || !connector->encoder->crtc)
4075                         continue;
4076
4077                 if (connector->encoder->crtc != crtc)
4078                         continue;
4079
4080                 connector->dpms = DRM_MODE_DPMS_OFF;
4081                 to_intel_encoder(connector->encoder)->connectors_active = false;
4082         }
4083 }
4084
4085 void intel_encoder_destroy(struct drm_encoder *encoder)
4086 {
4087         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4088
4089         drm_encoder_cleanup(encoder);
4090         kfree(intel_encoder);
4091 }
4092
4093 /* Simple dpms helper for encoders with just one connector, no cloning and only
4094  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4095  * state of the entire output pipe. */
4096 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4097 {
4098         if (mode == DRM_MODE_DPMS_ON) {
4099                 encoder->connectors_active = true;
4100
4101                 intel_crtc_update_dpms(encoder->base.crtc);
4102         } else {
4103                 encoder->connectors_active = false;
4104
4105                 intel_crtc_update_dpms(encoder->base.crtc);
4106         }
4107 }
4108
4109 /* Cross check the actual hw state with our own modeset state tracking (and it's
4110  * internal consistency). */
4111 static void intel_connector_check_state(struct intel_connector *connector)
4112 {
4113         if (connector->get_hw_state(connector)) {
4114                 struct intel_encoder *encoder = connector->encoder;
4115                 struct drm_crtc *crtc;
4116                 bool encoder_enabled;
4117                 enum pipe pipe;
4118
4119                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4120                               connector->base.base.id,
4121                               drm_get_connector_name(&connector->base));
4122
4123                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4124                      "wrong connector dpms state\n");
4125                 WARN(connector->base.encoder != &encoder->base,
4126                      "active connector not linked to encoder\n");
4127                 WARN(!encoder->connectors_active,
4128                      "encoder->connectors_active not set\n");
4129
4130                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4131                 WARN(!encoder_enabled, "encoder not enabled\n");
4132                 if (WARN_ON(!encoder->base.crtc))
4133                         return;
4134
4135                 crtc = encoder->base.crtc;
4136
4137                 WARN(!crtc->enabled, "crtc not enabled\n");
4138                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4139                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4140                      "encoder active on the wrong pipe\n");
4141         }
4142 }
4143
4144 /* Even simpler default implementation, if there's really no special case to
4145  * consider. */
4146 void intel_connector_dpms(struct drm_connector *connector, int mode)
4147 {
4148         /* All the simple cases only support two dpms states. */
4149         if (mode != DRM_MODE_DPMS_ON)
4150                 mode = DRM_MODE_DPMS_OFF;
4151
4152         if (mode == connector->dpms)
4153                 return;
4154
4155         connector->dpms = mode;
4156
4157         /* Only need to change hw state when actually enabled */
4158         if (connector->encoder)
4159                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4160
4161         intel_modeset_check_state(connector->dev);
4162 }
4163
4164 /* Simple connector->get_hw_state implementation for encoders that support only
4165  * one connector and no cloning and hence the encoder state determines the state
4166  * of the connector. */
4167 bool intel_connector_get_hw_state(struct intel_connector *connector)
4168 {
4169         enum pipe pipe = 0;
4170         struct intel_encoder *encoder = connector->encoder;
4171
4172         return encoder->get_hw_state(encoder, &pipe);
4173 }
4174
4175 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4176                                      struct intel_crtc_config *pipe_config)
4177 {
4178         struct drm_i915_private *dev_priv = dev->dev_private;
4179         struct intel_crtc *pipe_B_crtc =
4180                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4181
4182         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4183                       pipe_name(pipe), pipe_config->fdi_lanes);
4184         if (pipe_config->fdi_lanes > 4) {
4185                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4186                               pipe_name(pipe), pipe_config->fdi_lanes);
4187                 return false;
4188         }
4189
4190         if (IS_HASWELL(dev)) {
4191                 if (pipe_config->fdi_lanes > 2) {
4192                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4193                                       pipe_config->fdi_lanes);
4194                         return false;
4195                 } else {
4196                         return true;
4197                 }
4198         }
4199
4200         if (INTEL_INFO(dev)->num_pipes == 2)
4201                 return true;
4202
4203         /* Ivybridge 3 pipe is really complicated */
4204         switch (pipe) {
4205         case PIPE_A:
4206                 return true;
4207         case PIPE_B:
4208                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4209                     pipe_config->fdi_lanes > 2) {
4210                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4211                                       pipe_name(pipe), pipe_config->fdi_lanes);
4212                         return false;
4213                 }
4214                 return true;
4215         case PIPE_C:
4216                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4217                     pipe_B_crtc->config.fdi_lanes <= 2) {
4218                         if (pipe_config->fdi_lanes > 2) {
4219                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4220                                               pipe_name(pipe), pipe_config->fdi_lanes);
4221                                 return false;
4222                         }
4223                 } else {
4224                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4225                         return false;
4226                 }
4227                 return true;
4228         default:
4229                 BUG();
4230         }
4231 }
4232
4233 #define RETRY 1
4234 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4235                                        struct intel_crtc_config *pipe_config)
4236 {
4237         struct drm_device *dev = intel_crtc->base.dev;
4238         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4239         int lane, link_bw, fdi_dotclock;
4240         bool setup_ok, needs_recompute = false;
4241
4242 retry:
4243         /* FDI is a binary signal running at ~2.7GHz, encoding
4244          * each output octet as 10 bits. The actual frequency
4245          * is stored as a divider into a 100MHz clock, and the
4246          * mode pixel clock is stored in units of 1KHz.
4247          * Hence the bw of each lane in terms of the mode signal
4248          * is:
4249          */
4250         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4251
4252         fdi_dotclock = adjusted_mode->crtc_clock;
4253
4254         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4255                                            pipe_config->pipe_bpp);
4256
4257         pipe_config->fdi_lanes = lane;
4258
4259         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4260                                link_bw, &pipe_config->fdi_m_n);
4261
4262         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4263                                             intel_crtc->pipe, pipe_config);
4264         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4265                 pipe_config->pipe_bpp -= 2*3;
4266                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4267                               pipe_config->pipe_bpp);
4268                 needs_recompute = true;
4269                 pipe_config->bw_constrained = true;
4270
4271                 goto retry;
4272         }
4273
4274         if (needs_recompute)
4275                 return RETRY;
4276
4277         return setup_ok ? 0 : -EINVAL;
4278 }
4279
4280 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4281                                    struct intel_crtc_config *pipe_config)
4282 {
4283         pipe_config->ips_enabled = i915_enable_ips &&
4284                                    hsw_crtc_supports_ips(crtc) &&
4285                                    pipe_config->pipe_bpp <= 24;
4286 }
4287
4288 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4289                                      struct intel_crtc_config *pipe_config)
4290 {
4291         struct drm_device *dev = crtc->base.dev;
4292         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4293
4294         /* FIXME should check pixel clock limits on all platforms */
4295         if (INTEL_INFO(dev)->gen < 4) {
4296                 struct drm_i915_private *dev_priv = dev->dev_private;
4297                 int clock_limit =
4298                         dev_priv->display.get_display_clock_speed(dev);
4299
4300                 /*
4301                  * Enable pixel doubling when the dot clock
4302                  * is > 90% of the (display) core speed.
4303                  *
4304                  * GDG double wide on either pipe,
4305                  * otherwise pipe A only.
4306                  */
4307                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4308                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4309                         clock_limit *= 2;
4310                         pipe_config->double_wide = true;
4311                 }
4312
4313                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4314                         return -EINVAL;
4315         }
4316
4317         /*
4318          * Pipe horizontal size must be even in:
4319          * - DVO ganged mode
4320          * - LVDS dual channel mode
4321          * - Double wide pipe
4322          */
4323         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4324              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4325                 pipe_config->pipe_src_w &= ~1;
4326
4327         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4328          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4329          */
4330         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4331                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4332                 return -EINVAL;
4333
4334         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4335                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4336         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4337                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4338                  * for lvds. */
4339                 pipe_config->pipe_bpp = 8*3;
4340         }
4341
4342         if (HAS_IPS(dev))
4343                 hsw_compute_ips_config(crtc, pipe_config);
4344
4345         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4346          * clock survives for now. */
4347         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4348                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4349
4350         if (pipe_config->has_pch_encoder)
4351                 return ironlake_fdi_compute_config(crtc, pipe_config);
4352
4353         return 0;
4354 }
4355
4356 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4357 {
4358         return 400000; /* FIXME */
4359 }
4360
4361 static int i945_get_display_clock_speed(struct drm_device *dev)
4362 {
4363         return 400000;
4364 }
4365
4366 static int i915_get_display_clock_speed(struct drm_device *dev)
4367 {
4368         return 333000;
4369 }
4370
4371 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4372 {
4373         return 200000;
4374 }
4375
4376 static int pnv_get_display_clock_speed(struct drm_device *dev)
4377 {
4378         u16 gcfgc = 0;
4379
4380         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4381
4382         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4383         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4384                 return 267000;
4385         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4386                 return 333000;
4387         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4388                 return 444000;
4389         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4390                 return 200000;
4391         default:
4392                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4393         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4394                 return 133000;
4395         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4396                 return 167000;
4397         }
4398 }
4399
4400 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4401 {
4402         u16 gcfgc = 0;
4403
4404         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4405
4406         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4407                 return 133000;
4408         else {
4409                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4410                 case GC_DISPLAY_CLOCK_333_MHZ:
4411                         return 333000;
4412                 default:
4413                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4414                         return 190000;
4415                 }
4416         }
4417 }
4418
4419 static int i865_get_display_clock_speed(struct drm_device *dev)
4420 {
4421         return 266000;
4422 }
4423
4424 static int i855_get_display_clock_speed(struct drm_device *dev)
4425 {
4426         u16 hpllcc = 0;
4427         /* Assume that the hardware is in the high speed state.  This
4428          * should be the default.
4429          */
4430         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4431         case GC_CLOCK_133_200:
4432         case GC_CLOCK_100_200:
4433                 return 200000;
4434         case GC_CLOCK_166_250:
4435                 return 250000;
4436         case GC_CLOCK_100_133:
4437                 return 133000;
4438         }
4439
4440         /* Shouldn't happen */
4441         return 0;
4442 }
4443
4444 static int i830_get_display_clock_speed(struct drm_device *dev)
4445 {
4446         return 133000;
4447 }
4448
4449 static void
4450 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4451 {
4452         while (*num > DATA_LINK_M_N_MASK ||
4453                *den > DATA_LINK_M_N_MASK) {
4454                 *num >>= 1;
4455                 *den >>= 1;
4456         }
4457 }
4458
4459 static void compute_m_n(unsigned int m, unsigned int n,
4460                         uint32_t *ret_m, uint32_t *ret_n)
4461 {
4462         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4463         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4464         intel_reduce_m_n_ratio(ret_m, ret_n);
4465 }
4466
4467 void
4468 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4469                        int pixel_clock, int link_clock,
4470                        struct intel_link_m_n *m_n)
4471 {
4472         m_n->tu = 64;
4473
4474         compute_m_n(bits_per_pixel * pixel_clock,
4475                     link_clock * nlanes * 8,
4476                     &m_n->gmch_m, &m_n->gmch_n);
4477
4478         compute_m_n(pixel_clock, link_clock,
4479                     &m_n->link_m, &m_n->link_n);
4480 }
4481
4482 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4483 {
4484         if (i915_panel_use_ssc >= 0)
4485                 return i915_panel_use_ssc != 0;
4486         return dev_priv->vbt.lvds_use_ssc
4487                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4488 }
4489
4490 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4491 {
4492         struct drm_device *dev = crtc->dev;
4493         struct drm_i915_private *dev_priv = dev->dev_private;
4494         int refclk;
4495
4496         if (IS_VALLEYVIEW(dev)) {
4497                 refclk = 100000;
4498         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4499             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4500                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4501                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4502                               refclk / 1000);
4503         } else if (!IS_GEN2(dev)) {
4504                 refclk = 96000;
4505         } else {
4506                 refclk = 48000;
4507         }
4508
4509         return refclk;
4510 }
4511
4512 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4513 {
4514         return (1 << dpll->n) << 16 | dpll->m2;
4515 }
4516
4517 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4518 {
4519         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4520 }
4521
4522 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4523                                      intel_clock_t *reduced_clock)
4524 {
4525         struct drm_device *dev = crtc->base.dev;
4526         struct drm_i915_private *dev_priv = dev->dev_private;
4527         int pipe = crtc->pipe;
4528         u32 fp, fp2 = 0;
4529
4530         if (IS_PINEVIEW(dev)) {
4531                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4532                 if (reduced_clock)
4533                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4534         } else {
4535                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4536                 if (reduced_clock)
4537                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4538         }
4539
4540         I915_WRITE(FP0(pipe), fp);
4541         crtc->config.dpll_hw_state.fp0 = fp;
4542
4543         crtc->lowfreq_avail = false;
4544         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4545             reduced_clock && i915_powersave) {
4546                 I915_WRITE(FP1(pipe), fp2);
4547                 crtc->config.dpll_hw_state.fp1 = fp2;
4548                 crtc->lowfreq_avail = true;
4549         } else {
4550                 I915_WRITE(FP1(pipe), fp);
4551                 crtc->config.dpll_hw_state.fp1 = fp;
4552         }
4553 }
4554
4555 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4556                 pipe)
4557 {
4558         u32 reg_val;
4559
4560         /*
4561          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4562          * and set it to a reasonable value instead.
4563          */
4564         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4565         reg_val &= 0xffffff00;
4566         reg_val |= 0x00000030;
4567         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4568
4569         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4570         reg_val &= 0x8cffffff;
4571         reg_val = 0x8c000000;
4572         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4573
4574         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4575         reg_val &= 0xffffff00;
4576         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4577
4578         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4579         reg_val &= 0x00ffffff;
4580         reg_val |= 0xb0000000;
4581         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4582 }
4583
4584 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4585                                          struct intel_link_m_n *m_n)
4586 {
4587         struct drm_device *dev = crtc->base.dev;
4588         struct drm_i915_private *dev_priv = dev->dev_private;
4589         int pipe = crtc->pipe;
4590
4591         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4592         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4593         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4594         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4595 }
4596
4597 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4598                                          struct intel_link_m_n *m_n)
4599 {
4600         struct drm_device *dev = crtc->base.dev;
4601         struct drm_i915_private *dev_priv = dev->dev_private;
4602         int pipe = crtc->pipe;
4603         enum transcoder transcoder = crtc->config.cpu_transcoder;
4604
4605         if (INTEL_INFO(dev)->gen >= 5) {
4606                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4607                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4608                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4609                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4610         } else {
4611                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4612                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4613                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4614                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4615         }
4616 }
4617
4618 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4619 {
4620         if (crtc->config.has_pch_encoder)
4621                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4622         else
4623                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4624 }
4625
4626 static void vlv_update_pll(struct intel_crtc *crtc)
4627 {
4628         struct drm_device *dev = crtc->base.dev;
4629         struct drm_i915_private *dev_priv = dev->dev_private;
4630         int pipe = crtc->pipe;
4631         u32 dpll, mdiv;
4632         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4633         u32 coreclk, reg_val, dpll_md;
4634
4635         mutex_lock(&dev_priv->dpio_lock);
4636
4637         bestn = crtc->config.dpll.n;
4638         bestm1 = crtc->config.dpll.m1;
4639         bestm2 = crtc->config.dpll.m2;
4640         bestp1 = crtc->config.dpll.p1;
4641         bestp2 = crtc->config.dpll.p2;
4642
4643         /* See eDP HDMI DPIO driver vbios notes doc */
4644
4645         /* PLL B needs special handling */
4646         if (pipe)
4647                 vlv_pllb_recal_opamp(dev_priv, pipe);
4648
4649         /* Set up Tx target for periodic Rcomp update */
4650         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4651
4652         /* Disable target IRef on PLL */
4653         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4654         reg_val &= 0x00ffffff;
4655         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4656
4657         /* Disable fast lock */
4658         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4659
4660         /* Set idtafcrecal before PLL is enabled */
4661         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4662         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4663         mdiv |= ((bestn << DPIO_N_SHIFT));
4664         mdiv |= (1 << DPIO_K_SHIFT);
4665
4666         /*
4667          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4668          * but we don't support that).
4669          * Note: don't use the DAC post divider as it seems unstable.
4670          */
4671         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4672         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4673
4674         mdiv |= DPIO_ENABLE_CALIBRATION;
4675         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4676
4677         /* Set HBR and RBR LPF coefficients */
4678         if (crtc->config.port_clock == 162000 ||
4679             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4680             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4681                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4682                                  0x009f0003);
4683         else
4684                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4685                                  0x00d0000f);
4686
4687         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4688             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4689                 /* Use SSC source */
4690                 if (!pipe)
4691                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4692                                          0x0df40000);
4693                 else
4694                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4695                                          0x0df70000);
4696         } else { /* HDMI or VGA */
4697                 /* Use bend source */
4698                 if (!pipe)
4699                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4700                                          0x0df70000);
4701                 else
4702                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4703                                          0x0df40000);
4704         }
4705
4706         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4707         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4708         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4709             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4710                 coreclk |= 0x01000000;
4711         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4712
4713         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4714
4715         /* Enable DPIO clock input */
4716         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4717                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4718         /* We should never disable this, set it here for state tracking */
4719         if (pipe == PIPE_B)
4720                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4721         dpll |= DPLL_VCO_ENABLE;
4722         crtc->config.dpll_hw_state.dpll = dpll;
4723
4724         dpll_md = (crtc->config.pixel_multiplier - 1)
4725                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4726         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4727
4728         if (crtc->config.has_dp_encoder)
4729                 intel_dp_set_m_n(crtc);
4730
4731         mutex_unlock(&dev_priv->dpio_lock);
4732 }
4733
4734 static void i9xx_update_pll(struct intel_crtc *crtc,
4735                             intel_clock_t *reduced_clock,
4736                             int num_connectors)
4737 {
4738         struct drm_device *dev = crtc->base.dev;
4739         struct drm_i915_private *dev_priv = dev->dev_private;
4740         u32 dpll;
4741         bool is_sdvo;
4742         struct dpll *clock = &crtc->config.dpll;
4743
4744         i9xx_update_pll_dividers(crtc, reduced_clock);
4745
4746         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4747                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4748
4749         dpll = DPLL_VGA_MODE_DIS;
4750
4751         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4752                 dpll |= DPLLB_MODE_LVDS;
4753         else
4754                 dpll |= DPLLB_MODE_DAC_SERIAL;
4755
4756         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4757                 dpll |= (crtc->config.pixel_multiplier - 1)
4758                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4759         }
4760
4761         if (is_sdvo)
4762                 dpll |= DPLL_SDVO_HIGH_SPEED;
4763
4764         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4765                 dpll |= DPLL_SDVO_HIGH_SPEED;
4766
4767         /* compute bitmask from p1 value */
4768         if (IS_PINEVIEW(dev))
4769                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4770         else {
4771                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4772                 if (IS_G4X(dev) && reduced_clock)
4773                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4774         }
4775         switch (clock->p2) {
4776         case 5:
4777                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4778                 break;
4779         case 7:
4780                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4781                 break;
4782         case 10:
4783                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4784                 break;
4785         case 14:
4786                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4787                 break;
4788         }
4789         if (INTEL_INFO(dev)->gen >= 4)
4790                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4791
4792         if (crtc->config.sdvo_tv_clock)
4793                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4794         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4795                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4796                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4797         else
4798                 dpll |= PLL_REF_INPUT_DREFCLK;
4799
4800         dpll |= DPLL_VCO_ENABLE;
4801         crtc->config.dpll_hw_state.dpll = dpll;
4802
4803         if (INTEL_INFO(dev)->gen >= 4) {
4804                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4805                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4806                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4807         }
4808
4809         if (crtc->config.has_dp_encoder)
4810                 intel_dp_set_m_n(crtc);
4811 }
4812
4813 static void i8xx_update_pll(struct intel_crtc *crtc,
4814                             intel_clock_t *reduced_clock,
4815                             int num_connectors)
4816 {
4817         struct drm_device *dev = crtc->base.dev;
4818         struct drm_i915_private *dev_priv = dev->dev_private;
4819         u32 dpll;
4820         struct dpll *clock = &crtc->config.dpll;
4821
4822         i9xx_update_pll_dividers(crtc, reduced_clock);
4823
4824         dpll = DPLL_VGA_MODE_DIS;
4825
4826         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4827                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4828         } else {
4829                 if (clock->p1 == 2)
4830                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4831                 else
4832                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4833                 if (clock->p2 == 4)
4834                         dpll |= PLL_P2_DIVIDE_BY_4;
4835         }
4836
4837         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4838                 dpll |= DPLL_DVO_2X_MODE;
4839
4840         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4841                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4842                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4843         else
4844                 dpll |= PLL_REF_INPUT_DREFCLK;
4845
4846         dpll |= DPLL_VCO_ENABLE;
4847         crtc->config.dpll_hw_state.dpll = dpll;
4848 }
4849
4850 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4851 {
4852         struct drm_device *dev = intel_crtc->base.dev;
4853         struct drm_i915_private *dev_priv = dev->dev_private;
4854         enum pipe pipe = intel_crtc->pipe;
4855         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4856         struct drm_display_mode *adjusted_mode =
4857                 &intel_crtc->config.adjusted_mode;
4858         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4859
4860         /* We need to be careful not to changed the adjusted mode, for otherwise
4861          * the hw state checker will get angry at the mismatch. */
4862         crtc_vtotal = adjusted_mode->crtc_vtotal;
4863         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4864
4865         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4866                 /* the chip adds 2 halflines automatically */
4867                 crtc_vtotal -= 1;
4868                 crtc_vblank_end -= 1;
4869                 vsyncshift = adjusted_mode->crtc_hsync_start
4870                              - adjusted_mode->crtc_htotal / 2;
4871         } else {
4872                 vsyncshift = 0;
4873         }
4874
4875         if (INTEL_INFO(dev)->gen > 3)
4876                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4877
4878         I915_WRITE(HTOTAL(cpu_transcoder),
4879                    (adjusted_mode->crtc_hdisplay - 1) |
4880                    ((adjusted_mode->crtc_htotal - 1) << 16));
4881         I915_WRITE(HBLANK(cpu_transcoder),
4882                    (adjusted_mode->crtc_hblank_start - 1) |
4883                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4884         I915_WRITE(HSYNC(cpu_transcoder),
4885                    (adjusted_mode->crtc_hsync_start - 1) |
4886                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4887
4888         I915_WRITE(VTOTAL(cpu_transcoder),
4889                    (adjusted_mode->crtc_vdisplay - 1) |
4890                    ((crtc_vtotal - 1) << 16));
4891         I915_WRITE(VBLANK(cpu_transcoder),
4892                    (adjusted_mode->crtc_vblank_start - 1) |
4893                    ((crtc_vblank_end - 1) << 16));
4894         I915_WRITE(VSYNC(cpu_transcoder),
4895                    (adjusted_mode->crtc_vsync_start - 1) |
4896                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4897
4898         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4899          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4900          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4901          * bits. */
4902         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4903             (pipe == PIPE_B || pipe == PIPE_C))
4904                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4905
4906         /* pipesrc controls the size that is scaled from, which should
4907          * always be the user's requested size.
4908          */
4909         I915_WRITE(PIPESRC(pipe),
4910                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
4911                    (intel_crtc->config.pipe_src_h - 1));
4912 }
4913
4914 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4915                                    struct intel_crtc_config *pipe_config)
4916 {
4917         struct drm_device *dev = crtc->base.dev;
4918         struct drm_i915_private *dev_priv = dev->dev_private;
4919         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4920         uint32_t tmp;
4921
4922         tmp = I915_READ(HTOTAL(cpu_transcoder));
4923         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4924         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4925         tmp = I915_READ(HBLANK(cpu_transcoder));
4926         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4927         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4928         tmp = I915_READ(HSYNC(cpu_transcoder));
4929         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4930         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4931
4932         tmp = I915_READ(VTOTAL(cpu_transcoder));
4933         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4934         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4935         tmp = I915_READ(VBLANK(cpu_transcoder));
4936         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4937         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4938         tmp = I915_READ(VSYNC(cpu_transcoder));
4939         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4940         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4941
4942         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4943                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4944                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4945                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4946         }
4947
4948         tmp = I915_READ(PIPESRC(crtc->pipe));
4949         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4950         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4951
4952         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4953         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4954 }
4955
4956 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4957                                              struct intel_crtc_config *pipe_config)
4958 {
4959         struct drm_crtc *crtc = &intel_crtc->base;
4960
4961         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4962         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4963         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4964         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4965
4966         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4967         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4968         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4969         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4970
4971         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4972
4973         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
4974         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4975 }
4976
4977 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4978 {
4979         struct drm_device *dev = intel_crtc->base.dev;
4980         struct drm_i915_private *dev_priv = dev->dev_private;
4981         uint32_t pipeconf;
4982
4983         pipeconf = 0;
4984
4985         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4986             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4987                 pipeconf |= PIPECONF_ENABLE;
4988
4989         if (intel_crtc->config.double_wide)
4990                 pipeconf |= PIPECONF_DOUBLE_WIDE;
4991
4992         /* only g4x and later have fancy bpc/dither controls */
4993         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4994                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4995                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4996                         pipeconf |= PIPECONF_DITHER_EN |
4997                                     PIPECONF_DITHER_TYPE_SP;
4998
4999                 switch (intel_crtc->config.pipe_bpp) {
5000                 case 18:
5001                         pipeconf |= PIPECONF_6BPC;
5002                         break;
5003                 case 24:
5004                         pipeconf |= PIPECONF_8BPC;
5005                         break;
5006                 case 30:
5007                         pipeconf |= PIPECONF_10BPC;
5008                         break;
5009                 default:
5010                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5011                         BUG();
5012                 }
5013         }
5014
5015         if (HAS_PIPE_CXSR(dev)) {
5016                 if (intel_crtc->lowfreq_avail) {
5017                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5018                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5019                 } else {
5020                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5021                 }
5022         }
5023
5024         if (!IS_GEN2(dev) &&
5025             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5026                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5027         else
5028                 pipeconf |= PIPECONF_PROGRESSIVE;
5029
5030         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5031                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5032
5033         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5034         POSTING_READ(PIPECONF(intel_crtc->pipe));
5035 }
5036
5037 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5038                               int x, int y,
5039                               struct drm_framebuffer *fb)
5040 {
5041         struct drm_device *dev = crtc->dev;
5042         struct drm_i915_private *dev_priv = dev->dev_private;
5043         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5044         int pipe = intel_crtc->pipe;
5045         int plane = intel_crtc->plane;
5046         int refclk, num_connectors = 0;
5047         intel_clock_t clock, reduced_clock;
5048         u32 dspcntr;
5049         bool ok, has_reduced_clock = false;
5050         bool is_lvds = false, is_dsi = false;
5051         struct intel_encoder *encoder;
5052         const intel_limit_t *limit;
5053         int ret;
5054
5055         for_each_encoder_on_crtc(dev, crtc, encoder) {
5056                 switch (encoder->type) {
5057                 case INTEL_OUTPUT_LVDS:
5058                         is_lvds = true;
5059                         break;
5060                 case INTEL_OUTPUT_DSI:
5061                         is_dsi = true;
5062                         break;
5063                 }
5064
5065                 num_connectors++;
5066         }
5067
5068         if (is_dsi)
5069                 goto skip_dpll;
5070
5071         if (!intel_crtc->config.clock_set) {
5072                 refclk = i9xx_get_refclk(crtc, num_connectors);
5073
5074                 /*
5075                  * Returns a set of divisors for the desired target clock with
5076                  * the given refclk, or FALSE.  The returned values represent
5077                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5078                  * 2) / p1 / p2.
5079                  */
5080                 limit = intel_limit(crtc, refclk);
5081                 ok = dev_priv->display.find_dpll(limit, crtc,
5082                                                  intel_crtc->config.port_clock,
5083                                                  refclk, NULL, &clock);
5084                 if (!ok) {
5085                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5086                         return -EINVAL;
5087                 }
5088
5089                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5090                         /*
5091                          * Ensure we match the reduced clock's P to the target
5092                          * clock.  If the clocks don't match, we can't switch
5093                          * the display clock by using the FP0/FP1. In such case
5094                          * we will disable the LVDS downclock feature.
5095                          */
5096                         has_reduced_clock =
5097                                 dev_priv->display.find_dpll(limit, crtc,
5098                                                             dev_priv->lvds_downclock,
5099                                                             refclk, &clock,
5100                                                             &reduced_clock);
5101                 }
5102                 /* Compat-code for transition, will disappear. */
5103                 intel_crtc->config.dpll.n = clock.n;
5104                 intel_crtc->config.dpll.m1 = clock.m1;
5105                 intel_crtc->config.dpll.m2 = clock.m2;
5106                 intel_crtc->config.dpll.p1 = clock.p1;
5107                 intel_crtc->config.dpll.p2 = clock.p2;
5108         }
5109
5110         if (IS_GEN2(dev)) {
5111                 i8xx_update_pll(intel_crtc,
5112                                 has_reduced_clock ? &reduced_clock : NULL,
5113                                 num_connectors);
5114         } else if (IS_VALLEYVIEW(dev)) {
5115                 vlv_update_pll(intel_crtc);
5116         } else {
5117                 i9xx_update_pll(intel_crtc,
5118                                 has_reduced_clock ? &reduced_clock : NULL,
5119                                 num_connectors);
5120         }
5121
5122 skip_dpll:
5123         /* Set up the display plane register */
5124         dspcntr = DISPPLANE_GAMMA_ENABLE;
5125
5126         if (!IS_VALLEYVIEW(dev)) {
5127                 if (pipe == 0)
5128                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5129                 else
5130                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5131         }
5132
5133         intel_set_pipe_timings(intel_crtc);
5134
5135         /* pipesrc and dspsize control the size that is scaled from,
5136          * which should always be the user's requested size.
5137          */
5138         I915_WRITE(DSPSIZE(plane),
5139                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5140                    (intel_crtc->config.pipe_src_w - 1));
5141         I915_WRITE(DSPPOS(plane), 0);
5142
5143         i9xx_set_pipeconf(intel_crtc);
5144
5145         I915_WRITE(DSPCNTR(plane), dspcntr);
5146         POSTING_READ(DSPCNTR(plane));
5147
5148         ret = intel_pipe_set_base(crtc, x, y, fb);
5149
5150         return ret;
5151 }
5152
5153 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5154                                  struct intel_crtc_config *pipe_config)
5155 {
5156         struct drm_device *dev = crtc->base.dev;
5157         struct drm_i915_private *dev_priv = dev->dev_private;
5158         uint32_t tmp;
5159
5160         tmp = I915_READ(PFIT_CONTROL);
5161         if (!(tmp & PFIT_ENABLE))
5162                 return;
5163
5164         /* Check whether the pfit is attached to our pipe. */
5165         if (INTEL_INFO(dev)->gen < 4) {
5166                 if (crtc->pipe != PIPE_B)
5167                         return;
5168         } else {
5169                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5170                         return;
5171         }
5172
5173         pipe_config->gmch_pfit.control = tmp;
5174         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5175         if (INTEL_INFO(dev)->gen < 5)
5176                 pipe_config->gmch_pfit.lvds_border_bits =
5177                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5178 }
5179
5180 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5181                                struct intel_crtc_config *pipe_config)
5182 {
5183         struct drm_device *dev = crtc->base.dev;
5184         struct drm_i915_private *dev_priv = dev->dev_private;
5185         int pipe = pipe_config->cpu_transcoder;
5186         intel_clock_t clock;
5187         u32 mdiv;
5188         int refclk = 100000;
5189
5190         mutex_lock(&dev_priv->dpio_lock);
5191         mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5192         mutex_unlock(&dev_priv->dpio_lock);
5193
5194         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5195         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5196         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5197         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5198         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5199
5200         clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5201         clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
5202
5203         pipe_config->port_clock = clock.dot / 10;
5204 }
5205
5206 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5207                                  struct intel_crtc_config *pipe_config)
5208 {
5209         struct drm_device *dev = crtc->base.dev;
5210         struct drm_i915_private *dev_priv = dev->dev_private;
5211         uint32_t tmp;
5212
5213         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5214         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5215
5216         tmp = I915_READ(PIPECONF(crtc->pipe));
5217         if (!(tmp & PIPECONF_ENABLE))
5218                 return false;
5219
5220         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5221                 switch (tmp & PIPECONF_BPC_MASK) {
5222                 case PIPECONF_6BPC:
5223                         pipe_config->pipe_bpp = 18;
5224                         break;
5225                 case PIPECONF_8BPC:
5226                         pipe_config->pipe_bpp = 24;
5227                         break;
5228                 case PIPECONF_10BPC:
5229                         pipe_config->pipe_bpp = 30;
5230                         break;
5231                 default:
5232                         break;
5233                 }
5234         }
5235
5236         if (INTEL_INFO(dev)->gen < 4)
5237                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5238
5239         intel_get_pipe_timings(crtc, pipe_config);
5240
5241         i9xx_get_pfit_config(crtc, pipe_config);
5242
5243         if (INTEL_INFO(dev)->gen >= 4) {
5244                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5245                 pipe_config->pixel_multiplier =
5246                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5247                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5248                 pipe_config->dpll_hw_state.dpll_md = tmp;
5249         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5250                 tmp = I915_READ(DPLL(crtc->pipe));
5251                 pipe_config->pixel_multiplier =
5252                         ((tmp & SDVO_MULTIPLIER_MASK)
5253                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5254         } else {
5255                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5256                  * port and will be fixed up in the encoder->get_config
5257                  * function. */
5258                 pipe_config->pixel_multiplier = 1;
5259         }
5260         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5261         if (!IS_VALLEYVIEW(dev)) {
5262                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5263                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5264         } else {
5265                 /* Mask out read-only status bits. */
5266                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5267                                                      DPLL_PORTC_READY_MASK |
5268                                                      DPLL_PORTB_READY_MASK);
5269         }
5270
5271         if (IS_VALLEYVIEW(dev))
5272                 vlv_crtc_clock_get(crtc, pipe_config);
5273         else
5274                 i9xx_crtc_clock_get(crtc, pipe_config);
5275
5276         return true;
5277 }
5278
5279 static void ironlake_init_pch_refclk(struct drm_device *dev)
5280 {
5281         struct drm_i915_private *dev_priv = dev->dev_private;
5282         struct drm_mode_config *mode_config = &dev->mode_config;
5283         struct intel_encoder *encoder;
5284         u32 val, final;
5285         bool has_lvds = false;
5286         bool has_cpu_edp = false;
5287         bool has_panel = false;
5288         bool has_ck505 = false;
5289         bool can_ssc = false;
5290
5291         /* We need to take the global config into account */
5292         list_for_each_entry(encoder, &mode_config->encoder_list,
5293                             base.head) {
5294                 switch (encoder->type) {
5295                 case INTEL_OUTPUT_LVDS:
5296                         has_panel = true;
5297                         has_lvds = true;
5298                         break;
5299                 case INTEL_OUTPUT_EDP:
5300                         has_panel = true;
5301                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5302                                 has_cpu_edp = true;
5303                         break;
5304                 }
5305         }
5306
5307         if (HAS_PCH_IBX(dev)) {
5308                 has_ck505 = dev_priv->vbt.display_clock_mode;
5309                 can_ssc = has_ck505;
5310         } else {
5311                 has_ck505 = false;
5312                 can_ssc = true;
5313         }
5314
5315         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5316                       has_panel, has_lvds, has_ck505);
5317
5318         /* Ironlake: try to setup display ref clock before DPLL
5319          * enabling. This is only under driver's control after
5320          * PCH B stepping, previous chipset stepping should be
5321          * ignoring this setting.
5322          */
5323         val = I915_READ(PCH_DREF_CONTROL);
5324
5325         /* As we must carefully and slowly disable/enable each source in turn,
5326          * compute the final state we want first and check if we need to
5327          * make any changes at all.
5328          */
5329         final = val;
5330         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5331         if (has_ck505)
5332                 final |= DREF_NONSPREAD_CK505_ENABLE;
5333         else
5334                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5335
5336         final &= ~DREF_SSC_SOURCE_MASK;
5337         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5338         final &= ~DREF_SSC1_ENABLE;
5339
5340         if (has_panel) {
5341                 final |= DREF_SSC_SOURCE_ENABLE;
5342
5343                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5344                         final |= DREF_SSC1_ENABLE;
5345
5346                 if (has_cpu_edp) {
5347                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5348                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5349                         else
5350                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5351                 } else
5352                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5353         } else {
5354                 final |= DREF_SSC_SOURCE_DISABLE;
5355                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5356         }
5357
5358         if (final == val)
5359                 return;
5360
5361         /* Always enable nonspread source */
5362         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5363
5364         if (has_ck505)
5365                 val |= DREF_NONSPREAD_CK505_ENABLE;
5366         else
5367                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5368
5369         if (has_panel) {
5370                 val &= ~DREF_SSC_SOURCE_MASK;
5371                 val |= DREF_SSC_SOURCE_ENABLE;
5372
5373                 /* SSC must be turned on before enabling the CPU output  */
5374                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5375                         DRM_DEBUG_KMS("Using SSC on panel\n");
5376                         val |= DREF_SSC1_ENABLE;
5377                 } else
5378                         val &= ~DREF_SSC1_ENABLE;
5379
5380                 /* Get SSC going before enabling the outputs */
5381                 I915_WRITE(PCH_DREF_CONTROL, val);
5382                 POSTING_READ(PCH_DREF_CONTROL);
5383                 udelay(200);
5384
5385                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5386
5387                 /* Enable CPU source on CPU attached eDP */
5388                 if (has_cpu_edp) {
5389                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5390                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5391                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5392                         }
5393                         else
5394                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5395                 } else
5396                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5397
5398                 I915_WRITE(PCH_DREF_CONTROL, val);
5399                 POSTING_READ(PCH_DREF_CONTROL);
5400                 udelay(200);
5401         } else {
5402                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5403
5404                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5405
5406                 /* Turn off CPU output */
5407                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5408
5409                 I915_WRITE(PCH_DREF_CONTROL, val);
5410                 POSTING_READ(PCH_DREF_CONTROL);
5411                 udelay(200);
5412
5413                 /* Turn off the SSC source */
5414                 val &= ~DREF_SSC_SOURCE_MASK;
5415                 val |= DREF_SSC_SOURCE_DISABLE;
5416
5417                 /* Turn off SSC1 */
5418                 val &= ~DREF_SSC1_ENABLE;
5419
5420                 I915_WRITE(PCH_DREF_CONTROL, val);
5421                 POSTING_READ(PCH_DREF_CONTROL);
5422                 udelay(200);
5423         }
5424
5425         BUG_ON(val != final);
5426 }
5427
5428 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5429 {
5430         uint32_t tmp;
5431
5432         tmp = I915_READ(SOUTH_CHICKEN2);
5433         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5434         I915_WRITE(SOUTH_CHICKEN2, tmp);
5435
5436         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5437                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5438                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5439
5440         tmp = I915_READ(SOUTH_CHICKEN2);
5441         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5442         I915_WRITE(SOUTH_CHICKEN2, tmp);
5443
5444         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5445                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5446                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5447 }
5448
5449 /* WaMPhyProgramming:hsw */
5450 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5451 {
5452         uint32_t tmp;
5453
5454         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5455         tmp &= ~(0xFF << 24);
5456         tmp |= (0x12 << 24);
5457         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5458
5459         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5460         tmp |= (1 << 11);
5461         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5462
5463         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5464         tmp |= (1 << 11);
5465         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5466
5467         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5468         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5469         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5470
5471         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5472         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5473         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5474
5475         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5476         tmp &= ~(7 << 13);
5477         tmp |= (5 << 13);
5478         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5479
5480         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5481         tmp &= ~(7 << 13);
5482         tmp |= (5 << 13);
5483         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5484
5485         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5486         tmp &= ~0xFF;
5487         tmp |= 0x1C;
5488         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5489
5490         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5491         tmp &= ~0xFF;
5492         tmp |= 0x1C;
5493         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5494
5495         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5496         tmp &= ~(0xFF << 16);
5497         tmp |= (0x1C << 16);
5498         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5499
5500         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5501         tmp &= ~(0xFF << 16);
5502         tmp |= (0x1C << 16);
5503         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5504
5505         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5506         tmp |= (1 << 27);
5507         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5508
5509         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5510         tmp |= (1 << 27);
5511         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5512
5513         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5514         tmp &= ~(0xF << 28);
5515         tmp |= (4 << 28);
5516         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5517
5518         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5519         tmp &= ~(0xF << 28);
5520         tmp |= (4 << 28);
5521         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5522 }
5523
5524 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5525  * Programming" based on the parameters passed:
5526  * - Sequence to enable CLKOUT_DP
5527  * - Sequence to enable CLKOUT_DP without spread
5528  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5529  */
5530 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5531                                  bool with_fdi)
5532 {
5533         struct drm_i915_private *dev_priv = dev->dev_private;
5534         uint32_t reg, tmp;
5535
5536         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5537                 with_spread = true;
5538         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5539                  with_fdi, "LP PCH doesn't have FDI\n"))
5540                 with_fdi = false;
5541
5542         mutex_lock(&dev_priv->dpio_lock);
5543
5544         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5545         tmp &= ~SBI_SSCCTL_DISABLE;
5546         tmp |= SBI_SSCCTL_PATHALT;
5547         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5548
5549         udelay(24);
5550
5551         if (with_spread) {
5552                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5553                 tmp &= ~SBI_SSCCTL_PATHALT;
5554                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5555
5556                 if (with_fdi) {
5557                         lpt_reset_fdi_mphy(dev_priv);
5558                         lpt_program_fdi_mphy(dev_priv);
5559                 }
5560         }
5561
5562         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5563                SBI_GEN0 : SBI_DBUFF0;
5564         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5565         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5566         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5567
5568         mutex_unlock(&dev_priv->dpio_lock);
5569 }
5570
5571 /* Sequence to disable CLKOUT_DP */
5572 static void lpt_disable_clkout_dp(struct drm_device *dev)
5573 {
5574         struct drm_i915_private *dev_priv = dev->dev_private;
5575         uint32_t reg, tmp;
5576
5577         mutex_lock(&dev_priv->dpio_lock);
5578
5579         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5580                SBI_GEN0 : SBI_DBUFF0;
5581         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5582         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5583         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5584
5585         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5586         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5587                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5588                         tmp |= SBI_SSCCTL_PATHALT;
5589                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5590                         udelay(32);
5591                 }
5592                 tmp |= SBI_SSCCTL_DISABLE;
5593                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5594         }
5595
5596         mutex_unlock(&dev_priv->dpio_lock);
5597 }
5598
5599 static void lpt_init_pch_refclk(struct drm_device *dev)
5600 {
5601         struct drm_mode_config *mode_config = &dev->mode_config;
5602         struct intel_encoder *encoder;
5603         bool has_vga = false;
5604
5605         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5606                 switch (encoder->type) {
5607                 case INTEL_OUTPUT_ANALOG:
5608                         has_vga = true;
5609                         break;
5610                 }
5611         }
5612
5613         if (has_vga)
5614                 lpt_enable_clkout_dp(dev, true, true);
5615         else
5616                 lpt_disable_clkout_dp(dev);
5617 }
5618
5619 /*
5620  * Initialize reference clocks when the driver loads
5621  */
5622 void intel_init_pch_refclk(struct drm_device *dev)
5623 {
5624         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5625                 ironlake_init_pch_refclk(dev);
5626         else if (HAS_PCH_LPT(dev))
5627                 lpt_init_pch_refclk(dev);
5628 }
5629
5630 static int ironlake_get_refclk(struct drm_crtc *crtc)
5631 {
5632         struct drm_device *dev = crtc->dev;
5633         struct drm_i915_private *dev_priv = dev->dev_private;
5634         struct intel_encoder *encoder;
5635         int num_connectors = 0;
5636         bool is_lvds = false;
5637
5638         for_each_encoder_on_crtc(dev, crtc, encoder) {
5639                 switch (encoder->type) {
5640                 case INTEL_OUTPUT_LVDS:
5641                         is_lvds = true;
5642                         break;
5643                 }
5644                 num_connectors++;
5645         }
5646
5647         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5648                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5649                               dev_priv->vbt.lvds_ssc_freq);
5650                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5651         }
5652
5653         return 120000;
5654 }
5655
5656 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5657 {
5658         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5659         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5660         int pipe = intel_crtc->pipe;
5661         uint32_t val;
5662
5663         val = 0;
5664
5665         switch (intel_crtc->config.pipe_bpp) {
5666         case 18:
5667                 val |= PIPECONF_6BPC;
5668                 break;
5669         case 24:
5670                 val |= PIPECONF_8BPC;
5671                 break;
5672         case 30:
5673                 val |= PIPECONF_10BPC;
5674                 break;
5675         case 36:
5676                 val |= PIPECONF_12BPC;
5677                 break;
5678         default:
5679                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5680                 BUG();
5681         }
5682
5683         if (intel_crtc->config.dither)
5684                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5685
5686         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5687                 val |= PIPECONF_INTERLACED_ILK;
5688         else
5689                 val |= PIPECONF_PROGRESSIVE;
5690
5691         if (intel_crtc->config.limited_color_range)
5692                 val |= PIPECONF_COLOR_RANGE_SELECT;
5693
5694         I915_WRITE(PIPECONF(pipe), val);
5695         POSTING_READ(PIPECONF(pipe));
5696 }
5697
5698 /*
5699  * Set up the pipe CSC unit.
5700  *
5701  * Currently only full range RGB to limited range RGB conversion
5702  * is supported, but eventually this should handle various
5703  * RGB<->YCbCr scenarios as well.
5704  */
5705 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5706 {
5707         struct drm_device *dev = crtc->dev;
5708         struct drm_i915_private *dev_priv = dev->dev_private;
5709         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5710         int pipe = intel_crtc->pipe;
5711         uint16_t coeff = 0x7800; /* 1.0 */
5712
5713         /*
5714          * TODO: Check what kind of values actually come out of the pipe
5715          * with these coeff/postoff values and adjust to get the best
5716          * accuracy. Perhaps we even need to take the bpc value into
5717          * consideration.
5718          */
5719
5720         if (intel_crtc->config.limited_color_range)
5721                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5722
5723         /*
5724          * GY/GU and RY/RU should be the other way around according
5725          * to BSpec, but reality doesn't agree. Just set them up in
5726          * a way that results in the correct picture.
5727          */
5728         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5729         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5730
5731         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5732         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5733
5734         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5735         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5736
5737         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5738         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5739         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5740
5741         if (INTEL_INFO(dev)->gen > 6) {
5742                 uint16_t postoff = 0;
5743
5744                 if (intel_crtc->config.limited_color_range)
5745                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5746
5747                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5748                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5749                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5750
5751                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5752         } else {
5753                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5754
5755                 if (intel_crtc->config.limited_color_range)
5756                         mode |= CSC_BLACK_SCREEN_OFFSET;
5757
5758                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5759         }
5760 }
5761
5762 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5763 {
5764         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5766         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5767         uint32_t val;
5768
5769         val = 0;
5770
5771         if (intel_crtc->config.dither)
5772                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5773
5774         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5775                 val |= PIPECONF_INTERLACED_ILK;
5776         else
5777                 val |= PIPECONF_PROGRESSIVE;
5778
5779         I915_WRITE(PIPECONF(cpu_transcoder), val);
5780         POSTING_READ(PIPECONF(cpu_transcoder));
5781
5782         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5783         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5784 }
5785
5786 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5787                                     intel_clock_t *clock,
5788                                     bool *has_reduced_clock,
5789                                     intel_clock_t *reduced_clock)
5790 {
5791         struct drm_device *dev = crtc->dev;
5792         struct drm_i915_private *dev_priv = dev->dev_private;
5793         struct intel_encoder *intel_encoder;
5794         int refclk;
5795         const intel_limit_t *limit;
5796         bool ret, is_lvds = false;
5797
5798         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5799                 switch (intel_encoder->type) {
5800                 case INTEL_OUTPUT_LVDS:
5801                         is_lvds = true;
5802                         break;
5803                 }
5804         }
5805
5806         refclk = ironlake_get_refclk(crtc);
5807
5808         /*
5809          * Returns a set of divisors for the desired target clock with the given
5810          * refclk, or FALSE.  The returned values represent the clock equation:
5811          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5812          */
5813         limit = intel_limit(crtc, refclk);
5814         ret = dev_priv->display.find_dpll(limit, crtc,
5815                                           to_intel_crtc(crtc)->config.port_clock,
5816                                           refclk, NULL, clock);
5817         if (!ret)
5818                 return false;
5819
5820         if (is_lvds && dev_priv->lvds_downclock_avail) {
5821                 /*
5822                  * Ensure we match the reduced clock's P to the target clock.
5823                  * If the clocks don't match, we can't switch the display clock
5824                  * by using the FP0/FP1. In such case we will disable the LVDS
5825                  * downclock feature.
5826                 */
5827                 *has_reduced_clock =
5828                         dev_priv->display.find_dpll(limit, crtc,
5829                                                     dev_priv->lvds_downclock,
5830                                                     refclk, clock,
5831                                                     reduced_clock);
5832         }
5833
5834         return true;
5835 }
5836
5837 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5838 {
5839         struct drm_i915_private *dev_priv = dev->dev_private;
5840         uint32_t temp;
5841
5842         temp = I915_READ(SOUTH_CHICKEN1);
5843         if (temp & FDI_BC_BIFURCATION_SELECT)
5844                 return;
5845
5846         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5847         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5848
5849         temp |= FDI_BC_BIFURCATION_SELECT;
5850         DRM_DEBUG_KMS("enabling fdi C rx\n");
5851         I915_WRITE(SOUTH_CHICKEN1, temp);
5852         POSTING_READ(SOUTH_CHICKEN1);
5853 }
5854
5855 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5856 {
5857         struct drm_device *dev = intel_crtc->base.dev;
5858         struct drm_i915_private *dev_priv = dev->dev_private;
5859
5860         switch (intel_crtc->pipe) {
5861         case PIPE_A:
5862                 break;
5863         case PIPE_B:
5864                 if (intel_crtc->config.fdi_lanes > 2)
5865                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5866                 else
5867                         cpt_enable_fdi_bc_bifurcation(dev);
5868
5869                 break;
5870         case PIPE_C:
5871                 cpt_enable_fdi_bc_bifurcation(dev);
5872
5873                 break;
5874         default:
5875                 BUG();
5876         }
5877 }
5878
5879 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5880 {
5881         /*
5882          * Account for spread spectrum to avoid
5883          * oversubscribing the link. Max center spread
5884          * is 2.5%; use 5% for safety's sake.
5885          */
5886         u32 bps = target_clock * bpp * 21 / 20;
5887         return bps / (link_bw * 8) + 1;
5888 }
5889
5890 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5891 {
5892         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5893 }
5894
5895 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5896                                       u32 *fp,
5897                                       intel_clock_t *reduced_clock, u32 *fp2)
5898 {
5899         struct drm_crtc *crtc = &intel_crtc->base;
5900         struct drm_device *dev = crtc->dev;
5901         struct drm_i915_private *dev_priv = dev->dev_private;
5902         struct intel_encoder *intel_encoder;
5903         uint32_t dpll;
5904         int factor, num_connectors = 0;
5905         bool is_lvds = false, is_sdvo = false;
5906
5907         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5908                 switch (intel_encoder->type) {
5909                 case INTEL_OUTPUT_LVDS:
5910                         is_lvds = true;
5911                         break;
5912                 case INTEL_OUTPUT_SDVO:
5913                 case INTEL_OUTPUT_HDMI:
5914                         is_sdvo = true;
5915                         break;
5916                 }
5917
5918                 num_connectors++;
5919         }
5920
5921         /* Enable autotuning of the PLL clock (if permissible) */
5922         factor = 21;
5923         if (is_lvds) {
5924                 if ((intel_panel_use_ssc(dev_priv) &&
5925                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5926                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5927                         factor = 25;
5928         } else if (intel_crtc->config.sdvo_tv_clock)
5929                 factor = 20;
5930
5931         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5932                 *fp |= FP_CB_TUNE;
5933
5934         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5935                 *fp2 |= FP_CB_TUNE;
5936
5937         dpll = 0;
5938
5939         if (is_lvds)
5940                 dpll |= DPLLB_MODE_LVDS;
5941         else
5942                 dpll |= DPLLB_MODE_DAC_SERIAL;
5943
5944         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5945                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5946
5947         if (is_sdvo)
5948                 dpll |= DPLL_SDVO_HIGH_SPEED;
5949         if (intel_crtc->config.has_dp_encoder)
5950                 dpll |= DPLL_SDVO_HIGH_SPEED;
5951
5952         /* compute bitmask from p1 value */
5953         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5954         /* also FPA1 */
5955         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5956
5957         switch (intel_crtc->config.dpll.p2) {
5958         case 5:
5959                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5960                 break;
5961         case 7:
5962                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5963                 break;
5964         case 10:
5965                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5966                 break;
5967         case 14:
5968                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5969                 break;
5970         }
5971
5972         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5973                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5974         else
5975                 dpll |= PLL_REF_INPUT_DREFCLK;
5976
5977         return dpll | DPLL_VCO_ENABLE;
5978 }
5979
5980 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5981                                   int x, int y,
5982                                   struct drm_framebuffer *fb)
5983 {
5984         struct drm_device *dev = crtc->dev;
5985         struct drm_i915_private *dev_priv = dev->dev_private;
5986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5987         int pipe = intel_crtc->pipe;
5988         int plane = intel_crtc->plane;
5989         int num_connectors = 0;
5990         intel_clock_t clock, reduced_clock;
5991         u32 dpll = 0, fp = 0, fp2 = 0;
5992         bool ok, has_reduced_clock = false;
5993         bool is_lvds = false;
5994         struct intel_encoder *encoder;
5995         struct intel_shared_dpll *pll;
5996         int ret;
5997
5998         for_each_encoder_on_crtc(dev, crtc, encoder) {
5999                 switch (encoder->type) {
6000                 case INTEL_OUTPUT_LVDS:
6001                         is_lvds = true;
6002                         break;
6003                 }
6004
6005                 num_connectors++;
6006         }
6007
6008         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6009              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6010
6011         ok = ironlake_compute_clocks(crtc, &clock,
6012                                      &has_reduced_clock, &reduced_clock);
6013         if (!ok && !intel_crtc->config.clock_set) {
6014                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6015                 return -EINVAL;
6016         }
6017         /* Compat-code for transition, will disappear. */
6018         if (!intel_crtc->config.clock_set) {
6019                 intel_crtc->config.dpll.n = clock.n;
6020                 intel_crtc->config.dpll.m1 = clock.m1;
6021                 intel_crtc->config.dpll.m2 = clock.m2;
6022                 intel_crtc->config.dpll.p1 = clock.p1;
6023                 intel_crtc->config.dpll.p2 = clock.p2;
6024         }
6025
6026         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6027         if (intel_crtc->config.has_pch_encoder) {
6028                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6029                 if (has_reduced_clock)
6030                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6031
6032                 dpll = ironlake_compute_dpll(intel_crtc,
6033                                              &fp, &reduced_clock,
6034                                              has_reduced_clock ? &fp2 : NULL);
6035
6036                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6037                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6038                 if (has_reduced_clock)
6039                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6040                 else
6041                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6042
6043                 pll = intel_get_shared_dpll(intel_crtc);
6044                 if (pll == NULL) {
6045                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6046                                          pipe_name(pipe));
6047                         return -EINVAL;
6048                 }
6049         } else
6050                 intel_put_shared_dpll(intel_crtc);
6051
6052         if (intel_crtc->config.has_dp_encoder)
6053                 intel_dp_set_m_n(intel_crtc);
6054
6055         if (is_lvds && has_reduced_clock && i915_powersave)
6056                 intel_crtc->lowfreq_avail = true;
6057         else
6058                 intel_crtc->lowfreq_avail = false;
6059
6060         if (intel_crtc->config.has_pch_encoder) {
6061                 pll = intel_crtc_to_shared_dpll(intel_crtc);
6062
6063         }
6064
6065         intel_set_pipe_timings(intel_crtc);
6066
6067         if (intel_crtc->config.has_pch_encoder) {
6068                 intel_cpu_transcoder_set_m_n(intel_crtc,
6069                                              &intel_crtc->config.fdi_m_n);
6070         }
6071
6072         if (IS_IVYBRIDGE(dev))
6073                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
6074
6075         ironlake_set_pipeconf(crtc);
6076
6077         /* Set up the display plane register */
6078         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6079         POSTING_READ(DSPCNTR(plane));
6080
6081         ret = intel_pipe_set_base(crtc, x, y, fb);
6082
6083         return ret;
6084 }
6085
6086 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6087                                          struct intel_link_m_n *m_n)
6088 {
6089         struct drm_device *dev = crtc->base.dev;
6090         struct drm_i915_private *dev_priv = dev->dev_private;
6091         enum pipe pipe = crtc->pipe;
6092
6093         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6094         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6095         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6096                 & ~TU_SIZE_MASK;
6097         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6098         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6099                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6100 }
6101
6102 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6103                                          enum transcoder transcoder,
6104                                          struct intel_link_m_n *m_n)
6105 {
6106         struct drm_device *dev = crtc->base.dev;
6107         struct drm_i915_private *dev_priv = dev->dev_private;
6108         enum pipe pipe = crtc->pipe;
6109
6110         if (INTEL_INFO(dev)->gen >= 5) {
6111                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6112                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6113                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6114                         & ~TU_SIZE_MASK;
6115                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6116                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6117                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6118         } else {
6119                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6120                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6121                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6122                         & ~TU_SIZE_MASK;
6123                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6124                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6125                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6126         }
6127 }
6128
6129 void intel_dp_get_m_n(struct intel_crtc *crtc,
6130                       struct intel_crtc_config *pipe_config)
6131 {
6132         if (crtc->config.has_pch_encoder)
6133                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6134         else
6135                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6136                                              &pipe_config->dp_m_n);
6137 }
6138
6139 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6140                                         struct intel_crtc_config *pipe_config)
6141 {
6142         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6143                                      &pipe_config->fdi_m_n);
6144 }
6145
6146 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6147                                      struct intel_crtc_config *pipe_config)
6148 {
6149         struct drm_device *dev = crtc->base.dev;
6150         struct drm_i915_private *dev_priv = dev->dev_private;
6151         uint32_t tmp;
6152
6153         tmp = I915_READ(PF_CTL(crtc->pipe));
6154
6155         if (tmp & PF_ENABLE) {
6156                 pipe_config->pch_pfit.enabled = true;
6157                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6158                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6159
6160                 /* We currently do not free assignements of panel fitters on
6161                  * ivb/hsw (since we don't use the higher upscaling modes which
6162                  * differentiates them) so just WARN about this case for now. */
6163                 if (IS_GEN7(dev)) {
6164                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6165                                 PF_PIPE_SEL_IVB(crtc->pipe));
6166                 }
6167         }
6168 }
6169
6170 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6171                                      struct intel_crtc_config *pipe_config)
6172 {
6173         struct drm_device *dev = crtc->base.dev;
6174         struct drm_i915_private *dev_priv = dev->dev_private;
6175         uint32_t tmp;
6176
6177         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6178         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6179
6180         tmp = I915_READ(PIPECONF(crtc->pipe));
6181         if (!(tmp & PIPECONF_ENABLE))
6182                 return false;
6183
6184         switch (tmp & PIPECONF_BPC_MASK) {
6185         case PIPECONF_6BPC:
6186                 pipe_config->pipe_bpp = 18;
6187                 break;
6188         case PIPECONF_8BPC:
6189                 pipe_config->pipe_bpp = 24;
6190                 break;
6191         case PIPECONF_10BPC:
6192                 pipe_config->pipe_bpp = 30;
6193                 break;
6194         case PIPECONF_12BPC:
6195                 pipe_config->pipe_bpp = 36;
6196                 break;
6197         default:
6198                 break;
6199         }
6200
6201         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6202                 struct intel_shared_dpll *pll;
6203
6204                 pipe_config->has_pch_encoder = true;
6205
6206                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6207                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6208                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6209
6210                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6211
6212                 if (HAS_PCH_IBX(dev_priv->dev)) {
6213                         pipe_config->shared_dpll =
6214                                 (enum intel_dpll_id) crtc->pipe;
6215                 } else {
6216                         tmp = I915_READ(PCH_DPLL_SEL);
6217                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6218                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6219                         else
6220                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6221                 }
6222
6223                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6224
6225                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6226                                            &pipe_config->dpll_hw_state));
6227
6228                 tmp = pipe_config->dpll_hw_state.dpll;
6229                 pipe_config->pixel_multiplier =
6230                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6231                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6232
6233                 ironlake_pch_clock_get(crtc, pipe_config);
6234         } else {
6235                 pipe_config->pixel_multiplier = 1;
6236         }
6237
6238         intel_get_pipe_timings(crtc, pipe_config);
6239
6240         ironlake_get_pfit_config(crtc, pipe_config);
6241
6242         return true;
6243 }
6244
6245 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6246 {
6247         struct drm_device *dev = dev_priv->dev;
6248         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6249         struct intel_crtc *crtc;
6250         unsigned long irqflags;
6251         uint32_t val;
6252
6253         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6254                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6255                      pipe_name(crtc->pipe));
6256
6257         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6258         WARN(plls->spll_refcount, "SPLL enabled\n");
6259         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6260         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6261         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6262         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6263              "CPU PWM1 enabled\n");
6264         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6265              "CPU PWM2 enabled\n");
6266         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6267              "PCH PWM1 enabled\n");
6268         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6269              "Utility pin enabled\n");
6270         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6271
6272         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6273         val = I915_READ(DEIMR);
6274         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6275              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6276         val = I915_READ(SDEIMR);
6277         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6278              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6279         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6280 }
6281
6282 /*
6283  * This function implements pieces of two sequences from BSpec:
6284  * - Sequence for display software to disable LCPLL
6285  * - Sequence for display software to allow package C8+
6286  * The steps implemented here are just the steps that actually touch the LCPLL
6287  * register. Callers should take care of disabling all the display engine
6288  * functions, doing the mode unset, fixing interrupts, etc.
6289  */
6290 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6291                               bool switch_to_fclk, bool allow_power_down)
6292 {
6293         uint32_t val;
6294
6295         assert_can_disable_lcpll(dev_priv);
6296
6297         val = I915_READ(LCPLL_CTL);
6298
6299         if (switch_to_fclk) {
6300                 val |= LCPLL_CD_SOURCE_FCLK;
6301                 I915_WRITE(LCPLL_CTL, val);
6302
6303                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6304                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6305                         DRM_ERROR("Switching to FCLK failed\n");
6306
6307                 val = I915_READ(LCPLL_CTL);
6308         }
6309
6310         val |= LCPLL_PLL_DISABLE;
6311         I915_WRITE(LCPLL_CTL, val);
6312         POSTING_READ(LCPLL_CTL);
6313
6314         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6315                 DRM_ERROR("LCPLL still locked\n");
6316
6317         val = I915_READ(D_COMP);
6318         val |= D_COMP_COMP_DISABLE;
6319         mutex_lock(&dev_priv->rps.hw_lock);
6320         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6321                 DRM_ERROR("Failed to disable D_COMP\n");
6322         mutex_unlock(&dev_priv->rps.hw_lock);
6323         POSTING_READ(D_COMP);
6324         ndelay(100);
6325
6326         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6327                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6328
6329         if (allow_power_down) {
6330                 val = I915_READ(LCPLL_CTL);
6331                 val |= LCPLL_POWER_DOWN_ALLOW;
6332                 I915_WRITE(LCPLL_CTL, val);
6333                 POSTING_READ(LCPLL_CTL);
6334         }
6335 }
6336
6337 /*
6338  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6339  * source.
6340  */
6341 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6342 {
6343         uint32_t val;
6344
6345         val = I915_READ(LCPLL_CTL);
6346
6347         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6348                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6349                 return;
6350
6351         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6352          * we'll hang the machine! */
6353         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6354
6355         if (val & LCPLL_POWER_DOWN_ALLOW) {
6356                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6357                 I915_WRITE(LCPLL_CTL, val);
6358                 POSTING_READ(LCPLL_CTL);
6359         }
6360
6361         val = I915_READ(D_COMP);
6362         val |= D_COMP_COMP_FORCE;
6363         val &= ~D_COMP_COMP_DISABLE;
6364         mutex_lock(&dev_priv->rps.hw_lock);
6365         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6366                 DRM_ERROR("Failed to enable D_COMP\n");
6367         mutex_unlock(&dev_priv->rps.hw_lock);
6368         POSTING_READ(D_COMP);
6369
6370         val = I915_READ(LCPLL_CTL);
6371         val &= ~LCPLL_PLL_DISABLE;
6372         I915_WRITE(LCPLL_CTL, val);
6373
6374         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6375                 DRM_ERROR("LCPLL not locked yet\n");
6376
6377         if (val & LCPLL_CD_SOURCE_FCLK) {
6378                 val = I915_READ(LCPLL_CTL);
6379                 val &= ~LCPLL_CD_SOURCE_FCLK;
6380                 I915_WRITE(LCPLL_CTL, val);
6381
6382                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6383                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6384                         DRM_ERROR("Switching back to LCPLL failed\n");
6385         }
6386
6387         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6388 }
6389
6390 void hsw_enable_pc8_work(struct work_struct *__work)
6391 {
6392         struct drm_i915_private *dev_priv =
6393                 container_of(to_delayed_work(__work), struct drm_i915_private,
6394                              pc8.enable_work);
6395         struct drm_device *dev = dev_priv->dev;
6396         uint32_t val;
6397
6398         if (dev_priv->pc8.enabled)
6399                 return;
6400
6401         DRM_DEBUG_KMS("Enabling package C8+\n");
6402
6403         dev_priv->pc8.enabled = true;
6404
6405         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6406                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6407                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6408                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6409         }
6410
6411         lpt_disable_clkout_dp(dev);
6412         hsw_pc8_disable_interrupts(dev);
6413         hsw_disable_lcpll(dev_priv, true, true);
6414 }
6415
6416 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6417 {
6418         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6419         WARN(dev_priv->pc8.disable_count < 1,
6420              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6421
6422         dev_priv->pc8.disable_count--;
6423         if (dev_priv->pc8.disable_count != 0)
6424                 return;
6425
6426         schedule_delayed_work(&dev_priv->pc8.enable_work,
6427                               msecs_to_jiffies(i915_pc8_timeout));
6428 }
6429
6430 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6431 {
6432         struct drm_device *dev = dev_priv->dev;
6433         uint32_t val;
6434
6435         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6436         WARN(dev_priv->pc8.disable_count < 0,
6437              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6438
6439         dev_priv->pc8.disable_count++;
6440         if (dev_priv->pc8.disable_count != 1)
6441                 return;
6442
6443         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6444         if (!dev_priv->pc8.enabled)
6445                 return;
6446
6447         DRM_DEBUG_KMS("Disabling package C8+\n");
6448
6449         hsw_restore_lcpll(dev_priv);
6450         hsw_pc8_restore_interrupts(dev);
6451         lpt_init_pch_refclk(dev);
6452
6453         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6454                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6455                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6456                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6457         }
6458
6459         intel_prepare_ddi(dev);
6460         i915_gem_init_swizzling(dev);
6461         mutex_lock(&dev_priv->rps.hw_lock);
6462         gen6_update_ring_freq(dev);
6463         mutex_unlock(&dev_priv->rps.hw_lock);
6464         dev_priv->pc8.enabled = false;
6465 }
6466
6467 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6468 {
6469         mutex_lock(&dev_priv->pc8.lock);
6470         __hsw_enable_package_c8(dev_priv);
6471         mutex_unlock(&dev_priv->pc8.lock);
6472 }
6473
6474 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6475 {
6476         mutex_lock(&dev_priv->pc8.lock);
6477         __hsw_disable_package_c8(dev_priv);
6478         mutex_unlock(&dev_priv->pc8.lock);
6479 }
6480
6481 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6482 {
6483         struct drm_device *dev = dev_priv->dev;
6484         struct intel_crtc *crtc;
6485         uint32_t val;
6486
6487         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6488                 if (crtc->base.enabled)
6489                         return false;
6490
6491         /* This case is still possible since we have the i915.disable_power_well
6492          * parameter and also the KVMr or something else might be requesting the
6493          * power well. */
6494         val = I915_READ(HSW_PWR_WELL_DRIVER);
6495         if (val != 0) {
6496                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6497                 return false;
6498         }
6499
6500         return true;
6501 }
6502
6503 /* Since we're called from modeset_global_resources there's no way to
6504  * symmetrically increase and decrease the refcount, so we use
6505  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6506  * or not.
6507  */
6508 static void hsw_update_package_c8(struct drm_device *dev)
6509 {
6510         struct drm_i915_private *dev_priv = dev->dev_private;
6511         bool allow;
6512
6513         if (!i915_enable_pc8)
6514                 return;
6515
6516         mutex_lock(&dev_priv->pc8.lock);
6517
6518         allow = hsw_can_enable_package_c8(dev_priv);
6519
6520         if (allow == dev_priv->pc8.requirements_met)
6521                 goto done;
6522
6523         dev_priv->pc8.requirements_met = allow;
6524
6525         if (allow)
6526                 __hsw_enable_package_c8(dev_priv);
6527         else
6528                 __hsw_disable_package_c8(dev_priv);
6529
6530 done:
6531         mutex_unlock(&dev_priv->pc8.lock);
6532 }
6533
6534 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6535 {
6536         if (!dev_priv->pc8.gpu_idle) {
6537                 dev_priv->pc8.gpu_idle = true;
6538                 hsw_enable_package_c8(dev_priv);
6539         }
6540 }
6541
6542 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6543 {
6544         if (dev_priv->pc8.gpu_idle) {
6545                 dev_priv->pc8.gpu_idle = false;
6546                 hsw_disable_package_c8(dev_priv);
6547         }
6548 }
6549
6550 static void haswell_modeset_global_resources(struct drm_device *dev)
6551 {
6552         bool enable = false;
6553         struct intel_crtc *crtc;
6554
6555         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6556                 if (!crtc->base.enabled)
6557                         continue;
6558
6559                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6560                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6561                         enable = true;
6562         }
6563
6564         intel_set_power_well(dev, enable);
6565
6566         hsw_update_package_c8(dev);
6567 }
6568
6569 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6570                                  int x, int y,
6571                                  struct drm_framebuffer *fb)
6572 {
6573         struct drm_device *dev = crtc->dev;
6574         struct drm_i915_private *dev_priv = dev->dev_private;
6575         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6576         int plane = intel_crtc->plane;
6577         int ret;
6578
6579         if (!intel_ddi_pll_mode_set(crtc))
6580                 return -EINVAL;
6581
6582         if (intel_crtc->config.has_dp_encoder)
6583                 intel_dp_set_m_n(intel_crtc);
6584
6585         intel_crtc->lowfreq_avail = false;
6586
6587         intel_set_pipe_timings(intel_crtc);
6588
6589         if (intel_crtc->config.has_pch_encoder) {
6590                 intel_cpu_transcoder_set_m_n(intel_crtc,
6591                                              &intel_crtc->config.fdi_m_n);
6592         }
6593
6594         haswell_set_pipeconf(crtc);
6595
6596         intel_set_pipe_csc(crtc);
6597
6598         /* Set up the display plane register */
6599         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6600         POSTING_READ(DSPCNTR(plane));
6601
6602         ret = intel_pipe_set_base(crtc, x, y, fb);
6603
6604         return ret;
6605 }
6606
6607 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6608                                     struct intel_crtc_config *pipe_config)
6609 {
6610         struct drm_device *dev = crtc->base.dev;
6611         struct drm_i915_private *dev_priv = dev->dev_private;
6612         enum intel_display_power_domain pfit_domain;
6613         uint32_t tmp;
6614
6615         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6616         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6617
6618         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6619         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6620                 enum pipe trans_edp_pipe;
6621                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6622                 default:
6623                         WARN(1, "unknown pipe linked to edp transcoder\n");
6624                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6625                 case TRANS_DDI_EDP_INPUT_A_ON:
6626                         trans_edp_pipe = PIPE_A;
6627                         break;
6628                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6629                         trans_edp_pipe = PIPE_B;
6630                         break;
6631                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6632                         trans_edp_pipe = PIPE_C;
6633                         break;
6634                 }
6635
6636                 if (trans_edp_pipe == crtc->pipe)
6637                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6638         }
6639
6640         if (!intel_display_power_enabled(dev,
6641                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6642                 return false;
6643
6644         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6645         if (!(tmp & PIPECONF_ENABLE))
6646                 return false;
6647
6648         /*
6649          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6650          * DDI E. So just check whether this pipe is wired to DDI E and whether
6651          * the PCH transcoder is on.
6652          */
6653         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6654         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6655             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6656                 pipe_config->has_pch_encoder = true;
6657
6658                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6659                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6660                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6661
6662                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6663         }
6664
6665         intel_get_pipe_timings(crtc, pipe_config);
6666
6667         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6668         if (intel_display_power_enabled(dev, pfit_domain))
6669                 ironlake_get_pfit_config(crtc, pipe_config);
6670
6671         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6672                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6673
6674         pipe_config->pixel_multiplier = 1;
6675
6676         return true;
6677 }
6678
6679 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6680                                int x, int y,
6681                                struct drm_framebuffer *fb)
6682 {
6683         struct drm_device *dev = crtc->dev;
6684         struct drm_i915_private *dev_priv = dev->dev_private;
6685         struct intel_encoder *encoder;
6686         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6687         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6688         int pipe = intel_crtc->pipe;
6689         int ret;
6690
6691         drm_vblank_pre_modeset(dev, pipe);
6692
6693         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6694
6695         drm_vblank_post_modeset(dev, pipe);
6696
6697         if (ret != 0)
6698                 return ret;
6699
6700         for_each_encoder_on_crtc(dev, crtc, encoder) {
6701                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6702                         encoder->base.base.id,
6703                         drm_get_encoder_name(&encoder->base),
6704                         mode->base.id, mode->name);
6705                 encoder->mode_set(encoder);
6706         }
6707
6708         return 0;
6709 }
6710
6711 static bool intel_eld_uptodate(struct drm_connector *connector,
6712                                int reg_eldv, uint32_t bits_eldv,
6713                                int reg_elda, uint32_t bits_elda,
6714                                int reg_edid)
6715 {
6716         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6717         uint8_t *eld = connector->eld;
6718         uint32_t i;
6719
6720         i = I915_READ(reg_eldv);
6721         i &= bits_eldv;
6722
6723         if (!eld[0])
6724                 return !i;
6725
6726         if (!i)
6727                 return false;
6728
6729         i = I915_READ(reg_elda);
6730         i &= ~bits_elda;
6731         I915_WRITE(reg_elda, i);
6732
6733         for (i = 0; i < eld[2]; i++)
6734                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6735                         return false;
6736
6737         return true;
6738 }
6739
6740 static void g4x_write_eld(struct drm_connector *connector,
6741                           struct drm_crtc *crtc)
6742 {
6743         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6744         uint8_t *eld = connector->eld;
6745         uint32_t eldv;
6746         uint32_t len;
6747         uint32_t i;
6748
6749         i = I915_READ(G4X_AUD_VID_DID);
6750
6751         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6752                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6753         else
6754                 eldv = G4X_ELDV_DEVCTG;
6755
6756         if (intel_eld_uptodate(connector,
6757                                G4X_AUD_CNTL_ST, eldv,
6758                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6759                                G4X_HDMIW_HDMIEDID))
6760                 return;
6761
6762         i = I915_READ(G4X_AUD_CNTL_ST);
6763         i &= ~(eldv | G4X_ELD_ADDR);
6764         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6765         I915_WRITE(G4X_AUD_CNTL_ST, i);
6766
6767         if (!eld[0])
6768                 return;
6769
6770         len = min_t(uint8_t, eld[2], len);
6771         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6772         for (i = 0; i < len; i++)
6773                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6774
6775         i = I915_READ(G4X_AUD_CNTL_ST);
6776         i |= eldv;
6777         I915_WRITE(G4X_AUD_CNTL_ST, i);
6778 }
6779
6780 static void haswell_write_eld(struct drm_connector *connector,
6781                                      struct drm_crtc *crtc)
6782 {
6783         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6784         uint8_t *eld = connector->eld;
6785         struct drm_device *dev = crtc->dev;
6786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6787         uint32_t eldv;
6788         uint32_t i;
6789         int len;
6790         int pipe = to_intel_crtc(crtc)->pipe;
6791         int tmp;
6792
6793         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6794         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6795         int aud_config = HSW_AUD_CFG(pipe);
6796         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6797
6798
6799         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6800
6801         /* Audio output enable */
6802         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6803         tmp = I915_READ(aud_cntrl_st2);
6804         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6805         I915_WRITE(aud_cntrl_st2, tmp);
6806
6807         /* Wait for 1 vertical blank */
6808         intel_wait_for_vblank(dev, pipe);
6809
6810         /* Set ELD valid state */
6811         tmp = I915_READ(aud_cntrl_st2);
6812         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6813         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6814         I915_WRITE(aud_cntrl_st2, tmp);
6815         tmp = I915_READ(aud_cntrl_st2);
6816         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6817
6818         /* Enable HDMI mode */
6819         tmp = I915_READ(aud_config);
6820         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6821         /* clear N_programing_enable and N_value_index */
6822         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6823         I915_WRITE(aud_config, tmp);
6824
6825         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6826
6827         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6828         intel_crtc->eld_vld = true;
6829
6830         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6831                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6832                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6833                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6834         } else
6835                 I915_WRITE(aud_config, 0);
6836
6837         if (intel_eld_uptodate(connector,
6838                                aud_cntrl_st2, eldv,
6839                                aud_cntl_st, IBX_ELD_ADDRESS,
6840                                hdmiw_hdmiedid))
6841                 return;
6842
6843         i = I915_READ(aud_cntrl_st2);
6844         i &= ~eldv;
6845         I915_WRITE(aud_cntrl_st2, i);
6846
6847         if (!eld[0])
6848                 return;
6849
6850         i = I915_READ(aud_cntl_st);
6851         i &= ~IBX_ELD_ADDRESS;
6852         I915_WRITE(aud_cntl_st, i);
6853         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6854         DRM_DEBUG_DRIVER("port num:%d\n", i);
6855
6856         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6857         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6858         for (i = 0; i < len; i++)
6859                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6860
6861         i = I915_READ(aud_cntrl_st2);
6862         i |= eldv;
6863         I915_WRITE(aud_cntrl_st2, i);
6864
6865 }
6866
6867 static void ironlake_write_eld(struct drm_connector *connector,
6868                                      struct drm_crtc *crtc)
6869 {
6870         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6871         uint8_t *eld = connector->eld;
6872         uint32_t eldv;
6873         uint32_t i;
6874         int len;
6875         int hdmiw_hdmiedid;
6876         int aud_config;
6877         int aud_cntl_st;
6878         int aud_cntrl_st2;
6879         int pipe = to_intel_crtc(crtc)->pipe;
6880
6881         if (HAS_PCH_IBX(connector->dev)) {
6882                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6883                 aud_config = IBX_AUD_CFG(pipe);
6884                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6885                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6886         } else {
6887                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6888                 aud_config = CPT_AUD_CFG(pipe);
6889                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6890                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6891         }
6892
6893         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6894
6895         i = I915_READ(aud_cntl_st);
6896         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6897         if (!i) {
6898                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6899                 /* operate blindly on all ports */
6900                 eldv = IBX_ELD_VALIDB;
6901                 eldv |= IBX_ELD_VALIDB << 4;
6902                 eldv |= IBX_ELD_VALIDB << 8;
6903         } else {
6904                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6905                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6906         }
6907
6908         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6909                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6910                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6911                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6912         } else
6913                 I915_WRITE(aud_config, 0);
6914
6915         if (intel_eld_uptodate(connector,
6916                                aud_cntrl_st2, eldv,
6917                                aud_cntl_st, IBX_ELD_ADDRESS,
6918                                hdmiw_hdmiedid))
6919                 return;
6920
6921         i = I915_READ(aud_cntrl_st2);
6922         i &= ~eldv;
6923         I915_WRITE(aud_cntrl_st2, i);
6924
6925         if (!eld[0])
6926                 return;
6927
6928         i = I915_READ(aud_cntl_st);
6929         i &= ~IBX_ELD_ADDRESS;
6930         I915_WRITE(aud_cntl_st, i);
6931
6932         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6933         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6934         for (i = 0; i < len; i++)
6935                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6936
6937         i = I915_READ(aud_cntrl_st2);
6938         i |= eldv;
6939         I915_WRITE(aud_cntrl_st2, i);
6940 }
6941
6942 void intel_write_eld(struct drm_encoder *encoder,
6943                      struct drm_display_mode *mode)
6944 {
6945         struct drm_crtc *crtc = encoder->crtc;
6946         struct drm_connector *connector;
6947         struct drm_device *dev = encoder->dev;
6948         struct drm_i915_private *dev_priv = dev->dev_private;
6949
6950         connector = drm_select_eld(encoder, mode);
6951         if (!connector)
6952                 return;
6953
6954         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6955                          connector->base.id,
6956                          drm_get_connector_name(connector),
6957                          connector->encoder->base.id,
6958                          drm_get_encoder_name(connector->encoder));
6959
6960         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6961
6962         if (dev_priv->display.write_eld)
6963                 dev_priv->display.write_eld(connector, crtc);
6964 }
6965
6966 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6967 {
6968         struct drm_device *dev = crtc->dev;
6969         struct drm_i915_private *dev_priv = dev->dev_private;
6970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6971         bool visible = base != 0;
6972         u32 cntl;
6973
6974         if (intel_crtc->cursor_visible == visible)
6975                 return;
6976
6977         cntl = I915_READ(_CURACNTR);
6978         if (visible) {
6979                 /* On these chipsets we can only modify the base whilst
6980                  * the cursor is disabled.
6981                  */
6982                 I915_WRITE(_CURABASE, base);
6983
6984                 cntl &= ~(CURSOR_FORMAT_MASK);
6985                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6986                 cntl |= CURSOR_ENABLE |
6987                         CURSOR_GAMMA_ENABLE |
6988                         CURSOR_FORMAT_ARGB;
6989         } else
6990                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6991         I915_WRITE(_CURACNTR, cntl);
6992
6993         intel_crtc->cursor_visible = visible;
6994 }
6995
6996 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6997 {
6998         struct drm_device *dev = crtc->dev;
6999         struct drm_i915_private *dev_priv = dev->dev_private;
7000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7001         int pipe = intel_crtc->pipe;
7002         bool visible = base != 0;
7003
7004         if (intel_crtc->cursor_visible != visible) {
7005                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7006                 if (base) {
7007                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7008                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7009                         cntl |= pipe << 28; /* Connect to correct pipe */
7010                 } else {
7011                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7012                         cntl |= CURSOR_MODE_DISABLE;
7013                 }
7014                 I915_WRITE(CURCNTR(pipe), cntl);
7015
7016                 intel_crtc->cursor_visible = visible;
7017         }
7018         /* and commit changes on next vblank */
7019         I915_WRITE(CURBASE(pipe), base);
7020 }
7021
7022 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7023 {
7024         struct drm_device *dev = crtc->dev;
7025         struct drm_i915_private *dev_priv = dev->dev_private;
7026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7027         int pipe = intel_crtc->pipe;
7028         bool visible = base != 0;
7029
7030         if (intel_crtc->cursor_visible != visible) {
7031                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7032                 if (base) {
7033                         cntl &= ~CURSOR_MODE;
7034                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7035                 } else {
7036                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7037                         cntl |= CURSOR_MODE_DISABLE;
7038                 }
7039                 if (IS_HASWELL(dev)) {
7040                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7041                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7042                 }
7043                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7044
7045                 intel_crtc->cursor_visible = visible;
7046         }
7047         /* and commit changes on next vblank */
7048         I915_WRITE(CURBASE_IVB(pipe), base);
7049 }
7050
7051 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7052 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7053                                      bool on)
7054 {
7055         struct drm_device *dev = crtc->dev;
7056         struct drm_i915_private *dev_priv = dev->dev_private;
7057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7058         int pipe = intel_crtc->pipe;
7059         int x = intel_crtc->cursor_x;
7060         int y = intel_crtc->cursor_y;
7061         u32 base = 0, pos = 0;
7062         bool visible;
7063
7064         if (on)
7065                 base = intel_crtc->cursor_addr;
7066
7067         if (x >= intel_crtc->config.pipe_src_w)
7068                 base = 0;
7069
7070         if (y >= intel_crtc->config.pipe_src_h)
7071                 base = 0;
7072
7073         if (x < 0) {
7074                 if (x + intel_crtc->cursor_width <= 0)
7075                         base = 0;
7076
7077                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7078                 x = -x;
7079         }
7080         pos |= x << CURSOR_X_SHIFT;
7081
7082         if (y < 0) {
7083                 if (y + intel_crtc->cursor_height <= 0)
7084                         base = 0;
7085
7086                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7087                 y = -y;
7088         }
7089         pos |= y << CURSOR_Y_SHIFT;
7090
7091         visible = base != 0;
7092         if (!visible && !intel_crtc->cursor_visible)
7093                 return;
7094
7095         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7096                 I915_WRITE(CURPOS_IVB(pipe), pos);
7097                 ivb_update_cursor(crtc, base);
7098         } else {
7099                 I915_WRITE(CURPOS(pipe), pos);
7100                 if (IS_845G(dev) || IS_I865G(dev))
7101                         i845_update_cursor(crtc, base);
7102                 else
7103                         i9xx_update_cursor(crtc, base);
7104         }
7105 }
7106
7107 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7108                                  struct drm_file *file,
7109                                  uint32_t handle,
7110                                  uint32_t width, uint32_t height)
7111 {
7112         struct drm_device *dev = crtc->dev;
7113         struct drm_i915_private *dev_priv = dev->dev_private;
7114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7115         struct drm_i915_gem_object *obj;
7116         uint32_t addr;
7117         int ret;
7118
7119         /* if we want to turn off the cursor ignore width and height */
7120         if (!handle) {
7121                 DRM_DEBUG_KMS("cursor off\n");
7122                 addr = 0;
7123                 obj = NULL;
7124                 mutex_lock(&dev->struct_mutex);
7125                 goto finish;
7126         }
7127
7128         /* Currently we only support 64x64 cursors */
7129         if (width != 64 || height != 64) {
7130                 DRM_ERROR("we currently only support 64x64 cursors\n");
7131                 return -EINVAL;
7132         }
7133
7134         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7135         if (&obj->base == NULL)
7136                 return -ENOENT;
7137
7138         if (obj->base.size < width * height * 4) {
7139                 DRM_ERROR("buffer is to small\n");
7140                 ret = -ENOMEM;
7141                 goto fail;
7142         }
7143
7144         /* we only need to pin inside GTT if cursor is non-phy */
7145         mutex_lock(&dev->struct_mutex);
7146         if (!dev_priv->info->cursor_needs_physical) {
7147                 unsigned alignment;
7148
7149                 if (obj->tiling_mode) {
7150                         DRM_ERROR("cursor cannot be tiled\n");
7151                         ret = -EINVAL;
7152                         goto fail_locked;
7153                 }
7154
7155                 /* Note that the w/a also requires 2 PTE of padding following
7156                  * the bo. We currently fill all unused PTE with the shadow
7157                  * page and so we should always have valid PTE following the
7158                  * cursor preventing the VT-d warning.
7159                  */
7160                 alignment = 0;
7161                 if (need_vtd_wa(dev))
7162                         alignment = 64*1024;
7163
7164                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7165                 if (ret) {
7166                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7167                         goto fail_locked;
7168                 }
7169
7170                 ret = i915_gem_object_put_fence(obj);
7171                 if (ret) {
7172                         DRM_ERROR("failed to release fence for cursor");
7173                         goto fail_unpin;
7174                 }
7175
7176                 addr = i915_gem_obj_ggtt_offset(obj);
7177         } else {
7178                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7179                 ret = i915_gem_attach_phys_object(dev, obj,
7180                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7181                                                   align);
7182                 if (ret) {
7183                         DRM_ERROR("failed to attach phys object\n");
7184                         goto fail_locked;
7185                 }
7186                 addr = obj->phys_obj->handle->busaddr;
7187         }
7188
7189         if (IS_GEN2(dev))
7190                 I915_WRITE(CURSIZE, (height << 12) | width);
7191
7192  finish:
7193         if (intel_crtc->cursor_bo) {
7194                 if (dev_priv->info->cursor_needs_physical) {
7195                         if (intel_crtc->cursor_bo != obj)
7196                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7197                 } else
7198                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7199                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7200         }
7201
7202         mutex_unlock(&dev->struct_mutex);
7203
7204         intel_crtc->cursor_addr = addr;
7205         intel_crtc->cursor_bo = obj;
7206         intel_crtc->cursor_width = width;
7207         intel_crtc->cursor_height = height;
7208
7209         if (intel_crtc->active)
7210                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7211
7212         return 0;
7213 fail_unpin:
7214         i915_gem_object_unpin_from_display_plane(obj);
7215 fail_locked:
7216         mutex_unlock(&dev->struct_mutex);
7217 fail:
7218         drm_gem_object_unreference_unlocked(&obj->base);
7219         return ret;
7220 }
7221
7222 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7223 {
7224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7225
7226         intel_crtc->cursor_x = x;
7227         intel_crtc->cursor_y = y;
7228
7229         if (intel_crtc->active)
7230                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7231
7232         return 0;
7233 }
7234
7235 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7236                                  u16 *blue, uint32_t start, uint32_t size)
7237 {
7238         int end = (start + size > 256) ? 256 : start + size, i;
7239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7240
7241         for (i = start; i < end; i++) {
7242                 intel_crtc->lut_r[i] = red[i] >> 8;
7243                 intel_crtc->lut_g[i] = green[i] >> 8;
7244                 intel_crtc->lut_b[i] = blue[i] >> 8;
7245         }
7246
7247         intel_crtc_load_lut(crtc);
7248 }
7249
7250 /* VESA 640x480x72Hz mode to set on the pipe */
7251 static struct drm_display_mode load_detect_mode = {
7252         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7253                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7254 };
7255
7256 static struct drm_framebuffer *
7257 intel_framebuffer_create(struct drm_device *dev,
7258                          struct drm_mode_fb_cmd2 *mode_cmd,
7259                          struct drm_i915_gem_object *obj)
7260 {
7261         struct intel_framebuffer *intel_fb;
7262         int ret;
7263
7264         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7265         if (!intel_fb) {
7266                 drm_gem_object_unreference_unlocked(&obj->base);
7267                 return ERR_PTR(-ENOMEM);
7268         }
7269
7270         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7271         if (ret) {
7272                 drm_gem_object_unreference_unlocked(&obj->base);
7273                 kfree(intel_fb);
7274                 return ERR_PTR(ret);
7275         }
7276
7277         return &intel_fb->base;
7278 }
7279
7280 static u32
7281 intel_framebuffer_pitch_for_width(int width, int bpp)
7282 {
7283         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7284         return ALIGN(pitch, 64);
7285 }
7286
7287 static u32
7288 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7289 {
7290         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7291         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7292 }
7293
7294 static struct drm_framebuffer *
7295 intel_framebuffer_create_for_mode(struct drm_device *dev,
7296                                   struct drm_display_mode *mode,
7297                                   int depth, int bpp)
7298 {
7299         struct drm_i915_gem_object *obj;
7300         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7301
7302         obj = i915_gem_alloc_object(dev,
7303                                     intel_framebuffer_size_for_mode(mode, bpp));
7304         if (obj == NULL)
7305                 return ERR_PTR(-ENOMEM);
7306
7307         mode_cmd.width = mode->hdisplay;
7308         mode_cmd.height = mode->vdisplay;
7309         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7310                                                                 bpp);
7311         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7312
7313         return intel_framebuffer_create(dev, &mode_cmd, obj);
7314 }
7315
7316 static struct drm_framebuffer *
7317 mode_fits_in_fbdev(struct drm_device *dev,
7318                    struct drm_display_mode *mode)
7319 {
7320         struct drm_i915_private *dev_priv = dev->dev_private;
7321         struct drm_i915_gem_object *obj;
7322         struct drm_framebuffer *fb;
7323
7324         if (dev_priv->fbdev == NULL)
7325                 return NULL;
7326
7327         obj = dev_priv->fbdev->ifb.obj;
7328         if (obj == NULL)
7329                 return NULL;
7330
7331         fb = &dev_priv->fbdev->ifb.base;
7332         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7333                                                                fb->bits_per_pixel))
7334                 return NULL;
7335
7336         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7337                 return NULL;
7338
7339         return fb;
7340 }
7341
7342 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7343                                 struct drm_display_mode *mode,
7344                                 struct intel_load_detect_pipe *old)
7345 {
7346         struct intel_crtc *intel_crtc;
7347         struct intel_encoder *intel_encoder =
7348                 intel_attached_encoder(connector);
7349         struct drm_crtc *possible_crtc;
7350         struct drm_encoder *encoder = &intel_encoder->base;
7351         struct drm_crtc *crtc = NULL;
7352         struct drm_device *dev = encoder->dev;
7353         struct drm_framebuffer *fb;
7354         int i = -1;
7355
7356         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7357                       connector->base.id, drm_get_connector_name(connector),
7358                       encoder->base.id, drm_get_encoder_name(encoder));
7359
7360         /*
7361          * Algorithm gets a little messy:
7362          *
7363          *   - if the connector already has an assigned crtc, use it (but make
7364          *     sure it's on first)
7365          *
7366          *   - try to find the first unused crtc that can drive this connector,
7367          *     and use that if we find one
7368          */
7369
7370         /* See if we already have a CRTC for this connector */
7371         if (encoder->crtc) {
7372                 crtc = encoder->crtc;
7373
7374                 mutex_lock(&crtc->mutex);
7375
7376                 old->dpms_mode = connector->dpms;
7377                 old->load_detect_temp = false;
7378
7379                 /* Make sure the crtc and connector are running */
7380                 if (connector->dpms != DRM_MODE_DPMS_ON)
7381                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7382
7383                 return true;
7384         }
7385
7386         /* Find an unused one (if possible) */
7387         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7388                 i++;
7389                 if (!(encoder->possible_crtcs & (1 << i)))
7390                         continue;
7391                 if (!possible_crtc->enabled) {
7392                         crtc = possible_crtc;
7393                         break;
7394                 }
7395         }
7396
7397         /*
7398          * If we didn't find an unused CRTC, don't use any.
7399          */
7400         if (!crtc) {
7401                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7402                 return false;
7403         }
7404
7405         mutex_lock(&crtc->mutex);
7406         intel_encoder->new_crtc = to_intel_crtc(crtc);
7407         to_intel_connector(connector)->new_encoder = intel_encoder;
7408
7409         intel_crtc = to_intel_crtc(crtc);
7410         old->dpms_mode = connector->dpms;
7411         old->load_detect_temp = true;
7412         old->release_fb = NULL;
7413
7414         if (!mode)
7415                 mode = &load_detect_mode;
7416
7417         /* We need a framebuffer large enough to accommodate all accesses
7418          * that the plane may generate whilst we perform load detection.
7419          * We can not rely on the fbcon either being present (we get called
7420          * during its initialisation to detect all boot displays, or it may
7421          * not even exist) or that it is large enough to satisfy the
7422          * requested mode.
7423          */
7424         fb = mode_fits_in_fbdev(dev, mode);
7425         if (fb == NULL) {
7426                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7427                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7428                 old->release_fb = fb;
7429         } else
7430                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7431         if (IS_ERR(fb)) {
7432                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7433                 mutex_unlock(&crtc->mutex);
7434                 return false;
7435         }
7436
7437         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7438                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7439                 if (old->release_fb)
7440                         old->release_fb->funcs->destroy(old->release_fb);
7441                 mutex_unlock(&crtc->mutex);
7442                 return false;
7443         }
7444
7445         /* let the connector get through one full cycle before testing */
7446         intel_wait_for_vblank(dev, intel_crtc->pipe);
7447         return true;
7448 }
7449
7450 void intel_release_load_detect_pipe(struct drm_connector *connector,
7451                                     struct intel_load_detect_pipe *old)
7452 {
7453         struct intel_encoder *intel_encoder =
7454                 intel_attached_encoder(connector);
7455         struct drm_encoder *encoder = &intel_encoder->base;
7456         struct drm_crtc *crtc = encoder->crtc;
7457
7458         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7459                       connector->base.id, drm_get_connector_name(connector),
7460                       encoder->base.id, drm_get_encoder_name(encoder));
7461
7462         if (old->load_detect_temp) {
7463                 to_intel_connector(connector)->new_encoder = NULL;
7464                 intel_encoder->new_crtc = NULL;
7465                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7466
7467                 if (old->release_fb) {
7468                         drm_framebuffer_unregister_private(old->release_fb);
7469                         drm_framebuffer_unreference(old->release_fb);
7470                 }
7471
7472                 mutex_unlock(&crtc->mutex);
7473                 return;
7474         }
7475
7476         /* Switch crtc and encoder back off if necessary */
7477         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7478                 connector->funcs->dpms(connector, old->dpms_mode);
7479
7480         mutex_unlock(&crtc->mutex);
7481 }
7482
7483 static int i9xx_pll_refclk(struct drm_device *dev,
7484                            const struct intel_crtc_config *pipe_config)
7485 {
7486         struct drm_i915_private *dev_priv = dev->dev_private;
7487         u32 dpll = pipe_config->dpll_hw_state.dpll;
7488
7489         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7490                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7491         else if (HAS_PCH_SPLIT(dev))
7492                 return 120000;
7493         else if (!IS_GEN2(dev))
7494                 return 96000;
7495         else
7496                 return 48000;
7497 }
7498
7499 /* Returns the clock of the currently programmed mode of the given pipe. */
7500 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7501                                 struct intel_crtc_config *pipe_config)
7502 {
7503         struct drm_device *dev = crtc->base.dev;
7504         struct drm_i915_private *dev_priv = dev->dev_private;
7505         int pipe = pipe_config->cpu_transcoder;
7506         u32 dpll = pipe_config->dpll_hw_state.dpll;
7507         u32 fp;
7508         intel_clock_t clock;
7509         int refclk = i9xx_pll_refclk(dev, pipe_config);
7510
7511         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7512                 fp = pipe_config->dpll_hw_state.fp0;
7513         else
7514                 fp = pipe_config->dpll_hw_state.fp1;
7515
7516         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7517         if (IS_PINEVIEW(dev)) {
7518                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7519                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7520         } else {
7521                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7522                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7523         }
7524
7525         if (!IS_GEN2(dev)) {
7526                 if (IS_PINEVIEW(dev))
7527                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7528                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7529                 else
7530                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7531                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7532
7533                 switch (dpll & DPLL_MODE_MASK) {
7534                 case DPLLB_MODE_DAC_SERIAL:
7535                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7536                                 5 : 10;
7537                         break;
7538                 case DPLLB_MODE_LVDS:
7539                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7540                                 7 : 14;
7541                         break;
7542                 default:
7543                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7544                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7545                         return;
7546                 }
7547
7548                 if (IS_PINEVIEW(dev))
7549                         pineview_clock(refclk, &clock);
7550                 else
7551                         i9xx_clock(refclk, &clock);
7552         } else {
7553                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7554
7555                 if (is_lvds) {
7556                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7557                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7558                         clock.p2 = 14;
7559                 } else {
7560                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7561                                 clock.p1 = 2;
7562                         else {
7563                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7564                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7565                         }
7566                         if (dpll & PLL_P2_DIVIDE_BY_4)
7567                                 clock.p2 = 4;
7568                         else
7569                                 clock.p2 = 2;
7570                 }
7571
7572                 i9xx_clock(refclk, &clock);
7573         }
7574
7575         /*
7576          * This value includes pixel_multiplier. We will use
7577          * port_clock to compute adjusted_mode.crtc_clock in the
7578          * encoder's get_config() function.
7579          */
7580         pipe_config->port_clock = clock.dot;
7581 }
7582
7583 int intel_dotclock_calculate(int link_freq,
7584                              const struct intel_link_m_n *m_n)
7585 {
7586         /*
7587          * The calculation for the data clock is:
7588          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7589          * But we want to avoid losing precison if possible, so:
7590          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7591          *
7592          * and the link clock is simpler:
7593          * link_clock = (m * link_clock) / n
7594          */
7595
7596         if (!m_n->link_n)
7597                 return 0;
7598
7599         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7600 }
7601
7602 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7603                                    struct intel_crtc_config *pipe_config)
7604 {
7605         struct drm_device *dev = crtc->base.dev;
7606
7607         /* read out port_clock from the DPLL */
7608         i9xx_crtc_clock_get(crtc, pipe_config);
7609
7610         /*
7611          * This value does not include pixel_multiplier.
7612          * We will check that port_clock and adjusted_mode.crtc_clock
7613          * agree once we know their relationship in the encoder's
7614          * get_config() function.
7615          */
7616         pipe_config->adjusted_mode.crtc_clock =
7617                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7618                                          &pipe_config->fdi_m_n);
7619 }
7620
7621 /** Returns the currently programmed mode of the given pipe. */
7622 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7623                                              struct drm_crtc *crtc)
7624 {
7625         struct drm_i915_private *dev_priv = dev->dev_private;
7626         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7627         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7628         struct drm_display_mode *mode;
7629         struct intel_crtc_config pipe_config;
7630         int htot = I915_READ(HTOTAL(cpu_transcoder));
7631         int hsync = I915_READ(HSYNC(cpu_transcoder));
7632         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7633         int vsync = I915_READ(VSYNC(cpu_transcoder));
7634         enum pipe pipe = intel_crtc->pipe;
7635
7636         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7637         if (!mode)
7638                 return NULL;
7639
7640         /*
7641          * Construct a pipe_config sufficient for getting the clock info
7642          * back out of crtc_clock_get.
7643          *
7644          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7645          * to use a real value here instead.
7646          */
7647         pipe_config.cpu_transcoder = (enum transcoder) pipe;
7648         pipe_config.pixel_multiplier = 1;
7649         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7650         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7651         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7652         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7653
7654         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
7655         mode->hdisplay = (htot & 0xffff) + 1;
7656         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7657         mode->hsync_start = (hsync & 0xffff) + 1;
7658         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7659         mode->vdisplay = (vtot & 0xffff) + 1;
7660         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7661         mode->vsync_start = (vsync & 0xffff) + 1;
7662         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7663
7664         drm_mode_set_name(mode);
7665
7666         return mode;
7667 }
7668
7669 static void intel_increase_pllclock(struct drm_crtc *crtc)
7670 {
7671         struct drm_device *dev = crtc->dev;
7672         drm_i915_private_t *dev_priv = dev->dev_private;
7673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7674         int pipe = intel_crtc->pipe;
7675         int dpll_reg = DPLL(pipe);
7676         int dpll;
7677
7678         if (HAS_PCH_SPLIT(dev))
7679                 return;
7680
7681         if (!dev_priv->lvds_downclock_avail)
7682                 return;
7683
7684         dpll = I915_READ(dpll_reg);
7685         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7686                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7687
7688                 assert_panel_unlocked(dev_priv, pipe);
7689
7690                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7691                 I915_WRITE(dpll_reg, dpll);
7692                 intel_wait_for_vblank(dev, pipe);
7693
7694                 dpll = I915_READ(dpll_reg);
7695                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7696                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7697         }
7698 }
7699
7700 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7701 {
7702         struct drm_device *dev = crtc->dev;
7703         drm_i915_private_t *dev_priv = dev->dev_private;
7704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7705
7706         if (HAS_PCH_SPLIT(dev))
7707                 return;
7708
7709         if (!dev_priv->lvds_downclock_avail)
7710                 return;
7711
7712         /*
7713          * Since this is called by a timer, we should never get here in
7714          * the manual case.
7715          */
7716         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7717                 int pipe = intel_crtc->pipe;
7718                 int dpll_reg = DPLL(pipe);
7719                 int dpll;
7720
7721                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7722
7723                 assert_panel_unlocked(dev_priv, pipe);
7724
7725                 dpll = I915_READ(dpll_reg);
7726                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7727                 I915_WRITE(dpll_reg, dpll);
7728                 intel_wait_for_vblank(dev, pipe);
7729                 dpll = I915_READ(dpll_reg);
7730                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7731                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7732         }
7733
7734 }
7735
7736 void intel_mark_busy(struct drm_device *dev)
7737 {
7738         struct drm_i915_private *dev_priv = dev->dev_private;
7739
7740         hsw_package_c8_gpu_busy(dev_priv);
7741         i915_update_gfx_val(dev_priv);
7742 }
7743
7744 void intel_mark_idle(struct drm_device *dev)
7745 {
7746         struct drm_i915_private *dev_priv = dev->dev_private;
7747         struct drm_crtc *crtc;
7748
7749         hsw_package_c8_gpu_idle(dev_priv);
7750
7751         if (!i915_powersave)
7752                 return;
7753
7754         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7755                 if (!crtc->fb)
7756                         continue;
7757
7758                 intel_decrease_pllclock(crtc);
7759         }
7760
7761         if (dev_priv->info->gen >= 6)
7762                 gen6_rps_idle(dev->dev_private);
7763 }
7764
7765 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7766                         struct intel_ring_buffer *ring)
7767 {
7768         struct drm_device *dev = obj->base.dev;
7769         struct drm_crtc *crtc;
7770
7771         if (!i915_powersave)
7772                 return;
7773
7774         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7775                 if (!crtc->fb)
7776                         continue;
7777
7778                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7779                         continue;
7780
7781                 intel_increase_pllclock(crtc);
7782                 if (ring && intel_fbc_enabled(dev))
7783                         ring->fbc_dirty = true;
7784         }
7785 }
7786
7787 static void intel_crtc_destroy(struct drm_crtc *crtc)
7788 {
7789         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7790         struct drm_device *dev = crtc->dev;
7791         struct intel_unpin_work *work;
7792         unsigned long flags;
7793
7794         spin_lock_irqsave(&dev->event_lock, flags);
7795         work = intel_crtc->unpin_work;
7796         intel_crtc->unpin_work = NULL;
7797         spin_unlock_irqrestore(&dev->event_lock, flags);
7798
7799         if (work) {
7800                 cancel_work_sync(&work->work);
7801                 kfree(work);
7802         }
7803
7804         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7805
7806         drm_crtc_cleanup(crtc);
7807
7808         kfree(intel_crtc);
7809 }
7810
7811 static void intel_unpin_work_fn(struct work_struct *__work)
7812 {
7813         struct intel_unpin_work *work =
7814                 container_of(__work, struct intel_unpin_work, work);
7815         struct drm_device *dev = work->crtc->dev;
7816
7817         mutex_lock(&dev->struct_mutex);
7818         intel_unpin_fb_obj(work->old_fb_obj);
7819         drm_gem_object_unreference(&work->pending_flip_obj->base);
7820         drm_gem_object_unreference(&work->old_fb_obj->base);
7821
7822         intel_update_fbc(dev);
7823         mutex_unlock(&dev->struct_mutex);
7824
7825         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7826         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7827
7828         kfree(work);
7829 }
7830
7831 static void do_intel_finish_page_flip(struct drm_device *dev,
7832                                       struct drm_crtc *crtc)
7833 {
7834         drm_i915_private_t *dev_priv = dev->dev_private;
7835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7836         struct intel_unpin_work *work;
7837         unsigned long flags;
7838
7839         /* Ignore early vblank irqs */
7840         if (intel_crtc == NULL)
7841                 return;
7842
7843         spin_lock_irqsave(&dev->event_lock, flags);
7844         work = intel_crtc->unpin_work;
7845
7846         /* Ensure we don't miss a work->pending update ... */
7847         smp_rmb();
7848
7849         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7850                 spin_unlock_irqrestore(&dev->event_lock, flags);
7851                 return;
7852         }
7853
7854         /* and that the unpin work is consistent wrt ->pending. */
7855         smp_rmb();
7856
7857         intel_crtc->unpin_work = NULL;
7858
7859         if (work->event)
7860                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7861
7862         drm_vblank_put(dev, intel_crtc->pipe);
7863
7864         spin_unlock_irqrestore(&dev->event_lock, flags);
7865
7866         wake_up_all(&dev_priv->pending_flip_queue);
7867
7868         queue_work(dev_priv->wq, &work->work);
7869
7870         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7871 }
7872
7873 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7874 {
7875         drm_i915_private_t *dev_priv = dev->dev_private;
7876         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7877
7878         do_intel_finish_page_flip(dev, crtc);
7879 }
7880
7881 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7882 {
7883         drm_i915_private_t *dev_priv = dev->dev_private;
7884         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7885
7886         do_intel_finish_page_flip(dev, crtc);
7887 }
7888
7889 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7890 {
7891         drm_i915_private_t *dev_priv = dev->dev_private;
7892         struct intel_crtc *intel_crtc =
7893                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7894         unsigned long flags;
7895
7896         /* NB: An MMIO update of the plane base pointer will also
7897          * generate a page-flip completion irq, i.e. every modeset
7898          * is also accompanied by a spurious intel_prepare_page_flip().
7899          */
7900         spin_lock_irqsave(&dev->event_lock, flags);
7901         if (intel_crtc->unpin_work)
7902                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7903         spin_unlock_irqrestore(&dev->event_lock, flags);
7904 }
7905
7906 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7907 {
7908         /* Ensure that the work item is consistent when activating it ... */
7909         smp_wmb();
7910         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7911         /* and that it is marked active as soon as the irq could fire. */
7912         smp_wmb();
7913 }
7914
7915 static int intel_gen2_queue_flip(struct drm_device *dev,
7916                                  struct drm_crtc *crtc,
7917                                  struct drm_framebuffer *fb,
7918                                  struct drm_i915_gem_object *obj,
7919                                  uint32_t flags)
7920 {
7921         struct drm_i915_private *dev_priv = dev->dev_private;
7922         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7923         u32 flip_mask;
7924         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7925         int ret;
7926
7927         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7928         if (ret)
7929                 goto err;
7930
7931         ret = intel_ring_begin(ring, 6);
7932         if (ret)
7933                 goto err_unpin;
7934
7935         /* Can't queue multiple flips, so wait for the previous
7936          * one to finish before executing the next.
7937          */
7938         if (intel_crtc->plane)
7939                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7940         else
7941                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7942         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7943         intel_ring_emit(ring, MI_NOOP);
7944         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7945                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7946         intel_ring_emit(ring, fb->pitches[0]);
7947         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7948         intel_ring_emit(ring, 0); /* aux display base address, unused */
7949
7950         intel_mark_page_flip_active(intel_crtc);
7951         __intel_ring_advance(ring);
7952         return 0;
7953
7954 err_unpin:
7955         intel_unpin_fb_obj(obj);
7956 err:
7957         return ret;
7958 }
7959
7960 static int intel_gen3_queue_flip(struct drm_device *dev,
7961                                  struct drm_crtc *crtc,
7962                                  struct drm_framebuffer *fb,
7963                                  struct drm_i915_gem_object *obj,
7964                                  uint32_t flags)
7965 {
7966         struct drm_i915_private *dev_priv = dev->dev_private;
7967         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7968         u32 flip_mask;
7969         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7970         int ret;
7971
7972         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7973         if (ret)
7974                 goto err;
7975
7976         ret = intel_ring_begin(ring, 6);
7977         if (ret)
7978                 goto err_unpin;
7979
7980         if (intel_crtc->plane)
7981                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7982         else
7983                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7984         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7985         intel_ring_emit(ring, MI_NOOP);
7986         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7987                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7988         intel_ring_emit(ring, fb->pitches[0]);
7989         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7990         intel_ring_emit(ring, MI_NOOP);
7991
7992         intel_mark_page_flip_active(intel_crtc);
7993         __intel_ring_advance(ring);
7994         return 0;
7995
7996 err_unpin:
7997         intel_unpin_fb_obj(obj);
7998 err:
7999         return ret;
8000 }
8001
8002 static int intel_gen4_queue_flip(struct drm_device *dev,
8003                                  struct drm_crtc *crtc,
8004                                  struct drm_framebuffer *fb,
8005                                  struct drm_i915_gem_object *obj,
8006                                  uint32_t flags)
8007 {
8008         struct drm_i915_private *dev_priv = dev->dev_private;
8009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8010         uint32_t pf, pipesrc;
8011         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8012         int ret;
8013
8014         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8015         if (ret)
8016                 goto err;
8017
8018         ret = intel_ring_begin(ring, 4);
8019         if (ret)
8020                 goto err_unpin;
8021
8022         /* i965+ uses the linear or tiled offsets from the
8023          * Display Registers (which do not change across a page-flip)
8024          * so we need only reprogram the base address.
8025          */
8026         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8027                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8028         intel_ring_emit(ring, fb->pitches[0]);
8029         intel_ring_emit(ring,
8030                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8031                         obj->tiling_mode);
8032
8033         /* XXX Enabling the panel-fitter across page-flip is so far
8034          * untested on non-native modes, so ignore it for now.
8035          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8036          */
8037         pf = 0;
8038         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8039         intel_ring_emit(ring, pf | pipesrc);
8040
8041         intel_mark_page_flip_active(intel_crtc);
8042         __intel_ring_advance(ring);
8043         return 0;
8044
8045 err_unpin:
8046         intel_unpin_fb_obj(obj);
8047 err:
8048         return ret;
8049 }
8050
8051 static int intel_gen6_queue_flip(struct drm_device *dev,
8052                                  struct drm_crtc *crtc,
8053                                  struct drm_framebuffer *fb,
8054                                  struct drm_i915_gem_object *obj,
8055                                  uint32_t flags)
8056 {
8057         struct drm_i915_private *dev_priv = dev->dev_private;
8058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8059         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8060         uint32_t pf, pipesrc;
8061         int ret;
8062
8063         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8064         if (ret)
8065                 goto err;
8066
8067         ret = intel_ring_begin(ring, 4);
8068         if (ret)
8069                 goto err_unpin;
8070
8071         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8072                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8073         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8074         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8075
8076         /* Contrary to the suggestions in the documentation,
8077          * "Enable Panel Fitter" does not seem to be required when page
8078          * flipping with a non-native mode, and worse causes a normal
8079          * modeset to fail.
8080          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8081          */
8082         pf = 0;
8083         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8084         intel_ring_emit(ring, pf | pipesrc);
8085
8086         intel_mark_page_flip_active(intel_crtc);
8087         __intel_ring_advance(ring);
8088         return 0;
8089
8090 err_unpin:
8091         intel_unpin_fb_obj(obj);
8092 err:
8093         return ret;
8094 }
8095
8096 static int intel_gen7_queue_flip(struct drm_device *dev,
8097                                  struct drm_crtc *crtc,
8098                                  struct drm_framebuffer *fb,
8099                                  struct drm_i915_gem_object *obj,
8100                                  uint32_t flags)
8101 {
8102         struct drm_i915_private *dev_priv = dev->dev_private;
8103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8104         struct intel_ring_buffer *ring;
8105         uint32_t plane_bit = 0;
8106         int len, ret;
8107
8108         ring = obj->ring;
8109         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8110                 ring = &dev_priv->ring[BCS];
8111
8112         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8113         if (ret)
8114                 goto err;
8115
8116         switch(intel_crtc->plane) {
8117         case PLANE_A:
8118                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8119                 break;
8120         case PLANE_B:
8121                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8122                 break;
8123         case PLANE_C:
8124                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8125                 break;
8126         default:
8127                 WARN_ONCE(1, "unknown plane in flip command\n");
8128                 ret = -ENODEV;
8129                 goto err_unpin;
8130         }
8131
8132         len = 4;
8133         if (ring->id == RCS)
8134                 len += 6;
8135
8136         ret = intel_ring_begin(ring, len);
8137         if (ret)
8138                 goto err_unpin;
8139
8140         /* Unmask the flip-done completion message. Note that the bspec says that
8141          * we should do this for both the BCS and RCS, and that we must not unmask
8142          * more than one flip event at any time (or ensure that one flip message
8143          * can be sent by waiting for flip-done prior to queueing new flips).
8144          * Experimentation says that BCS works despite DERRMR masking all
8145          * flip-done completion events and that unmasking all planes at once
8146          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8147          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8148          */
8149         if (ring->id == RCS) {
8150                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8151                 intel_ring_emit(ring, DERRMR);
8152                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8153                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8154                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8155                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8156                 intel_ring_emit(ring, DERRMR);
8157                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8158         }
8159
8160         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8161         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8162         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8163         intel_ring_emit(ring, (MI_NOOP));
8164
8165         intel_mark_page_flip_active(intel_crtc);
8166         __intel_ring_advance(ring);
8167         return 0;
8168
8169 err_unpin:
8170         intel_unpin_fb_obj(obj);
8171 err:
8172         return ret;
8173 }
8174
8175 static int intel_default_queue_flip(struct drm_device *dev,
8176                                     struct drm_crtc *crtc,
8177                                     struct drm_framebuffer *fb,
8178                                     struct drm_i915_gem_object *obj,
8179                                     uint32_t flags)
8180 {
8181         return -ENODEV;
8182 }
8183
8184 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8185                                 struct drm_framebuffer *fb,
8186                                 struct drm_pending_vblank_event *event,
8187                                 uint32_t page_flip_flags)
8188 {
8189         struct drm_device *dev = crtc->dev;
8190         struct drm_i915_private *dev_priv = dev->dev_private;
8191         struct drm_framebuffer *old_fb = crtc->fb;
8192         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8194         struct intel_unpin_work *work;
8195         unsigned long flags;
8196         int ret;
8197
8198         /* Can't change pixel format via MI display flips. */
8199         if (fb->pixel_format != crtc->fb->pixel_format)
8200                 return -EINVAL;
8201
8202         /*
8203          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8204          * Note that pitch changes could also affect these register.
8205          */
8206         if (INTEL_INFO(dev)->gen > 3 &&
8207             (fb->offsets[0] != crtc->fb->offsets[0] ||
8208              fb->pitches[0] != crtc->fb->pitches[0]))
8209                 return -EINVAL;
8210
8211         work = kzalloc(sizeof(*work), GFP_KERNEL);
8212         if (work == NULL)
8213                 return -ENOMEM;
8214
8215         work->event = event;
8216         work->crtc = crtc;
8217         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8218         INIT_WORK(&work->work, intel_unpin_work_fn);
8219
8220         ret = drm_vblank_get(dev, intel_crtc->pipe);
8221         if (ret)
8222                 goto free_work;
8223
8224         /* We borrow the event spin lock for protecting unpin_work */
8225         spin_lock_irqsave(&dev->event_lock, flags);
8226         if (intel_crtc->unpin_work) {
8227                 spin_unlock_irqrestore(&dev->event_lock, flags);
8228                 kfree(work);
8229                 drm_vblank_put(dev, intel_crtc->pipe);
8230
8231                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8232                 return -EBUSY;
8233         }
8234         intel_crtc->unpin_work = work;
8235         spin_unlock_irqrestore(&dev->event_lock, flags);
8236
8237         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8238                 flush_workqueue(dev_priv->wq);
8239
8240         ret = i915_mutex_lock_interruptible(dev);
8241         if (ret)
8242                 goto cleanup;
8243
8244         /* Reference the objects for the scheduled work. */
8245         drm_gem_object_reference(&work->old_fb_obj->base);
8246         drm_gem_object_reference(&obj->base);
8247
8248         crtc->fb = fb;
8249
8250         work->pending_flip_obj = obj;
8251
8252         work->enable_stall_check = true;
8253
8254         atomic_inc(&intel_crtc->unpin_work_count);
8255         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8256
8257         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8258         if (ret)
8259                 goto cleanup_pending;
8260
8261         intel_disable_fbc(dev);
8262         intel_mark_fb_busy(obj, NULL);
8263         mutex_unlock(&dev->struct_mutex);
8264
8265         trace_i915_flip_request(intel_crtc->plane, obj);
8266
8267         return 0;
8268
8269 cleanup_pending:
8270         atomic_dec(&intel_crtc->unpin_work_count);
8271         crtc->fb = old_fb;
8272         drm_gem_object_unreference(&work->old_fb_obj->base);
8273         drm_gem_object_unreference(&obj->base);
8274         mutex_unlock(&dev->struct_mutex);
8275
8276 cleanup:
8277         spin_lock_irqsave(&dev->event_lock, flags);
8278         intel_crtc->unpin_work = NULL;
8279         spin_unlock_irqrestore(&dev->event_lock, flags);
8280
8281         drm_vblank_put(dev, intel_crtc->pipe);
8282 free_work:
8283         kfree(work);
8284
8285         return ret;
8286 }
8287
8288 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8289         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8290         .load_lut = intel_crtc_load_lut,
8291 };
8292
8293 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8294                                   struct drm_crtc *crtc)
8295 {
8296         struct drm_device *dev;
8297         struct drm_crtc *tmp;
8298         int crtc_mask = 1;
8299
8300         WARN(!crtc, "checking null crtc?\n");
8301
8302         dev = crtc->dev;
8303
8304         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8305                 if (tmp == crtc)
8306                         break;
8307                 crtc_mask <<= 1;
8308         }
8309
8310         if (encoder->possible_crtcs & crtc_mask)
8311                 return true;
8312         return false;
8313 }
8314
8315 /**
8316  * intel_modeset_update_staged_output_state
8317  *
8318  * Updates the staged output configuration state, e.g. after we've read out the
8319  * current hw state.
8320  */
8321 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8322 {
8323         struct intel_encoder *encoder;
8324         struct intel_connector *connector;
8325
8326         list_for_each_entry(connector, &dev->mode_config.connector_list,
8327                             base.head) {
8328                 connector->new_encoder =
8329                         to_intel_encoder(connector->base.encoder);
8330         }
8331
8332         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8333                             base.head) {
8334                 encoder->new_crtc =
8335                         to_intel_crtc(encoder->base.crtc);
8336         }
8337 }
8338
8339 /**
8340  * intel_modeset_commit_output_state
8341  *
8342  * This function copies the stage display pipe configuration to the real one.
8343  */
8344 static void intel_modeset_commit_output_state(struct drm_device *dev)
8345 {
8346         struct intel_encoder *encoder;
8347         struct intel_connector *connector;
8348
8349         list_for_each_entry(connector, &dev->mode_config.connector_list,
8350                             base.head) {
8351                 connector->base.encoder = &connector->new_encoder->base;
8352         }
8353
8354         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8355                             base.head) {
8356                 encoder->base.crtc = &encoder->new_crtc->base;
8357         }
8358 }
8359
8360 static void
8361 connected_sink_compute_bpp(struct intel_connector * connector,
8362                            struct intel_crtc_config *pipe_config)
8363 {
8364         int bpp = pipe_config->pipe_bpp;
8365
8366         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8367                 connector->base.base.id,
8368                 drm_get_connector_name(&connector->base));
8369
8370         /* Don't use an invalid EDID bpc value */
8371         if (connector->base.display_info.bpc &&
8372             connector->base.display_info.bpc * 3 < bpp) {
8373                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8374                               bpp, connector->base.display_info.bpc*3);
8375                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8376         }
8377
8378         /* Clamp bpp to 8 on screens without EDID 1.4 */
8379         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8380                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8381                               bpp);
8382                 pipe_config->pipe_bpp = 24;
8383         }
8384 }
8385
8386 static int
8387 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8388                           struct drm_framebuffer *fb,
8389                           struct intel_crtc_config *pipe_config)
8390 {
8391         struct drm_device *dev = crtc->base.dev;
8392         struct intel_connector *connector;
8393         int bpp;
8394
8395         switch (fb->pixel_format) {
8396         case DRM_FORMAT_C8:
8397                 bpp = 8*3; /* since we go through a colormap */
8398                 break;
8399         case DRM_FORMAT_XRGB1555:
8400         case DRM_FORMAT_ARGB1555:
8401                 /* checked in intel_framebuffer_init already */
8402                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8403                         return -EINVAL;
8404         case DRM_FORMAT_RGB565:
8405                 bpp = 6*3; /* min is 18bpp */
8406                 break;
8407         case DRM_FORMAT_XBGR8888:
8408         case DRM_FORMAT_ABGR8888:
8409                 /* checked in intel_framebuffer_init already */
8410                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8411                         return -EINVAL;
8412         case DRM_FORMAT_XRGB8888:
8413         case DRM_FORMAT_ARGB8888:
8414                 bpp = 8*3;
8415                 break;
8416         case DRM_FORMAT_XRGB2101010:
8417         case DRM_FORMAT_ARGB2101010:
8418         case DRM_FORMAT_XBGR2101010:
8419         case DRM_FORMAT_ABGR2101010:
8420                 /* checked in intel_framebuffer_init already */
8421                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8422                         return -EINVAL;
8423                 bpp = 10*3;
8424                 break;
8425         /* TODO: gen4+ supports 16 bpc floating point, too. */
8426         default:
8427                 DRM_DEBUG_KMS("unsupported depth\n");
8428                 return -EINVAL;
8429         }
8430
8431         pipe_config->pipe_bpp = bpp;
8432
8433         /* Clamp display bpp to EDID value */
8434         list_for_each_entry(connector, &dev->mode_config.connector_list,
8435                             base.head) {
8436                 if (!connector->new_encoder ||
8437                     connector->new_encoder->new_crtc != crtc)
8438                         continue;
8439
8440                 connected_sink_compute_bpp(connector, pipe_config);
8441         }
8442
8443         return bpp;
8444 }
8445
8446 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8447 {
8448         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8449                         "type: 0x%x flags: 0x%x\n",
8450                 mode->crtc_clock,
8451                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8452                 mode->crtc_hsync_end, mode->crtc_htotal,
8453                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8454                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8455 }
8456
8457 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8458                                    struct intel_crtc_config *pipe_config,
8459                                    const char *context)
8460 {
8461         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8462                       context, pipe_name(crtc->pipe));
8463
8464         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8465         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8466                       pipe_config->pipe_bpp, pipe_config->dither);
8467         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8468                       pipe_config->has_pch_encoder,
8469                       pipe_config->fdi_lanes,
8470                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8471                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8472                       pipe_config->fdi_m_n.tu);
8473         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8474                       pipe_config->has_dp_encoder,
8475                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8476                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8477                       pipe_config->dp_m_n.tu);
8478         DRM_DEBUG_KMS("requested mode:\n");
8479         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8480         DRM_DEBUG_KMS("adjusted mode:\n");
8481         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8482         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8483         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8484         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8485                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8486         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8487                       pipe_config->gmch_pfit.control,
8488                       pipe_config->gmch_pfit.pgm_ratios,
8489                       pipe_config->gmch_pfit.lvds_border_bits);
8490         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8491                       pipe_config->pch_pfit.pos,
8492                       pipe_config->pch_pfit.size,
8493                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8494         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8495         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8496 }
8497
8498 static bool check_encoder_cloning(struct drm_crtc *crtc)
8499 {
8500         int num_encoders = 0;
8501         bool uncloneable_encoders = false;
8502         struct intel_encoder *encoder;
8503
8504         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8505                             base.head) {
8506                 if (&encoder->new_crtc->base != crtc)
8507                         continue;
8508
8509                 num_encoders++;
8510                 if (!encoder->cloneable)
8511                         uncloneable_encoders = true;
8512         }
8513
8514         return !(num_encoders > 1 && uncloneable_encoders);
8515 }
8516
8517 static struct intel_crtc_config *
8518 intel_modeset_pipe_config(struct drm_crtc *crtc,
8519                           struct drm_framebuffer *fb,
8520                           struct drm_display_mode *mode)
8521 {
8522         struct drm_device *dev = crtc->dev;
8523         struct intel_encoder *encoder;
8524         struct intel_crtc_config *pipe_config;
8525         int plane_bpp, ret = -EINVAL;
8526         bool retry = true;
8527
8528         if (!check_encoder_cloning(crtc)) {
8529                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8530                 return ERR_PTR(-EINVAL);
8531         }
8532
8533         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8534         if (!pipe_config)
8535                 return ERR_PTR(-ENOMEM);
8536
8537         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8538         drm_mode_copy(&pipe_config->requested_mode, mode);
8539
8540         pipe_config->cpu_transcoder =
8541                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8542         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8543
8544         /*
8545          * Sanitize sync polarity flags based on requested ones. If neither
8546          * positive or negative polarity is requested, treat this as meaning
8547          * negative polarity.
8548          */
8549         if (!(pipe_config->adjusted_mode.flags &
8550               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8551                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8552
8553         if (!(pipe_config->adjusted_mode.flags &
8554               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8555                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8556
8557         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8558          * plane pixel format and any sink constraints into account. Returns the
8559          * source plane bpp so that dithering can be selected on mismatches
8560          * after encoders and crtc also have had their say. */
8561         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8562                                               fb, pipe_config);
8563         if (plane_bpp < 0)
8564                 goto fail;
8565
8566         /*
8567          * Determine the real pipe dimensions. Note that stereo modes can
8568          * increase the actual pipe size due to the frame doubling and
8569          * insertion of additional space for blanks between the frame. This
8570          * is stored in the crtc timings. We use the requested mode to do this
8571          * computation to clearly distinguish it from the adjusted mode, which
8572          * can be changed by the connectors in the below retry loop.
8573          */
8574         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8575         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8576         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8577
8578 encoder_retry:
8579         /* Ensure the port clock defaults are reset when retrying. */
8580         pipe_config->port_clock = 0;
8581         pipe_config->pixel_multiplier = 1;
8582
8583         /* Fill in default crtc timings, allow encoders to overwrite them. */
8584         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8585
8586         /* Pass our mode to the connectors and the CRTC to give them a chance to
8587          * adjust it according to limitations or connector properties, and also
8588          * a chance to reject the mode entirely.
8589          */
8590         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8591                             base.head) {
8592
8593                 if (&encoder->new_crtc->base != crtc)
8594                         continue;
8595
8596                 if (!(encoder->compute_config(encoder, pipe_config))) {
8597                         DRM_DEBUG_KMS("Encoder config failure\n");
8598                         goto fail;
8599                 }
8600         }
8601
8602         /* Set default port clock if not overwritten by the encoder. Needs to be
8603          * done afterwards in case the encoder adjusts the mode. */
8604         if (!pipe_config->port_clock)
8605                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8606                         * pipe_config->pixel_multiplier;
8607
8608         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8609         if (ret < 0) {
8610                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8611                 goto fail;
8612         }
8613
8614         if (ret == RETRY) {
8615                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8616                         ret = -EINVAL;
8617                         goto fail;
8618                 }
8619
8620                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8621                 retry = false;
8622                 goto encoder_retry;
8623         }
8624
8625         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8626         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8627                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8628
8629         return pipe_config;
8630 fail:
8631         kfree(pipe_config);
8632         return ERR_PTR(ret);
8633 }
8634
8635 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8636  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8637 static void
8638 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8639                              unsigned *prepare_pipes, unsigned *disable_pipes)
8640 {
8641         struct intel_crtc *intel_crtc;
8642         struct drm_device *dev = crtc->dev;
8643         struct intel_encoder *encoder;
8644         struct intel_connector *connector;
8645         struct drm_crtc *tmp_crtc;
8646
8647         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8648
8649         /* Check which crtcs have changed outputs connected to them, these need
8650          * to be part of the prepare_pipes mask. We don't (yet) support global
8651          * modeset across multiple crtcs, so modeset_pipes will only have one
8652          * bit set at most. */
8653         list_for_each_entry(connector, &dev->mode_config.connector_list,
8654                             base.head) {
8655                 if (connector->base.encoder == &connector->new_encoder->base)
8656                         continue;
8657
8658                 if (connector->base.encoder) {
8659                         tmp_crtc = connector->base.encoder->crtc;
8660
8661                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8662                 }
8663
8664                 if (connector->new_encoder)
8665                         *prepare_pipes |=
8666                                 1 << connector->new_encoder->new_crtc->pipe;
8667         }
8668
8669         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8670                             base.head) {
8671                 if (encoder->base.crtc == &encoder->new_crtc->base)
8672                         continue;
8673
8674                 if (encoder->base.crtc) {
8675                         tmp_crtc = encoder->base.crtc;
8676
8677                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8678                 }
8679
8680                 if (encoder->new_crtc)
8681                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8682         }
8683
8684         /* Check for any pipes that will be fully disabled ... */
8685         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8686                             base.head) {
8687                 bool used = false;
8688
8689                 /* Don't try to disable disabled crtcs. */
8690                 if (!intel_crtc->base.enabled)
8691                         continue;
8692
8693                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8694                                     base.head) {
8695                         if (encoder->new_crtc == intel_crtc)
8696                                 used = true;
8697                 }
8698
8699                 if (!used)
8700                         *disable_pipes |= 1 << intel_crtc->pipe;
8701         }
8702
8703
8704         /* set_mode is also used to update properties on life display pipes. */
8705         intel_crtc = to_intel_crtc(crtc);
8706         if (crtc->enabled)
8707                 *prepare_pipes |= 1 << intel_crtc->pipe;
8708
8709         /*
8710          * For simplicity do a full modeset on any pipe where the output routing
8711          * changed. We could be more clever, but that would require us to be
8712          * more careful with calling the relevant encoder->mode_set functions.
8713          */
8714         if (*prepare_pipes)
8715                 *modeset_pipes = *prepare_pipes;
8716
8717         /* ... and mask these out. */
8718         *modeset_pipes &= ~(*disable_pipes);
8719         *prepare_pipes &= ~(*disable_pipes);
8720
8721         /*
8722          * HACK: We don't (yet) fully support global modesets. intel_set_config
8723          * obies this rule, but the modeset restore mode of
8724          * intel_modeset_setup_hw_state does not.
8725          */
8726         *modeset_pipes &= 1 << intel_crtc->pipe;
8727         *prepare_pipes &= 1 << intel_crtc->pipe;
8728
8729         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8730                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8731 }
8732
8733 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8734 {
8735         struct drm_encoder *encoder;
8736         struct drm_device *dev = crtc->dev;
8737
8738         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8739                 if (encoder->crtc == crtc)
8740                         return true;
8741
8742         return false;
8743 }
8744
8745 static void
8746 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8747 {
8748         struct intel_encoder *intel_encoder;
8749         struct intel_crtc *intel_crtc;
8750         struct drm_connector *connector;
8751
8752         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8753                             base.head) {
8754                 if (!intel_encoder->base.crtc)
8755                         continue;
8756
8757                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8758
8759                 if (prepare_pipes & (1 << intel_crtc->pipe))
8760                         intel_encoder->connectors_active = false;
8761         }
8762
8763         intel_modeset_commit_output_state(dev);
8764
8765         /* Update computed state. */
8766         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8767                             base.head) {
8768                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8769         }
8770
8771         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8772                 if (!connector->encoder || !connector->encoder->crtc)
8773                         continue;
8774
8775                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8776
8777                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8778                         struct drm_property *dpms_property =
8779                                 dev->mode_config.dpms_property;
8780
8781                         connector->dpms = DRM_MODE_DPMS_ON;
8782                         drm_object_property_set_value(&connector->base,
8783                                                          dpms_property,
8784                                                          DRM_MODE_DPMS_ON);
8785
8786                         intel_encoder = to_intel_encoder(connector->encoder);
8787                         intel_encoder->connectors_active = true;
8788                 }
8789         }
8790
8791 }
8792
8793 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8794 {
8795         int diff;
8796
8797         if (clock1 == clock2)
8798                 return true;
8799
8800         if (!clock1 || !clock2)
8801                 return false;
8802
8803         diff = abs(clock1 - clock2);
8804
8805         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8806                 return true;
8807
8808         return false;
8809 }
8810
8811 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8812         list_for_each_entry((intel_crtc), \
8813                             &(dev)->mode_config.crtc_list, \
8814                             base.head) \
8815                 if (mask & (1 <<(intel_crtc)->pipe))
8816
8817 static bool
8818 intel_pipe_config_compare(struct drm_device *dev,
8819                           struct intel_crtc_config *current_config,
8820                           struct intel_crtc_config *pipe_config)
8821 {
8822 #define PIPE_CONF_CHECK_X(name) \
8823         if (current_config->name != pipe_config->name) { \
8824                 DRM_ERROR("mismatch in " #name " " \
8825                           "(expected 0x%08x, found 0x%08x)\n", \
8826                           current_config->name, \
8827                           pipe_config->name); \
8828                 return false; \
8829         }
8830
8831 #define PIPE_CONF_CHECK_I(name) \
8832         if (current_config->name != pipe_config->name) { \
8833                 DRM_ERROR("mismatch in " #name " " \
8834                           "(expected %i, found %i)\n", \
8835                           current_config->name, \
8836                           pipe_config->name); \
8837                 return false; \
8838         }
8839
8840 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8841         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8842                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8843                           "(expected %i, found %i)\n", \
8844                           current_config->name & (mask), \
8845                           pipe_config->name & (mask)); \
8846                 return false; \
8847         }
8848
8849 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8850         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8851                 DRM_ERROR("mismatch in " #name " " \
8852                           "(expected %i, found %i)\n", \
8853                           current_config->name, \
8854                           pipe_config->name); \
8855                 return false; \
8856         }
8857
8858 #define PIPE_CONF_QUIRK(quirk)  \
8859         ((current_config->quirks | pipe_config->quirks) & (quirk))
8860
8861         PIPE_CONF_CHECK_I(cpu_transcoder);
8862
8863         PIPE_CONF_CHECK_I(has_pch_encoder);
8864         PIPE_CONF_CHECK_I(fdi_lanes);
8865         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8866         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8867         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8868         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8869         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8870
8871         PIPE_CONF_CHECK_I(has_dp_encoder);
8872         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8873         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8874         PIPE_CONF_CHECK_I(dp_m_n.link_m);
8875         PIPE_CONF_CHECK_I(dp_m_n.link_n);
8876         PIPE_CONF_CHECK_I(dp_m_n.tu);
8877
8878         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8879         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8880         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8881         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8882         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8883         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8884
8885         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8886         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8887         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8888         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8889         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8890         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8891
8892         PIPE_CONF_CHECK_I(pixel_multiplier);
8893
8894         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8895                               DRM_MODE_FLAG_INTERLACE);
8896
8897         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8898                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8899                                       DRM_MODE_FLAG_PHSYNC);
8900                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8901                                       DRM_MODE_FLAG_NHSYNC);
8902                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8903                                       DRM_MODE_FLAG_PVSYNC);
8904                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8905                                       DRM_MODE_FLAG_NVSYNC);
8906         }
8907
8908         PIPE_CONF_CHECK_I(pipe_src_w);
8909         PIPE_CONF_CHECK_I(pipe_src_h);
8910
8911         PIPE_CONF_CHECK_I(gmch_pfit.control);
8912         /* pfit ratios are autocomputed by the hw on gen4+ */
8913         if (INTEL_INFO(dev)->gen < 4)
8914                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8915         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8916         PIPE_CONF_CHECK_I(pch_pfit.enabled);
8917         if (current_config->pch_pfit.enabled) {
8918                 PIPE_CONF_CHECK_I(pch_pfit.pos);
8919                 PIPE_CONF_CHECK_I(pch_pfit.size);
8920         }
8921
8922         PIPE_CONF_CHECK_I(ips_enabled);
8923
8924         PIPE_CONF_CHECK_I(double_wide);
8925
8926         PIPE_CONF_CHECK_I(shared_dpll);
8927         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8928         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8929         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8930         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8931
8932         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8933                 PIPE_CONF_CHECK_I(pipe_bpp);
8934
8935         if (!IS_HASWELL(dev)) {
8936                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
8937                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8938         }
8939
8940 #undef PIPE_CONF_CHECK_X
8941 #undef PIPE_CONF_CHECK_I
8942 #undef PIPE_CONF_CHECK_FLAGS
8943 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8944 #undef PIPE_CONF_QUIRK
8945
8946         return true;
8947 }
8948
8949 static void
8950 check_connector_state(struct drm_device *dev)
8951 {
8952         struct intel_connector *connector;
8953
8954         list_for_each_entry(connector, &dev->mode_config.connector_list,
8955                             base.head) {
8956                 /* This also checks the encoder/connector hw state with the
8957                  * ->get_hw_state callbacks. */
8958                 intel_connector_check_state(connector);
8959
8960                 WARN(&connector->new_encoder->base != connector->base.encoder,
8961                      "connector's staged encoder doesn't match current encoder\n");
8962         }
8963 }
8964
8965 static void
8966 check_encoder_state(struct drm_device *dev)
8967 {
8968         struct intel_encoder *encoder;
8969         struct intel_connector *connector;
8970
8971         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8972                             base.head) {
8973                 bool enabled = false;
8974                 bool active = false;
8975                 enum pipe pipe, tracked_pipe;
8976
8977                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8978                               encoder->base.base.id,
8979                               drm_get_encoder_name(&encoder->base));
8980
8981                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8982                      "encoder's stage crtc doesn't match current crtc\n");
8983                 WARN(encoder->connectors_active && !encoder->base.crtc,
8984                      "encoder's active_connectors set, but no crtc\n");
8985
8986                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8987                                     base.head) {
8988                         if (connector->base.encoder != &encoder->base)
8989                                 continue;
8990                         enabled = true;
8991                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8992                                 active = true;
8993                 }
8994                 WARN(!!encoder->base.crtc != enabled,
8995                      "encoder's enabled state mismatch "
8996                      "(expected %i, found %i)\n",
8997                      !!encoder->base.crtc, enabled);
8998                 WARN(active && !encoder->base.crtc,
8999                      "active encoder with no crtc\n");
9000
9001                 WARN(encoder->connectors_active != active,
9002                      "encoder's computed active state doesn't match tracked active state "
9003                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9004
9005                 active = encoder->get_hw_state(encoder, &pipe);
9006                 WARN(active != encoder->connectors_active,
9007                      "encoder's hw state doesn't match sw tracking "
9008                      "(expected %i, found %i)\n",
9009                      encoder->connectors_active, active);
9010
9011                 if (!encoder->base.crtc)
9012                         continue;
9013
9014                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9015                 WARN(active && pipe != tracked_pipe,
9016                      "active encoder's pipe doesn't match"
9017                      "(expected %i, found %i)\n",
9018                      tracked_pipe, pipe);
9019
9020         }
9021 }
9022
9023 static void
9024 check_crtc_state(struct drm_device *dev)
9025 {
9026         drm_i915_private_t *dev_priv = dev->dev_private;
9027         struct intel_crtc *crtc;
9028         struct intel_encoder *encoder;
9029         struct intel_crtc_config pipe_config;
9030
9031         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9032                             base.head) {
9033                 bool enabled = false;
9034                 bool active = false;
9035
9036                 memset(&pipe_config, 0, sizeof(pipe_config));
9037
9038                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9039                               crtc->base.base.id);
9040
9041                 WARN(crtc->active && !crtc->base.enabled,
9042                      "active crtc, but not enabled in sw tracking\n");
9043
9044                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9045                                     base.head) {
9046                         if (encoder->base.crtc != &crtc->base)
9047                                 continue;
9048                         enabled = true;
9049                         if (encoder->connectors_active)
9050                                 active = true;
9051                 }
9052
9053                 WARN(active != crtc->active,
9054                      "crtc's computed active state doesn't match tracked active state "
9055                      "(expected %i, found %i)\n", active, crtc->active);
9056                 WARN(enabled != crtc->base.enabled,
9057                      "crtc's computed enabled state doesn't match tracked enabled state "
9058                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9059
9060                 active = dev_priv->display.get_pipe_config(crtc,
9061                                                            &pipe_config);
9062
9063                 /* hw state is inconsistent with the pipe A quirk */
9064                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9065                         active = crtc->active;
9066
9067                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9068                                     base.head) {
9069                         enum pipe pipe;
9070                         if (encoder->base.crtc != &crtc->base)
9071                                 continue;
9072                         if (encoder->get_config &&
9073                             encoder->get_hw_state(encoder, &pipe))
9074                                 encoder->get_config(encoder, &pipe_config);
9075                 }
9076
9077                 WARN(crtc->active != active,
9078                      "crtc active state doesn't match with hw state "
9079                      "(expected %i, found %i)\n", crtc->active, active);
9080
9081                 if (active &&
9082                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9083                         WARN(1, "pipe state doesn't match!\n");
9084                         intel_dump_pipe_config(crtc, &pipe_config,
9085                                                "[hw state]");
9086                         intel_dump_pipe_config(crtc, &crtc->config,
9087                                                "[sw state]");
9088                 }
9089         }
9090 }
9091
9092 static void
9093 check_shared_dpll_state(struct drm_device *dev)
9094 {
9095         drm_i915_private_t *dev_priv = dev->dev_private;
9096         struct intel_crtc *crtc;
9097         struct intel_dpll_hw_state dpll_hw_state;
9098         int i;
9099
9100         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9101                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9102                 int enabled_crtcs = 0, active_crtcs = 0;
9103                 bool active;
9104
9105                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9106
9107                 DRM_DEBUG_KMS("%s\n", pll->name);
9108
9109                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9110
9111                 WARN(pll->active > pll->refcount,
9112                      "more active pll users than references: %i vs %i\n",
9113                      pll->active, pll->refcount);
9114                 WARN(pll->active && !pll->on,
9115                      "pll in active use but not on in sw tracking\n");
9116                 WARN(pll->on && !pll->active,
9117                      "pll in on but not on in use in sw tracking\n");
9118                 WARN(pll->on != active,
9119                      "pll on state mismatch (expected %i, found %i)\n",
9120                      pll->on, active);
9121
9122                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9123                                     base.head) {
9124                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9125                                 enabled_crtcs++;
9126                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9127                                 active_crtcs++;
9128                 }
9129                 WARN(pll->active != active_crtcs,
9130                      "pll active crtcs mismatch (expected %i, found %i)\n",
9131                      pll->active, active_crtcs);
9132                 WARN(pll->refcount != enabled_crtcs,
9133                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9134                      pll->refcount, enabled_crtcs);
9135
9136                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9137                                        sizeof(dpll_hw_state)),
9138                      "pll hw state mismatch\n");
9139         }
9140 }
9141
9142 void
9143 intel_modeset_check_state(struct drm_device *dev)
9144 {
9145         check_connector_state(dev);
9146         check_encoder_state(dev);
9147         check_crtc_state(dev);
9148         check_shared_dpll_state(dev);
9149 }
9150
9151 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9152                                      int dotclock)
9153 {
9154         /*
9155          * FDI already provided one idea for the dotclock.
9156          * Yell if the encoder disagrees.
9157          */
9158         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9159              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9160              pipe_config->adjusted_mode.crtc_clock, dotclock);
9161 }
9162
9163 static int __intel_set_mode(struct drm_crtc *crtc,
9164                             struct drm_display_mode *mode,
9165                             int x, int y, struct drm_framebuffer *fb)
9166 {
9167         struct drm_device *dev = crtc->dev;
9168         drm_i915_private_t *dev_priv = dev->dev_private;
9169         struct drm_display_mode *saved_mode, *saved_hwmode;
9170         struct intel_crtc_config *pipe_config = NULL;
9171         struct intel_crtc *intel_crtc;
9172         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9173         int ret = 0;
9174
9175         saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9176         if (!saved_mode)
9177                 return -ENOMEM;
9178         saved_hwmode = saved_mode + 1;
9179
9180         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9181                                      &prepare_pipes, &disable_pipes);
9182
9183         *saved_hwmode = crtc->hwmode;
9184         *saved_mode = crtc->mode;
9185
9186         /* Hack: Because we don't (yet) support global modeset on multiple
9187          * crtcs, we don't keep track of the new mode for more than one crtc.
9188          * Hence simply check whether any bit is set in modeset_pipes in all the
9189          * pieces of code that are not yet converted to deal with mutliple crtcs
9190          * changing their mode at the same time. */
9191         if (modeset_pipes) {
9192                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9193                 if (IS_ERR(pipe_config)) {
9194                         ret = PTR_ERR(pipe_config);
9195                         pipe_config = NULL;
9196
9197                         goto out;
9198                 }
9199                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9200                                        "[modeset]");
9201         }
9202
9203         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9204                 intel_crtc_disable(&intel_crtc->base);
9205
9206         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9207                 if (intel_crtc->base.enabled)
9208                         dev_priv->display.crtc_disable(&intel_crtc->base);
9209         }
9210
9211         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9212          * to set it here already despite that we pass it down the callchain.
9213          */
9214         if (modeset_pipes) {
9215                 crtc->mode = *mode;
9216                 /* mode_set/enable/disable functions rely on a correct pipe
9217                  * config. */
9218                 to_intel_crtc(crtc)->config = *pipe_config;
9219         }
9220
9221         /* Only after disabling all output pipelines that will be changed can we
9222          * update the the output configuration. */
9223         intel_modeset_update_state(dev, prepare_pipes);
9224
9225         if (dev_priv->display.modeset_global_resources)
9226                 dev_priv->display.modeset_global_resources(dev);
9227
9228         /* Set up the DPLL and any encoders state that needs to adjust or depend
9229          * on the DPLL.
9230          */
9231         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9232                 ret = intel_crtc_mode_set(&intel_crtc->base,
9233                                           x, y, fb);
9234                 if (ret)
9235                         goto done;
9236         }
9237
9238         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9239         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9240                 dev_priv->display.crtc_enable(&intel_crtc->base);
9241
9242         if (modeset_pipes) {
9243                 /* Store real post-adjustment hardware mode. */
9244                 crtc->hwmode = pipe_config->adjusted_mode;
9245
9246                 /* Calculate and store various constants which
9247                  * are later needed by vblank and swap-completion
9248                  * timestamping. They are derived from true hwmode.
9249                  */
9250                 drm_calc_timestamping_constants(crtc);
9251         }
9252
9253         /* FIXME: add subpixel order */
9254 done:
9255         if (ret && crtc->enabled) {
9256                 crtc->hwmode = *saved_hwmode;
9257                 crtc->mode = *saved_mode;
9258         }
9259
9260 out:
9261         kfree(pipe_config);
9262         kfree(saved_mode);
9263         return ret;
9264 }
9265
9266 static int intel_set_mode(struct drm_crtc *crtc,
9267                           struct drm_display_mode *mode,
9268                           int x, int y, struct drm_framebuffer *fb)
9269 {
9270         int ret;
9271
9272         ret = __intel_set_mode(crtc, mode, x, y, fb);
9273
9274         if (ret == 0)
9275                 intel_modeset_check_state(crtc->dev);
9276
9277         return ret;
9278 }
9279
9280 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9281 {
9282         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9283 }
9284
9285 #undef for_each_intel_crtc_masked
9286
9287 static void intel_set_config_free(struct intel_set_config *config)
9288 {
9289         if (!config)
9290                 return;
9291
9292         kfree(config->save_connector_encoders);
9293         kfree(config->save_encoder_crtcs);
9294         kfree(config);
9295 }
9296
9297 static int intel_set_config_save_state(struct drm_device *dev,
9298                                        struct intel_set_config *config)
9299 {
9300         struct drm_encoder *encoder;
9301         struct drm_connector *connector;
9302         int count;
9303
9304         config->save_encoder_crtcs =
9305                 kcalloc(dev->mode_config.num_encoder,
9306                         sizeof(struct drm_crtc *), GFP_KERNEL);
9307         if (!config->save_encoder_crtcs)
9308                 return -ENOMEM;
9309
9310         config->save_connector_encoders =
9311                 kcalloc(dev->mode_config.num_connector,
9312                         sizeof(struct drm_encoder *), GFP_KERNEL);
9313         if (!config->save_connector_encoders)
9314                 return -ENOMEM;
9315
9316         /* Copy data. Note that driver private data is not affected.
9317          * Should anything bad happen only the expected state is
9318          * restored, not the drivers personal bookkeeping.
9319          */
9320         count = 0;
9321         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9322                 config->save_encoder_crtcs[count++] = encoder->crtc;
9323         }
9324
9325         count = 0;
9326         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9327                 config->save_connector_encoders[count++] = connector->encoder;
9328         }
9329
9330         return 0;
9331 }
9332
9333 static void intel_set_config_restore_state(struct drm_device *dev,
9334                                            struct intel_set_config *config)
9335 {
9336         struct intel_encoder *encoder;
9337         struct intel_connector *connector;
9338         int count;
9339
9340         count = 0;
9341         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9342                 encoder->new_crtc =
9343                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9344         }
9345
9346         count = 0;
9347         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9348                 connector->new_encoder =
9349                         to_intel_encoder(config->save_connector_encoders[count++]);
9350         }
9351 }
9352
9353 static bool
9354 is_crtc_connector_off(struct drm_mode_set *set)
9355 {
9356         int i;
9357
9358         if (set->num_connectors == 0)
9359                 return false;
9360
9361         if (WARN_ON(set->connectors == NULL))
9362                 return false;
9363
9364         for (i = 0; i < set->num_connectors; i++)
9365                 if (set->connectors[i]->encoder &&
9366                     set->connectors[i]->encoder->crtc == set->crtc &&
9367                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9368                         return true;
9369
9370         return false;
9371 }
9372
9373 static void
9374 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9375                                       struct intel_set_config *config)
9376 {
9377
9378         /* We should be able to check here if the fb has the same properties
9379          * and then just flip_or_move it */
9380         if (is_crtc_connector_off(set)) {
9381                 config->mode_changed = true;
9382         } else if (set->crtc->fb != set->fb) {
9383                 /* If we have no fb then treat it as a full mode set */
9384                 if (set->crtc->fb == NULL) {
9385                         struct intel_crtc *intel_crtc =
9386                                 to_intel_crtc(set->crtc);
9387
9388                         if (intel_crtc->active && i915_fastboot) {
9389                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9390                                 config->fb_changed = true;
9391                         } else {
9392                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9393                                 config->mode_changed = true;
9394                         }
9395                 } else if (set->fb == NULL) {
9396                         config->mode_changed = true;
9397                 } else if (set->fb->pixel_format !=
9398                            set->crtc->fb->pixel_format) {
9399                         config->mode_changed = true;
9400                 } else {
9401                         config->fb_changed = true;
9402                 }
9403         }
9404
9405         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9406                 config->fb_changed = true;
9407
9408         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9409                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9410                 drm_mode_debug_printmodeline(&set->crtc->mode);
9411                 drm_mode_debug_printmodeline(set->mode);
9412                 config->mode_changed = true;
9413         }
9414
9415         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9416                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9417 }
9418
9419 static int
9420 intel_modeset_stage_output_state(struct drm_device *dev,
9421                                  struct drm_mode_set *set,
9422                                  struct intel_set_config *config)
9423 {
9424         struct drm_crtc *new_crtc;
9425         struct intel_connector *connector;
9426         struct intel_encoder *encoder;
9427         int ro;
9428
9429         /* The upper layers ensure that we either disable a crtc or have a list
9430          * of connectors. For paranoia, double-check this. */
9431         WARN_ON(!set->fb && (set->num_connectors != 0));
9432         WARN_ON(set->fb && (set->num_connectors == 0));
9433
9434         list_for_each_entry(connector, &dev->mode_config.connector_list,
9435                             base.head) {
9436                 /* Otherwise traverse passed in connector list and get encoders
9437                  * for them. */
9438                 for (ro = 0; ro < set->num_connectors; ro++) {
9439                         if (set->connectors[ro] == &connector->base) {
9440                                 connector->new_encoder = connector->encoder;
9441                                 break;
9442                         }
9443                 }
9444
9445                 /* If we disable the crtc, disable all its connectors. Also, if
9446                  * the connector is on the changing crtc but not on the new
9447                  * connector list, disable it. */
9448                 if ((!set->fb || ro == set->num_connectors) &&
9449                     connector->base.encoder &&
9450                     connector->base.encoder->crtc == set->crtc) {
9451                         connector->new_encoder = NULL;
9452
9453                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9454                                 connector->base.base.id,
9455                                 drm_get_connector_name(&connector->base));
9456                 }
9457
9458
9459                 if (&connector->new_encoder->base != connector->base.encoder) {
9460                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9461                         config->mode_changed = true;
9462                 }
9463         }
9464         /* connector->new_encoder is now updated for all connectors. */
9465
9466         /* Update crtc of enabled connectors. */
9467         list_for_each_entry(connector, &dev->mode_config.connector_list,
9468                             base.head) {
9469                 if (!connector->new_encoder)
9470                         continue;
9471
9472                 new_crtc = connector->new_encoder->base.crtc;
9473
9474                 for (ro = 0; ro < set->num_connectors; ro++) {
9475                         if (set->connectors[ro] == &connector->base)
9476                                 new_crtc = set->crtc;
9477                 }
9478
9479                 /* Make sure the new CRTC will work with the encoder */
9480                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9481                                            new_crtc)) {
9482                         return -EINVAL;
9483                 }
9484                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9485
9486                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9487                         connector->base.base.id,
9488                         drm_get_connector_name(&connector->base),
9489                         new_crtc->base.id);
9490         }
9491
9492         /* Check for any encoders that needs to be disabled. */
9493         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9494                             base.head) {
9495                 list_for_each_entry(connector,
9496                                     &dev->mode_config.connector_list,
9497                                     base.head) {
9498                         if (connector->new_encoder == encoder) {
9499                                 WARN_ON(!connector->new_encoder->new_crtc);
9500
9501                                 goto next_encoder;
9502                         }
9503                 }
9504                 encoder->new_crtc = NULL;
9505 next_encoder:
9506                 /* Only now check for crtc changes so we don't miss encoders
9507                  * that will be disabled. */
9508                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9509                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9510                         config->mode_changed = true;
9511                 }
9512         }
9513         /* Now we've also updated encoder->new_crtc for all encoders. */
9514
9515         return 0;
9516 }
9517
9518 static int intel_crtc_set_config(struct drm_mode_set *set)
9519 {
9520         struct drm_device *dev;
9521         struct drm_mode_set save_set;
9522         struct intel_set_config *config;
9523         int ret;
9524
9525         BUG_ON(!set);
9526         BUG_ON(!set->crtc);
9527         BUG_ON(!set->crtc->helper_private);
9528
9529         /* Enforce sane interface api - has been abused by the fb helper. */
9530         BUG_ON(!set->mode && set->fb);
9531         BUG_ON(set->fb && set->num_connectors == 0);
9532
9533         if (set->fb) {
9534                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9535                                 set->crtc->base.id, set->fb->base.id,
9536                                 (int)set->num_connectors, set->x, set->y);
9537         } else {
9538                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9539         }
9540
9541         dev = set->crtc->dev;
9542
9543         ret = -ENOMEM;
9544         config = kzalloc(sizeof(*config), GFP_KERNEL);
9545         if (!config)
9546                 goto out_config;
9547
9548         ret = intel_set_config_save_state(dev, config);
9549         if (ret)
9550                 goto out_config;
9551
9552         save_set.crtc = set->crtc;
9553         save_set.mode = &set->crtc->mode;
9554         save_set.x = set->crtc->x;
9555         save_set.y = set->crtc->y;
9556         save_set.fb = set->crtc->fb;
9557
9558         /* Compute whether we need a full modeset, only an fb base update or no
9559          * change at all. In the future we might also check whether only the
9560          * mode changed, e.g. for LVDS where we only change the panel fitter in
9561          * such cases. */
9562         intel_set_config_compute_mode_changes(set, config);
9563
9564         ret = intel_modeset_stage_output_state(dev, set, config);
9565         if (ret)
9566                 goto fail;
9567
9568         if (config->mode_changed) {
9569                 ret = intel_set_mode(set->crtc, set->mode,
9570                                      set->x, set->y, set->fb);
9571         } else if (config->fb_changed) {
9572                 intel_crtc_wait_for_pending_flips(set->crtc);
9573
9574                 ret = intel_pipe_set_base(set->crtc,
9575                                           set->x, set->y, set->fb);
9576         }
9577
9578         if (ret) {
9579                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9580                               set->crtc->base.id, ret);
9581 fail:
9582                 intel_set_config_restore_state(dev, config);
9583
9584                 /* Try to restore the config */
9585                 if (config->mode_changed &&
9586                     intel_set_mode(save_set.crtc, save_set.mode,
9587                                    save_set.x, save_set.y, save_set.fb))
9588                         DRM_ERROR("failed to restore config after modeset failure\n");
9589         }
9590
9591 out_config:
9592         intel_set_config_free(config);
9593         return ret;
9594 }
9595
9596 static const struct drm_crtc_funcs intel_crtc_funcs = {
9597         .cursor_set = intel_crtc_cursor_set,
9598         .cursor_move = intel_crtc_cursor_move,
9599         .gamma_set = intel_crtc_gamma_set,
9600         .set_config = intel_crtc_set_config,
9601         .destroy = intel_crtc_destroy,
9602         .page_flip = intel_crtc_page_flip,
9603 };
9604
9605 static void intel_cpu_pll_init(struct drm_device *dev)
9606 {
9607         if (HAS_DDI(dev))
9608                 intel_ddi_pll_init(dev);
9609 }
9610
9611 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9612                                       struct intel_shared_dpll *pll,
9613                                       struct intel_dpll_hw_state *hw_state)
9614 {
9615         uint32_t val;
9616
9617         val = I915_READ(PCH_DPLL(pll->id));
9618         hw_state->dpll = val;
9619         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9620         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9621
9622         return val & DPLL_VCO_ENABLE;
9623 }
9624
9625 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9626                                   struct intel_shared_dpll *pll)
9627 {
9628         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9629         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9630 }
9631
9632 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9633                                 struct intel_shared_dpll *pll)
9634 {
9635         /* PCH refclock must be enabled first */
9636         assert_pch_refclk_enabled(dev_priv);
9637
9638         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9639
9640         /* Wait for the clocks to stabilize. */
9641         POSTING_READ(PCH_DPLL(pll->id));
9642         udelay(150);
9643
9644         /* The pixel multiplier can only be updated once the
9645          * DPLL is enabled and the clocks are stable.
9646          *
9647          * So write it again.
9648          */
9649         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9650         POSTING_READ(PCH_DPLL(pll->id));
9651         udelay(200);
9652 }
9653
9654 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9655                                  struct intel_shared_dpll *pll)
9656 {
9657         struct drm_device *dev = dev_priv->dev;
9658         struct intel_crtc *crtc;
9659
9660         /* Make sure no transcoder isn't still depending on us. */
9661         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9662                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9663                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9664         }
9665
9666         I915_WRITE(PCH_DPLL(pll->id), 0);
9667         POSTING_READ(PCH_DPLL(pll->id));
9668         udelay(200);
9669 }
9670
9671 static char *ibx_pch_dpll_names[] = {
9672         "PCH DPLL A",
9673         "PCH DPLL B",
9674 };
9675
9676 static void ibx_pch_dpll_init(struct drm_device *dev)
9677 {
9678         struct drm_i915_private *dev_priv = dev->dev_private;
9679         int i;
9680
9681         dev_priv->num_shared_dpll = 2;
9682
9683         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9684                 dev_priv->shared_dplls[i].id = i;
9685                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9686                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9687                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9688                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9689                 dev_priv->shared_dplls[i].get_hw_state =
9690                         ibx_pch_dpll_get_hw_state;
9691         }
9692 }
9693
9694 static void intel_shared_dpll_init(struct drm_device *dev)
9695 {
9696         struct drm_i915_private *dev_priv = dev->dev_private;
9697
9698         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9699                 ibx_pch_dpll_init(dev);
9700         else
9701                 dev_priv->num_shared_dpll = 0;
9702
9703         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9704         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9705                       dev_priv->num_shared_dpll);
9706 }
9707
9708 static void intel_crtc_init(struct drm_device *dev, int pipe)
9709 {
9710         drm_i915_private_t *dev_priv = dev->dev_private;
9711         struct intel_crtc *intel_crtc;
9712         int i;
9713
9714         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
9715         if (intel_crtc == NULL)
9716                 return;
9717
9718         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9719
9720         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9721         for (i = 0; i < 256; i++) {
9722                 intel_crtc->lut_r[i] = i;
9723                 intel_crtc->lut_g[i] = i;
9724                 intel_crtc->lut_b[i] = i;
9725         }
9726
9727         /* Swap pipes & planes for FBC on pre-965 */
9728         intel_crtc->pipe = pipe;
9729         intel_crtc->plane = pipe;
9730         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9731                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9732                 intel_crtc->plane = !pipe;
9733         }
9734
9735         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9736                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9737         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9738         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9739
9740         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9741 }
9742
9743 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9744                                 struct drm_file *file)
9745 {
9746         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9747         struct drm_mode_object *drmmode_obj;
9748         struct intel_crtc *crtc;
9749
9750         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9751                 return -ENODEV;
9752
9753         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9754                         DRM_MODE_OBJECT_CRTC);
9755
9756         if (!drmmode_obj) {
9757                 DRM_ERROR("no such CRTC id\n");
9758                 return -EINVAL;
9759         }
9760
9761         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9762         pipe_from_crtc_id->pipe = crtc->pipe;
9763
9764         return 0;
9765 }
9766
9767 static int intel_encoder_clones(struct intel_encoder *encoder)
9768 {
9769         struct drm_device *dev = encoder->base.dev;
9770         struct intel_encoder *source_encoder;
9771         int index_mask = 0;
9772         int entry = 0;
9773
9774         list_for_each_entry(source_encoder,
9775                             &dev->mode_config.encoder_list, base.head) {
9776
9777                 if (encoder == source_encoder)
9778                         index_mask |= (1 << entry);
9779
9780                 /* Intel hw has only one MUX where enocoders could be cloned. */
9781                 if (encoder->cloneable && source_encoder->cloneable)
9782                         index_mask |= (1 << entry);
9783
9784                 entry++;
9785         }
9786
9787         return index_mask;
9788 }
9789
9790 static bool has_edp_a(struct drm_device *dev)
9791 {
9792         struct drm_i915_private *dev_priv = dev->dev_private;
9793
9794         if (!IS_MOBILE(dev))
9795                 return false;
9796
9797         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9798                 return false;
9799
9800         if (IS_GEN5(dev) &&
9801             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9802                 return false;
9803
9804         return true;
9805 }
9806
9807 static void intel_setup_outputs(struct drm_device *dev)
9808 {
9809         struct drm_i915_private *dev_priv = dev->dev_private;
9810         struct intel_encoder *encoder;
9811         bool dpd_is_edp = false;
9812
9813         intel_lvds_init(dev);
9814
9815         if (!IS_ULT(dev))
9816                 intel_crt_init(dev);
9817
9818         if (HAS_DDI(dev)) {
9819                 int found;
9820
9821                 /* Haswell uses DDI functions to detect digital outputs */
9822                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9823                 /* DDI A only supports eDP */
9824                 if (found)
9825                         intel_ddi_init(dev, PORT_A);
9826
9827                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9828                  * register */
9829                 found = I915_READ(SFUSE_STRAP);
9830
9831                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9832                         intel_ddi_init(dev, PORT_B);
9833                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9834                         intel_ddi_init(dev, PORT_C);
9835                 if (found & SFUSE_STRAP_DDID_DETECTED)
9836                         intel_ddi_init(dev, PORT_D);
9837         } else if (HAS_PCH_SPLIT(dev)) {
9838                 int found;
9839                 dpd_is_edp = intel_dpd_is_edp(dev);
9840
9841                 if (has_edp_a(dev))
9842                         intel_dp_init(dev, DP_A, PORT_A);
9843
9844                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9845                         /* PCH SDVOB multiplex with HDMIB */
9846                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9847                         if (!found)
9848                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9849                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9850                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9851                 }
9852
9853                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9854                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9855
9856                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9857                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9858
9859                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9860                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9861
9862                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9863                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9864         } else if (IS_VALLEYVIEW(dev)) {
9865                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9866                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9867                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9868                                         PORT_C);
9869                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9870                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9871                                               PORT_C);
9872                 }
9873
9874                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9875                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9876                                         PORT_B);
9877                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9878                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9879                 }
9880
9881                 intel_dsi_init(dev);
9882         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9883                 bool found = false;
9884
9885                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9886                         DRM_DEBUG_KMS("probing SDVOB\n");
9887                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9888                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9889                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9890                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9891                         }
9892
9893                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9894                                 intel_dp_init(dev, DP_B, PORT_B);
9895                 }
9896
9897                 /* Before G4X SDVOC doesn't have its own detect register */
9898
9899                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9900                         DRM_DEBUG_KMS("probing SDVOC\n");
9901                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9902                 }
9903
9904                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9905
9906                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9907                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9908                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9909                         }
9910                         if (SUPPORTS_INTEGRATED_DP(dev))
9911                                 intel_dp_init(dev, DP_C, PORT_C);
9912                 }
9913
9914                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9915                     (I915_READ(DP_D) & DP_DETECTED))
9916                         intel_dp_init(dev, DP_D, PORT_D);
9917         } else if (IS_GEN2(dev))
9918                 intel_dvo_init(dev);
9919
9920         if (SUPPORTS_TV(dev))
9921                 intel_tv_init(dev);
9922
9923         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9924                 encoder->base.possible_crtcs = encoder->crtc_mask;
9925                 encoder->base.possible_clones =
9926                         intel_encoder_clones(encoder);
9927         }
9928
9929         intel_init_pch_refclk(dev);
9930
9931         drm_helper_move_panel_connectors_to_head(dev);
9932 }
9933
9934 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9935 {
9936         drm_framebuffer_cleanup(&fb->base);
9937         drm_gem_object_unreference_unlocked(&fb->obj->base);
9938 }
9939
9940 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9941 {
9942         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9943
9944         intel_framebuffer_fini(intel_fb);
9945         kfree(intel_fb);
9946 }
9947
9948 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9949                                                 struct drm_file *file,
9950                                                 unsigned int *handle)
9951 {
9952         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9953         struct drm_i915_gem_object *obj = intel_fb->obj;
9954
9955         return drm_gem_handle_create(file, &obj->base, handle);
9956 }
9957
9958 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9959         .destroy = intel_user_framebuffer_destroy,
9960         .create_handle = intel_user_framebuffer_create_handle,
9961 };
9962
9963 int intel_framebuffer_init(struct drm_device *dev,
9964                            struct intel_framebuffer *intel_fb,
9965                            struct drm_mode_fb_cmd2 *mode_cmd,
9966                            struct drm_i915_gem_object *obj)
9967 {
9968         int pitch_limit;
9969         int ret;
9970
9971         if (obj->tiling_mode == I915_TILING_Y) {
9972                 DRM_DEBUG("hardware does not support tiling Y\n");
9973                 return -EINVAL;
9974         }
9975
9976         if (mode_cmd->pitches[0] & 63) {
9977                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9978                           mode_cmd->pitches[0]);
9979                 return -EINVAL;
9980         }
9981
9982         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9983                 pitch_limit = 32*1024;
9984         } else if (INTEL_INFO(dev)->gen >= 4) {
9985                 if (obj->tiling_mode)
9986                         pitch_limit = 16*1024;
9987                 else
9988                         pitch_limit = 32*1024;
9989         } else if (INTEL_INFO(dev)->gen >= 3) {
9990                 if (obj->tiling_mode)
9991                         pitch_limit = 8*1024;
9992                 else
9993                         pitch_limit = 16*1024;
9994         } else
9995                 /* XXX DSPC is limited to 4k tiled */
9996                 pitch_limit = 8*1024;
9997
9998         if (mode_cmd->pitches[0] > pitch_limit) {
9999                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10000                           obj->tiling_mode ? "tiled" : "linear",
10001                           mode_cmd->pitches[0], pitch_limit);
10002                 return -EINVAL;
10003         }
10004
10005         if (obj->tiling_mode != I915_TILING_NONE &&
10006             mode_cmd->pitches[0] != obj->stride) {
10007                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10008                           mode_cmd->pitches[0], obj->stride);
10009                 return -EINVAL;
10010         }
10011
10012         /* Reject formats not supported by any plane early. */
10013         switch (mode_cmd->pixel_format) {
10014         case DRM_FORMAT_C8:
10015         case DRM_FORMAT_RGB565:
10016         case DRM_FORMAT_XRGB8888:
10017         case DRM_FORMAT_ARGB8888:
10018                 break;
10019         case DRM_FORMAT_XRGB1555:
10020         case DRM_FORMAT_ARGB1555:
10021                 if (INTEL_INFO(dev)->gen > 3) {
10022                         DRM_DEBUG("unsupported pixel format: %s\n",
10023                                   drm_get_format_name(mode_cmd->pixel_format));
10024                         return -EINVAL;
10025                 }
10026                 break;
10027         case DRM_FORMAT_XBGR8888:
10028         case DRM_FORMAT_ABGR8888:
10029         case DRM_FORMAT_XRGB2101010:
10030         case DRM_FORMAT_ARGB2101010:
10031         case DRM_FORMAT_XBGR2101010:
10032         case DRM_FORMAT_ABGR2101010:
10033                 if (INTEL_INFO(dev)->gen < 4) {
10034                         DRM_DEBUG("unsupported pixel format: %s\n",
10035                                   drm_get_format_name(mode_cmd->pixel_format));
10036                         return -EINVAL;
10037                 }
10038                 break;
10039         case DRM_FORMAT_YUYV:
10040         case DRM_FORMAT_UYVY:
10041         case DRM_FORMAT_YVYU:
10042         case DRM_FORMAT_VYUY:
10043                 if (INTEL_INFO(dev)->gen < 5) {
10044                         DRM_DEBUG("unsupported pixel format: %s\n",
10045                                   drm_get_format_name(mode_cmd->pixel_format));
10046                         return -EINVAL;
10047                 }
10048                 break;
10049         default:
10050                 DRM_DEBUG("unsupported pixel format: %s\n",
10051                           drm_get_format_name(mode_cmd->pixel_format));
10052                 return -EINVAL;
10053         }
10054
10055         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10056         if (mode_cmd->offsets[0] != 0)
10057                 return -EINVAL;
10058
10059         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10060         intel_fb->obj = obj;
10061
10062         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10063         if (ret) {
10064                 DRM_ERROR("framebuffer init failed %d\n", ret);
10065                 return ret;
10066         }
10067
10068         return 0;
10069 }
10070
10071 static struct drm_framebuffer *
10072 intel_user_framebuffer_create(struct drm_device *dev,
10073                               struct drm_file *filp,
10074                               struct drm_mode_fb_cmd2 *mode_cmd)
10075 {
10076         struct drm_i915_gem_object *obj;
10077
10078         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10079                                                 mode_cmd->handles[0]));
10080         if (&obj->base == NULL)
10081                 return ERR_PTR(-ENOENT);
10082
10083         return intel_framebuffer_create(dev, mode_cmd, obj);
10084 }
10085
10086 static const struct drm_mode_config_funcs intel_mode_funcs = {
10087         .fb_create = intel_user_framebuffer_create,
10088         .output_poll_changed = intel_fb_output_poll_changed,
10089 };
10090
10091 /* Set up chip specific display functions */
10092 static void intel_init_display(struct drm_device *dev)
10093 {
10094         struct drm_i915_private *dev_priv = dev->dev_private;
10095
10096         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10097                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10098         else if (IS_VALLEYVIEW(dev))
10099                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10100         else if (IS_PINEVIEW(dev))
10101                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10102         else
10103                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10104
10105         if (HAS_DDI(dev)) {
10106                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10107                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10108                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10109                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10110                 dev_priv->display.off = haswell_crtc_off;
10111                 dev_priv->display.update_plane = ironlake_update_plane;
10112         } else if (HAS_PCH_SPLIT(dev)) {
10113                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10114                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10115                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10116                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10117                 dev_priv->display.off = ironlake_crtc_off;
10118                 dev_priv->display.update_plane = ironlake_update_plane;
10119         } else if (IS_VALLEYVIEW(dev)) {
10120                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10121                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10122                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10123                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10124                 dev_priv->display.off = i9xx_crtc_off;
10125                 dev_priv->display.update_plane = i9xx_update_plane;
10126         } else {
10127                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10128                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10129                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10130                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10131                 dev_priv->display.off = i9xx_crtc_off;
10132                 dev_priv->display.update_plane = i9xx_update_plane;
10133         }
10134
10135         /* Returns the core display clock speed */
10136         if (IS_VALLEYVIEW(dev))
10137                 dev_priv->display.get_display_clock_speed =
10138                         valleyview_get_display_clock_speed;
10139         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10140                 dev_priv->display.get_display_clock_speed =
10141                         i945_get_display_clock_speed;
10142         else if (IS_I915G(dev))
10143                 dev_priv->display.get_display_clock_speed =
10144                         i915_get_display_clock_speed;
10145         else if (IS_I945GM(dev) || IS_845G(dev))
10146                 dev_priv->display.get_display_clock_speed =
10147                         i9xx_misc_get_display_clock_speed;
10148         else if (IS_PINEVIEW(dev))
10149                 dev_priv->display.get_display_clock_speed =
10150                         pnv_get_display_clock_speed;
10151         else if (IS_I915GM(dev))
10152                 dev_priv->display.get_display_clock_speed =
10153                         i915gm_get_display_clock_speed;
10154         else if (IS_I865G(dev))
10155                 dev_priv->display.get_display_clock_speed =
10156                         i865_get_display_clock_speed;
10157         else if (IS_I85X(dev))
10158                 dev_priv->display.get_display_clock_speed =
10159                         i855_get_display_clock_speed;
10160         else /* 852, 830 */
10161                 dev_priv->display.get_display_clock_speed =
10162                         i830_get_display_clock_speed;
10163
10164         if (HAS_PCH_SPLIT(dev)) {
10165                 if (IS_GEN5(dev)) {
10166                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10167                         dev_priv->display.write_eld = ironlake_write_eld;
10168                 } else if (IS_GEN6(dev)) {
10169                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10170                         dev_priv->display.write_eld = ironlake_write_eld;
10171                 } else if (IS_IVYBRIDGE(dev)) {
10172                         /* FIXME: detect B0+ stepping and use auto training */
10173                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10174                         dev_priv->display.write_eld = ironlake_write_eld;
10175                         dev_priv->display.modeset_global_resources =
10176                                 ivb_modeset_global_resources;
10177                 } else if (IS_HASWELL(dev)) {
10178                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10179                         dev_priv->display.write_eld = haswell_write_eld;
10180                         dev_priv->display.modeset_global_resources =
10181                                 haswell_modeset_global_resources;
10182                 }
10183         } else if (IS_G4X(dev)) {
10184                 dev_priv->display.write_eld = g4x_write_eld;
10185         }
10186
10187         /* Default just returns -ENODEV to indicate unsupported */
10188         dev_priv->display.queue_flip = intel_default_queue_flip;
10189
10190         switch (INTEL_INFO(dev)->gen) {
10191         case 2:
10192                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10193                 break;
10194
10195         case 3:
10196                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10197                 break;
10198
10199         case 4:
10200         case 5:
10201                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10202                 break;
10203
10204         case 6:
10205                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10206                 break;
10207         case 7:
10208                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10209                 break;
10210         }
10211 }
10212
10213 /*
10214  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10215  * resume, or other times.  This quirk makes sure that's the case for
10216  * affected systems.
10217  */
10218 static void quirk_pipea_force(struct drm_device *dev)
10219 {
10220         struct drm_i915_private *dev_priv = dev->dev_private;
10221
10222         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10223         DRM_INFO("applying pipe a force quirk\n");
10224 }
10225
10226 /*
10227  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10228  */
10229 static void quirk_ssc_force_disable(struct drm_device *dev)
10230 {
10231         struct drm_i915_private *dev_priv = dev->dev_private;
10232         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10233         DRM_INFO("applying lvds SSC disable quirk\n");
10234 }
10235
10236 /*
10237  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10238  * brightness value
10239  */
10240 static void quirk_invert_brightness(struct drm_device *dev)
10241 {
10242         struct drm_i915_private *dev_priv = dev->dev_private;
10243         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10244         DRM_INFO("applying inverted panel brightness quirk\n");
10245 }
10246
10247 /*
10248  * Some machines (Dell XPS13) suffer broken backlight controls if
10249  * BLM_PCH_PWM_ENABLE is set.
10250  */
10251 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10252 {
10253         struct drm_i915_private *dev_priv = dev->dev_private;
10254         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10255         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10256 }
10257
10258 struct intel_quirk {
10259         int device;
10260         int subsystem_vendor;
10261         int subsystem_device;
10262         void (*hook)(struct drm_device *dev);
10263 };
10264
10265 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10266 struct intel_dmi_quirk {
10267         void (*hook)(struct drm_device *dev);
10268         const struct dmi_system_id (*dmi_id_list)[];
10269 };
10270
10271 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10272 {
10273         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10274         return 1;
10275 }
10276
10277 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10278         {
10279                 .dmi_id_list = &(const struct dmi_system_id[]) {
10280                         {
10281                                 .callback = intel_dmi_reverse_brightness,
10282                                 .ident = "NCR Corporation",
10283                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10284                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10285                                 },
10286                         },
10287                         { }  /* terminating entry */
10288                 },
10289                 .hook = quirk_invert_brightness,
10290         },
10291 };
10292
10293 static struct intel_quirk intel_quirks[] = {
10294         /* HP Mini needs pipe A force quirk (LP: #322104) */
10295         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10296
10297         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10298         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10299
10300         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10301         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10302
10303         /* 830/845 need to leave pipe A & dpll A up */
10304         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10305         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10306
10307         /* Lenovo U160 cannot use SSC on LVDS */
10308         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10309
10310         /* Sony Vaio Y cannot use SSC on LVDS */
10311         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10312
10313         /*
10314          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10315          * seem to use inverted backlight PWM.
10316          */
10317         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10318
10319         /* Dell XPS13 HD Sandy Bridge */
10320         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10321         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10322         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10323 };
10324
10325 static void intel_init_quirks(struct drm_device *dev)
10326 {
10327         struct pci_dev *d = dev->pdev;
10328         int i;
10329
10330         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10331                 struct intel_quirk *q = &intel_quirks[i];
10332
10333                 if (d->device == q->device &&
10334                     (d->subsystem_vendor == q->subsystem_vendor ||
10335                      q->subsystem_vendor == PCI_ANY_ID) &&
10336                     (d->subsystem_device == q->subsystem_device ||
10337                      q->subsystem_device == PCI_ANY_ID))
10338                         q->hook(dev);
10339         }
10340         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10341                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10342                         intel_dmi_quirks[i].hook(dev);
10343         }
10344 }
10345
10346 /* Disable the VGA plane that we never use */
10347 static void i915_disable_vga(struct drm_device *dev)
10348 {
10349         struct drm_i915_private *dev_priv = dev->dev_private;
10350         u8 sr1;
10351         u32 vga_reg = i915_vgacntrl_reg(dev);
10352
10353         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10354         outb(SR01, VGA_SR_INDEX);
10355         sr1 = inb(VGA_SR_DATA);
10356         outb(sr1 | 1<<5, VGA_SR_DATA);
10357         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10358         udelay(300);
10359
10360         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10361         POSTING_READ(vga_reg);
10362 }
10363
10364 void intel_modeset_init_hw(struct drm_device *dev)
10365 {
10366         struct drm_i915_private *dev_priv = dev->dev_private;
10367
10368         intel_prepare_ddi(dev);
10369
10370         intel_init_clock_gating(dev);
10371
10372         /* Enable the CRI clock source so we can get at the display */
10373         if (IS_VALLEYVIEW(dev))
10374                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10375                            DPLL_INTEGRATED_CRI_CLK_VLV);
10376
10377         intel_init_dpio(dev);
10378
10379         mutex_lock(&dev->struct_mutex);
10380         intel_enable_gt_powersave(dev);
10381         mutex_unlock(&dev->struct_mutex);
10382 }
10383
10384 void intel_modeset_suspend_hw(struct drm_device *dev)
10385 {
10386         intel_suspend_hw(dev);
10387 }
10388
10389 void intel_modeset_init(struct drm_device *dev)
10390 {
10391         struct drm_i915_private *dev_priv = dev->dev_private;
10392         int i, j, ret;
10393
10394         drm_mode_config_init(dev);
10395
10396         dev->mode_config.min_width = 0;
10397         dev->mode_config.min_height = 0;
10398
10399         dev->mode_config.preferred_depth = 24;
10400         dev->mode_config.prefer_shadow = 1;
10401
10402         dev->mode_config.funcs = &intel_mode_funcs;
10403
10404         intel_init_quirks(dev);
10405
10406         intel_init_pm(dev);
10407
10408         if (INTEL_INFO(dev)->num_pipes == 0)
10409                 return;
10410
10411         intel_init_display(dev);
10412
10413         if (IS_GEN2(dev)) {
10414                 dev->mode_config.max_width = 2048;
10415                 dev->mode_config.max_height = 2048;
10416         } else if (IS_GEN3(dev)) {
10417                 dev->mode_config.max_width = 4096;
10418                 dev->mode_config.max_height = 4096;
10419         } else {
10420                 dev->mode_config.max_width = 8192;
10421                 dev->mode_config.max_height = 8192;
10422         }
10423         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10424
10425         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10426                       INTEL_INFO(dev)->num_pipes,
10427                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10428
10429         for_each_pipe(i) {
10430                 intel_crtc_init(dev, i);
10431                 for (j = 0; j < dev_priv->num_plane; j++) {
10432                         ret = intel_plane_init(dev, i, j);
10433                         if (ret)
10434                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10435                                               pipe_name(i), sprite_name(i, j), ret);
10436                 }
10437         }
10438
10439         intel_cpu_pll_init(dev);
10440         intel_shared_dpll_init(dev);
10441
10442         /* Just disable it once at startup */
10443         i915_disable_vga(dev);
10444         intel_setup_outputs(dev);
10445
10446         /* Just in case the BIOS is doing something questionable. */
10447         intel_disable_fbc(dev);
10448 }
10449
10450 static void
10451 intel_connector_break_all_links(struct intel_connector *connector)
10452 {
10453         connector->base.dpms = DRM_MODE_DPMS_OFF;
10454         connector->base.encoder = NULL;
10455         connector->encoder->connectors_active = false;
10456         connector->encoder->base.crtc = NULL;
10457 }
10458
10459 static void intel_enable_pipe_a(struct drm_device *dev)
10460 {
10461         struct intel_connector *connector;
10462         struct drm_connector *crt = NULL;
10463         struct intel_load_detect_pipe load_detect_temp;
10464
10465         /* We can't just switch on the pipe A, we need to set things up with a
10466          * proper mode and output configuration. As a gross hack, enable pipe A
10467          * by enabling the load detect pipe once. */
10468         list_for_each_entry(connector,
10469                             &dev->mode_config.connector_list,
10470                             base.head) {
10471                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10472                         crt = &connector->base;
10473                         break;
10474                 }
10475         }
10476
10477         if (!crt)
10478                 return;
10479
10480         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10481                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10482
10483
10484 }
10485
10486 static bool
10487 intel_check_plane_mapping(struct intel_crtc *crtc)
10488 {
10489         struct drm_device *dev = crtc->base.dev;
10490         struct drm_i915_private *dev_priv = dev->dev_private;
10491         u32 reg, val;
10492
10493         if (INTEL_INFO(dev)->num_pipes == 1)
10494                 return true;
10495
10496         reg = DSPCNTR(!crtc->plane);
10497         val = I915_READ(reg);
10498
10499         if ((val & DISPLAY_PLANE_ENABLE) &&
10500             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10501                 return false;
10502
10503         return true;
10504 }
10505
10506 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10507 {
10508         struct drm_device *dev = crtc->base.dev;
10509         struct drm_i915_private *dev_priv = dev->dev_private;
10510         u32 reg;
10511
10512         /* Clear any frame start delays used for debugging left by the BIOS */
10513         reg = PIPECONF(crtc->config.cpu_transcoder);
10514         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10515
10516         /* We need to sanitize the plane -> pipe mapping first because this will
10517          * disable the crtc (and hence change the state) if it is wrong. Note
10518          * that gen4+ has a fixed plane -> pipe mapping.  */
10519         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10520                 struct intel_connector *connector;
10521                 bool plane;
10522
10523                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10524                               crtc->base.base.id);
10525
10526                 /* Pipe has the wrong plane attached and the plane is active.
10527                  * Temporarily change the plane mapping and disable everything
10528                  * ...  */
10529                 plane = crtc->plane;
10530                 crtc->plane = !plane;
10531                 dev_priv->display.crtc_disable(&crtc->base);
10532                 crtc->plane = plane;
10533
10534                 /* ... and break all links. */
10535                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10536                                     base.head) {
10537                         if (connector->encoder->base.crtc != &crtc->base)
10538                                 continue;
10539
10540                         intel_connector_break_all_links(connector);
10541                 }
10542
10543                 WARN_ON(crtc->active);
10544                 crtc->base.enabled = false;
10545         }
10546
10547         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10548             crtc->pipe == PIPE_A && !crtc->active) {
10549                 /* BIOS forgot to enable pipe A, this mostly happens after
10550                  * resume. Force-enable the pipe to fix this, the update_dpms
10551                  * call below we restore the pipe to the right state, but leave
10552                  * the required bits on. */
10553                 intel_enable_pipe_a(dev);
10554         }
10555
10556         /* Adjust the state of the output pipe according to whether we
10557          * have active connectors/encoders. */
10558         intel_crtc_update_dpms(&crtc->base);
10559
10560         if (crtc->active != crtc->base.enabled) {
10561                 struct intel_encoder *encoder;
10562
10563                 /* This can happen either due to bugs in the get_hw_state
10564                  * functions or because the pipe is force-enabled due to the
10565                  * pipe A quirk. */
10566                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10567                               crtc->base.base.id,
10568                               crtc->base.enabled ? "enabled" : "disabled",
10569                               crtc->active ? "enabled" : "disabled");
10570
10571                 crtc->base.enabled = crtc->active;
10572
10573                 /* Because we only establish the connector -> encoder ->
10574                  * crtc links if something is active, this means the
10575                  * crtc is now deactivated. Break the links. connector
10576                  * -> encoder links are only establish when things are
10577                  *  actually up, hence no need to break them. */
10578                 WARN_ON(crtc->active);
10579
10580                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10581                         WARN_ON(encoder->connectors_active);
10582                         encoder->base.crtc = NULL;
10583                 }
10584         }
10585 }
10586
10587 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10588 {
10589         struct intel_connector *connector;
10590         struct drm_device *dev = encoder->base.dev;
10591
10592         /* We need to check both for a crtc link (meaning that the
10593          * encoder is active and trying to read from a pipe) and the
10594          * pipe itself being active. */
10595         bool has_active_crtc = encoder->base.crtc &&
10596                 to_intel_crtc(encoder->base.crtc)->active;
10597
10598         if (encoder->connectors_active && !has_active_crtc) {
10599                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10600                               encoder->base.base.id,
10601                               drm_get_encoder_name(&encoder->base));
10602
10603                 /* Connector is active, but has no active pipe. This is
10604                  * fallout from our resume register restoring. Disable
10605                  * the encoder manually again. */
10606                 if (encoder->base.crtc) {
10607                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10608                                       encoder->base.base.id,
10609                                       drm_get_encoder_name(&encoder->base));
10610                         encoder->disable(encoder);
10611                 }
10612
10613                 /* Inconsistent output/port/pipe state happens presumably due to
10614                  * a bug in one of the get_hw_state functions. Or someplace else
10615                  * in our code, like the register restore mess on resume. Clamp
10616                  * things to off as a safer default. */
10617                 list_for_each_entry(connector,
10618                                     &dev->mode_config.connector_list,
10619                                     base.head) {
10620                         if (connector->encoder != encoder)
10621                                 continue;
10622
10623                         intel_connector_break_all_links(connector);
10624                 }
10625         }
10626         /* Enabled encoders without active connectors will be fixed in
10627          * the crtc fixup. */
10628 }
10629
10630 void i915_redisable_vga(struct drm_device *dev)
10631 {
10632         struct drm_i915_private *dev_priv = dev->dev_private;
10633         u32 vga_reg = i915_vgacntrl_reg(dev);
10634
10635         /* This function can be called both from intel_modeset_setup_hw_state or
10636          * at a very early point in our resume sequence, where the power well
10637          * structures are not yet restored. Since this function is at a very
10638          * paranoid "someone might have enabled VGA while we were not looking"
10639          * level, just check if the power well is enabled instead of trying to
10640          * follow the "don't touch the power well if we don't need it" policy
10641          * the rest of the driver uses. */
10642         if (HAS_POWER_WELL(dev) &&
10643             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10644                 return;
10645
10646         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10647                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10648                 i915_disable_vga(dev);
10649         }
10650 }
10651
10652 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10653 {
10654         struct drm_i915_private *dev_priv = dev->dev_private;
10655         enum pipe pipe;
10656         struct intel_crtc *crtc;
10657         struct intel_encoder *encoder;
10658         struct intel_connector *connector;
10659         int i;
10660
10661         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10662                             base.head) {
10663                 memset(&crtc->config, 0, sizeof(crtc->config));
10664
10665                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10666                                                                  &crtc->config);
10667
10668                 crtc->base.enabled = crtc->active;
10669
10670                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10671                               crtc->base.base.id,
10672                               crtc->active ? "enabled" : "disabled");
10673         }
10674
10675         /* FIXME: Smash this into the new shared dpll infrastructure. */
10676         if (HAS_DDI(dev))
10677                 intel_ddi_setup_hw_pll_state(dev);
10678
10679         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10680                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10681
10682                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10683                 pll->active = 0;
10684                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10685                                     base.head) {
10686                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10687                                 pll->active++;
10688                 }
10689                 pll->refcount = pll->active;
10690
10691                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10692                               pll->name, pll->refcount, pll->on);
10693         }
10694
10695         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10696                             base.head) {
10697                 pipe = 0;
10698
10699                 if (encoder->get_hw_state(encoder, &pipe)) {
10700                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10701                         encoder->base.crtc = &crtc->base;
10702                         if (encoder->get_config)
10703                                 encoder->get_config(encoder, &crtc->config);
10704                 } else {
10705                         encoder->base.crtc = NULL;
10706                 }
10707
10708                 encoder->connectors_active = false;
10709                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10710                               encoder->base.base.id,
10711                               drm_get_encoder_name(&encoder->base),
10712                               encoder->base.crtc ? "enabled" : "disabled",
10713                               pipe);
10714         }
10715
10716         list_for_each_entry(connector, &dev->mode_config.connector_list,
10717                             base.head) {
10718                 if (connector->get_hw_state(connector)) {
10719                         connector->base.dpms = DRM_MODE_DPMS_ON;
10720                         connector->encoder->connectors_active = true;
10721                         connector->base.encoder = &connector->encoder->base;
10722                 } else {
10723                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10724                         connector->base.encoder = NULL;
10725                 }
10726                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10727                               connector->base.base.id,
10728                               drm_get_connector_name(&connector->base),
10729                               connector->base.encoder ? "enabled" : "disabled");
10730         }
10731 }
10732
10733 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10734  * and i915 state tracking structures. */
10735 void intel_modeset_setup_hw_state(struct drm_device *dev,
10736                                   bool force_restore)
10737 {
10738         struct drm_i915_private *dev_priv = dev->dev_private;
10739         enum pipe pipe;
10740         struct intel_crtc *crtc;
10741         struct intel_encoder *encoder;
10742         int i;
10743
10744         intel_modeset_readout_hw_state(dev);
10745
10746         /*
10747          * Now that we have the config, copy it to each CRTC struct
10748          * Note that this could go away if we move to using crtc_config
10749          * checking everywhere.
10750          */
10751         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10752                             base.head) {
10753                 if (crtc->active && i915_fastboot) {
10754                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10755
10756                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10757                                       crtc->base.base.id);
10758                         drm_mode_debug_printmodeline(&crtc->base.mode);
10759                 }
10760         }
10761
10762         /* HW state is read out, now we need to sanitize this mess. */
10763         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10764                             base.head) {
10765                 intel_sanitize_encoder(encoder);
10766         }
10767
10768         for_each_pipe(pipe) {
10769                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10770                 intel_sanitize_crtc(crtc);
10771                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10772         }
10773
10774         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10775                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10776
10777                 if (!pll->on || pll->active)
10778                         continue;
10779
10780                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10781
10782                 pll->disable(dev_priv, pll);
10783                 pll->on = false;
10784         }
10785
10786         if (force_restore) {
10787                 i915_redisable_vga(dev);
10788
10789                 /*
10790                  * We need to use raw interfaces for restoring state to avoid
10791                  * checking (bogus) intermediate states.
10792                  */
10793                 for_each_pipe(pipe) {
10794                         struct drm_crtc *crtc =
10795                                 dev_priv->pipe_to_crtc_mapping[pipe];
10796
10797                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10798                                          crtc->fb);
10799                 }
10800         } else {
10801                 intel_modeset_update_staged_output_state(dev);
10802         }
10803
10804         intel_modeset_check_state(dev);
10805
10806         drm_mode_config_reset(dev);
10807 }
10808
10809 void intel_modeset_gem_init(struct drm_device *dev)
10810 {
10811         intel_modeset_init_hw(dev);
10812
10813         intel_setup_overlay(dev);
10814
10815         intel_modeset_setup_hw_state(dev, false);
10816 }
10817
10818 void intel_modeset_cleanup(struct drm_device *dev)
10819 {
10820         struct drm_i915_private *dev_priv = dev->dev_private;
10821         struct drm_crtc *crtc;
10822         struct drm_connector *connector;
10823
10824         /*
10825          * Interrupts and polling as the first thing to avoid creating havoc.
10826          * Too much stuff here (turning of rps, connectors, ...) would
10827          * experience fancy races otherwise.
10828          */
10829         drm_irq_uninstall(dev);
10830         cancel_work_sync(&dev_priv->hotplug_work);
10831         /*
10832          * Due to the hpd irq storm handling the hotplug work can re-arm the
10833          * poll handlers. Hence disable polling after hpd handling is shut down.
10834          */
10835         drm_kms_helper_poll_fini(dev);
10836
10837         mutex_lock(&dev->struct_mutex);
10838
10839         intel_unregister_dsm_handler();
10840
10841         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10842                 /* Skip inactive CRTCs */
10843                 if (!crtc->fb)
10844                         continue;
10845
10846                 intel_increase_pllclock(crtc);
10847         }
10848
10849         intel_disable_fbc(dev);
10850
10851         intel_disable_gt_powersave(dev);
10852
10853         ironlake_teardown_rc6(dev);
10854
10855         mutex_unlock(&dev->struct_mutex);
10856
10857         /* flush any delayed tasks or pending work */
10858         flush_scheduled_work();
10859
10860         /* destroy backlight, if any, before the connectors */
10861         intel_panel_destroy_backlight(dev);
10862
10863         /* destroy the sysfs files before encoders/connectors */
10864         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10865                 drm_sysfs_connector_remove(connector);
10866
10867         drm_mode_config_cleanup(dev);
10868
10869         intel_cleanup_overlay(dev);
10870 }
10871
10872 /*
10873  * Return which encoder is currently attached for connector.
10874  */
10875 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10876 {
10877         return &intel_attached_encoder(connector)->base;
10878 }
10879
10880 void intel_connector_attach_encoder(struct intel_connector *connector,
10881                                     struct intel_encoder *encoder)
10882 {
10883         connector->encoder = encoder;
10884         drm_mode_connector_attach_encoder(&connector->base,
10885                                           &encoder->base);
10886 }
10887
10888 /*
10889  * set vga decode state - true == enable VGA decode
10890  */
10891 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10892 {
10893         struct drm_i915_private *dev_priv = dev->dev_private;
10894         u16 gmch_ctrl;
10895
10896         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10897         if (state)
10898                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10899         else
10900                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10901         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10902         return 0;
10903 }
10904
10905 struct intel_display_error_state {
10906
10907         u32 power_well_driver;
10908
10909         int num_transcoders;
10910
10911         struct intel_cursor_error_state {
10912                 u32 control;
10913                 u32 position;
10914                 u32 base;
10915                 u32 size;
10916         } cursor[I915_MAX_PIPES];
10917
10918         struct intel_pipe_error_state {
10919                 u32 source;
10920         } pipe[I915_MAX_PIPES];
10921
10922         struct intel_plane_error_state {
10923                 u32 control;
10924                 u32 stride;
10925                 u32 size;
10926                 u32 pos;
10927                 u32 addr;
10928                 u32 surface;
10929                 u32 tile_offset;
10930         } plane[I915_MAX_PIPES];
10931
10932         struct intel_transcoder_error_state {
10933                 enum transcoder cpu_transcoder;
10934
10935                 u32 conf;
10936
10937                 u32 htotal;
10938                 u32 hblank;
10939                 u32 hsync;
10940                 u32 vtotal;
10941                 u32 vblank;
10942                 u32 vsync;
10943         } transcoder[4];
10944 };
10945
10946 struct intel_display_error_state *
10947 intel_display_capture_error_state(struct drm_device *dev)
10948 {
10949         drm_i915_private_t *dev_priv = dev->dev_private;
10950         struct intel_display_error_state *error;
10951         int transcoders[] = {
10952                 TRANSCODER_A,
10953                 TRANSCODER_B,
10954                 TRANSCODER_C,
10955                 TRANSCODER_EDP,
10956         };
10957         int i;
10958
10959         if (INTEL_INFO(dev)->num_pipes == 0)
10960                 return NULL;
10961
10962         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10963         if (error == NULL)
10964                 return NULL;
10965
10966         if (HAS_POWER_WELL(dev))
10967                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10968
10969         for_each_pipe(i) {
10970                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10971                         error->cursor[i].control = I915_READ(CURCNTR(i));
10972                         error->cursor[i].position = I915_READ(CURPOS(i));
10973                         error->cursor[i].base = I915_READ(CURBASE(i));
10974                 } else {
10975                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10976                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10977                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10978                 }
10979
10980                 error->plane[i].control = I915_READ(DSPCNTR(i));
10981                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10982                 if (INTEL_INFO(dev)->gen <= 3) {
10983                         error->plane[i].size = I915_READ(DSPSIZE(i));
10984                         error->plane[i].pos = I915_READ(DSPPOS(i));
10985                 }
10986                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10987                         error->plane[i].addr = I915_READ(DSPADDR(i));
10988                 if (INTEL_INFO(dev)->gen >= 4) {
10989                         error->plane[i].surface = I915_READ(DSPSURF(i));
10990                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10991                 }
10992
10993                 error->pipe[i].source = I915_READ(PIPESRC(i));
10994         }
10995
10996         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10997         if (HAS_DDI(dev_priv->dev))
10998                 error->num_transcoders++; /* Account for eDP. */
10999
11000         for (i = 0; i < error->num_transcoders; i++) {
11001                 enum transcoder cpu_transcoder = transcoders[i];
11002
11003                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11004
11005                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11006                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11007                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11008                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11009                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11010                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11011                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11012         }
11013
11014         /* In the code above we read the registers without checking if the power
11015          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11016          * prevent the next I915_WRITE from detecting it and printing an error
11017          * message. */
11018         intel_uncore_clear_errors(dev);
11019
11020         return error;
11021 }
11022
11023 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11024
11025 void
11026 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11027                                 struct drm_device *dev,
11028                                 struct intel_display_error_state *error)
11029 {
11030         int i;
11031
11032         if (!error)
11033                 return;
11034
11035         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11036         if (HAS_POWER_WELL(dev))
11037                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11038                            error->power_well_driver);
11039         for_each_pipe(i) {
11040                 err_printf(m, "Pipe [%d]:\n", i);
11041                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11042
11043                 err_printf(m, "Plane [%d]:\n", i);
11044                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11045                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11046                 if (INTEL_INFO(dev)->gen <= 3) {
11047                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11048                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11049                 }
11050                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11051                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11052                 if (INTEL_INFO(dev)->gen >= 4) {
11053                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11054                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11055                 }
11056
11057                 err_printf(m, "Cursor [%d]:\n", i);
11058                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11059                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11060                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11061         }
11062
11063         for (i = 0; i < error->num_transcoders; i++) {
11064                 err_printf(m, "  CPU transcoder: %c\n",
11065                            transcoder_name(error->transcoder[i].cpu_transcoder));
11066                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11067                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11068                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11069                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11070                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11071                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11072                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11073         }
11074 }