drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <drm/i915_powerwell.h>
  34
  35 /**
  36  * RC6 is a special power stage which allows the GPU to enter an very
  37  * low-voltage mode when idle, using down to 0V while at this stage.  This
  38  * stage is entered automatically when the GPU is idle when RC6 support is
  39  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  40  *
  41  * There are different RC6 modes available in Intel GPU, which differentiate
  42  * among each other with the latency required to enter and leave RC6 and
  43  * voltage consumed by the GPU in different states.
  44  *
  45  * The combination of the following flags define which states GPU is allowed
  46  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  47  * RC6pp is deepest RC6. Their support by hardware varies according to the
  48  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  49  * which brings the most power savings; deeper states save more power, but
  50  * require higher latency to switch to and wake up.
  51  */
  52 #define INTEL_RC6_ENABLE                        (1<<0)
  53 #define INTEL_RC6p_ENABLE                       (1<<1)
  54 #define INTEL_RC6pp_ENABLE                      (1<<2)
  55
  56 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  57  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  58  * during in-memory transfers and, therefore, reduce the power packet.
  59  *
  60  * The benefits of FBC are mostly visible with solid backgrounds and
  61  * variation-less patterns.
  62  *
  63  * FBC-related functionality can be enabled by the means of the
  64  * i915.i915_enable_fbc parameter
  65  */
  66
  67 static void i8xx_disable_fbc(struct drm_device *dev)
  68 {
  69         struct drm_i915_private *dev_priv = dev->dev_private;
  70         u32 fbc_ctl;
  71
  72         /* Disable compression */
  73         fbc_ctl = I915_READ(FBC_CONTROL);
  74         if ((fbc_ctl & FBC_CTL_EN) == 0)
  75                 return;
  76
  77         fbc_ctl &= ~FBC_CTL_EN;
  78         I915_WRITE(FBC_CONTROL, fbc_ctl);
  79
  80         /* Wait for compressing bit to clear */
  81         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  82                 DRM_DEBUG_KMS("FBC idle timed out\n");
  83                 return;
  84         }
  85
  86         DRM_DEBUG_KMS("disabled FBC\n");
  87 }
  88
  89 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  90 {
  91         struct drm_device *dev = crtc->dev;
  92         struct drm_i915_private *dev_priv = dev->dev_private;
  93         struct drm_framebuffer *fb = crtc->fb;
  94         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  95         struct drm_i915_gem_object *obj = intel_fb->obj;
  96         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  97         int cfb_pitch;
  98         int plane, i;
  99         u32 fbc_ctl, fbc_ctl2;
 100
 101         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 102         if (fb->pitches[0] < cfb_pitch)
 103                 cfb_pitch = fb->pitches[0];
 104
 105         /* FBC_CTL wants 64B units */
 106         cfb_pitch = (cfb_pitch / 64) - 1;
 107         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 108
 109         /* Clear old tags */
 110         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 111                 I915_WRITE(FBC_TAG + (i * 4), 0);
 112
 113         /* Set it up... */
 114         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 115         fbc_ctl2 |= plane;
 116         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 117         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 118
 119         /* enable it... */
 120         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 121         if (IS_I945GM(dev))
 122                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 123         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 124         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 125         fbc_ctl |= obj->fence_reg;
 126         I915_WRITE(FBC_CONTROL, fbc_ctl);
 127
 128         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 129                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 130 }
 131
 132 static bool i8xx_fbc_enabled(struct drm_device *dev)
 133 {
 134         struct drm_i915_private *dev_priv = dev->dev_private;
 135
 136         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 137 }
 138
 139 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 140 {
 141         struct drm_device *dev = crtc->dev;
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143         struct drm_framebuffer *fb = crtc->fb;
 144         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 145         struct drm_i915_gem_object *obj = intel_fb->obj;
 146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 147         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 148         unsigned long stall_watermark = 200;
 149         u32 dpfc_ctl;
 150
 151         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 152         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 153         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 154
 155         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 156                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 157                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 158         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 159
 160         /* enable it... */
 161         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 162
 163         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 164 }
 165
 166 static void g4x_disable_fbc(struct drm_device *dev)
 167 {
 168         struct drm_i915_private *dev_priv = dev->dev_private;
 169         u32 dpfc_ctl;
 170
 171         /* Disable compression */
 172         dpfc_ctl = I915_READ(DPFC_CONTROL);
 173         if (dpfc_ctl & DPFC_CTL_EN) {
 174                 dpfc_ctl &= ~DPFC_CTL_EN;
 175                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 176
 177                 DRM_DEBUG_KMS("disabled FBC\n");
 178         }
 179 }
 180
 181 static bool g4x_fbc_enabled(struct drm_device *dev)
 182 {
 183         struct drm_i915_private *dev_priv = dev->dev_private;
 184
 185         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 186 }
 187
 188 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         u32 blt_ecoskpd;
 192
 193         /* Make sure blitter notifies FBC of writes */
 194         gen6_gt_force_wake_get(dev_priv);
 195         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 196         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 197                 GEN6_BLITTER_LOCK_SHIFT;
 198         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 199         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 200         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 201         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 202                          GEN6_BLITTER_LOCK_SHIFT);
 203         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 204         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 205         gen6_gt_force_wake_put(dev_priv);
 206 }
 207
 208 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 209 {
 210         struct drm_device *dev = crtc->dev;
 211         struct drm_i915_private *dev_priv = dev->dev_private;
 212         struct drm_framebuffer *fb = crtc->fb;
 213         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 214         struct drm_i915_gem_object *obj = intel_fb->obj;
 215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 216         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 217         unsigned long stall_watermark = 200;
 218         u32 dpfc_ctl;
 219
 220         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 221         dpfc_ctl &= DPFC_RESERVED;
 222         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 223         /* Set persistent mode for front-buffer rendering, ala X. */
 224         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 225         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 226         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 227
 228         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 229                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 230                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 231         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 232         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 233         /* enable it... */
 234         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 235
 236         if (IS_GEN6(dev)) {
 237                 I915_WRITE(SNB_DPFC_CTL_SA,
 238                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 239                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 240                 sandybridge_blit_fbc_update(dev);
 241         }
 242
 243         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 244 }
 245
 246 static void ironlake_disable_fbc(struct drm_device *dev)
 247 {
 248         struct drm_i915_private *dev_priv = dev->dev_private;
 249         u32 dpfc_ctl;
 250
 251         /* Disable compression */
 252         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 253         if (dpfc_ctl & DPFC_CTL_EN) {
 254                 dpfc_ctl &= ~DPFC_CTL_EN;
 255                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 256
 257                 if (IS_IVYBRIDGE(dev))
 258                         /* WaFbcDisableDpfcClockGating:ivb */
 259                         I915_WRITE(ILK_DSPCLK_GATE_D,
 260                                    I915_READ(ILK_DSPCLK_GATE_D) &
 261                                    ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 262
 263                 if (IS_HASWELL(dev))
 264                         /* WaFbcDisableDpfcClockGating:hsw */
 265                         I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 266                                    I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
 267                                    ~HSW_DPFC_GATING_DISABLE);
 268
 269                 DRM_DEBUG_KMS("disabled FBC\n");
 270         }
 271 }
 272
 273 static bool ironlake_fbc_enabled(struct drm_device *dev)
 274 {
 275         struct drm_i915_private *dev_priv = dev->dev_private;
 276
 277         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 278 }
 279
 280 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 281 {
 282         struct drm_device *dev = crtc->dev;
 283         struct drm_i915_private *dev_priv = dev->dev_private;
 284         struct drm_framebuffer *fb = crtc->fb;
 285         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 286         struct drm_i915_gem_object *obj = intel_fb->obj;
 287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 288
 289         I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
 290
 291         I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
 292                    IVB_DPFC_CTL_FENCE_EN |
 293                    intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 294
 295         if (IS_IVYBRIDGE(dev)) {
 296                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 297                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 298                 /* WaFbcDisableDpfcClockGating:ivb */
 299                 I915_WRITE(ILK_DSPCLK_GATE_D,
 300                            I915_READ(ILK_DSPCLK_GATE_D) |
 301                            ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 302         } else {
 303                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
 304                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 305                            HSW_BYPASS_FBC_QUEUE);
 306                 /* WaFbcDisableDpfcClockGating:hsw */
 307                 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 308                            I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
 309                            HSW_DPFC_GATING_DISABLE);
 310         }
 311
 312         I915_WRITE(SNB_DPFC_CTL_SA,
 313                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 314         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 315
 316         sandybridge_blit_fbc_update(dev);
 317
 318         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 319 }
 320
 321 bool intel_fbc_enabled(struct drm_device *dev)
 322 {
 323         struct drm_i915_private *dev_priv = dev->dev_private;
 324
 325         if (!dev_priv->display.fbc_enabled)
 326                 return false;
 327
 328         return dev_priv->display.fbc_enabled(dev);
 329 }
 330
 331 static void intel_fbc_work_fn(struct work_struct *__work)
 332 {
 333         struct intel_fbc_work *work =
 334                 container_of(to_delayed_work(__work),
 335                              struct intel_fbc_work, work);
 336         struct drm_device *dev = work->crtc->dev;
 337         struct drm_i915_private *dev_priv = dev->dev_private;
 338
 339         mutex_lock(&dev->struct_mutex);
 340         if (work == dev_priv->fbc.fbc_work) {
 341                 /* Double check that we haven't switched fb without cancelling
 342                  * the prior work.
 343                  */
 344                 if (work->crtc->fb == work->fb) {
 345                         dev_priv->display.enable_fbc(work->crtc,
 346                                                      work->interval);
 347
 348                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 349                         dev_priv->fbc.fb_id = work->crtc->fb->base.id;
 350                         dev_priv->fbc.y = work->crtc->y;
 351                 }
 352
 353                 dev_priv->fbc.fbc_work = NULL;
 354         }
 355         mutex_unlock(&dev->struct_mutex);
 356
 357         kfree(work);
 358 }
 359
 360 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 361 {
 362         if (dev_priv->fbc.fbc_work == NULL)
 363                 return;
 364
 365         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 366
 367         /* Synchronisation is provided by struct_mutex and checking of
 368          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 369          * entirely asynchronously.
 370          */
 371         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 372                 /* tasklet was killed before being run, clean up */
 373                 kfree(dev_priv->fbc.fbc_work);
 374
 375         /* Mark the work as no longer wanted so that if it does
 376          * wake-up (because the work was already running and waiting
 377          * for our mutex), it will discover that is no longer
 378          * necessary to run.
 379          */
 380         dev_priv->fbc.fbc_work = NULL;
 381 }
 382
 383 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 384 {
 385         struct intel_fbc_work *work;
 386         struct drm_device *dev = crtc->dev;
 387         struct drm_i915_private *dev_priv = dev->dev_private;
 388
 389         if (!dev_priv->display.enable_fbc)
 390                 return;
 391
 392         intel_cancel_fbc_work(dev_priv);
 393
 394         work = kzalloc(sizeof(*work), GFP_KERNEL);
 395         if (work == NULL) {
 396                 DRM_ERROR("Failed to allocate FBC work structure\n");
 397                 dev_priv->display.enable_fbc(crtc, interval);
 398                 return;
 399         }
 400
 401         work->crtc = crtc;
 402         work->fb = crtc->fb;
 403         work->interval = interval;
 404         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 405
 406         dev_priv->fbc.fbc_work = work;
 407
 408         /* Delay the actual enabling to let pageflipping cease and the
 409          * display to settle before starting the compression. Note that
 410          * this delay also serves a second purpose: it allows for a
 411          * vblank to pass after disabling the FBC before we attempt
 412          * to modify the control registers.
 413          *
 414          * A more complicated solution would involve tracking vblanks
 415          * following the termination of the page-flipping sequence
 416          * and indeed performing the enable as a co-routine and not
 417          * waiting synchronously upon the vblank.
 418          *
 419          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 420          */
 421         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 422 }
 423
 424 void intel_disable_fbc(struct drm_device *dev)
 425 {
 426         struct drm_i915_private *dev_priv = dev->dev_private;
 427
 428         intel_cancel_fbc_work(dev_priv);
 429
 430         if (!dev_priv->display.disable_fbc)
 431                 return;
 432
 433         dev_priv->display.disable_fbc(dev);
 434         dev_priv->fbc.plane = -1;
 435 }
 436
 437 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 438                               enum no_fbc_reason reason)
 439 {
 440         if (dev_priv->fbc.no_fbc_reason == reason)
 441                 return false;
 442
 443         dev_priv->fbc.no_fbc_reason = reason;
 444         return true;
 445 }
 446
 447 /**
 448  * intel_update_fbc - enable/disable FBC as needed
 449  * @dev: the drm_device
 450  *
 451  * Set up the framebuffer compression hardware at mode set time.  We
 452  * enable it if possible:
 453  *   - plane A only (on pre-965)
 454  *   - no pixel mulitply/line duplication
 455  *   - no alpha buffer discard
 456  *   - no dual wide
 457  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 458  *
 459  * We can't assume that any compression will take place (worst case),
 460  * so the compressed buffer has to be the same size as the uncompressed
 461  * one.  It also must reside (along with the line length buffer) in
 462  * stolen memory.
 463  *
 464  * We need to enable/disable FBC on a global basis.
 465  */
 466 void intel_update_fbc(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469         struct drm_crtc *crtc = NULL, *tmp_crtc;
 470         struct intel_crtc *intel_crtc;
 471         struct drm_framebuffer *fb;
 472         struct intel_framebuffer *intel_fb;
 473         struct drm_i915_gem_object *obj;
 474         const struct drm_display_mode *adjusted_mode;
 475         unsigned int max_width, max_height;
 476
 477         if (!I915_HAS_FBC(dev)) {
 478                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 479                 return;
 480         }
 481
 482         if (!i915_powersave) {
 483                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 484                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 485                 return;
 486         }
 487
 488         /*
 489          * If FBC is already on, we just have to verify that we can
 490          * keep it that way...
 491          * Need to disable if:
 492          *   - more than one pipe is active
 493          *   - changing FBC params (stride, fence, mode)
 494          *   - new fb is too large to fit in compressed buffer
 495          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 496          */
 497         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 498                 if (intel_crtc_active(tmp_crtc) &&
 499                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 500                         if (crtc) {
 501                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 502                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 503                                 goto out_disable;
 504                         }
 505                         crtc = tmp_crtc;
 506                 }
 507         }
 508
 509         if (!crtc || crtc->fb == NULL) {
 510                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 511                         DRM_DEBUG_KMS("no output, disabling\n");
 512                 goto out_disable;
 513         }
 514
 515         intel_crtc = to_intel_crtc(crtc);
 516         fb = crtc->fb;
 517         intel_fb = to_intel_framebuffer(fb);
 518         obj = intel_fb->obj;
 519         adjusted_mode = &intel_crtc->config.adjusted_mode;
 520
 521         if (i915_enable_fbc < 0 &&
 522             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 523                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 524                         DRM_DEBUG_KMS("disabled per chip default\n");
 525                 goto out_disable;
 526         }
 527         if (!i915_enable_fbc) {
 528                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 529                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 530                 goto out_disable;
 531         }
 532         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 533             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 534                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 535                         DRM_DEBUG_KMS("mode incompatible with compression, "
 536                                       "disabling\n");
 537                 goto out_disable;
 538         }
 539
 540         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 541                 max_width = 4096;
 542                 max_height = 2048;
 543         } else {
 544                 max_width = 2048;
 545                 max_height = 1536;
 546         }
 547         if (intel_crtc->config.pipe_src_w > max_width ||
 548             intel_crtc->config.pipe_src_h > max_height) {
 549                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 550                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 551                 goto out_disable;
 552         }
 553         if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
 554             intel_crtc->plane != 0) {
 555                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 556                         DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 557                 goto out_disable;
 558         }
 559
 560         /* The use of a CPU fence is mandatory in order to detect writes
 561          * by the CPU to the scanout and trigger updates to the FBC.
 562          */
 563         if (obj->tiling_mode != I915_TILING_X ||
 564             obj->fence_reg == I915_FENCE_REG_NONE) {
 565                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 566                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 567                 goto out_disable;
 568         }
 569
 570         /* If the kernel debugger is active, always disable compression */
 571         if (in_dbg_master())
 572                 goto out_disable;
 573
 574         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 575                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 576                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 577                 goto out_disable;
 578         }
 579
 580         /* If the scanout has not changed, don't modify the FBC settings.
 581          * Note that we make the fundamental assumption that the fb->obj
 582          * cannot be unpinned (and have its GTT offset and fence revoked)
 583          * without first being decoupled from the scanout and FBC disabled.
 584          */
 585         if (dev_priv->fbc.plane == intel_crtc->plane &&
 586             dev_priv->fbc.fb_id == fb->base.id &&
 587             dev_priv->fbc.y == crtc->y)
 588                 return;
 589
 590         if (intel_fbc_enabled(dev)) {
 591                 /* We update FBC along two paths, after changing fb/crtc
 592                  * configuration (modeswitching) and after page-flipping
 593                  * finishes. For the latter, we know that not only did
 594                  * we disable the FBC at the start of the page-flip
 595                  * sequence, but also more than one vblank has passed.
 596                  *
 597                  * For the former case of modeswitching, it is possible
 598                  * to switch between two FBC valid configurations
 599                  * instantaneously so we do need to disable the FBC
 600                  * before we can modify its control registers. We also
 601                  * have to wait for the next vblank for that to take
 602                  * effect. However, since we delay enabling FBC we can
 603                  * assume that a vblank has passed since disabling and
 604                  * that we can safely alter the registers in the deferred
 605                  * callback.
 606                  *
 607                  * In the scenario that we go from a valid to invalid
 608                  * and then back to valid FBC configuration we have
 609                  * no strict enforcement that a vblank occurred since
 610                  * disabling the FBC. However, along all current pipe
 611                  * disabling paths we do need to wait for a vblank at
 612                  * some point. And we wait before enabling FBC anyway.
 613                  */
 614                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 615                 intel_disable_fbc(dev);
 616         }
 617
 618         intel_enable_fbc(crtc, 500);
 619         dev_priv->fbc.no_fbc_reason = FBC_OK;
 620         return;
 621
 622 out_disable:
 623         /* Multiple disables should be harmless */
 624         if (intel_fbc_enabled(dev)) {
 625                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 626                 intel_disable_fbc(dev);
 627         }
 628         i915_gem_stolen_cleanup_compression(dev);
 629 }
 630
 631 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 632 {
 633         drm_i915_private_t *dev_priv = dev->dev_private;
 634         u32 tmp;
 635
 636         tmp = I915_READ(CLKCFG);
 637
 638         switch (tmp & CLKCFG_FSB_MASK) {
 639         case CLKCFG_FSB_533:
 640                 dev_priv->fsb_freq = 533; /* 133*4 */
 641                 break;
 642         case CLKCFG_FSB_800:
 643                 dev_priv->fsb_freq = 800; /* 200*4 */
 644                 break;
 645         case CLKCFG_FSB_667:
 646                 dev_priv->fsb_freq =  667; /* 167*4 */
 647                 break;
 648         case CLKCFG_FSB_400:
 649                 dev_priv->fsb_freq = 400; /* 100*4 */
 650                 break;
 651         }
 652
 653         switch (tmp & CLKCFG_MEM_MASK) {
 654         case CLKCFG_MEM_533:
 655                 dev_priv->mem_freq = 533;
 656                 break;
 657         case CLKCFG_MEM_667:
 658                 dev_priv->mem_freq = 667;
 659                 break;
 660         case CLKCFG_MEM_800:
 661                 dev_priv->mem_freq = 800;
 662                 break;
 663         }
 664
 665         /* detect pineview DDR3 setting */
 666         tmp = I915_READ(CSHRDDR3CTL);
 667         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 668 }
 669
 670 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 671 {
 672         drm_i915_private_t *dev_priv = dev->dev_private;
 673         u16 ddrpll, csipll;
 674
 675         ddrpll = I915_READ16(DDRMPLL1);
 676         csipll = I915_READ16(CSIPLL0);
 677
 678         switch (ddrpll & 0xff) {
 679         case 0xc:
 680                 dev_priv->mem_freq = 800;
 681                 break;
 682         case 0x10:
 683                 dev_priv->mem_freq = 1066;
 684                 break;
 685         case 0x14:
 686                 dev_priv->mem_freq = 1333;
 687                 break;
 688         case 0x18:
 689                 dev_priv->mem_freq = 1600;
 690                 break;
 691         default:
 692                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 693                                  ddrpll & 0xff);
 694                 dev_priv->mem_freq = 0;
 695                 break;
 696         }
 697
 698         dev_priv->ips.r_t = dev_priv->mem_freq;
 699
 700         switch (csipll & 0x3ff) {
 701         case 0x00c:
 702                 dev_priv->fsb_freq = 3200;
 703                 break;
 704         case 0x00e:
 705                 dev_priv->fsb_freq = 3733;
 706                 break;
 707         case 0x010:
 708                 dev_priv->fsb_freq = 4266;
 709                 break;
 710         case 0x012:
 711                 dev_priv->fsb_freq = 4800;
 712                 break;
 713         case 0x014:
 714                 dev_priv->fsb_freq = 5333;
 715                 break;
 716         case 0x016:
 717                 dev_priv->fsb_freq = 5866;
 718                 break;
 719         case 0x018:
 720                 dev_priv->fsb_freq = 6400;
 721                 break;
 722         default:
 723                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 724                                  csipll & 0x3ff);
 725                 dev_priv->fsb_freq = 0;
 726                 break;
 727         }
 728
 729         if (dev_priv->fsb_freq == 3200) {
 730                 dev_priv->ips.c_m = 0;
 731         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 732                 dev_priv->ips.c_m = 1;
 733         } else {
 734                 dev_priv->ips.c_m = 2;
 735         }
 736 }
 737
 738 static const struct cxsr_latency cxsr_latency_table[] = {
 739         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 740         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 741         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 742         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 743         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 744
 745         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 746         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 747         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 748         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 749         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 750
 751         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 752         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 753         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 754         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 755         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 756
 757         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 758         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 759         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 760         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 761         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 762
 763         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 764         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 765         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 766         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 767         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 768
 769         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 770         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 771         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 772         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 773         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 774 };
 775
 776 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 777                                                          int is_ddr3,
 778                                                          int fsb,
 779                                                          int mem)
 780 {
 781         const struct cxsr_latency *latency;
 782         int i;
 783
 784         if (fsb == 0 || mem == 0)
 785                 return NULL;
 786
 787         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 788                 latency = &cxsr_latency_table[i];
 789                 if (is_desktop == latency->is_desktop &&
 790                     is_ddr3 == latency->is_ddr3 &&
 791                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 792                         return latency;
 793         }
 794
 795         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 796
 797         return NULL;
 798 }
 799
 800 static void pineview_disable_cxsr(struct drm_device *dev)
 801 {
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803
 804         /* deactivate cxsr */
 805         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 806 }
 807
 808 /*
 809  * Latency for FIFO fetches is dependent on several factors:
 810  *   - memory configuration (speed, channels)
 811  *   - chipset
 812  *   - current MCH state
 813  * It can be fairly high in some situations, so here we assume a fairly
 814  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 815  * set this value too high, the FIFO will fetch frequently to stay full)
 816  * and power consumption (set it too low to save power and we might see
 817  * FIFO underruns and display "flicker").
 818  *
 819  * A value of 5us seems to be a good balance; safe for very low end
 820  * platforms but not overly aggressive on lower latency configs.
 821  */
 822 static const int latency_ns = 5000;
 823
 824 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 825 {
 826         struct drm_i915_private *dev_priv = dev->dev_private;
 827         uint32_t dsparb = I915_READ(DSPARB);
 828         int size;
 829
 830         size = dsparb & 0x7f;
 831         if (plane)
 832                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 833
 834         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 835                       plane ? "B" : "A", size);
 836
 837         return size;
 838 }
 839
 840 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 841 {
 842         struct drm_i915_private *dev_priv = dev->dev_private;
 843         uint32_t dsparb = I915_READ(DSPARB);
 844         int size;
 845
 846         size = dsparb & 0x1ff;
 847         if (plane)
 848                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 849         size >>= 1; /* Convert to cachelines */
 850
 851         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 852                       plane ? "B" : "A", size);
 853
 854         return size;
 855 }
 856
 857 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 858 {
 859         struct drm_i915_private *dev_priv = dev->dev_private;
 860         uint32_t dsparb = I915_READ(DSPARB);
 861         int size;
 862
 863         size = dsparb & 0x7f;
 864         size >>= 2; /* Convert to cachelines */
 865
 866         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 867                       plane ? "B" : "A",
 868                       size);
 869
 870         return size;
 871 }
 872
 873 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 874 {
 875         struct drm_i915_private *dev_priv = dev->dev_private;
 876         uint32_t dsparb = I915_READ(DSPARB);
 877         int size;
 878
 879         size = dsparb & 0x7f;
 880         size >>= 1; /* Convert to cachelines */
 881
 882         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 883                       plane ? "B" : "A", size);
 884
 885         return size;
 886 }
 887
 888 /* Pineview has different values for various configs */
 889 static const struct intel_watermark_params pineview_display_wm = {
 890         PINEVIEW_DISPLAY_FIFO,
 891         PINEVIEW_MAX_WM,
 892         PINEVIEW_DFT_WM,
 893         PINEVIEW_GUARD_WM,
 894         PINEVIEW_FIFO_LINE_SIZE
 895 };
 896 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 897         PINEVIEW_DISPLAY_FIFO,
 898         PINEVIEW_MAX_WM,
 899         PINEVIEW_DFT_HPLLOFF_WM,
 900         PINEVIEW_GUARD_WM,
 901         PINEVIEW_FIFO_LINE_SIZE
 902 };
 903 static const struct intel_watermark_params pineview_cursor_wm = {
 904         PINEVIEW_CURSOR_FIFO,
 905         PINEVIEW_CURSOR_MAX_WM,
 906         PINEVIEW_CURSOR_DFT_WM,
 907         PINEVIEW_CURSOR_GUARD_WM,
 908         PINEVIEW_FIFO_LINE_SIZE,
 909 };
 910 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 911         PINEVIEW_CURSOR_FIFO,
 912         PINEVIEW_CURSOR_MAX_WM,
 913         PINEVIEW_CURSOR_DFT_WM,
 914         PINEVIEW_CURSOR_GUARD_WM,
 915         PINEVIEW_FIFO_LINE_SIZE
 916 };
 917 static const struct intel_watermark_params g4x_wm_info = {
 918         G4X_FIFO_SIZE,
 919         G4X_MAX_WM,
 920         G4X_MAX_WM,
 921         2,
 922         G4X_FIFO_LINE_SIZE,
 923 };
 924 static const struct intel_watermark_params g4x_cursor_wm_info = {
 925         I965_CURSOR_FIFO,
 926         I965_CURSOR_MAX_WM,
 927         I965_CURSOR_DFT_WM,
 928         2,
 929         G4X_FIFO_LINE_SIZE,
 930 };
 931 static const struct intel_watermark_params valleyview_wm_info = {
 932         VALLEYVIEW_FIFO_SIZE,
 933         VALLEYVIEW_MAX_WM,
 934         VALLEYVIEW_MAX_WM,
 935         2,
 936         G4X_FIFO_LINE_SIZE,
 937 };
 938 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 939         I965_CURSOR_FIFO,
 940         VALLEYVIEW_CURSOR_MAX_WM,
 941         I965_CURSOR_DFT_WM,
 942         2,
 943         G4X_FIFO_LINE_SIZE,
 944 };
 945 static const struct intel_watermark_params i965_cursor_wm_info = {
 946         I965_CURSOR_FIFO,
 947         I965_CURSOR_MAX_WM,
 948         I965_CURSOR_DFT_WM,
 949         2,
 950         I915_FIFO_LINE_SIZE,
 951 };
 952 static const struct intel_watermark_params i945_wm_info = {
 953         I945_FIFO_SIZE,
 954         I915_MAX_WM,
 955         1,
 956         2,
 957         I915_FIFO_LINE_SIZE
 958 };
 959 static const struct intel_watermark_params i915_wm_info = {
 960         I915_FIFO_SIZE,
 961         I915_MAX_WM,
 962         1,
 963         2,
 964         I915_FIFO_LINE_SIZE
 965 };
 966 static const struct intel_watermark_params i855_wm_info = {
 967         I855GM_FIFO_SIZE,
 968         I915_MAX_WM,
 969         1,
 970         2,
 971         I830_FIFO_LINE_SIZE
 972 };
 973 static const struct intel_watermark_params i830_wm_info = {
 974         I830_FIFO_SIZE,
 975         I915_MAX_WM,
 976         1,
 977         2,
 978         I830_FIFO_LINE_SIZE
 979 };
 980
 981 static const struct intel_watermark_params ironlake_display_wm_info = {
 982         ILK_DISPLAY_FIFO,
 983         ILK_DISPLAY_MAXWM,
 984         ILK_DISPLAY_DFTWM,
 985         2,
 986         ILK_FIFO_LINE_SIZE
 987 };
 988 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 989         ILK_CURSOR_FIFO,
 990         ILK_CURSOR_MAXWM,
 991         ILK_CURSOR_DFTWM,
 992         2,
 993         ILK_FIFO_LINE_SIZE
 994 };
 995 static const struct intel_watermark_params ironlake_display_srwm_info = {
 996         ILK_DISPLAY_SR_FIFO,
 997         ILK_DISPLAY_MAX_SRWM,
 998         ILK_DISPLAY_DFT_SRWM,
 999         2,
1000         ILK_FIFO_LINE_SIZE
1001 };
1002 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
1003         ILK_CURSOR_SR_FIFO,
1004         ILK_CURSOR_MAX_SRWM,
1005         ILK_CURSOR_DFT_SRWM,
1006         2,
1007         ILK_FIFO_LINE_SIZE
1008 };
1009
1010 static const struct intel_watermark_params sandybridge_display_wm_info = {
1011         SNB_DISPLAY_FIFO,
1012         SNB_DISPLAY_MAXWM,
1013         SNB_DISPLAY_DFTWM,
1014         2,
1015         SNB_FIFO_LINE_SIZE
1016 };
1017 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1018         SNB_CURSOR_FIFO,
1019         SNB_CURSOR_MAXWM,
1020         SNB_CURSOR_DFTWM,
1021         2,
1022         SNB_FIFO_LINE_SIZE
1023 };
1024 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1025         SNB_DISPLAY_SR_FIFO,
1026         SNB_DISPLAY_MAX_SRWM,
1027         SNB_DISPLAY_DFT_SRWM,
1028         2,
1029         SNB_FIFO_LINE_SIZE
1030 };
1031 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1032         SNB_CURSOR_SR_FIFO,
1033         SNB_CURSOR_MAX_SRWM,
1034         SNB_CURSOR_DFT_SRWM,
1035         2,
1036         SNB_FIFO_LINE_SIZE
1037 };
1038
1039
1040 /**
1041  * intel_calculate_wm - calculate watermark level
1042  * @clock_in_khz: pixel clock
1043  * @wm: chip FIFO params
1044  * @pixel_size: display pixel size
1045  * @latency_ns: memory latency for the platform
1046  *
1047  * Calculate the watermark level (the level at which the display plane will
1048  * start fetching from memory again).  Each chip has a different display
1049  * FIFO size and allocation, so the caller needs to figure that out and pass
1050  * in the correct intel_watermark_params structure.
1051  *
1052  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1053  * on the pixel size.  When it reaches the watermark level, it'll start
1054  * fetching FIFO line sized based chunks from memory until the FIFO fills
1055  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1056  * will occur, and a display engine hang could result.
1057  */
1058 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1059                                         const struct intel_watermark_params *wm,
1060                                         int fifo_size,
1061                                         int pixel_size,
1062                                         unsigned long latency_ns)
1063 {
1064         long entries_required, wm_size;
1065
1066         /*
1067          * Note: we need to make sure we don't overflow for various clock &
1068          * latency values.
1069          * clocks go from a few thousand to several hundred thousand.
1070          * latency is usually a few thousand
1071          */
1072         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1073                 1000;
1074         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1075
1076         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1077
1078         wm_size = fifo_size - (entries_required + wm->guard_size);
1079
1080         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1081
1082         /* Don't promote wm_size to unsigned... */
1083         if (wm_size > (long)wm->max_wm)
1084                 wm_size = wm->max_wm;
1085         if (wm_size <= 0)
1086                 wm_size = wm->default_wm;
1087         return wm_size;
1088 }
1089
1090 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1091 {
1092         struct drm_crtc *crtc, *enabled = NULL;
1093
1094         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1095                 if (intel_crtc_active(crtc)) {
1096                         if (enabled)
1097                                 return NULL;
1098                         enabled = crtc;
1099                 }
1100         }
1101
1102         return enabled;
1103 }
1104
1105 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1106 {
1107         struct drm_device *dev = unused_crtc->dev;
1108         struct drm_i915_private *dev_priv = dev->dev_private;
1109         struct drm_crtc *crtc;
1110         const struct cxsr_latency *latency;
1111         u32 reg;
1112         unsigned long wm;
1113
1114         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1115                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1116         if (!latency) {
1117                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1118                 pineview_disable_cxsr(dev);
1119                 return;
1120         }
1121
1122         crtc = single_enabled_crtc(dev);
1123         if (crtc) {
1124                 const struct drm_display_mode *adjusted_mode;
1125                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1126                 int clock;
1127
1128                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1129                 clock = adjusted_mode->crtc_clock;
1130
1131                 /* Display SR */
1132                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1133                                         pineview_display_wm.fifo_size,
1134                                         pixel_size, latency->display_sr);
1135                 reg = I915_READ(DSPFW1);
1136                 reg &= ~DSPFW_SR_MASK;
1137                 reg |= wm << DSPFW_SR_SHIFT;
1138                 I915_WRITE(DSPFW1, reg);
1139                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1140
1141                 /* cursor SR */
1142                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1143                                         pineview_display_wm.fifo_size,
1144                                         pixel_size, latency->cursor_sr);
1145                 reg = I915_READ(DSPFW3);
1146                 reg &= ~DSPFW_CURSOR_SR_MASK;
1147                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1148                 I915_WRITE(DSPFW3, reg);
1149
1150                 /* Display HPLL off SR */
1151                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1152                                         pineview_display_hplloff_wm.fifo_size,
1153                                         pixel_size, latency->display_hpll_disable);
1154                 reg = I915_READ(DSPFW3);
1155                 reg &= ~DSPFW_HPLL_SR_MASK;
1156                 reg |= wm & DSPFW_HPLL_SR_MASK;
1157                 I915_WRITE(DSPFW3, reg);
1158
1159                 /* cursor HPLL off SR */
1160                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1161                                         pineview_display_hplloff_wm.fifo_size,
1162                                         pixel_size, latency->cursor_hpll_disable);
1163                 reg = I915_READ(DSPFW3);
1164                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1165                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1166                 I915_WRITE(DSPFW3, reg);
1167                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1168
1169                 /* activate cxsr */
1170                 I915_WRITE(DSPFW3,
1171                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1172                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1173         } else {
1174                 pineview_disable_cxsr(dev);
1175                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1176         }
1177 }
1178
1179 static bool g4x_compute_wm0(struct drm_device *dev,
1180                             int plane,
1181                             const struct intel_watermark_params *display,
1182                             int display_latency_ns,
1183                             const struct intel_watermark_params *cursor,
1184                             int cursor_latency_ns,
1185                             int *plane_wm,
1186                             int *cursor_wm)
1187 {
1188         struct drm_crtc *crtc;
1189         const struct drm_display_mode *adjusted_mode;
1190         int htotal, hdisplay, clock, pixel_size;
1191         int line_time_us, line_count;
1192         int entries, tlb_miss;
1193
1194         crtc = intel_get_crtc_for_plane(dev, plane);
1195         if (!intel_crtc_active(crtc)) {
1196                 *cursor_wm = cursor->guard_size;
1197                 *plane_wm = display->guard_size;
1198                 return false;
1199         }
1200
1201         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1202         clock = adjusted_mode->crtc_clock;
1203         htotal = adjusted_mode->htotal;
1204         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1205         pixel_size = crtc->fb->bits_per_pixel / 8;
1206
1207         /* Use the small buffer method to calculate plane watermark */
1208         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1209         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1210         if (tlb_miss > 0)
1211                 entries += tlb_miss;
1212         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1213         *plane_wm = entries + display->guard_size;
1214         if (*plane_wm > (int)display->max_wm)
1215                 *plane_wm = display->max_wm;
1216
1217         /* Use the large buffer method to calculate cursor watermark */
1218         line_time_us = ((htotal * 1000) / clock);
1219         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1220         entries = line_count * 64 * pixel_size;
1221         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1222         if (tlb_miss > 0)
1223                 entries += tlb_miss;
1224         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1225         *cursor_wm = entries + cursor->guard_size;
1226         if (*cursor_wm > (int)cursor->max_wm)
1227                 *cursor_wm = (int)cursor->max_wm;
1228
1229         return true;
1230 }
1231
1232 /*
1233  * Check the wm result.
1234  *
1235  * If any calculated watermark values is larger than the maximum value that
1236  * can be programmed into the associated watermark register, that watermark
1237  * must be disabled.
1238  */
1239 static bool g4x_check_srwm(struct drm_device *dev,
1240                            int display_wm, int cursor_wm,
1241                            const struct intel_watermark_params *display,
1242                            const struct intel_watermark_params *cursor)
1243 {
1244         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1245                       display_wm, cursor_wm);
1246
1247         if (display_wm > display->max_wm) {
1248                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1249                               display_wm, display->max_wm);
1250                 return false;
1251         }
1252
1253         if (cursor_wm > cursor->max_wm) {
1254                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1255                               cursor_wm, cursor->max_wm);
1256                 return false;
1257         }
1258
1259         if (!(display_wm || cursor_wm)) {
1260                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1261                 return false;
1262         }
1263
1264         return true;
1265 }
1266
1267 static bool g4x_compute_srwm(struct drm_device *dev,
1268                              int plane,
1269                              int latency_ns,
1270                              const struct intel_watermark_params *display,
1271                              const struct intel_watermark_params *cursor,
1272                              int *display_wm, int *cursor_wm)
1273 {
1274         struct drm_crtc *crtc;
1275         const struct drm_display_mode *adjusted_mode;
1276         int hdisplay, htotal, pixel_size, clock;
1277         unsigned long line_time_us;
1278         int line_count, line_size;
1279         int small, large;
1280         int entries;
1281
1282         if (!latency_ns) {
1283                 *display_wm = *cursor_wm = 0;
1284                 return false;
1285         }
1286
1287         crtc = intel_get_crtc_for_plane(dev, plane);
1288         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1289         clock = adjusted_mode->crtc_clock;
1290         htotal = adjusted_mode->htotal;
1291         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1292         pixel_size = crtc->fb->bits_per_pixel / 8;
1293
1294         line_time_us = (htotal * 1000) / clock;
1295         line_count = (latency_ns / line_time_us + 1000) / 1000;
1296         line_size = hdisplay * pixel_size;
1297
1298         /* Use the minimum of the small and large buffer method for primary */
1299         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1300         large = line_count * line_size;
1301
1302         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1303         *display_wm = entries + display->guard_size;
1304
1305         /* calculate the self-refresh watermark for display cursor */
1306         entries = line_count * pixel_size * 64;
1307         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1308         *cursor_wm = entries + cursor->guard_size;
1309
1310         return g4x_check_srwm(dev,
1311                               *display_wm, *cursor_wm,
1312                               display, cursor);
1313 }
1314
1315 static bool vlv_compute_drain_latency(struct drm_device *dev,
1316                                      int plane,
1317                                      int *plane_prec_mult,
1318                                      int *plane_dl,
1319                                      int *cursor_prec_mult,
1320                                      int *cursor_dl)
1321 {
1322         struct drm_crtc *crtc;
1323         int clock, pixel_size;
1324         int entries;
1325
1326         crtc = intel_get_crtc_for_plane(dev, plane);
1327         if (!intel_crtc_active(crtc))
1328                 return false;
1329
1330         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1331         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1332
1333         entries = (clock / 1000) * pixel_size;
1334         *plane_prec_mult = (entries > 256) ?
1335                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1336         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1337                                                      pixel_size);
1338
1339         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1340         *cursor_prec_mult = (entries > 256) ?
1341                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1342         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1343
1344         return true;
1345 }
1346
1347 /*
1348  * Update drain latency registers of memory arbiter
1349  *
1350  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1351  * to be programmed. Each plane has a drain latency multiplier and a drain
1352  * latency value.
1353  */
1354
1355 static void vlv_update_drain_latency(struct drm_device *dev)
1356 {
1357         struct drm_i915_private *dev_priv = dev->dev_private;
1358         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1359         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1360         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1361                                                         either 16 or 32 */
1362
1363         /* For plane A, Cursor A */
1364         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1365                                       &cursor_prec_mult, &cursora_dl)) {
1366                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1367                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1368                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1369                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1370
1371                 I915_WRITE(VLV_DDL1, cursora_prec |
1372                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1373                                 planea_prec | planea_dl);
1374         }
1375
1376         /* For plane B, Cursor B */
1377         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1378                                       &cursor_prec_mult, &cursorb_dl)) {
1379                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1380                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1381                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1382                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1383
1384                 I915_WRITE(VLV_DDL2, cursorb_prec |
1385                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1386                                 planeb_prec | planeb_dl);
1387         }
1388 }
1389
1390 #define single_plane_enabled(mask) is_power_of_2(mask)
1391
1392 static void valleyview_update_wm(struct drm_crtc *crtc)
1393 {
1394         struct drm_device *dev = crtc->dev;
1395         static const int sr_latency_ns = 12000;
1396         struct drm_i915_private *dev_priv = dev->dev_private;
1397         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1398         int plane_sr, cursor_sr;
1399         int ignore_plane_sr, ignore_cursor_sr;
1400         unsigned int enabled = 0;
1401
1402         vlv_update_drain_latency(dev);
1403
1404         if (g4x_compute_wm0(dev, PIPE_A,
1405                             &valleyview_wm_info, latency_ns,
1406                             &valleyview_cursor_wm_info, latency_ns,
1407                             &planea_wm, &cursora_wm))
1408                 enabled |= 1 << PIPE_A;
1409
1410         if (g4x_compute_wm0(dev, PIPE_B,
1411                             &valleyview_wm_info, latency_ns,
1412                             &valleyview_cursor_wm_info, latency_ns,
1413                             &planeb_wm, &cursorb_wm))
1414                 enabled |= 1 << PIPE_B;
1415
1416         if (single_plane_enabled(enabled) &&
1417             g4x_compute_srwm(dev, ffs(enabled) - 1,
1418                              sr_latency_ns,
1419                              &valleyview_wm_info,
1420                              &valleyview_cursor_wm_info,
1421                              &plane_sr, &ignore_cursor_sr) &&
1422             g4x_compute_srwm(dev, ffs(enabled) - 1,
1423                              2*sr_latency_ns,
1424                              &valleyview_wm_info,
1425                              &valleyview_cursor_wm_info,
1426                              &ignore_plane_sr, &cursor_sr)) {
1427                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1428         } else {
1429                 I915_WRITE(FW_BLC_SELF_VLV,
1430                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1431                 plane_sr = cursor_sr = 0;
1432         }
1433
1434         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1435                       planea_wm, cursora_wm,
1436                       planeb_wm, cursorb_wm,
1437                       plane_sr, cursor_sr);
1438
1439         I915_WRITE(DSPFW1,
1440                    (plane_sr << DSPFW_SR_SHIFT) |
1441                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1442                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1443                    planea_wm);
1444         I915_WRITE(DSPFW2,
1445                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1446                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1447         I915_WRITE(DSPFW3,
1448                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1449                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1450 }
1451
1452 static void g4x_update_wm(struct drm_crtc *crtc)
1453 {
1454         struct drm_device *dev = crtc->dev;
1455         static const int sr_latency_ns = 12000;
1456         struct drm_i915_private *dev_priv = dev->dev_private;
1457         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1458         int plane_sr, cursor_sr;
1459         unsigned int enabled = 0;
1460
1461         if (g4x_compute_wm0(dev, PIPE_A,
1462                             &g4x_wm_info, latency_ns,
1463                             &g4x_cursor_wm_info, latency_ns,
1464                             &planea_wm, &cursora_wm))
1465                 enabled |= 1 << PIPE_A;
1466
1467         if (g4x_compute_wm0(dev, PIPE_B,
1468                             &g4x_wm_info, latency_ns,
1469                             &g4x_cursor_wm_info, latency_ns,
1470                             &planeb_wm, &cursorb_wm))
1471                 enabled |= 1 << PIPE_B;
1472
1473         if (single_plane_enabled(enabled) &&
1474             g4x_compute_srwm(dev, ffs(enabled) - 1,
1475                              sr_latency_ns,
1476                              &g4x_wm_info,
1477                              &g4x_cursor_wm_info,
1478                              &plane_sr, &cursor_sr)) {
1479                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1480         } else {
1481                 I915_WRITE(FW_BLC_SELF,
1482                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1483                 plane_sr = cursor_sr = 0;
1484         }
1485
1486         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1487                       planea_wm, cursora_wm,
1488                       planeb_wm, cursorb_wm,
1489                       plane_sr, cursor_sr);
1490
1491         I915_WRITE(DSPFW1,
1492                    (plane_sr << DSPFW_SR_SHIFT) |
1493                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1494                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1495                    planea_wm);
1496         I915_WRITE(DSPFW2,
1497                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1498                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1499         /* HPLL off in SR has some issues on G4x... disable it */
1500         I915_WRITE(DSPFW3,
1501                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1502                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1503 }
1504
1505 static void i965_update_wm(struct drm_crtc *unused_crtc)
1506 {
1507         struct drm_device *dev = unused_crtc->dev;
1508         struct drm_i915_private *dev_priv = dev->dev_private;
1509         struct drm_crtc *crtc;
1510         int srwm = 1;
1511         int cursor_sr = 16;
1512
1513         /* Calc sr entries for one plane configs */
1514         crtc = single_enabled_crtc(dev);
1515         if (crtc) {
1516                 /* self-refresh has much higher latency */
1517                 static const int sr_latency_ns = 12000;
1518                 const struct drm_display_mode *adjusted_mode =
1519                         &to_intel_crtc(crtc)->config.adjusted_mode;
1520                 int clock = adjusted_mode->crtc_clock;
1521                 int htotal = adjusted_mode->htotal;
1522                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1523                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1524                 unsigned long line_time_us;
1525                 int entries;
1526
1527                 line_time_us = ((htotal * 1000) / clock);
1528
1529                 /* Use ns/us then divide to preserve precision */
1530                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1531                         pixel_size * hdisplay;
1532                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1533                 srwm = I965_FIFO_SIZE - entries;
1534                 if (srwm < 0)
1535                         srwm = 1;
1536                 srwm &= 0x1ff;
1537                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1538                               entries, srwm);
1539
1540                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1541                         pixel_size * 64;
1542                 entries = DIV_ROUND_UP(entries,
1543                                           i965_cursor_wm_info.cacheline_size);
1544                 cursor_sr = i965_cursor_wm_info.fifo_size -
1545                         (entries + i965_cursor_wm_info.guard_size);
1546
1547                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1548                         cursor_sr = i965_cursor_wm_info.max_wm;
1549
1550                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1551                               "cursor %d\n", srwm, cursor_sr);
1552
1553                 if (IS_CRESTLINE(dev))
1554                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1555         } else {
1556                 /* Turn off self refresh if both pipes are enabled */
1557                 if (IS_CRESTLINE(dev))
1558                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1559                                    & ~FW_BLC_SELF_EN);
1560         }
1561
1562         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1563                       srwm);
1564
1565         /* 965 has limitations... */
1566         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1567                    (8 << 16) | (8 << 8) | (8 << 0));
1568         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1569         /* update cursor SR watermark */
1570         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1571 }
1572
1573 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1574 {
1575         struct drm_device *dev = unused_crtc->dev;
1576         struct drm_i915_private *dev_priv = dev->dev_private;
1577         const struct intel_watermark_params *wm_info;
1578         uint32_t fwater_lo;
1579         uint32_t fwater_hi;
1580         int cwm, srwm = 1;
1581         int fifo_size;
1582         int planea_wm, planeb_wm;
1583         struct drm_crtc *crtc, *enabled = NULL;
1584
1585         if (IS_I945GM(dev))
1586                 wm_info = &i945_wm_info;
1587         else if (!IS_GEN2(dev))
1588                 wm_info = &i915_wm_info;
1589         else
1590                 wm_info = &i855_wm_info;
1591
1592         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1593         crtc = intel_get_crtc_for_plane(dev, 0);
1594         if (intel_crtc_active(crtc)) {
1595                 const struct drm_display_mode *adjusted_mode;
1596                 int cpp = crtc->fb->bits_per_pixel / 8;
1597                 if (IS_GEN2(dev))
1598                         cpp = 4;
1599
1600                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1601                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1602                                                wm_info, fifo_size, cpp,
1603                                                latency_ns);
1604                 enabled = crtc;
1605         } else
1606                 planea_wm = fifo_size - wm_info->guard_size;
1607
1608         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1609         crtc = intel_get_crtc_for_plane(dev, 1);
1610         if (intel_crtc_active(crtc)) {
1611                 const struct drm_display_mode *adjusted_mode;
1612                 int cpp = crtc->fb->bits_per_pixel / 8;
1613                 if (IS_GEN2(dev))
1614                         cpp = 4;
1615
1616                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1617                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1618                                                wm_info, fifo_size, cpp,
1619                                                latency_ns);
1620                 if (enabled == NULL)
1621                         enabled = crtc;
1622                 else
1623                         enabled = NULL;
1624         } else
1625                 planeb_wm = fifo_size - wm_info->guard_size;
1626
1627         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1628
1629         /*
1630          * Overlay gets an aggressive default since video jitter is bad.
1631          */
1632         cwm = 2;
1633
1634         /* Play safe and disable self-refresh before adjusting watermarks. */
1635         if (IS_I945G(dev) || IS_I945GM(dev))
1636                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1637         else if (IS_I915GM(dev))
1638                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1639
1640         /* Calc sr entries for one plane configs */
1641         if (HAS_FW_BLC(dev) && enabled) {
1642                 /* self-refresh has much higher latency */
1643                 static const int sr_latency_ns = 6000;
1644                 const struct drm_display_mode *adjusted_mode =
1645                         &to_intel_crtc(enabled)->config.adjusted_mode;
1646                 int clock = adjusted_mode->crtc_clock;
1647                 int htotal = adjusted_mode->htotal;
1648                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1649                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1650                 unsigned long line_time_us;
1651                 int entries;
1652
1653                 line_time_us = (htotal * 1000) / clock;
1654
1655                 /* Use ns/us then divide to preserve precision */
1656                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1657                         pixel_size * hdisplay;
1658                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1659                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1660                 srwm = wm_info->fifo_size - entries;
1661                 if (srwm < 0)
1662                         srwm = 1;
1663
1664                 if (IS_I945G(dev) || IS_I945GM(dev))
1665                         I915_WRITE(FW_BLC_SELF,
1666                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1667                 else if (IS_I915GM(dev))
1668                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1669         }
1670
1671         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1672                       planea_wm, planeb_wm, cwm, srwm);
1673
1674         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1675         fwater_hi = (cwm & 0x1f);
1676
1677         /* Set request length to 8 cachelines per fetch */
1678         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1679         fwater_hi = fwater_hi | (1 << 8);
1680
1681         I915_WRITE(FW_BLC, fwater_lo);
1682         I915_WRITE(FW_BLC2, fwater_hi);
1683
1684         if (HAS_FW_BLC(dev)) {
1685                 if (enabled) {
1686                         if (IS_I945G(dev) || IS_I945GM(dev))
1687                                 I915_WRITE(FW_BLC_SELF,
1688                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1689                         else if (IS_I915GM(dev))
1690                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1691                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1692                 } else
1693                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1694         }
1695 }
1696
1697 static void i830_update_wm(struct drm_crtc *unused_crtc)
1698 {
1699         struct drm_device *dev = unused_crtc->dev;
1700         struct drm_i915_private *dev_priv = dev->dev_private;
1701         struct drm_crtc *crtc;
1702         const struct drm_display_mode *adjusted_mode;
1703         uint32_t fwater_lo;
1704         int planea_wm;
1705
1706         crtc = single_enabled_crtc(dev);
1707         if (crtc == NULL)
1708                 return;
1709
1710         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1711         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1712                                        &i830_wm_info,
1713                                        dev_priv->display.get_fifo_size(dev, 0),
1714                                        4, latency_ns);
1715         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1716         fwater_lo |= (3<<8) | planea_wm;
1717
1718         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1719
1720         I915_WRITE(FW_BLC, fwater_lo);
1721 }
1722
1723 /*
1724  * Check the wm result.
1725  *
1726  * If any calculated watermark values is larger than the maximum value that
1727  * can be programmed into the associated watermark register, that watermark
1728  * must be disabled.
1729  */
1730 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1731                                 int fbc_wm, int display_wm, int cursor_wm,
1732                                 const struct intel_watermark_params *display,
1733                                 const struct intel_watermark_params *cursor)
1734 {
1735         struct drm_i915_private *dev_priv = dev->dev_private;
1736
1737         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1738                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1739
1740         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1741                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1742                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1743
1744                 /* fbc has it's own way to disable FBC WM */
1745                 I915_WRITE(DISP_ARB_CTL,
1746                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1747                 return false;
1748         } else if (INTEL_INFO(dev)->gen >= 6) {
1749                 /* enable FBC WM (except on ILK, where it must remain off) */
1750                 I915_WRITE(DISP_ARB_CTL,
1751                            I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1752         }
1753
1754         if (display_wm > display->max_wm) {
1755                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1756                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1757                 return false;
1758         }
1759
1760         if (cursor_wm > cursor->max_wm) {
1761                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1762                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1763                 return false;
1764         }
1765
1766         if (!(fbc_wm || display_wm || cursor_wm)) {
1767                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1768                 return false;
1769         }
1770
1771         return true;
1772 }
1773
1774 /*
1775  * Compute watermark values of WM[1-3],
1776  */
1777 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1778                                   int latency_ns,
1779                                   const struct intel_watermark_params *display,
1780                                   const struct intel_watermark_params *cursor,
1781                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1782 {
1783         struct drm_crtc *crtc;
1784         const struct drm_display_mode *adjusted_mode;
1785         unsigned long line_time_us;
1786         int hdisplay, htotal, pixel_size, clock;
1787         int line_count, line_size;
1788         int small, large;
1789         int entries;
1790
1791         if (!latency_ns) {
1792                 *fbc_wm = *display_wm = *cursor_wm = 0;
1793                 return false;
1794         }
1795
1796         crtc = intel_get_crtc_for_plane(dev, plane);
1797         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1798         clock = adjusted_mode->crtc_clock;
1799         htotal = adjusted_mode->htotal;
1800         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1801         pixel_size = crtc->fb->bits_per_pixel / 8;
1802
1803         line_time_us = (htotal * 1000) / clock;
1804         line_count = (latency_ns / line_time_us + 1000) / 1000;
1805         line_size = hdisplay * pixel_size;
1806
1807         /* Use the minimum of the small and large buffer method for primary */
1808         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1809         large = line_count * line_size;
1810
1811         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1812         *display_wm = entries + display->guard_size;
1813
1814         /*
1815          * Spec says:
1816          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1817          */
1818         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1819
1820         /* calculate the self-refresh watermark for display cursor */
1821         entries = line_count * pixel_size * 64;
1822         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1823         *cursor_wm = entries + cursor->guard_size;
1824
1825         return ironlake_check_srwm(dev, level,
1826                                    *fbc_wm, *display_wm, *cursor_wm,
1827                                    display, cursor);
1828 }
1829
1830 static void ironlake_update_wm(struct drm_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         int fbc_wm, plane_wm, cursor_wm;
1835         unsigned int enabled;
1836
1837         enabled = 0;
1838         if (g4x_compute_wm0(dev, PIPE_A,
1839                             &ironlake_display_wm_info,
1840                             dev_priv->wm.pri_latency[0] * 100,
1841                             &ironlake_cursor_wm_info,
1842                             dev_priv->wm.cur_latency[0] * 100,
1843                             &plane_wm, &cursor_wm)) {
1844                 I915_WRITE(WM0_PIPEA_ILK,
1845                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1846                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1847                               " plane %d, " "cursor: %d\n",
1848                               plane_wm, cursor_wm);
1849                 enabled |= 1 << PIPE_A;
1850         }
1851
1852         if (g4x_compute_wm0(dev, PIPE_B,
1853                             &ironlake_display_wm_info,
1854                             dev_priv->wm.pri_latency[0] * 100,
1855                             &ironlake_cursor_wm_info,
1856                             dev_priv->wm.cur_latency[0] * 100,
1857                             &plane_wm, &cursor_wm)) {
1858                 I915_WRITE(WM0_PIPEB_ILK,
1859                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1860                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1861                               " plane %d, cursor: %d\n",
1862                               plane_wm, cursor_wm);
1863                 enabled |= 1 << PIPE_B;
1864         }
1865
1866         /*
1867          * Calculate and update the self-refresh watermark only when one
1868          * display plane is used.
1869          */
1870         I915_WRITE(WM3_LP_ILK, 0);
1871         I915_WRITE(WM2_LP_ILK, 0);
1872         I915_WRITE(WM1_LP_ILK, 0);
1873
1874         if (!single_plane_enabled(enabled))
1875                 return;
1876         enabled = ffs(enabled) - 1;
1877
1878         /* WM1 */
1879         if (!ironlake_compute_srwm(dev, 1, enabled,
1880                                    dev_priv->wm.pri_latency[1] * 500,
1881                                    &ironlake_display_srwm_info,
1882                                    &ironlake_cursor_srwm_info,
1883                                    &fbc_wm, &plane_wm, &cursor_wm))
1884                 return;
1885
1886         I915_WRITE(WM1_LP_ILK,
1887                    WM1_LP_SR_EN |
1888                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1889                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1890                    (plane_wm << WM1_LP_SR_SHIFT) |
1891                    cursor_wm);
1892
1893         /* WM2 */
1894         if (!ironlake_compute_srwm(dev, 2, enabled,
1895                                    dev_priv->wm.pri_latency[2] * 500,
1896                                    &ironlake_display_srwm_info,
1897                                    &ironlake_cursor_srwm_info,
1898                                    &fbc_wm, &plane_wm, &cursor_wm))
1899                 return;
1900
1901         I915_WRITE(WM2_LP_ILK,
1902                    WM2_LP_EN |
1903                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1904                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1905                    (plane_wm << WM1_LP_SR_SHIFT) |
1906                    cursor_wm);
1907
1908         /*
1909          * WM3 is unsupported on ILK, probably because we don't have latency
1910          * data for that power state
1911          */
1912 }
1913
1914 static void sandybridge_update_wm(struct drm_crtc *crtc)
1915 {
1916         struct drm_device *dev = crtc->dev;
1917         struct drm_i915_private *dev_priv = dev->dev_private;
1918         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
1919         u32 val;
1920         int fbc_wm, plane_wm, cursor_wm;
1921         unsigned int enabled;
1922
1923         enabled = 0;
1924         if (g4x_compute_wm0(dev, PIPE_A,
1925                             &sandybridge_display_wm_info, latency,
1926                             &sandybridge_cursor_wm_info, latency,
1927                             &plane_wm, &cursor_wm)) {
1928                 val = I915_READ(WM0_PIPEA_ILK);
1929                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1930                 I915_WRITE(WM0_PIPEA_ILK, val |
1931                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1932                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1933                               " plane %d, " "cursor: %d\n",
1934                               plane_wm, cursor_wm);
1935                 enabled |= 1 << PIPE_A;
1936         }
1937
1938         if (g4x_compute_wm0(dev, PIPE_B,
1939                             &sandybridge_display_wm_info, latency,
1940                             &sandybridge_cursor_wm_info, latency,
1941                             &plane_wm, &cursor_wm)) {
1942                 val = I915_READ(WM0_PIPEB_ILK);
1943                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1944                 I915_WRITE(WM0_PIPEB_ILK, val |
1945                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1946                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1947                               " plane %d, cursor: %d\n",
1948                               plane_wm, cursor_wm);
1949                 enabled |= 1 << PIPE_B;
1950         }
1951
1952         /*
1953          * Calculate and update the self-refresh watermark only when one
1954          * display plane is used.
1955          *
1956          * SNB support 3 levels of watermark.
1957          *
1958          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1959          * and disabled in the descending order
1960          *
1961          */
1962         I915_WRITE(WM3_LP_ILK, 0);
1963         I915_WRITE(WM2_LP_ILK, 0);
1964         I915_WRITE(WM1_LP_ILK, 0);
1965
1966         if (!single_plane_enabled(enabled) ||
1967             dev_priv->sprite_scaling_enabled)
1968                 return;
1969         enabled = ffs(enabled) - 1;
1970
1971         /* WM1 */
1972         if (!ironlake_compute_srwm(dev, 1, enabled,
1973                                    dev_priv->wm.pri_latency[1] * 500,
1974                                    &sandybridge_display_srwm_info,
1975                                    &sandybridge_cursor_srwm_info,
1976                                    &fbc_wm, &plane_wm, &cursor_wm))
1977                 return;
1978
1979         I915_WRITE(WM1_LP_ILK,
1980                    WM1_LP_SR_EN |
1981                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1982                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1983                    (plane_wm << WM1_LP_SR_SHIFT) |
1984                    cursor_wm);
1985
1986         /* WM2 */
1987         if (!ironlake_compute_srwm(dev, 2, enabled,
1988                                    dev_priv->wm.pri_latency[2] * 500,
1989                                    &sandybridge_display_srwm_info,
1990                                    &sandybridge_cursor_srwm_info,
1991                                    &fbc_wm, &plane_wm, &cursor_wm))
1992                 return;
1993
1994         I915_WRITE(WM2_LP_ILK,
1995                    WM2_LP_EN |
1996                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1997                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1998                    (plane_wm << WM1_LP_SR_SHIFT) |
1999                    cursor_wm);
2000
2001         /* WM3 */
2002         if (!ironlake_compute_srwm(dev, 3, enabled,
2003                                    dev_priv->wm.pri_latency[3] * 500,
2004                                    &sandybridge_display_srwm_info,
2005                                    &sandybridge_cursor_srwm_info,
2006                                    &fbc_wm, &plane_wm, &cursor_wm))
2007                 return;
2008
2009         I915_WRITE(WM3_LP_ILK,
2010                    WM3_LP_EN |
2011                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2012                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2013                    (plane_wm << WM1_LP_SR_SHIFT) |
2014                    cursor_wm);
2015 }
2016
2017 static void ivybridge_update_wm(struct drm_crtc *crtc)
2018 {
2019         struct drm_device *dev = crtc->dev;
2020         struct drm_i915_private *dev_priv = dev->dev_private;
2021         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
2022         u32 val;
2023         int fbc_wm, plane_wm, cursor_wm;
2024         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2025         unsigned int enabled;
2026
2027         enabled = 0;
2028         if (g4x_compute_wm0(dev, PIPE_A,
2029                             &sandybridge_display_wm_info, latency,
2030                             &sandybridge_cursor_wm_info, latency,
2031                             &plane_wm, &cursor_wm)) {
2032                 val = I915_READ(WM0_PIPEA_ILK);
2033                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2034                 I915_WRITE(WM0_PIPEA_ILK, val |
2035                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2036                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2037                               " plane %d, " "cursor: %d\n",
2038                               plane_wm, cursor_wm);
2039                 enabled |= 1 << PIPE_A;
2040         }
2041
2042         if (g4x_compute_wm0(dev, PIPE_B,
2043                             &sandybridge_display_wm_info, latency,
2044                             &sandybridge_cursor_wm_info, latency,
2045                             &plane_wm, &cursor_wm)) {
2046                 val = I915_READ(WM0_PIPEB_ILK);
2047                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2048                 I915_WRITE(WM0_PIPEB_ILK, val |
2049                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2050                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2051                               " plane %d, cursor: %d\n",
2052                               plane_wm, cursor_wm);
2053                 enabled |= 1 << PIPE_B;
2054         }
2055
2056         if (g4x_compute_wm0(dev, PIPE_C,
2057                             &sandybridge_display_wm_info, latency,
2058                             &sandybridge_cursor_wm_info, latency,
2059                             &plane_wm, &cursor_wm)) {
2060                 val = I915_READ(WM0_PIPEC_IVB);
2061                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2062                 I915_WRITE(WM0_PIPEC_IVB, val |
2063                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2064                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2065                               " plane %d, cursor: %d\n",
2066                               plane_wm, cursor_wm);
2067                 enabled |= 1 << PIPE_C;
2068         }
2069
2070         /*
2071          * Calculate and update the self-refresh watermark only when one
2072          * display plane is used.
2073          *
2074          * SNB support 3 levels of watermark.
2075          *
2076          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2077          * and disabled in the descending order
2078          *
2079          */
2080         I915_WRITE(WM3_LP_ILK, 0);
2081         I915_WRITE(WM2_LP_ILK, 0);
2082         I915_WRITE(WM1_LP_ILK, 0);
2083
2084         if (!single_plane_enabled(enabled) ||
2085             dev_priv->sprite_scaling_enabled)
2086                 return;
2087         enabled = ffs(enabled) - 1;
2088
2089         /* WM1 */
2090         if (!ironlake_compute_srwm(dev, 1, enabled,
2091                                    dev_priv->wm.pri_latency[1] * 500,
2092                                    &sandybridge_display_srwm_info,
2093                                    &sandybridge_cursor_srwm_info,
2094                                    &fbc_wm, &plane_wm, &cursor_wm))
2095                 return;
2096
2097         I915_WRITE(WM1_LP_ILK,
2098                    WM1_LP_SR_EN |
2099                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2100                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2101                    (plane_wm << WM1_LP_SR_SHIFT) |
2102                    cursor_wm);
2103
2104         /* WM2 */
2105         if (!ironlake_compute_srwm(dev, 2, enabled,
2106                                    dev_priv->wm.pri_latency[2] * 500,
2107                                    &sandybridge_display_srwm_info,
2108                                    &sandybridge_cursor_srwm_info,
2109                                    &fbc_wm, &plane_wm, &cursor_wm))
2110                 return;
2111
2112         I915_WRITE(WM2_LP_ILK,
2113                    WM2_LP_EN |
2114                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2115                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2116                    (plane_wm << WM1_LP_SR_SHIFT) |
2117                    cursor_wm);
2118
2119         /* WM3, note we have to correct the cursor latency */
2120         if (!ironlake_compute_srwm(dev, 3, enabled,
2121                                    dev_priv->wm.pri_latency[3] * 500,
2122                                    &sandybridge_display_srwm_info,
2123                                    &sandybridge_cursor_srwm_info,
2124                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2125             !ironlake_compute_srwm(dev, 3, enabled,
2126                                    dev_priv->wm.cur_latency[3] * 500,
2127                                    &sandybridge_display_srwm_info,
2128                                    &sandybridge_cursor_srwm_info,
2129                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2130                 return;
2131
2132         I915_WRITE(WM3_LP_ILK,
2133                    WM3_LP_EN |
2134                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2135                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2136                    (plane_wm << WM1_LP_SR_SHIFT) |
2137                    cursor_wm);
2138 }
2139
2140 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2141                                     struct drm_crtc *crtc)
2142 {
2143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2144         uint32_t pixel_rate;
2145
2146         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2147
2148         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2149          * adjust the pixel_rate here. */
2150
2151         if (intel_crtc->config.pch_pfit.enabled) {
2152                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2153                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2154
2155                 pipe_w = intel_crtc->config.pipe_src_w;
2156                 pipe_h = intel_crtc->config.pipe_src_h;
2157                 pfit_w = (pfit_size >> 16) & 0xFFFF;
2158                 pfit_h = pfit_size & 0xFFFF;
2159                 if (pipe_w < pfit_w)
2160                         pipe_w = pfit_w;
2161                 if (pipe_h < pfit_h)
2162                         pipe_h = pfit_h;
2163
2164                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2165                                      pfit_w * pfit_h);
2166         }
2167
2168         return pixel_rate;
2169 }
2170
2171 /* latency must be in 0.1us units. */
2172 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2173                                uint32_t latency)
2174 {
2175         uint64_t ret;
2176
2177         if (WARN(latency == 0, "Latency value missing\n"))
2178                 return UINT_MAX;
2179
2180         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2181         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2182
2183         return ret;
2184 }
2185
2186 /* latency must be in 0.1us units. */
2187 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2188                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2189                                uint32_t latency)
2190 {
2191         uint32_t ret;
2192
2193         if (WARN(latency == 0, "Latency value missing\n"))
2194                 return UINT_MAX;
2195
2196         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2197         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2198         ret = DIV_ROUND_UP(ret, 64) + 2;
2199         return ret;
2200 }
2201
2202 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2203                            uint8_t bytes_per_pixel)
2204 {
2205         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2206 }
2207
2208 struct hsw_pipe_wm_parameters {
2209         bool active;
2210         uint32_t pipe_htotal;
2211         uint32_t pixel_rate;
2212         struct intel_plane_wm_parameters pri;
2213         struct intel_plane_wm_parameters spr;
2214         struct intel_plane_wm_parameters cur;
2215 };
2216
2217 struct hsw_wm_maximums {
2218         uint16_t pri;
2219         uint16_t spr;
2220         uint16_t cur;
2221         uint16_t fbc;
2222 };
2223
2224 /* used in computing the new watermarks state */
2225 struct intel_wm_config {
2226         unsigned int num_pipes_active;
2227         bool sprites_enabled;
2228         bool sprites_scaled;
2229 };
2230
2231 /*
2232  * For both WM_PIPE and WM_LP.
2233  * mem_value must be in 0.1us units.
2234  */
2235 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2236                                    uint32_t mem_value,
2237                                    bool is_lp)
2238 {
2239         uint32_t method1, method2;
2240
2241         if (!params->active || !params->pri.enabled)
2242                 return 0;
2243
2244         method1 = ilk_wm_method1(params->pixel_rate,
2245                                  params->pri.bytes_per_pixel,
2246                                  mem_value);
2247
2248         if (!is_lp)
2249                 return method1;
2250
2251         method2 = ilk_wm_method2(params->pixel_rate,
2252                                  params->pipe_htotal,
2253                                  params->pri.horiz_pixels,
2254                                  params->pri.bytes_per_pixel,
2255                                  mem_value);
2256
2257         return min(method1, method2);
2258 }
2259
2260 /*
2261  * For both WM_PIPE and WM_LP.
2262  * mem_value must be in 0.1us units.
2263  */
2264 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2265                                    uint32_t mem_value)
2266 {
2267         uint32_t method1, method2;
2268
2269         if (!params->active || !params->spr.enabled)
2270                 return 0;
2271
2272         method1 = ilk_wm_method1(params->pixel_rate,
2273                                  params->spr.bytes_per_pixel,
2274                                  mem_value);
2275         method2 = ilk_wm_method2(params->pixel_rate,
2276                                  params->pipe_htotal,
2277                                  params->spr.horiz_pixels,
2278                                  params->spr.bytes_per_pixel,
2279                                  mem_value);
2280         return min(method1, method2);
2281 }
2282
2283 /*
2284  * For both WM_PIPE and WM_LP.
2285  * mem_value must be in 0.1us units.
2286  */
2287 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2288                                    uint32_t mem_value)
2289 {
2290         if (!params->active || !params->cur.enabled)
2291                 return 0;
2292
2293         return ilk_wm_method2(params->pixel_rate,
2294                               params->pipe_htotal,
2295                               params->cur.horiz_pixels,
2296                               params->cur.bytes_per_pixel,
2297                               mem_value);
2298 }
2299
2300 /* Only for WM_LP. */
2301 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2302                                    uint32_t pri_val)
2303 {
2304         if (!params->active || !params->pri.enabled)
2305                 return 0;
2306
2307         return ilk_wm_fbc(pri_val,
2308                           params->pri.horiz_pixels,
2309                           params->pri.bytes_per_pixel);
2310 }
2311
2312 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2313 {
2314         if (INTEL_INFO(dev)->gen >= 7)
2315                 return 768;
2316         else
2317                 return 512;
2318 }
2319
2320 /* Calculate the maximum primary/sprite plane watermark */
2321 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2322                                      int level,
2323                                      const struct intel_wm_config *config,
2324                                      enum intel_ddb_partitioning ddb_partitioning,
2325                                      bool is_sprite)
2326 {
2327         unsigned int fifo_size = ilk_display_fifo_size(dev);
2328         unsigned int max;
2329
2330         /* if sprites aren't enabled, sprites get nothing */
2331         if (is_sprite && !config->sprites_enabled)
2332                 return 0;
2333
2334         /* HSW allows LP1+ watermarks even with multiple pipes */
2335         if (level == 0 || config->num_pipes_active > 1) {
2336                 fifo_size /= INTEL_INFO(dev)->num_pipes;
2337
2338                 /*
2339                  * For some reason the non self refresh
2340                  * FIFO size is only half of the self
2341                  * refresh FIFO size on ILK/SNB.
2342                  */
2343                 if (INTEL_INFO(dev)->gen <= 6)
2344                         fifo_size /= 2;
2345         }
2346
2347         if (config->sprites_enabled) {
2348                 /* level 0 is always calculated with 1:1 split */
2349                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2350                         if (is_sprite)
2351                                 fifo_size *= 5;
2352                         fifo_size /= 6;
2353                 } else {
2354                         fifo_size /= 2;
2355                 }
2356         }
2357
2358         /* clamp to max that the registers can hold */
2359         if (INTEL_INFO(dev)->gen >= 7)
2360                 /* IVB/HSW primary/sprite plane watermarks */
2361                 max = level == 0 ? 127 : 1023;
2362         else if (!is_sprite)
2363                 /* ILK/SNB primary plane watermarks */
2364                 max = level == 0 ? 127 : 511;
2365         else
2366                 /* ILK/SNB sprite plane watermarks */
2367                 max = level == 0 ? 63 : 255;
2368
2369         return min(fifo_size, max);
2370 }
2371
2372 /* Calculate the maximum cursor plane watermark */
2373 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2374                                       int level,
2375                                       const struct intel_wm_config *config)
2376 {
2377         /* HSW LP1+ watermarks w/ multiple pipes */
2378         if (level > 0 && config->num_pipes_active > 1)
2379                 return 64;
2380
2381         /* otherwise just report max that registers can hold */
2382         if (INTEL_INFO(dev)->gen >= 7)
2383                 return level == 0 ? 63 : 255;
2384         else
2385                 return level == 0 ? 31 : 63;
2386 }
2387
2388 /* Calculate the maximum FBC watermark */
2389 static unsigned int ilk_fbc_wm_max(void)
2390 {
2391         /* max that registers can hold */
2392         return 15;
2393 }
2394
2395 static void ilk_compute_wm_maximums(struct drm_device *dev,
2396                                     int level,
2397                                     const struct intel_wm_config *config,
2398                                     enum intel_ddb_partitioning ddb_partitioning,
2399                                     struct hsw_wm_maximums *max)
2400 {
2401         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2402         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2403         max->cur = ilk_cursor_wm_max(dev, level, config);
2404         max->fbc = ilk_fbc_wm_max();
2405 }
2406
2407 static bool ilk_validate_wm_level(int level,
2408                                   const struct hsw_wm_maximums *max,
2409                                   struct intel_wm_level *result)
2410 {
2411         bool ret;
2412
2413         /* already determined to be invalid? */
2414         if (!result->enable)
2415                 return false;
2416
2417         result->enable = result->pri_val <= max->pri &&
2418                          result->spr_val <= max->spr &&
2419                          result->cur_val <= max->cur;
2420
2421         ret = result->enable;
2422
2423         /*
2424          * HACK until we can pre-compute everything,
2425          * and thus fail gracefully if LP0 watermarks
2426          * are exceeded...
2427          */
2428         if (level == 0 && !result->enable) {
2429                 if (result->pri_val > max->pri)
2430                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2431                                       level, result->pri_val, max->pri);
2432                 if (result->spr_val > max->spr)
2433                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2434                                       level, result->spr_val, max->spr);
2435                 if (result->cur_val > max->cur)
2436                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2437                                       level, result->cur_val, max->cur);
2438
2439                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2440                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2441                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2442                 result->enable = true;
2443         }
2444
2445         return ret;
2446 }
2447
2448 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2449                                  int level,
2450                                  const struct hsw_pipe_wm_parameters *p,
2451                                  struct intel_wm_level *result)
2452 {
2453         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2454         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2455         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2456
2457         /* WM1+ latency values stored in 0.5us units */
2458         if (level > 0) {
2459                 pri_latency *= 5;
2460                 spr_latency *= 5;
2461                 cur_latency *= 5;
2462         }
2463
2464         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2465         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2466         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2467         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2468         result->enable = true;
2469 }
2470
2471 static uint32_t
2472 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2473 {
2474         struct drm_i915_private *dev_priv = dev->dev_private;
2475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2476         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2477         u32 linetime, ips_linetime;
2478
2479         if (!intel_crtc_active(crtc))
2480                 return 0;
2481
2482         /* The WM are computed with base on how long it takes to fill a single
2483          * row at the given clock rate, multiplied by 8.
2484          * */
2485         linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2486         ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2487                                          intel_ddi_get_cdclk_freq(dev_priv));
2488
2489         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2490                PIPE_WM_LINETIME_TIME(linetime);
2491 }
2492
2493 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2494 {
2495         struct drm_i915_private *dev_priv = dev->dev_private;
2496
2497         if (IS_HASWELL(dev)) {
2498                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2499
2500                 wm[0] = (sskpd >> 56) & 0xFF;
2501                 if (wm[0] == 0)
2502                         wm[0] = sskpd & 0xF;
2503                 wm[1] = (sskpd >> 4) & 0xFF;
2504                 wm[2] = (sskpd >> 12) & 0xFF;
2505                 wm[3] = (sskpd >> 20) & 0x1FF;
2506                 wm[4] = (sskpd >> 32) & 0x1FF;
2507         } else if (INTEL_INFO(dev)->gen >= 6) {
2508                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2509
2510                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2511                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2512                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2513                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2514         } else if (INTEL_INFO(dev)->gen >= 5) {
2515                 uint32_t mltr = I915_READ(MLTR_ILK);
2516
2517                 /* ILK primary LP0 latency is 700 ns */
2518                 wm[0] = 7;
2519                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2520                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2521         }
2522 }
2523
2524 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2525 {
2526         /* ILK sprite LP0 latency is 1300 ns */
2527         if (INTEL_INFO(dev)->gen == 5)
2528                 wm[0] = 13;
2529 }
2530
2531 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2532 {
2533         /* ILK cursor LP0 latency is 1300 ns */
2534         if (INTEL_INFO(dev)->gen == 5)
2535                 wm[0] = 13;
2536
2537         /* WaDoubleCursorLP3Latency:ivb */
2538         if (IS_IVYBRIDGE(dev))
2539                 wm[3] *= 2;
2540 }
2541
2542 static int ilk_wm_max_level(const struct drm_device *dev)
2543 {
2544         /* how many WM levels are we expecting */
2545         if (IS_HASWELL(dev))
2546                 return 4;
2547         else if (INTEL_INFO(dev)->gen >= 6)
2548                 return 3;
2549         else
2550                 return 2;
2551 }
2552
2553 static void intel_print_wm_latency(struct drm_device *dev,
2554                                    const char *name,
2555                                    const uint16_t wm[5])
2556 {
2557         int level, max_level = ilk_wm_max_level(dev);
2558
2559         for (level = 0; level <= max_level; level++) {
2560                 unsigned int latency = wm[level];
2561
2562                 if (latency == 0) {
2563                         DRM_ERROR("%s WM%d latency not provided\n",
2564                                   name, level);
2565                         continue;
2566                 }
2567
2568                 /* WM1+ latency values in 0.5us units */
2569                 if (level > 0)
2570                         latency *= 5;
2571
2572                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2573                               name, level, wm[level],
2574                               latency / 10, latency % 10);
2575         }
2576 }
2577
2578 static void intel_setup_wm_latency(struct drm_device *dev)
2579 {
2580         struct drm_i915_private *dev_priv = dev->dev_private;
2581
2582         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2583
2584         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2585                sizeof(dev_priv->wm.pri_latency));
2586         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2587                sizeof(dev_priv->wm.pri_latency));
2588
2589         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2590         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2591
2592         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2593         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2594         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2595 }
2596
2597 static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2598                                       struct hsw_pipe_wm_parameters *p,
2599                                       struct intel_wm_config *config)
2600 {
2601         struct drm_device *dev = crtc->dev;
2602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2603         enum pipe pipe = intel_crtc->pipe;
2604         struct drm_plane *plane;
2605
2606         p->active = intel_crtc_active(crtc);
2607         if (p->active) {
2608                 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2609                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2610                 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2611                 p->cur.bytes_per_pixel = 4;
2612                 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2613                 p->cur.horiz_pixels = 64;
2614                 /* TODO: for now, assume primary and cursor planes are always enabled. */
2615                 p->pri.enabled = true;
2616                 p->cur.enabled = true;
2617         }
2618
2619         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2620                 config->num_pipes_active += intel_crtc_active(crtc);
2621
2622         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2623                 struct intel_plane *intel_plane = to_intel_plane(plane);
2624
2625                 if (intel_plane->pipe == pipe)
2626                         p->spr = intel_plane->wm;
2627
2628                 config->sprites_enabled |= intel_plane->wm.enabled;
2629                 config->sprites_scaled |= intel_plane->wm.scaled;
2630         }
2631 }
2632
2633 /* Compute new watermarks for the pipe */
2634 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2635                                   const struct hsw_pipe_wm_parameters *params,
2636                                   struct intel_pipe_wm *pipe_wm)
2637 {
2638         struct drm_device *dev = crtc->dev;
2639         struct drm_i915_private *dev_priv = dev->dev_private;
2640         int level, max_level = ilk_wm_max_level(dev);
2641         /* LP0 watermark maximums depend on this pipe alone */
2642         struct intel_wm_config config = {
2643                 .num_pipes_active = 1,
2644                 .sprites_enabled = params->spr.enabled,
2645                 .sprites_scaled = params->spr.scaled,
2646         };
2647         struct hsw_wm_maximums max;
2648
2649         /* LP0 watermarks always use 1/2 DDB partitioning */
2650         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2651
2652         for (level = 0; level <= max_level; level++)
2653                 ilk_compute_wm_level(dev_priv, level, params,
2654                                      &pipe_wm->wm[level]);
2655
2656         pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2657
2658         /* At least LP0 must be valid */
2659         return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2660 }
2661
2662 /*
2663  * Merge the watermarks from all active pipes for a specific level.
2664  */
2665 static void ilk_merge_wm_level(struct drm_device *dev,
2666                                int level,
2667                                struct intel_wm_level *ret_wm)
2668 {
2669         const struct intel_crtc *intel_crtc;
2670
2671         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2672                 const struct intel_wm_level *wm =
2673                         &intel_crtc->wm.active.wm[level];
2674
2675                 if (!wm->enable)
2676                         return;
2677
2678                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2679                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2680                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2681                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2682         }
2683
2684         ret_wm->enable = true;
2685 }
2686
2687 /*
2688  * Merge all low power watermarks for all active pipes.
2689  */
2690 static void ilk_wm_merge(struct drm_device *dev,
2691                          const struct hsw_wm_maximums *max,
2692                          struct intel_pipe_wm *merged)
2693 {
2694         int level, max_level = ilk_wm_max_level(dev);
2695
2696         merged->fbc_wm_enabled = true;
2697
2698         /* merge each WM1+ level */
2699         for (level = 1; level <= max_level; level++) {
2700                 struct intel_wm_level *wm = &merged->wm[level];
2701
2702                 ilk_merge_wm_level(dev, level, wm);
2703
2704                 if (!ilk_validate_wm_level(level, max, wm))
2705                         break;
2706
2707                 /*
2708                  * The spec says it is preferred to disable
2709                  * FBC WMs instead of disabling a WM level.
2710                  */
2711                 if (wm->fbc_val > max->fbc) {
2712                         merged->fbc_wm_enabled = false;
2713                         wm->fbc_val = 0;
2714                 }
2715         }
2716 }
2717
2718 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2719 {
2720         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2721         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2722 }
2723
2724 static void hsw_compute_wm_results(struct drm_device *dev,
2725                                    const struct intel_pipe_wm *merged,
2726                                    enum intel_ddb_partitioning partitioning,
2727                                    struct hsw_wm_values *results)
2728 {
2729         struct intel_crtc *intel_crtc;
2730         int level, wm_lp;
2731
2732         results->enable_fbc_wm = merged->fbc_wm_enabled;
2733         results->partitioning = partitioning;
2734
2735         /* LP1+ register values */
2736         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2737                 const struct intel_wm_level *r;
2738
2739                 level = ilk_wm_lp_to_level(wm_lp, merged);
2740
2741                 r = &merged->wm[level];
2742                 if (!r->enable)
2743                         break;
2744
2745                 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2746                                                           r->fbc_val,
2747                                                           r->pri_val,
2748                                                           r->cur_val);
2749                 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2750         }
2751
2752         /* LP0 register values */
2753         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2754                 enum pipe pipe = intel_crtc->pipe;
2755                 const struct intel_wm_level *r =
2756                         &intel_crtc->wm.active.wm[0];
2757
2758                 if (WARN_ON(!r->enable))
2759                         continue;
2760
2761                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2762
2763                 results->wm_pipe[pipe] =
2764                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2765                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2766                         r->cur_val;
2767         }
2768 }
2769
2770 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2771  * case both are at the same level. Prefer r1 in case they're the same. */
2772 static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2773                                                   struct intel_pipe_wm *r1,
2774                                                   struct intel_pipe_wm *r2)
2775 {
2776         int level, max_level = ilk_wm_max_level(dev);
2777         int level1 = 0, level2 = 0;
2778
2779         for (level = 1; level <= max_level; level++) {
2780                 if (r1->wm[level].enable)
2781                         level1 = level;
2782                 if (r2->wm[level].enable)
2783                         level2 = level;
2784         }
2785
2786         if (level1 == level2) {
2787                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2788                         return r2;
2789                 else
2790                         return r1;
2791         } else if (level1 > level2) {
2792                 return r1;
2793         } else {
2794                 return r2;
2795         }
2796 }
2797
2798 /* dirty bits used to track which watermarks need changes */
2799 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2800 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2801 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2802 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2803 #define WM_DIRTY_FBC (1 << 24)
2804 #define WM_DIRTY_DDB (1 << 25)
2805
2806 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2807                                          const struct hsw_wm_values *old,
2808                                          const struct hsw_wm_values *new)
2809 {
2810         unsigned int dirty = 0;
2811         enum pipe pipe;
2812         int wm_lp;
2813
2814         for_each_pipe(pipe) {
2815                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2816                         dirty |= WM_DIRTY_LINETIME(pipe);
2817                         /* Must disable LP1+ watermarks too */
2818                         dirty |= WM_DIRTY_LP_ALL;
2819                 }
2820
2821                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2822                         dirty |= WM_DIRTY_PIPE(pipe);
2823                         /* Must disable LP1+ watermarks too */
2824                         dirty |= WM_DIRTY_LP_ALL;
2825                 }
2826         }
2827
2828         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2829                 dirty |= WM_DIRTY_FBC;
2830                 /* Must disable LP1+ watermarks too */
2831                 dirty |= WM_DIRTY_LP_ALL;
2832         }
2833
2834         if (old->partitioning != new->partitioning) {
2835                 dirty |= WM_DIRTY_DDB;
2836                 /* Must disable LP1+ watermarks too */
2837                 dirty |= WM_DIRTY_LP_ALL;
2838         }
2839
2840         /* LP1+ watermarks already deemed dirty, no need to continue */
2841         if (dirty & WM_DIRTY_LP_ALL)
2842                 return dirty;
2843
2844         /* Find the lowest numbered LP1+ watermark in need of an update... */
2845         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2846                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2847                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2848                         break;
2849         }
2850
2851         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2852         for (; wm_lp <= 3; wm_lp++)
2853                 dirty |= WM_DIRTY_LP(wm_lp);
2854
2855         return dirty;
2856 }
2857
2858 /*
2859  * The spec says we shouldn't write when we don't need, because every write
2860  * causes WMs to be re-evaluated, expending some power.
2861  */
2862 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2863                                 struct hsw_wm_values *results)
2864 {
2865         struct hsw_wm_values *previous = &dev_priv->wm.hw;
2866         unsigned int dirty;
2867         uint32_t val;
2868
2869         dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
2870         if (!dirty)
2871                 return;
2872
2873         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
2874                 I915_WRITE(WM3_LP_ILK, 0);
2875         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
2876                 I915_WRITE(WM2_LP_ILK, 0);
2877         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
2878                 I915_WRITE(WM1_LP_ILK, 0);
2879
2880         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2881                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2882         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2883                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2884         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2885                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2886
2887         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2888                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2889         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2890                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2891         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2892                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2893
2894         if (dirty & WM_DIRTY_DDB) {
2895                 val = I915_READ(WM_MISC);
2896                 if (results->partitioning == INTEL_DDB_PART_1_2)
2897                         val &= ~WM_MISC_DATA_PARTITION_5_6;
2898                 else
2899                         val |= WM_MISC_DATA_PARTITION_5_6;
2900                 I915_WRITE(WM_MISC, val);
2901         }
2902
2903         if (dirty & WM_DIRTY_FBC) {
2904                 val = I915_READ(DISP_ARB_CTL);
2905                 if (results->enable_fbc_wm)
2906                         val &= ~DISP_FBC_WM_DIS;
2907                 else
2908                         val |= DISP_FBC_WM_DIS;
2909                 I915_WRITE(DISP_ARB_CTL, val);
2910         }
2911
2912         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2913                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2914         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2915                 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2916         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2917                 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2918
2919         if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
2920                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2921         if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
2922                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2923         if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
2924                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2925
2926         dev_priv->wm.hw = *results;
2927 }
2928
2929 static void haswell_update_wm(struct drm_crtc *crtc)
2930 {
2931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2932         struct drm_device *dev = crtc->dev;
2933         struct drm_i915_private *dev_priv = dev->dev_private;
2934         struct hsw_wm_maximums max;
2935         struct hsw_pipe_wm_parameters params = {};
2936         struct hsw_wm_values results = {};
2937         enum intel_ddb_partitioning partitioning;
2938         struct intel_pipe_wm pipe_wm = {};
2939         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2940         struct intel_wm_config config = {};
2941
2942         hsw_compute_wm_parameters(crtc, &params, &config);
2943
2944         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2945
2946         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2947                 return;
2948
2949         intel_crtc->wm.active = pipe_wm;
2950
2951         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2952         ilk_wm_merge(dev, &max, &lp_wm_1_2);
2953
2954         /* 5/6 split only in single pipe config on IVB+ */
2955         if (INTEL_INFO(dev)->gen >= 7 &&
2956             config.num_pipes_active == 1 && config.sprites_enabled) {
2957                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2958                 ilk_wm_merge(dev, &max, &lp_wm_5_6);
2959
2960                 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2961         } else {
2962                 best_lp_wm = &lp_wm_1_2;
2963         }
2964
2965         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2966                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2967
2968         hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2969
2970         hsw_write_wm_values(dev_priv, &results);
2971 }
2972
2973 static void haswell_update_sprite_wm(struct drm_plane *plane,
2974                                      struct drm_crtc *crtc,
2975                                      uint32_t sprite_width, int pixel_size,
2976                                      bool enabled, bool scaled)
2977 {
2978         struct intel_plane *intel_plane = to_intel_plane(plane);
2979
2980         intel_plane->wm.enabled = enabled;
2981         intel_plane->wm.scaled = scaled;
2982         intel_plane->wm.horiz_pixels = sprite_width;
2983         intel_plane->wm.bytes_per_pixel = pixel_size;
2984
2985         haswell_update_wm(crtc);
2986 }
2987
2988 static bool
2989 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2990                               uint32_t sprite_width, int pixel_size,
2991                               const struct intel_watermark_params *display,
2992                               int display_latency_ns, int *sprite_wm)
2993 {
2994         struct drm_crtc *crtc;
2995         int clock;
2996         int entries, tlb_miss;
2997
2998         crtc = intel_get_crtc_for_plane(dev, plane);
2999         if (!intel_crtc_active(crtc)) {
3000                 *sprite_wm = display->guard_size;
3001                 return false;
3002         }
3003
3004         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3005
3006         /* Use the small buffer method to calculate the sprite watermark */
3007         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3008         tlb_miss = display->fifo_size*display->cacheline_size -
3009                 sprite_width * 8;
3010         if (tlb_miss > 0)
3011                 entries += tlb_miss;
3012         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3013         *sprite_wm = entries + display->guard_size;
3014         if (*sprite_wm > (int)display->max_wm)
3015                 *sprite_wm = display->max_wm;
3016
3017         return true;
3018 }
3019
3020 static bool
3021 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3022                                 uint32_t sprite_width, int pixel_size,
3023                                 const struct intel_watermark_params *display,
3024                                 int latency_ns, int *sprite_wm)
3025 {
3026         struct drm_crtc *crtc;
3027         unsigned long line_time_us;
3028         int clock;
3029         int line_count, line_size;
3030         int small, large;
3031         int entries;
3032
3033         if (!latency_ns) {
3034                 *sprite_wm = 0;
3035                 return false;
3036         }
3037
3038         crtc = intel_get_crtc_for_plane(dev, plane);
3039         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3040         if (!clock) {
3041                 *sprite_wm = 0;
3042                 return false;
3043         }
3044
3045         line_time_us = (sprite_width * 1000) / clock;
3046         if (!line_time_us) {
3047                 *sprite_wm = 0;
3048                 return false;
3049         }
3050
3051         line_count = (latency_ns / line_time_us + 1000) / 1000;
3052         line_size = sprite_width * pixel_size;
3053
3054         /* Use the minimum of the small and large buffer method for primary */
3055         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3056         large = line_count * line_size;
3057
3058         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3059         *sprite_wm = entries + display->guard_size;
3060
3061         return *sprite_wm > 0x3ff ? false : true;
3062 }
3063
3064 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3065                                          struct drm_crtc *crtc,
3066                                          uint32_t sprite_width, int pixel_size,
3067                                          bool enabled, bool scaled)
3068 {
3069         struct drm_device *dev = plane->dev;
3070         struct drm_i915_private *dev_priv = dev->dev_private;
3071         int pipe = to_intel_plane(plane)->pipe;
3072         int latency = dev_priv->wm.spr_latency[0] * 100;        /* In unit 0.1us */
3073         u32 val;
3074         int sprite_wm, reg;
3075         int ret;
3076
3077         if (!enabled)
3078                 return;
3079
3080         switch (pipe) {
3081         case 0:
3082                 reg = WM0_PIPEA_ILK;
3083                 break;
3084         case 1:
3085                 reg = WM0_PIPEB_ILK;
3086                 break;
3087         case 2:
3088                 reg = WM0_PIPEC_IVB;
3089                 break;
3090         default:
3091                 return; /* bad pipe */
3092         }
3093
3094         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3095                                             &sandybridge_display_wm_info,
3096                                             latency, &sprite_wm);
3097         if (!ret) {
3098                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3099                               pipe_name(pipe));
3100                 return;
3101         }
3102
3103         val = I915_READ(reg);
3104         val &= ~WM0_PIPE_SPRITE_MASK;
3105         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3106         DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3107
3108
3109         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3110                                               pixel_size,
3111                                               &sandybridge_display_srwm_info,
3112                                               dev_priv->wm.spr_latency[1] * 500,
3113                                               &sprite_wm);
3114         if (!ret) {
3115                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3116                               pipe_name(pipe));
3117                 return;
3118         }
3119         I915_WRITE(WM1S_LP_ILK, sprite_wm);
3120
3121         /* Only IVB has two more LP watermarks for sprite */
3122         if (!IS_IVYBRIDGE(dev))
3123                 return;
3124
3125         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3126                                               pixel_size,
3127                                               &sandybridge_display_srwm_info,
3128                                               dev_priv->wm.spr_latency[2] * 500,
3129                                               &sprite_wm);
3130         if (!ret) {
3131                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3132                               pipe_name(pipe));
3133                 return;
3134         }
3135         I915_WRITE(WM2S_LP_IVB, sprite_wm);
3136
3137         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3138                                               pixel_size,
3139                                               &sandybridge_display_srwm_info,
3140                                               dev_priv->wm.spr_latency[3] * 500,
3141                                               &sprite_wm);
3142         if (!ret) {
3143                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3144                               pipe_name(pipe));
3145                 return;
3146         }
3147         I915_WRITE(WM3S_LP_IVB, sprite_wm);
3148 }
3149
3150 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3151 {
3152         struct drm_device *dev = crtc->dev;
3153         struct drm_i915_private *dev_priv = dev->dev_private;
3154         struct hsw_wm_values *hw = &dev_priv->wm.hw;
3155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3156         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3157         enum pipe pipe = intel_crtc->pipe;
3158         static const unsigned int wm0_pipe_reg[] = {
3159                 [PIPE_A] = WM0_PIPEA_ILK,
3160                 [PIPE_B] = WM0_PIPEB_ILK,
3161                 [PIPE_C] = WM0_PIPEC_IVB,
3162         };
3163
3164         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3165         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3166
3167         if (intel_crtc_active(crtc)) {
3168                 u32 tmp = hw->wm_pipe[pipe];
3169
3170                 /*
3171                  * For active pipes LP0 watermark is marked as
3172                  * enabled, and LP1+ watermaks as disabled since
3173                  * we can't really reverse compute them in case
3174                  * multiple pipes are active.
3175                  */
3176                 active->wm[0].enable = true;
3177                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3178                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3179                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3180                 active->linetime = hw->wm_linetime[pipe];
3181         } else {
3182                 int level, max_level = ilk_wm_max_level(dev);
3183
3184                 /*
3185                  * For inactive pipes, all watermark levels
3186                  * should be marked as enabled but zeroed,
3187                  * which is what we'd compute them to.
3188                  */
3189                 for (level = 0; level <= max_level; level++)
3190                         active->wm[level].enable = true;
3191         }
3192 }
3193
3194 void ilk_wm_get_hw_state(struct drm_device *dev)
3195 {
3196         struct drm_i915_private *dev_priv = dev->dev_private;
3197         struct hsw_wm_values *hw = &dev_priv->wm.hw;
3198         struct drm_crtc *crtc;
3199
3200         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3201                 ilk_pipe_wm_get_hw_state(crtc);
3202
3203         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3204         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3205         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3206
3207         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3208         hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3209         hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3210
3211         hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3212                 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3213
3214         hw->enable_fbc_wm =
3215                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3216 }
3217
3218 /**
3219  * intel_update_watermarks - update FIFO watermark values based on current modes
3220  *
3221  * Calculate watermark values for the various WM regs based on current mode
3222  * and plane configuration.
3223  *
3224  * There are several cases to deal with here:
3225  *   - normal (i.e. non-self-refresh)
3226  *   - self-refresh (SR) mode
3227  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3228  *   - lines are small relative to FIFO size (buffer can hold more than 2
3229  *     lines), so need to account for TLB latency
3230  *
3231  *   The normal calculation is:
3232  *     watermark = dotclock * bytes per pixel * latency
3233  *   where latency is platform & configuration dependent (we assume pessimal
3234  *   values here).
3235  *
3236  *   The SR calculation is:
3237  *     watermark = (trunc(latency/line time)+1) * surface width *
3238  *       bytes per pixel
3239  *   where
3240  *     line time = htotal / dotclock
3241  *     surface width = hdisplay for normal plane and 64 for cursor
3242  *   and latency is assumed to be high, as above.
3243  *
3244  * The final value programmed to the register should always be rounded up,
3245  * and include an extra 2 entries to account for clock crossings.
3246  *
3247  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3248  * to set the non-SR watermarks to 8.
3249  */
3250 void intel_update_watermarks(struct drm_crtc *crtc)
3251 {
3252         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3253
3254         if (dev_priv->display.update_wm)
3255                 dev_priv->display.update_wm(crtc);
3256 }
3257
3258 void intel_update_sprite_watermarks(struct drm_plane *plane,
3259                                     struct drm_crtc *crtc,
3260                                     uint32_t sprite_width, int pixel_size,
3261                                     bool enabled, bool scaled)
3262 {
3263         struct drm_i915_private *dev_priv = plane->dev->dev_private;
3264
3265         if (dev_priv->display.update_sprite_wm)
3266                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3267                                                    pixel_size, enabled, scaled);
3268 }
3269
3270 static struct drm_i915_gem_object *
3271 intel_alloc_context_page(struct drm_device *dev)
3272 {
3273         struct drm_i915_gem_object *ctx;
3274         int ret;
3275
3276         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3277
3278         ctx = i915_gem_alloc_object(dev, 4096);
3279         if (!ctx) {
3280                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3281                 return NULL;
3282         }
3283
3284         ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3285         if (ret) {
3286                 DRM_ERROR("failed to pin power context: %d\n", ret);
3287                 goto err_unref;
3288         }
3289
3290         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3291         if (ret) {
3292                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3293                 goto err_unpin;
3294         }
3295
3296         return ctx;
3297
3298 err_unpin:
3299         i915_gem_object_unpin(ctx);
3300 err_unref:
3301         drm_gem_object_unreference(&ctx->base);
3302         return NULL;
3303 }
3304
3305 /**
3306  * Lock protecting IPS related data structures
3307  */
3308 DEFINE_SPINLOCK(mchdev_lock);
3309
3310 /* Global for IPS driver to get at the current i915 device. Protected by
3311  * mchdev_lock. */
3312 static struct drm_i915_private *i915_mch_dev;
3313
3314 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3315 {
3316         struct drm_i915_private *dev_priv = dev->dev_private;
3317         u16 rgvswctl;
3318
3319         assert_spin_locked(&mchdev_lock);
3320
3321         rgvswctl = I915_READ16(MEMSWCTL);
3322         if (rgvswctl & MEMCTL_CMD_STS) {
3323                 DRM_DEBUG("gpu busy, RCS change rejected\n");
3324                 return false; /* still busy with another command */
3325         }
3326
3327         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3328                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3329         I915_WRITE16(MEMSWCTL, rgvswctl);
3330         POSTING_READ16(MEMSWCTL);
3331
3332         rgvswctl |= MEMCTL_CMD_STS;
3333         I915_WRITE16(MEMSWCTL, rgvswctl);
3334
3335         return true;
3336 }
3337
3338 static void ironlake_enable_drps(struct drm_device *dev)
3339 {
3340         struct drm_i915_private *dev_priv = dev->dev_private;
3341         u32 rgvmodectl = I915_READ(MEMMODECTL);
3342         u8 fmax, fmin, fstart, vstart;
3343
3344         spin_lock_irq(&mchdev_lock);
3345
3346         /* Enable temp reporting */
3347         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3348         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3349
3350         /* 100ms RC evaluation intervals */
3351         I915_WRITE(RCUPEI, 100000);
3352         I915_WRITE(RCDNEI, 100000);
3353
3354         /* Set max/min thresholds to 90ms and 80ms respectively */
3355         I915_WRITE(RCBMAXAVG, 90000);
3356         I915_WRITE(RCBMINAVG, 80000);
3357
3358         I915_WRITE(MEMIHYST, 1);
3359
3360         /* Set up min, max, and cur for interrupt handling */
3361         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3362         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3363         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3364                 MEMMODE_FSTART_SHIFT;
3365
3366         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3367                 PXVFREQ_PX_SHIFT;
3368
3369         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3370         dev_priv->ips.fstart = fstart;
3371
3372         dev_priv->ips.max_delay = fstart;
3373         dev_priv->ips.min_delay = fmin;
3374         dev_priv->ips.cur_delay = fstart;
3375
3376         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3377                          fmax, fmin, fstart);
3378
3379         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3380
3381         /*
3382          * Interrupts will be enabled in ironlake_irq_postinstall
3383          */
3384
3385         I915_WRITE(VIDSTART, vstart);
3386         POSTING_READ(VIDSTART);
3387
3388         rgvmodectl |= MEMMODE_SWMODE_EN;
3389         I915_WRITE(MEMMODECTL, rgvmodectl);
3390
3391         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3392                 DRM_ERROR("stuck trying to change perf mode\n");
3393         mdelay(1);
3394
3395         ironlake_set_drps(dev, fstart);
3396
3397         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3398                 I915_READ(0x112e0);
3399         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3400         dev_priv->ips.last_count2 = I915_READ(0x112f4);
3401         getrawmonotonic(&dev_priv->ips.last_time2);
3402
3403         spin_unlock_irq(&mchdev_lock);
3404 }
3405
3406 static void ironlake_disable_drps(struct drm_device *dev)
3407 {
3408         struct drm_i915_private *dev_priv = dev->dev_private;
3409         u16 rgvswctl;
3410
3411         spin_lock_irq(&mchdev_lock);
3412
3413         rgvswctl = I915_READ16(MEMSWCTL);
3414
3415         /* Ack interrupts, disable EFC interrupt */
3416         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3417         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3418         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3419         I915_WRITE(DEIIR, DE_PCU_EVENT);
3420         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3421
3422         /* Go back to the starting frequency */
3423         ironlake_set_drps(dev, dev_priv->ips.fstart);
3424         mdelay(1);
3425         rgvswctl |= MEMCTL_CMD_STS;
3426         I915_WRITE(MEMSWCTL, rgvswctl);
3427         mdelay(1);
3428
3429         spin_unlock_irq(&mchdev_lock);
3430 }
3431
3432 /* There's a funny hw issue where the hw returns all 0 when reading from
3433  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3434  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3435  * all limits and the gpu stuck at whatever frequency it is at atm).
3436  */
3437 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
3438 {
3439         u32 limits;
3440
3441         limits = 0;
3442
3443         if (*val >= dev_priv->rps.max_delay)
3444                 *val = dev_priv->rps.max_delay;
3445         limits |= dev_priv->rps.max_delay << 24;
3446
3447         /* Only set the down limit when we've reached the lowest level to avoid
3448          * getting more interrupts, otherwise leave this clear. This prevents a
3449          * race in the hw when coming out of rc6: There's a tiny window where
3450          * the hw runs at the minimal clock before selecting the desired
3451          * frequency, if the down threshold expires in that window we will not
3452          * receive a down interrupt. */
3453         if (*val <= dev_priv->rps.min_delay) {
3454                 *val = dev_priv->rps.min_delay;
3455                 limits |= dev_priv->rps.min_delay << 16;
3456         }
3457
3458         return limits;
3459 }
3460
3461 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3462 {
3463         int new_power;
3464
3465         new_power = dev_priv->rps.power;
3466         switch (dev_priv->rps.power) {
3467         case LOW_POWER:
3468                 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3469                         new_power = BETWEEN;
3470                 break;
3471
3472         case BETWEEN:
3473                 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3474                         new_power = LOW_POWER;
3475                 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3476                         new_power = HIGH_POWER;
3477                 break;
3478
3479         case HIGH_POWER:
3480                 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3481                         new_power = BETWEEN;
3482                 break;
3483         }
3484         /* Max/min bins are special */
3485         if (val == dev_priv->rps.min_delay)
3486                 new_power = LOW_POWER;
3487         if (val == dev_priv->rps.max_delay)
3488                 new_power = HIGH_POWER;
3489         if (new_power == dev_priv->rps.power)
3490                 return;
3491
3492         /* Note the units here are not exactly 1us, but 1280ns. */
3493         switch (new_power) {
3494         case LOW_POWER:
3495                 /* Upclock if more than 95% busy over 16ms */
3496                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3497                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3498
3499                 /* Downclock if less than 85% busy over 32ms */
3500                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3501                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3502
3503                 I915_WRITE(GEN6_RP_CONTROL,
3504                            GEN6_RP_MEDIA_TURBO |
3505                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3506                            GEN6_RP_MEDIA_IS_GFX |
3507                            GEN6_RP_ENABLE |
3508                            GEN6_RP_UP_BUSY_AVG |
3509                            GEN6_RP_DOWN_IDLE_AVG);
3510                 break;
3511
3512         case BETWEEN:
3513                 /* Upclock if more than 90% busy over 13ms */
3514                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3515                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3516
3517                 /* Downclock if less than 75% busy over 32ms */
3518                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3519                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3520
3521                 I915_WRITE(GEN6_RP_CONTROL,
3522                            GEN6_RP_MEDIA_TURBO |
3523                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3524                            GEN6_RP_MEDIA_IS_GFX |
3525                            GEN6_RP_ENABLE |
3526                            GEN6_RP_UP_BUSY_AVG |
3527                            GEN6_RP_DOWN_IDLE_AVG);
3528                 break;
3529
3530         case HIGH_POWER:
3531                 /* Upclock if more than 85% busy over 10ms */
3532                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3533                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3534
3535                 /* Downclock if less than 60% busy over 32ms */
3536                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3537                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3538
3539                 I915_WRITE(GEN6_RP_CONTROL,
3540                            GEN6_RP_MEDIA_TURBO |
3541                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3542                            GEN6_RP_MEDIA_IS_GFX |
3543                            GEN6_RP_ENABLE |
3544                            GEN6_RP_UP_BUSY_AVG |
3545                            GEN6_RP_DOWN_IDLE_AVG);
3546                 break;
3547         }
3548
3549         dev_priv->rps.power = new_power;
3550         dev_priv->rps.last_adj = 0;
3551 }
3552
3553 void gen6_set_rps(struct drm_device *dev, u8 val)
3554 {
3555         struct drm_i915_private *dev_priv = dev->dev_private;
3556         u32 limits = gen6_rps_limits(dev_priv, &val);
3557
3558         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3559         WARN_ON(val > dev_priv->rps.max_delay);
3560         WARN_ON(val < dev_priv->rps.min_delay);
3561
3562         if (val == dev_priv->rps.cur_delay)
3563                 return;
3564
3565         gen6_set_rps_thresholds(dev_priv, val);
3566
3567         if (IS_HASWELL(dev))
3568                 I915_WRITE(GEN6_RPNSWREQ,
3569                            HSW_FREQUENCY(val));
3570         else
3571                 I915_WRITE(GEN6_RPNSWREQ,
3572                            GEN6_FREQUENCY(val) |
3573                            GEN6_OFFSET(0) |
3574                            GEN6_AGGRESSIVE_TURBO);
3575
3576         /* Make sure we continue to get interrupts
3577          * until we hit the minimum or maximum frequencies.
3578          */
3579         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3580
3581         POSTING_READ(GEN6_RPNSWREQ);
3582
3583         dev_priv->rps.cur_delay = val;
3584
3585         trace_intel_gpu_freq_change(val * 50);
3586 }
3587
3588 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3589 {
3590         mutex_lock(&dev_priv->rps.hw_lock);
3591         if (dev_priv->rps.enabled) {
3592                 if (dev_priv->info->is_valleyview)
3593                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3594                 else
3595                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3596                 dev_priv->rps.last_adj = 0;
3597         }
3598         mutex_unlock(&dev_priv->rps.hw_lock);
3599 }
3600
3601 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3602 {
3603         mutex_lock(&dev_priv->rps.hw_lock);
3604         if (dev_priv->rps.enabled) {
3605                 if (dev_priv->info->is_valleyview)
3606                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3607                 else
3608                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3609                 dev_priv->rps.last_adj = 0;
3610         }
3611         mutex_unlock(&dev_priv->rps.hw_lock);
3612 }
3613
3614 /*
3615  * Wait until the previous freq change has completed,
3616  * or the timeout elapsed, and then update our notion
3617  * of the current GPU frequency.
3618  */
3619 static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3620 {
3621         u32 pval;
3622
3623         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3624
3625         if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3626                 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3627
3628         pval >>= 8;
3629
3630         if (pval != dev_priv->rps.cur_delay)
3631                 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3632                                  vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3633                                  dev_priv->rps.cur_delay,
3634                                  vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3635
3636         dev_priv->rps.cur_delay = pval;
3637 }
3638
3639 void valleyview_set_rps(struct drm_device *dev, u8 val)
3640 {
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642
3643         gen6_rps_limits(dev_priv, &val);
3644
3645         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3646         WARN_ON(val > dev_priv->rps.max_delay);
3647         WARN_ON(val < dev_priv->rps.min_delay);
3648
3649         vlv_update_rps_cur_delay(dev_priv);
3650
3651         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3652                          vlv_gpu_freq(dev_priv->mem_freq,
3653                                       dev_priv->rps.cur_delay),
3654                          dev_priv->rps.cur_delay,
3655                          vlv_gpu_freq(dev_priv->mem_freq, val), val);
3656
3657         if (val == dev_priv->rps.cur_delay)
3658                 return;
3659
3660         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3661
3662         dev_priv->rps.cur_delay = val;
3663
3664         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3665 }
3666
3667 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3668 {
3669         struct drm_i915_private *dev_priv = dev->dev_private;
3670
3671         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3672         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3673         /* Complete PM interrupt masking here doesn't race with the rps work
3674          * item again unmasking PM interrupts because that is using a different
3675          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3676          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3677
3678         spin_lock_irq(&dev_priv->irq_lock);
3679         dev_priv->rps.pm_iir = 0;
3680         spin_unlock_irq(&dev_priv->irq_lock);
3681
3682         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3683 }
3684
3685 static void gen6_disable_rps(struct drm_device *dev)
3686 {
3687         struct drm_i915_private *dev_priv = dev->dev_private;
3688
3689         I915_WRITE(GEN6_RC_CONTROL, 0);
3690         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3691
3692         gen6_disable_rps_interrupts(dev);
3693 }
3694
3695 static void valleyview_disable_rps(struct drm_device *dev)
3696 {
3697         struct drm_i915_private *dev_priv = dev->dev_private;
3698
3699         I915_WRITE(GEN6_RC_CONTROL, 0);
3700
3701         gen6_disable_rps_interrupts(dev);
3702
3703         if (dev_priv->vlv_pctx) {
3704                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3705                 dev_priv->vlv_pctx = NULL;
3706         }
3707 }
3708
3709 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3710 {
3711         if (IS_GEN6(dev))
3712                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3713
3714         if (IS_HASWELL(dev))
3715                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3716
3717         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3718                         (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3719                         (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3720                         (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3721 }
3722
3723 int intel_enable_rc6(const struct drm_device *dev)
3724 {
3725         /* No RC6 before Ironlake */
3726         if (INTEL_INFO(dev)->gen < 5)
3727                 return 0;
3728
3729         /* Respect the kernel parameter if it is set */
3730         if (i915_enable_rc6 >= 0)
3731                 return i915_enable_rc6;
3732
3733         /* Disable RC6 on Ironlake */
3734         if (INTEL_INFO(dev)->gen == 5)
3735                 return 0;
3736
3737         if (IS_HASWELL(dev))
3738                 return INTEL_RC6_ENABLE;
3739
3740         /* snb/ivb have more than one rc6 state. */
3741         if (INTEL_INFO(dev)->gen == 6)
3742                 return INTEL_RC6_ENABLE;
3743
3744         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3745 }
3746
3747 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3748 {
3749         struct drm_i915_private *dev_priv = dev->dev_private;
3750         u32 enabled_intrs;
3751
3752         spin_lock_irq(&dev_priv->irq_lock);
3753         WARN_ON(dev_priv->rps.pm_iir);
3754         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3755         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3756         spin_unlock_irq(&dev_priv->irq_lock);
3757
3758         /* only unmask PM interrupts we need. Mask all others. */
3759         enabled_intrs = GEN6_PM_RPS_EVENTS;
3760
3761         /* IVB and SNB hard hangs on looping batchbuffer
3762          * if GEN6_PM_UP_EI_EXPIRED is masked.
3763          */
3764         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3765                 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3766
3767         I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3768 }
3769
3770 static void gen6_enable_rps(struct drm_device *dev)
3771 {
3772         struct drm_i915_private *dev_priv = dev->dev_private;
3773         struct intel_ring_buffer *ring;
3774         u32 rp_state_cap;
3775         u32 gt_perf_status;
3776         u32 rc6vids, pcu_mbox, rc6_mask = 0;
3777         u32 gtfifodbg;
3778         int rc6_mode;
3779         int i, ret;
3780
3781         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3782
3783         /* Here begins a magic sequence of register writes to enable
3784          * auto-downclocking.
3785          *
3786          * Perhaps there might be some value in exposing these to
3787          * userspace...
3788          */
3789         I915_WRITE(GEN6_RC_STATE, 0);
3790
3791         /* Clear the DBG now so we don't confuse earlier errors */
3792         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3793                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3794                 I915_WRITE(GTFIFODBG, gtfifodbg);
3795         }
3796
3797         gen6_gt_force_wake_get(dev_priv);
3798
3799         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3800         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3801
3802         /* In units of 50MHz */
3803         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3804         dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3805         dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
3806         dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
3807         dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3808         dev_priv->rps.cur_delay = 0;
3809
3810         /* disable the counters and set deterministic thresholds */
3811         I915_WRITE(GEN6_RC_CONTROL, 0);
3812
3813         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3814         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3815         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3816         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3817         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3818
3819         for_each_ring(ring, dev_priv, i)
3820                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3821
3822         I915_WRITE(GEN6_RC_SLEEP, 0);
3823         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3824         if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3825                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3826         else
3827                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3828         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3829         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3830
3831         /* Check if we are enabling RC6 */
3832         rc6_mode = intel_enable_rc6(dev_priv->dev);
3833         if (rc6_mode & INTEL_RC6_ENABLE)
3834                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3835
3836         /* We don't use those on Haswell */
3837         if (!IS_HASWELL(dev)) {
3838                 if (rc6_mode & INTEL_RC6p_ENABLE)
3839                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3840
3841                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3842                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3843         }
3844
3845         intel_print_rc6_info(dev, rc6_mask);
3846
3847         I915_WRITE(GEN6_RC_CONTROL,
3848                    rc6_mask |
3849                    GEN6_RC_CTL_EI_MODE(1) |
3850                    GEN6_RC_CTL_HW_ENABLE);
3851
3852         /* Power down if completely idle for over 50ms */
3853         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3854         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3855
3856         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3857         if (!ret) {
3858                 pcu_mbox = 0;
3859                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3860                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3861                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3862                                          (dev_priv->rps.max_delay & 0xff) * 50,
3863                                          (pcu_mbox & 0xff) * 50);
3864                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
3865                 }
3866         } else {
3867                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3868         }
3869
3870         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3871         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3872
3873         gen6_enable_rps_interrupts(dev);
3874
3875         rc6vids = 0;
3876         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3877         if (IS_GEN6(dev) && ret) {
3878                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3879         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3880                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3881                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3882                 rc6vids &= 0xffff00;
3883                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3884                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3885                 if (ret)
3886                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3887         }
3888
3889         gen6_gt_force_wake_put(dev_priv);
3890 }
3891
3892 void gen6_update_ring_freq(struct drm_device *dev)
3893 {
3894         struct drm_i915_private *dev_priv = dev->dev_private;
3895         int min_freq = 15;
3896         unsigned int gpu_freq;
3897         unsigned int max_ia_freq, min_ring_freq;
3898         int scaling_factor = 180;
3899         struct cpufreq_policy *policy;
3900
3901         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3902
3903         policy = cpufreq_cpu_get(0);
3904         if (policy) {
3905                 max_ia_freq = policy->cpuinfo.max_freq;
3906                 cpufreq_cpu_put(policy);
3907         } else {
3908                 /*
3909                  * Default to measured freq if none found, PCU will ensure we
3910                  * don't go over
3911                  */
3912                 max_ia_freq = tsc_khz;
3913         }
3914
3915         /* Convert from kHz to MHz */
3916         max_ia_freq /= 1000;
3917
3918         min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
3919         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3920         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3921
3922         /*
3923          * For each potential GPU frequency, load a ring frequency we'd like
3924          * to use for memory access.  We do this by specifying the IA frequency
3925          * the PCU should use as a reference to determine the ring frequency.
3926          */
3927         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3928              gpu_freq--) {
3929                 int diff = dev_priv->rps.max_delay - gpu_freq;
3930                 unsigned int ia_freq = 0, ring_freq = 0;
3931
3932                 if (IS_HASWELL(dev)) {
3933                         ring_freq = mult_frac(gpu_freq, 5, 4);
3934                         ring_freq = max(min_ring_freq, ring_freq);
3935                         /* leave ia_freq as the default, chosen by cpufreq */
3936                 } else {
3937                         /* On older processors, there is no separate ring
3938                          * clock domain, so in order to boost the bandwidth
3939                          * of the ring, we need to upclock the CPU (ia_freq).
3940                          *
3941                          * For GPU frequencies less than 750MHz,
3942                          * just use the lowest ring freq.
3943                          */
3944                         if (gpu_freq < min_freq)
3945                                 ia_freq = 800;
3946                         else
3947                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3948                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3949                 }
3950
3951                 sandybridge_pcode_write(dev_priv,
3952                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3953                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3954                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3955                                         gpu_freq);
3956         }
3957 }
3958
3959 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3960 {
3961         u32 val, rp0;
3962
3963         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3964
3965         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3966         /* Clamp to max */
3967         rp0 = min_t(u32, rp0, 0xea);
3968
3969         return rp0;
3970 }
3971
3972 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3973 {
3974         u32 val, rpe;
3975
3976         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3977         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3978         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3979         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3980
3981         return rpe;
3982 }
3983
3984 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3985 {
3986         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3987 }
3988
3989 static void valleyview_setup_pctx(struct drm_device *dev)
3990 {
3991         struct drm_i915_private *dev_priv = dev->dev_private;
3992         struct drm_i915_gem_object *pctx;
3993         unsigned long pctx_paddr;
3994         u32 pcbr;
3995         int pctx_size = 24*1024;
3996
3997         pcbr = I915_READ(VLV_PCBR);
3998         if (pcbr) {
3999                 /* BIOS set it up already, grab the pre-alloc'd space */
4000                 int pcbr_offset;
4001
4002                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4003                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4004                                                                       pcbr_offset,
4005                                                                       I915_GTT_OFFSET_NONE,
4006                                                                       pctx_size);
4007                 goto out;
4008         }
4009
4010         /*
4011          * From the Gunit register HAS:
4012          * The Gfx driver is expected to program this register and ensure
4013          * proper allocation within Gfx stolen memory.  For example, this
4014          * register should be programmed such than the PCBR range does not
4015          * overlap with other ranges, such as the frame buffer, protected
4016          * memory, or any other relevant ranges.
4017          */
4018         pctx = i915_gem_object_create_stolen(dev, pctx_size);
4019         if (!pctx) {
4020                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4021                 return;
4022         }
4023
4024         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4025         I915_WRITE(VLV_PCBR, pctx_paddr);
4026
4027 out:
4028         dev_priv->vlv_pctx = pctx;
4029 }
4030
4031 static void valleyview_enable_rps(struct drm_device *dev)
4032 {
4033         struct drm_i915_private *dev_priv = dev->dev_private;
4034         struct intel_ring_buffer *ring;
4035         u32 gtfifodbg, val, rc6_mode = 0;
4036         int i;
4037
4038         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4039
4040         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4041                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4042                                  gtfifodbg);
4043                 I915_WRITE(GTFIFODBG, gtfifodbg);
4044         }
4045
4046         valleyview_setup_pctx(dev);
4047
4048         gen6_gt_force_wake_get(dev_priv);
4049
4050         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4051         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4052         I915_WRITE(GEN6_RP_UP_EI, 66000);
4053         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4054
4055         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4056
4057         I915_WRITE(GEN6_RP_CONTROL,
4058                    GEN6_RP_MEDIA_TURBO |
4059                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4060                    GEN6_RP_MEDIA_IS_GFX |
4061                    GEN6_RP_ENABLE |
4062                    GEN6_RP_UP_BUSY_AVG |
4063                    GEN6_RP_DOWN_IDLE_CONT);
4064
4065         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4066         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4067         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4068
4069         for_each_ring(ring, dev_priv, i)
4070                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4071
4072         I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
4073
4074         /* allows RC6 residency counter to work */
4075         I915_WRITE(VLV_COUNTER_CONTROL,
4076                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4077                                       VLV_MEDIA_RC6_COUNT_EN |
4078                                       VLV_RENDER_RC6_COUNT_EN));
4079         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4080                 rc6_mode = GEN7_RC_CTL_TO_MODE;
4081
4082         intel_print_rc6_info(dev, rc6_mode);
4083
4084         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4085
4086         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4087         switch ((val >> 6) & 3) {
4088         case 0:
4089         case 1:
4090                 dev_priv->mem_freq = 800;
4091                 break;
4092         case 2:
4093                 dev_priv->mem_freq = 1066;
4094                 break;
4095         case 3:
4096                 dev_priv->mem_freq = 1333;
4097                 break;
4098         }
4099         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4100
4101         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4102         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4103
4104         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
4105         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4106                          vlv_gpu_freq(dev_priv->mem_freq,
4107                                       dev_priv->rps.cur_delay),
4108                          dev_priv->rps.cur_delay);
4109
4110         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4111         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
4112         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4113                          vlv_gpu_freq(dev_priv->mem_freq,
4114                                       dev_priv->rps.max_delay),
4115                          dev_priv->rps.max_delay);
4116
4117         dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4118         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4119                          vlv_gpu_freq(dev_priv->mem_freq,
4120                                       dev_priv->rps.rpe_delay),
4121                          dev_priv->rps.rpe_delay);
4122
4123         dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4124         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4125                          vlv_gpu_freq(dev_priv->mem_freq,
4126                                       dev_priv->rps.min_delay),
4127                          dev_priv->rps.min_delay);
4128
4129         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4130                          vlv_gpu_freq(dev_priv->mem_freq,
4131                                       dev_priv->rps.rpe_delay),
4132                          dev_priv->rps.rpe_delay);
4133
4134         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4135
4136         gen6_enable_rps_interrupts(dev);
4137
4138         gen6_gt_force_wake_put(dev_priv);
4139 }
4140
4141 void ironlake_teardown_rc6(struct drm_device *dev)
4142 {
4143         struct drm_i915_private *dev_priv = dev->dev_private;
4144
4145         if (dev_priv->ips.renderctx) {
4146                 i915_gem_object_unpin(dev_priv->ips.renderctx);
4147                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4148                 dev_priv->ips.renderctx = NULL;
4149         }
4150
4151         if (dev_priv->ips.pwrctx) {
4152                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4153                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4154                 dev_priv->ips.pwrctx = NULL;
4155         }
4156 }
4157
4158 static void ironlake_disable_rc6(struct drm_device *dev)
4159 {
4160         struct drm_i915_private *dev_priv = dev->dev_private;
4161
4162         if (I915_READ(PWRCTXA)) {
4163                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4164                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4165                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4166                          50);
4167
4168                 I915_WRITE(PWRCTXA, 0);
4169                 POSTING_READ(PWRCTXA);
4170
4171                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4172                 POSTING_READ(RSTDBYCTL);
4173         }
4174 }
4175
4176 static int ironlake_setup_rc6(struct drm_device *dev)
4177 {
4178         struct drm_i915_private *dev_priv = dev->dev_private;
4179
4180         if (dev_priv->ips.renderctx == NULL)
4181                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4182         if (!dev_priv->ips.renderctx)
4183                 return -ENOMEM;
4184
4185         if (dev_priv->ips.pwrctx == NULL)
4186                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4187         if (!dev_priv->ips.pwrctx) {
4188                 ironlake_teardown_rc6(dev);
4189                 return -ENOMEM;
4190         }
4191
4192         return 0;
4193 }
4194
4195 static void ironlake_enable_rc6(struct drm_device *dev)
4196 {
4197         struct drm_i915_private *dev_priv = dev->dev_private;
4198         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4199         bool was_interruptible;
4200         int ret;
4201
4202         /* rc6 disabled by default due to repeated reports of hanging during
4203          * boot and resume.
4204          */
4205         if (!intel_enable_rc6(dev))
4206                 return;
4207
4208         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4209
4210         ret = ironlake_setup_rc6(dev);
4211         if (ret)
4212                 return;
4213
4214         was_interruptible = dev_priv->mm.interruptible;
4215         dev_priv->mm.interruptible = false;
4216
4217         /*
4218          * GPU can automatically power down the render unit if given a page
4219          * to save state.
4220          */
4221         ret = intel_ring_begin(ring, 6);
4222         if (ret) {
4223                 ironlake_teardown_rc6(dev);
4224                 dev_priv->mm.interruptible = was_interruptible;
4225                 return;
4226         }
4227
4228         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4229         intel_ring_emit(ring, MI_SET_CONTEXT);
4230         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4231                         MI_MM_SPACE_GTT |
4232                         MI_SAVE_EXT_STATE_EN |
4233                         MI_RESTORE_EXT_STATE_EN |
4234                         MI_RESTORE_INHIBIT);
4235         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4236         intel_ring_emit(ring, MI_NOOP);
4237         intel_ring_emit(ring, MI_FLUSH);
4238         intel_ring_advance(ring);
4239
4240         /*
4241          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4242          * does an implicit flush, combined with MI_FLUSH above, it should be
4243          * safe to assume that renderctx is valid
4244          */
4245         ret = intel_ring_idle(ring);
4246         dev_priv->mm.interruptible = was_interruptible;
4247         if (ret) {
4248                 DRM_ERROR("failed to enable ironlake power savings\n");
4249                 ironlake_teardown_rc6(dev);
4250                 return;
4251         }
4252
4253         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4254         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4255
4256         intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
4257 }
4258
4259 static unsigned long intel_pxfreq(u32 vidfreq)
4260 {
4261         unsigned long freq;
4262         int div = (vidfreq & 0x3f0000) >> 16;
4263         int post = (vidfreq & 0x3000) >> 12;
4264         int pre = (vidfreq & 0x7);
4265
4266         if (!pre)
4267                 return 0;
4268
4269         freq = ((div * 133333) / ((1<<post) * pre));
4270
4271         return freq;
4272 }
4273
4274 static const struct cparams {
4275         u16 i;
4276         u16 t;
4277         u16 m;
4278         u16 c;
4279 } cparams[] = {
4280         { 1, 1333, 301, 28664 },
4281         { 1, 1066, 294, 24460 },
4282         { 1, 800, 294, 25192 },
4283         { 0, 1333, 276, 27605 },
4284         { 0, 1066, 276, 27605 },
4285         { 0, 800, 231, 23784 },
4286 };
4287
4288 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4289 {
4290         u64 total_count, diff, ret;
4291         u32 count1, count2, count3, m = 0, c = 0;
4292         unsigned long now = jiffies_to_msecs(jiffies), diff1;
4293         int i;
4294
4295         assert_spin_locked(&mchdev_lock);
4296
4297         diff1 = now - dev_priv->ips.last_time1;
4298
4299         /* Prevent division-by-zero if we are asking too fast.
4300          * Also, we don't get interesting results if we are polling
4301          * faster than once in 10ms, so just return the saved value
4302          * in such cases.
4303          */
4304         if (diff1 <= 10)
4305                 return dev_priv->ips.chipset_power;
4306
4307         count1 = I915_READ(DMIEC);
4308         count2 = I915_READ(DDREC);
4309         count3 = I915_READ(CSIEC);
4310
4311         total_count = count1 + count2 + count3;
4312
4313         /* FIXME: handle per-counter overflow */
4314         if (total_count < dev_priv->ips.last_count1) {
4315                 diff = ~0UL - dev_priv->ips.last_count1;
4316                 diff += total_count;
4317         } else {
4318                 diff = total_count - dev_priv->ips.last_count1;
4319         }
4320
4321         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4322                 if (cparams[i].i == dev_priv->ips.c_m &&
4323                     cparams[i].t == dev_priv->ips.r_t) {
4324                         m = cparams[i].m;
4325                         c = cparams[i].c;
4326                         break;
4327                 }
4328         }
4329
4330         diff = div_u64(diff, diff1);
4331         ret = ((m * diff) + c);
4332         ret = div_u64(ret, 10);
4333
4334         dev_priv->ips.last_count1 = total_count;
4335         dev_priv->ips.last_time1 = now;
4336
4337         dev_priv->ips.chipset_power = ret;
4338
4339         return ret;
4340 }
4341
4342 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4343 {
4344         unsigned long val;
4345
4346         if (dev_priv->info->gen != 5)
4347                 return 0;
4348
4349         spin_lock_irq(&mchdev_lock);
4350
4351         val = __i915_chipset_val(dev_priv);
4352
4353         spin_unlock_irq(&mchdev_lock);
4354
4355         return val;
4356 }
4357
4358 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4359 {
4360         unsigned long m, x, b;
4361         u32 tsfs;
4362
4363         tsfs = I915_READ(TSFS);
4364
4365         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4366         x = I915_READ8(TR1);
4367
4368         b = tsfs & TSFS_INTR_MASK;
4369
4370         return ((m * x) / 127) - b;
4371 }
4372
4373 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4374 {
4375         static const struct v_table {
4376                 u16 vd; /* in .1 mil */
4377                 u16 vm; /* in .1 mil */
4378         } v_table[] = {
4379                 { 0, 0, },
4380                 { 375, 0, },
4381                 { 500, 0, },
4382                 { 625, 0, },
4383                 { 750, 0, },
4384                 { 875, 0, },
4385                 { 1000, 0, },
4386                 { 1125, 0, },
4387                 { 4125, 3000, },
4388                 { 4125, 3000, },
4389                 { 4125, 3000, },
4390                 { 4125, 3000, },
4391                 { 4125, 3000, },
4392                 { 4125, 3000, },
4393                 { 4125, 3000, },
4394                 { 4125, 3000, },
4395                 { 4125, 3000, },
4396                 { 4125, 3000, },
4397                 { 4125, 3000, },
4398                 { 4125, 3000, },
4399                 { 4125, 3000, },
4400                 { 4125, 3000, },
4401                 { 4125, 3000, },
4402                 { 4125, 3000, },
4403                 { 4125, 3000, },
4404                 { 4125, 3000, },
4405                 { 4125, 3000, },
4406                 { 4125, 3000, },
4407                 { 4125, 3000, },
4408                 { 4125, 3000, },
4409                 { 4125, 3000, },
4410                 { 4125, 3000, },
4411                 { 4250, 3125, },
4412                 { 4375, 3250, },
4413                 { 4500, 3375, },
4414                 { 4625, 3500, },
4415                 { 4750, 3625, },
4416                 { 4875, 3750, },
4417                 { 5000, 3875, },
4418                 { 5125, 4000, },
4419                 { 5250, 4125, },
4420                 { 5375, 4250, },
4421                 { 5500, 4375, },
4422                 { 5625, 4500, },
4423                 { 5750, 4625, },
4424                 { 5875, 4750, },
4425                 { 6000, 4875, },
4426                 { 6125, 5000, },
4427                 { 6250, 5125, },
4428                 { 6375, 5250, },
4429                 { 6500, 5375, },
4430                 { 6625, 5500, },
4431                 { 6750, 5625, },
4432                 { 6875, 5750, },
4433                 { 7000, 5875, },
4434                 { 7125, 6000, },
4435                 { 7250, 6125, },
4436                 { 7375, 6250, },
4437                 { 7500, 6375, },
4438                 { 7625, 6500, },
4439                 { 7750, 6625, },
4440                 { 7875, 6750, },
4441                 { 8000, 6875, },
4442                 { 8125, 7000, },
4443                 { 8250, 7125, },
4444                 { 8375, 7250, },
4445                 { 8500, 7375, },
4446                 { 8625, 7500, },
4447                 { 8750, 7625, },
4448                 { 8875, 7750, },
4449                 { 9000, 7875, },
4450                 { 9125, 8000, },
4451                 { 9250, 8125, },
4452                 { 9375, 8250, },
4453                 { 9500, 8375, },
4454                 { 9625, 8500, },
4455                 { 9750, 8625, },
4456                 { 9875, 8750, },
4457                 { 10000, 8875, },
4458                 { 10125, 9000, },
4459                 { 10250, 9125, },
4460                 { 10375, 9250, },
4461                 { 10500, 9375, },
4462                 { 10625, 9500, },
4463                 { 10750, 9625, },
4464                 { 10875, 9750, },
4465                 { 11000, 9875, },
4466                 { 11125, 10000, },
4467                 { 11250, 10125, },
4468                 { 11375, 10250, },
4469                 { 11500, 10375, },
4470                 { 11625, 10500, },
4471                 { 11750, 10625, },
4472                 { 11875, 10750, },
4473                 { 12000, 10875, },
4474                 { 12125, 11000, },
4475                 { 12250, 11125, },
4476                 { 12375, 11250, },
4477                 { 12500, 11375, },
4478                 { 12625, 11500, },
4479                 { 12750, 11625, },
4480                 { 12875, 11750, },
4481                 { 13000, 11875, },
4482                 { 13125, 12000, },
4483                 { 13250, 12125, },
4484                 { 13375, 12250, },
4485                 { 13500, 12375, },
4486                 { 13625, 12500, },
4487                 { 13750, 12625, },
4488                 { 13875, 12750, },
4489                 { 14000, 12875, },
4490                 { 14125, 13000, },
4491                 { 14250, 13125, },
4492                 { 14375, 13250, },
4493                 { 14500, 13375, },
4494                 { 14625, 13500, },
4495                 { 14750, 13625, },
4496                 { 14875, 13750, },
4497                 { 15000, 13875, },
4498                 { 15125, 14000, },
4499                 { 15250, 14125, },
4500                 { 15375, 14250, },
4501                 { 15500, 14375, },
4502                 { 15625, 14500, },
4503                 { 15750, 14625, },
4504                 { 15875, 14750, },
4505                 { 16000, 14875, },
4506                 { 16125, 15000, },
4507         };
4508         if (dev_priv->info->is_mobile)
4509                 return v_table[pxvid].vm;
4510         else
4511                 return v_table[pxvid].vd;
4512 }
4513
4514 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4515 {
4516         struct timespec now, diff1;
4517         u64 diff;
4518         unsigned long diffms;
4519         u32 count;
4520
4521         assert_spin_locked(&mchdev_lock);
4522
4523         getrawmonotonic(&now);
4524         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4525
4526         /* Don't divide by 0 */
4527         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4528         if (!diffms)
4529                 return;
4530
4531         count = I915_READ(GFXEC);
4532
4533         if (count < dev_priv->ips.last_count2) {
4534                 diff = ~0UL - dev_priv->ips.last_count2;
4535                 diff += count;
4536         } else {
4537                 diff = count - dev_priv->ips.last_count2;
4538         }
4539
4540         dev_priv->ips.last_count2 = count;
4541         dev_priv->ips.last_time2 = now;
4542
4543         /* More magic constants... */
4544         diff = diff * 1181;
4545         diff = div_u64(diff, diffms * 10);
4546         dev_priv->ips.gfx_power = diff;
4547 }
4548
4549 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4550 {
4551         if (dev_priv->info->gen != 5)
4552                 return;
4553
4554         spin_lock_irq(&mchdev_lock);
4555
4556         __i915_update_gfx_val(dev_priv);
4557
4558         spin_unlock_irq(&mchdev_lock);
4559 }
4560
4561 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4562 {
4563         unsigned long t, corr, state1, corr2, state2;
4564         u32 pxvid, ext_v;
4565
4566         assert_spin_locked(&mchdev_lock);
4567
4568         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4569         pxvid = (pxvid >> 24) & 0x7f;
4570         ext_v = pvid_to_extvid(dev_priv, pxvid);
4571
4572         state1 = ext_v;
4573
4574         t = i915_mch_val(dev_priv);
4575
4576         /* Revel in the empirically derived constants */
4577
4578         /* Correction factor in 1/100000 units */
4579         if (t > 80)
4580                 corr = ((t * 2349) + 135940);
4581         else if (t >= 50)
4582                 corr = ((t * 964) + 29317);
4583         else /* < 50 */
4584                 corr = ((t * 301) + 1004);
4585
4586         corr = corr * ((150142 * state1) / 10000 - 78642);
4587         corr /= 100000;
4588         corr2 = (corr * dev_priv->ips.corr);
4589
4590         state2 = (corr2 * state1) / 10000;
4591         state2 /= 100; /* convert to mW */
4592
4593         __i915_update_gfx_val(dev_priv);
4594
4595         return dev_priv->ips.gfx_power + state2;
4596 }
4597
4598 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4599 {
4600         unsigned long val;
4601
4602         if (dev_priv->info->gen != 5)
4603                 return 0;
4604
4605         spin_lock_irq(&mchdev_lock);
4606
4607         val = __i915_gfx_val(dev_priv);
4608
4609         spin_unlock_irq(&mchdev_lock);
4610
4611         return val;
4612 }
4613
4614 /**
4615  * i915_read_mch_val - return value for IPS use
4616  *
4617  * Calculate and return a value for the IPS driver to use when deciding whether
4618  * we have thermal and power headroom to increase CPU or GPU power budget.
4619  */
4620 unsigned long i915_read_mch_val(void)
4621 {
4622         struct drm_i915_private *dev_priv;
4623         unsigned long chipset_val, graphics_val, ret = 0;
4624
4625         spin_lock_irq(&mchdev_lock);
4626         if (!i915_mch_dev)
4627                 goto out_unlock;
4628         dev_priv = i915_mch_dev;
4629
4630         chipset_val = __i915_chipset_val(dev_priv);
4631         graphics_val = __i915_gfx_val(dev_priv);
4632
4633         ret = chipset_val + graphics_val;
4634
4635 out_unlock:
4636         spin_unlock_irq(&mchdev_lock);
4637
4638         return ret;
4639 }
4640 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4641
4642 /**
4643  * i915_gpu_raise - raise GPU frequency limit
4644  *
4645  * Raise the limit; IPS indicates we have thermal headroom.
4646  */
4647 bool i915_gpu_raise(void)
4648 {
4649         struct drm_i915_private *dev_priv;
4650         bool ret = true;
4651
4652         spin_lock_irq(&mchdev_lock);
4653         if (!i915_mch_dev) {
4654                 ret = false;
4655                 goto out_unlock;
4656         }
4657         dev_priv = i915_mch_dev;
4658
4659         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4660                 dev_priv->ips.max_delay--;
4661
4662 out_unlock:
4663         spin_unlock_irq(&mchdev_lock);
4664
4665         return ret;
4666 }
4667 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4668
4669 /**
4670  * i915_gpu_lower - lower GPU frequency limit
4671  *
4672  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4673  * frequency maximum.
4674  */
4675 bool i915_gpu_lower(void)
4676 {
4677         struct drm_i915_private *dev_priv;
4678         bool ret = true;
4679
4680         spin_lock_irq(&mchdev_lock);
4681         if (!i915_mch_dev) {
4682                 ret = false;
4683                 goto out_unlock;
4684         }
4685         dev_priv = i915_mch_dev;
4686
4687         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4688                 dev_priv->ips.max_delay++;
4689
4690 out_unlock:
4691         spin_unlock_irq(&mchdev_lock);
4692
4693         return ret;
4694 }
4695 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4696
4697 /**
4698  * i915_gpu_busy - indicate GPU business to IPS
4699  *
4700  * Tell the IPS driver whether or not the GPU is busy.
4701  */
4702 bool i915_gpu_busy(void)
4703 {
4704         struct drm_i915_private *dev_priv;
4705         struct intel_ring_buffer *ring;
4706         bool ret = false;
4707         int i;
4708
4709         spin_lock_irq(&mchdev_lock);
4710         if (!i915_mch_dev)
4711                 goto out_unlock;
4712         dev_priv = i915_mch_dev;
4713
4714         for_each_ring(ring, dev_priv, i)
4715                 ret |= !list_empty(&ring->request_list);
4716
4717 out_unlock:
4718         spin_unlock_irq(&mchdev_lock);
4719
4720         return ret;
4721 }
4722 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4723
4724 /**
4725  * i915_gpu_turbo_disable - disable graphics turbo
4726  *
4727  * Disable graphics turbo by resetting the max frequency and setting the
4728  * current frequency to the default.
4729  */
4730 bool i915_gpu_turbo_disable(void)
4731 {
4732         struct drm_i915_private *dev_priv;
4733         bool ret = true;
4734
4735         spin_lock_irq(&mchdev_lock);
4736         if (!i915_mch_dev) {
4737                 ret = false;
4738                 goto out_unlock;
4739         }
4740         dev_priv = i915_mch_dev;
4741
4742         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4743
4744         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4745                 ret = false;
4746
4747 out_unlock:
4748         spin_unlock_irq(&mchdev_lock);
4749
4750         return ret;
4751 }
4752 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4753
4754 /**
4755  * Tells the intel_ips driver that the i915 driver is now loaded, if
4756  * IPS got loaded first.
4757  *
4758  * This awkward dance is so that neither module has to depend on the
4759  * other in order for IPS to do the appropriate communication of
4760  * GPU turbo limits to i915.
4761  */
4762 static void
4763 ips_ping_for_i915_load(void)
4764 {
4765         void (*link)(void);
4766
4767         link = symbol_get(ips_link_to_i915_driver);
4768         if (link) {
4769                 link();
4770                 symbol_put(ips_link_to_i915_driver);
4771         }
4772 }
4773
4774 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4775 {
4776         /* We only register the i915 ips part with intel-ips once everything is
4777          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4778         spin_lock_irq(&mchdev_lock);
4779         i915_mch_dev = dev_priv;
4780         spin_unlock_irq(&mchdev_lock);
4781
4782         ips_ping_for_i915_load();
4783 }
4784
4785 void intel_gpu_ips_teardown(void)
4786 {
4787         spin_lock_irq(&mchdev_lock);
4788         i915_mch_dev = NULL;
4789         spin_unlock_irq(&mchdev_lock);
4790 }
4791 static void intel_init_emon(struct drm_device *dev)
4792 {
4793         struct drm_i915_private *dev_priv = dev->dev_private;
4794         u32 lcfuse;
4795         u8 pxw[16];
4796         int i;
4797
4798         /* Disable to program */
4799         I915_WRITE(ECR, 0);
4800         POSTING_READ(ECR);
4801
4802         /* Program energy weights for various events */
4803         I915_WRITE(SDEW, 0x15040d00);
4804         I915_WRITE(CSIEW0, 0x007f0000);
4805         I915_WRITE(CSIEW1, 0x1e220004);
4806         I915_WRITE(CSIEW2, 0x04000004);
4807
4808         for (i = 0; i < 5; i++)
4809                 I915_WRITE(PEW + (i * 4), 0);
4810         for (i = 0; i < 3; i++)
4811                 I915_WRITE(DEW + (i * 4), 0);
4812
4813         /* Program P-state weights to account for frequency power adjustment */
4814         for (i = 0; i < 16; i++) {
4815                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4816                 unsigned long freq = intel_pxfreq(pxvidfreq);
4817                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4818                         PXVFREQ_PX_SHIFT;
4819                 unsigned long val;
4820
4821                 val = vid * vid;
4822                 val *= (freq / 1000);
4823                 val *= 255;
4824                 val /= (127*127*900);
4825                 if (val > 0xff)
4826                         DRM_ERROR("bad pxval: %ld\n", val);
4827                 pxw[i] = val;
4828         }
4829         /* Render standby states get 0 weight */
4830         pxw[14] = 0;
4831         pxw[15] = 0;
4832
4833         for (i = 0; i < 4; i++) {
4834                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4835                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4836                 I915_WRITE(PXW + (i * 4), val);
4837         }
4838
4839         /* Adjust magic regs to magic values (more experimental results) */
4840         I915_WRITE(OGW0, 0);
4841         I915_WRITE(OGW1, 0);
4842         I915_WRITE(EG0, 0x00007f00);
4843         I915_WRITE(EG1, 0x0000000e);
4844         I915_WRITE(EG2, 0x000e0000);
4845         I915_WRITE(EG3, 0x68000300);
4846         I915_WRITE(EG4, 0x42000000);
4847         I915_WRITE(EG5, 0x00140031);
4848         I915_WRITE(EG6, 0);
4849         I915_WRITE(EG7, 0);
4850
4851         for (i = 0; i < 8; i++)
4852                 I915_WRITE(PXWL + (i * 4), 0);
4853
4854         /* Enable PMON + select events */
4855         I915_WRITE(ECR, 0x80000019);
4856
4857         lcfuse = I915_READ(LCFUSE02);
4858
4859         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4860 }
4861
4862 void intel_disable_gt_powersave(struct drm_device *dev)
4863 {
4864         struct drm_i915_private *dev_priv = dev->dev_private;
4865
4866         /* Interrupts should be disabled already to avoid re-arming. */
4867         WARN_ON(dev->irq_enabled);
4868
4869         if (IS_IRONLAKE_M(dev)) {
4870                 ironlake_disable_drps(dev);
4871                 ironlake_disable_rc6(dev);
4872         } else if (INTEL_INFO(dev)->gen >= 6) {
4873                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4874                 cancel_work_sync(&dev_priv->rps.work);
4875                 mutex_lock(&dev_priv->rps.hw_lock);
4876                 if (IS_VALLEYVIEW(dev))
4877                         valleyview_disable_rps(dev);
4878                 else
4879                         gen6_disable_rps(dev);
4880                 dev_priv->rps.enabled = false;
4881                 mutex_unlock(&dev_priv->rps.hw_lock);
4882         }
4883 }
4884
4885 static void intel_gen6_powersave_work(struct work_struct *work)
4886 {
4887         struct drm_i915_private *dev_priv =
4888                 container_of(work, struct drm_i915_private,
4889                              rps.delayed_resume_work.work);
4890         struct drm_device *dev = dev_priv->dev;
4891
4892         mutex_lock(&dev_priv->rps.hw_lock);
4893
4894         if (IS_VALLEYVIEW(dev)) {
4895                 valleyview_enable_rps(dev);
4896         } else {
4897                 gen6_enable_rps(dev);
4898                 gen6_update_ring_freq(dev);
4899         }
4900         dev_priv->rps.enabled = true;
4901         mutex_unlock(&dev_priv->rps.hw_lock);
4902 }
4903
4904 void intel_enable_gt_powersave(struct drm_device *dev)
4905 {
4906         struct drm_i915_private *dev_priv = dev->dev_private;
4907
4908         if (IS_IRONLAKE_M(dev)) {
4909                 ironlake_enable_drps(dev);
4910                 ironlake_enable_rc6(dev);
4911                 intel_init_emon(dev);
4912         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4913                 /*
4914                  * PCU communication is slow and this doesn't need to be
4915                  * done at any specific time, so do this out of our fast path
4916                  * to make resume and init faster.
4917                  */
4918                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4919                                       round_jiffies_up_relative(HZ));
4920         }
4921 }
4922
4923 static void ibx_init_clock_gating(struct drm_device *dev)
4924 {
4925         struct drm_i915_private *dev_priv = dev->dev_private;
4926
4927         /*
4928          * On Ibex Peak and Cougar Point, we need to disable clock
4929          * gating for the panel power sequencer or it will fail to
4930          * start up when no ports are active.
4931          */
4932         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4933 }
4934
4935 static void g4x_disable_trickle_feed(struct drm_device *dev)
4936 {
4937         struct drm_i915_private *dev_priv = dev->dev_private;
4938         int pipe;
4939
4940         for_each_pipe(pipe) {
4941                 I915_WRITE(DSPCNTR(pipe),
4942                            I915_READ(DSPCNTR(pipe)) |
4943                            DISPPLANE_TRICKLE_FEED_DISABLE);
4944                 intel_flush_primary_plane(dev_priv, pipe);
4945         }
4946 }
4947
4948 static void ironlake_init_clock_gating(struct drm_device *dev)
4949 {
4950         struct drm_i915_private *dev_priv = dev->dev_private;
4951         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4952
4953         /*
4954          * Required for FBC
4955          * WaFbcDisableDpfcClockGating:ilk
4956          */
4957         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4958                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4959                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4960
4961         I915_WRITE(PCH_3DCGDIS0,
4962                    MARIUNIT_CLOCK_GATE_DISABLE |
4963                    SVSMUNIT_CLOCK_GATE_DISABLE);
4964         I915_WRITE(PCH_3DCGDIS1,
4965                    VFMUNIT_CLOCK_GATE_DISABLE);
4966
4967         /*
4968          * According to the spec the following bits should be set in
4969          * order to enable memory self-refresh
4970          * The bit 22/21 of 0x42004
4971          * The bit 5 of 0x42020
4972          * The bit 15 of 0x45000
4973          */
4974         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4975                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4976                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4977         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4978         I915_WRITE(DISP_ARB_CTL,
4979                    (I915_READ(DISP_ARB_CTL) |
4980                     DISP_FBC_WM_DIS));
4981         I915_WRITE(WM3_LP_ILK, 0);
4982         I915_WRITE(WM2_LP_ILK, 0);
4983         I915_WRITE(WM1_LP_ILK, 0);
4984
4985         /*
4986          * Based on the document from hardware guys the following bits
4987          * should be set unconditionally in order to enable FBC.
4988          * The bit 22 of 0x42000
4989          * The bit 22 of 0x42004
4990          * The bit 7,8,9 of 0x42020.
4991          */
4992         if (IS_IRONLAKE_M(dev)) {
4993                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4994                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4995                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4996                            ILK_FBCQ_DIS);
4997                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4998                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4999                            ILK_DPARB_GATE);
5000         }
5001
5002         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5003
5004         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5005                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5006                    ILK_ELPIN_409_SELECT);
5007         I915_WRITE(_3D_CHICKEN2,
5008                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5009                    _3D_CHICKEN2_WM_READ_PIPELINED);
5010
5011         /* WaDisableRenderCachePipelinedFlush:ilk */
5012         I915_WRITE(CACHE_MODE_0,
5013                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5014
5015         g4x_disable_trickle_feed(dev);
5016
5017         ibx_init_clock_gating(dev);
5018 }
5019
5020 static void cpt_init_clock_gating(struct drm_device *dev)
5021 {
5022         struct drm_i915_private *dev_priv = dev->dev_private;
5023         int pipe;
5024         uint32_t val;
5025
5026         /*
5027          * On Ibex Peak and Cougar Point, we need to disable clock
5028          * gating for the panel power sequencer or it will fail to
5029          * start up when no ports are active.
5030          */
5031         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5032                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5033                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
5034         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5035                    DPLS_EDP_PPS_FIX_DIS);
5036         /* The below fixes the weird display corruption, a few pixels shifted
5037          * downward, on (only) LVDS of some HP laptops with IVY.
5038          */
5039         for_each_pipe(pipe) {
5040                 val = I915_READ(TRANS_CHICKEN2(pipe));
5041                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5042                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5043                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5044                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5045                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5046                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5047                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5048                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5049         }
5050         /* WADP0ClockGatingDisable */
5051         for_each_pipe(pipe) {
5052                 I915_WRITE(TRANS_CHICKEN1(pipe),
5053                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5054         }
5055 }
5056
5057 static void gen6_check_mch_setup(struct drm_device *dev)
5058 {
5059         struct drm_i915_private *dev_priv = dev->dev_private;
5060         uint32_t tmp;
5061
5062         tmp = I915_READ(MCH_SSKPD);
5063         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5064                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5065                 DRM_INFO("This can cause pipe underruns and display issues.\n");
5066                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5067         }
5068 }
5069
5070 static void gen6_init_clock_gating(struct drm_device *dev)
5071 {
5072         struct drm_i915_private *dev_priv = dev->dev_private;
5073         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5074
5075         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5076
5077         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5078                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5079                    ILK_ELPIN_409_SELECT);
5080
5081         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5082         I915_WRITE(_3D_CHICKEN,
5083                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5084
5085         /* WaSetupGtModeTdRowDispatch:snb */
5086         if (IS_SNB_GT1(dev))
5087                 I915_WRITE(GEN6_GT_MODE,
5088                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5089
5090         I915_WRITE(WM3_LP_ILK, 0);
5091         I915_WRITE(WM2_LP_ILK, 0);
5092         I915_WRITE(WM1_LP_ILK, 0);
5093
5094         I915_WRITE(CACHE_MODE_0,
5095                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5096
5097         I915_WRITE(GEN6_UCGCTL1,
5098                    I915_READ(GEN6_UCGCTL1) |
5099                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5100                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5101
5102         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5103          * gating disable must be set.  Failure to set it results in
5104          * flickering pixels due to Z write ordering failures after
5105          * some amount of runtime in the Mesa "fire" demo, and Unigine
5106          * Sanctuary and Tropics, and apparently anything else with
5107          * alpha test or pixel discard.
5108          *
5109          * According to the spec, bit 11 (RCCUNIT) must also be set,
5110          * but we didn't debug actual testcases to find it out.
5111          *
5112          * Also apply WaDisableVDSUnitClockGating:snb and
5113          * WaDisableRCPBUnitClockGating:snb.
5114          */
5115         I915_WRITE(GEN6_UCGCTL2,
5116                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5117                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5118                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5119
5120         /* Bspec says we need to always set all mask bits. */
5121         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5122                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
5123
5124         /*
5125          * According to the spec the following bits should be
5126          * set in order to enable memory self-refresh and fbc:
5127          * The bit21 and bit22 of 0x42000
5128          * The bit21 and bit22 of 0x42004
5129          * The bit5 and bit7 of 0x42020
5130          * The bit14 of 0x70180
5131          * The bit14 of 0x71180
5132          *
5133          * WaFbcAsynchFlipDisableFbcQueue:snb
5134          */
5135         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5136                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5137                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5138         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5139                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5140                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5141         I915_WRITE(ILK_DSPCLK_GATE_D,
5142                    I915_READ(ILK_DSPCLK_GATE_D) |
5143                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
5144                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5145
5146         g4x_disable_trickle_feed(dev);
5147
5148         /* The default value should be 0x200 according to docs, but the two
5149          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5150         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5151         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5152
5153         cpt_init_clock_gating(dev);
5154
5155         gen6_check_mch_setup(dev);
5156 }
5157
5158 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5159 {
5160         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5161
5162         reg &= ~GEN7_FF_SCHED_MASK;
5163         reg |= GEN7_FF_TS_SCHED_HW;
5164         reg |= GEN7_FF_VS_SCHED_HW;
5165         reg |= GEN7_FF_DS_SCHED_HW;
5166
5167         if (IS_HASWELL(dev_priv->dev))
5168                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5169
5170         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5171 }
5172
5173 static void lpt_init_clock_gating(struct drm_device *dev)
5174 {
5175         struct drm_i915_private *dev_priv = dev->dev_private;
5176
5177         /*
5178          * TODO: this bit should only be enabled when really needed, then
5179          * disabled when not needed anymore in order to save power.
5180          */
5181         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5182                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5183                            I915_READ(SOUTH_DSPCLK_GATE_D) |
5184                            PCH_LP_PARTITION_LEVEL_DISABLE);
5185
5186         /* WADPOClockGatingDisable:hsw */
5187         I915_WRITE(_TRANSA_CHICKEN1,
5188                    I915_READ(_TRANSA_CHICKEN1) |
5189                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5190 }
5191
5192 static void lpt_suspend_hw(struct drm_device *dev)
5193 {
5194         struct drm_i915_private *dev_priv = dev->dev_private;
5195
5196         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5197                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5198
5199                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5200                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5201         }
5202 }
5203
5204 static void haswell_init_clock_gating(struct drm_device *dev)
5205 {
5206         struct drm_i915_private *dev_priv = dev->dev_private;
5207
5208         I915_WRITE(WM3_LP_ILK, 0);
5209         I915_WRITE(WM2_LP_ILK, 0);
5210         I915_WRITE(WM1_LP_ILK, 0);
5211
5212         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5213          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5214          */
5215         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5216
5217         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5218         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5219                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5220
5221         /* WaApplyL3ControlAndL3ChickenMode:hsw */
5222         I915_WRITE(GEN7_L3CNTLREG1,
5223                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5224         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5225                         GEN7_WA_L3_CHICKEN_MODE);
5226
5227         /* L3 caching of data atomics doesn't work -- disable it. */
5228         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5229         I915_WRITE(HSW_ROW_CHICKEN3,
5230                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5231
5232         /* This is required by WaCatErrorRejectionIssue:hsw */
5233         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5234                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5235                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5236
5237         /* WaVSRefCountFullforceMissDisable:hsw */
5238         gen7_setup_fixed_func_scheduler(dev_priv);
5239
5240         /* WaDisable4x2SubspanOptimization:hsw */
5241         I915_WRITE(CACHE_MODE_1,
5242                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5243
5244         /* WaSwitchSolVfFArbitrationPriority:hsw */
5245         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5246
5247         /* WaRsPkgCStateDisplayPMReq:hsw */
5248         I915_WRITE(CHICKEN_PAR1_1,
5249                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5250
5251         lpt_init_clock_gating(dev);
5252 }
5253
5254 static void ivybridge_init_clock_gating(struct drm_device *dev)
5255 {
5256         struct drm_i915_private *dev_priv = dev->dev_private;
5257         uint32_t snpcr;
5258
5259         I915_WRITE(WM3_LP_ILK, 0);
5260         I915_WRITE(WM2_LP_ILK, 0);
5261         I915_WRITE(WM1_LP_ILK, 0);
5262
5263         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5264
5265         /* WaDisableEarlyCull:ivb */
5266         I915_WRITE(_3D_CHICKEN3,
5267                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5268
5269         /* WaDisableBackToBackFlipFix:ivb */
5270         I915_WRITE(IVB_CHICKEN3,
5271                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5272                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5273
5274         /* WaDisablePSDDualDispatchEnable:ivb */
5275         if (IS_IVB_GT1(dev))
5276                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5277                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5278         else
5279                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5280                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5281
5282         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5283         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5284                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5285
5286         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5287         I915_WRITE(GEN7_L3CNTLREG1,
5288                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5289         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5290                    GEN7_WA_L3_CHICKEN_MODE);
5291         if (IS_IVB_GT1(dev))
5292                 I915_WRITE(GEN7_ROW_CHICKEN2,
5293                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5294         else
5295                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5296                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5297
5298
5299         /* WaForceL3Serialization:ivb */
5300         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5301                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5302
5303         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5304          * gating disable must be set.  Failure to set it results in
5305          * flickering pixels due to Z write ordering failures after
5306          * some amount of runtime in the Mesa "fire" demo, and Unigine
5307          * Sanctuary and Tropics, and apparently anything else with
5308          * alpha test or pixel discard.
5309          *
5310          * According to the spec, bit 11 (RCCUNIT) must also be set,
5311          * but we didn't debug actual testcases to find it out.
5312          *
5313          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5314          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5315          */
5316         I915_WRITE(GEN6_UCGCTL2,
5317                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5318                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5319
5320         /* This is required by WaCatErrorRejectionIssue:ivb */
5321         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5322                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5323                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5324
5325         g4x_disable_trickle_feed(dev);
5326
5327         /* WaVSRefCountFullforceMissDisable:ivb */
5328         gen7_setup_fixed_func_scheduler(dev_priv);
5329
5330         /* WaDisable4x2SubspanOptimization:ivb */
5331         I915_WRITE(CACHE_MODE_1,
5332                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5333
5334         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5335         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5336         snpcr |= GEN6_MBC_SNPCR_MED;
5337         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5338
5339         if (!HAS_PCH_NOP(dev))
5340                 cpt_init_clock_gating(dev);
5341
5342         gen6_check_mch_setup(dev);
5343 }
5344
5345 static void valleyview_init_clock_gating(struct drm_device *dev)
5346 {
5347         struct drm_i915_private *dev_priv = dev->dev_private;
5348
5349         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5350
5351         /* WaDisableEarlyCull:vlv */
5352         I915_WRITE(_3D_CHICKEN3,
5353                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5354
5355         /* WaDisableBackToBackFlipFix:vlv */
5356         I915_WRITE(IVB_CHICKEN3,
5357                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5358                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5359
5360         /* WaDisablePSDDualDispatchEnable:vlv */
5361         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5362                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5363                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5364
5365         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5366         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5367                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5368
5369         /* WaApplyL3ControlAndL3ChickenMode:vlv */
5370         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5371         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5372
5373         /* WaForceL3Serialization:vlv */
5374         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5375                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5376
5377         /* WaDisableDopClockGating:vlv */
5378         I915_WRITE(GEN7_ROW_CHICKEN2,
5379                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5380
5381         /* This is required by WaCatErrorRejectionIssue:vlv */
5382         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5383                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5384                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5385
5386         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5387          * gating disable must be set.  Failure to set it results in
5388          * flickering pixels due to Z write ordering failures after
5389          * some amount of runtime in the Mesa "fire" demo, and Unigine
5390          * Sanctuary and Tropics, and apparently anything else with
5391          * alpha test or pixel discard.
5392          *
5393          * According to the spec, bit 11 (RCCUNIT) must also be set,
5394          * but we didn't debug actual testcases to find it out.
5395          *
5396          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5397          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5398          *
5399          * Also apply WaDisableVDSUnitClockGating:vlv and
5400          * WaDisableRCPBUnitClockGating:vlv.
5401          */
5402         I915_WRITE(GEN6_UCGCTL2,
5403                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5404                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5405                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5406                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5407                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5408
5409         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5410
5411         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5412
5413         I915_WRITE(CACHE_MODE_1,
5414                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5415
5416         /*
5417          * WaDisableVLVClockGating_VBIIssue:vlv
5418          * Disable clock gating on th GCFG unit to prevent a delay
5419          * in the reporting of vblank events.
5420          */
5421         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5422
5423         /* Conservative clock gating settings for now */
5424         I915_WRITE(0x9400, 0xffffffff);
5425         I915_WRITE(0x9404, 0xffffffff);
5426         I915_WRITE(0x9408, 0xffffffff);
5427         I915_WRITE(0x940c, 0xffffffff);
5428         I915_WRITE(0x9410, 0xffffffff);
5429         I915_WRITE(0x9414, 0xffffffff);
5430         I915_WRITE(0x9418, 0xffffffff);
5431 }
5432
5433 static void g4x_init_clock_gating(struct drm_device *dev)
5434 {
5435         struct drm_i915_private *dev_priv = dev->dev_private;
5436         uint32_t dspclk_gate;
5437
5438         I915_WRITE(RENCLK_GATE_D1, 0);
5439         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5440                    GS_UNIT_CLOCK_GATE_DISABLE |
5441                    CL_UNIT_CLOCK_GATE_DISABLE);
5442         I915_WRITE(RAMCLK_GATE_D, 0);
5443         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5444                 OVRUNIT_CLOCK_GATE_DISABLE |
5445                 OVCUNIT_CLOCK_GATE_DISABLE;
5446         if (IS_GM45(dev))
5447                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5448         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5449
5450         /* WaDisableRenderCachePipelinedFlush */
5451         I915_WRITE(CACHE_MODE_0,
5452                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5453
5454         g4x_disable_trickle_feed(dev);
5455 }
5456
5457 static void crestline_init_clock_gating(struct drm_device *dev)
5458 {
5459         struct drm_i915_private *dev_priv = dev->dev_private;
5460
5461         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5462         I915_WRITE(RENCLK_GATE_D2, 0);
5463         I915_WRITE(DSPCLK_GATE_D, 0);
5464         I915_WRITE(RAMCLK_GATE_D, 0);
5465         I915_WRITE16(DEUC, 0);
5466         I915_WRITE(MI_ARB_STATE,
5467                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5468 }
5469
5470 static void broadwater_init_clock_gating(struct drm_device *dev)
5471 {
5472         struct drm_i915_private *dev_priv = dev->dev_private;
5473
5474         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5475                    I965_RCC_CLOCK_GATE_DISABLE |
5476                    I965_RCPB_CLOCK_GATE_DISABLE |
5477                    I965_ISC_CLOCK_GATE_DISABLE |
5478                    I965_FBC_CLOCK_GATE_DISABLE);
5479         I915_WRITE(RENCLK_GATE_D2, 0);
5480         I915_WRITE(MI_ARB_STATE,
5481                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5482 }
5483
5484 static void gen3_init_clock_gating(struct drm_device *dev)
5485 {
5486         struct drm_i915_private *dev_priv = dev->dev_private;
5487         u32 dstate = I915_READ(D_STATE);
5488
5489         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5490                 DSTATE_DOT_CLOCK_GATING;
5491         I915_WRITE(D_STATE, dstate);
5492
5493         if (IS_PINEVIEW(dev))
5494                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5495
5496         /* IIR "flip pending" means done if this bit is set */
5497         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5498 }
5499
5500 static void i85x_init_clock_gating(struct drm_device *dev)
5501 {
5502         struct drm_i915_private *dev_priv = dev->dev_private;
5503
5504         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5505 }
5506
5507 static void i830_init_clock_gating(struct drm_device *dev)
5508 {
5509         struct drm_i915_private *dev_priv = dev->dev_private;
5510
5511         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5512 }
5513
5514 void intel_init_clock_gating(struct drm_device *dev)
5515 {
5516         struct drm_i915_private *dev_priv = dev->dev_private;
5517
5518         dev_priv->display.init_clock_gating(dev);
5519 }
5520
5521 void intel_suspend_hw(struct drm_device *dev)
5522 {
5523         if (HAS_PCH_LPT(dev))
5524                 lpt_suspend_hw(dev);
5525 }
5526
5527 static bool is_always_on_power_domain(struct drm_device *dev,
5528                                       enum intel_display_power_domain domain)
5529 {
5530         unsigned long always_on_domains;
5531
5532         BUG_ON(BIT(domain) & ~POWER_DOMAIN_MASK);
5533
5534         if (IS_HASWELL(dev)) {
5535                 always_on_domains = HSW_ALWAYS_ON_POWER_DOMAINS;
5536         } else {
5537                 WARN_ON(1);
5538                 return true;
5539         }
5540
5541         return BIT(domain) & always_on_domains;
5542 }
5543
5544 /**
5545  * We should only use the power well if we explicitly asked the hardware to
5546  * enable it, so check if it's enabled and also check if we've requested it to
5547  * be enabled.
5548  */
5549 bool intel_display_power_enabled(struct drm_device *dev,
5550                                  enum intel_display_power_domain domain)
5551 {
5552         struct drm_i915_private *dev_priv = dev->dev_private;
5553
5554         if (!HAS_POWER_WELL(dev))
5555                 return true;
5556
5557         if (is_always_on_power_domain(dev, domain))
5558                 return true;
5559
5560         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5561                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5562 }
5563
5564 static void __intel_set_power_well(struct drm_device *dev, bool enable)
5565 {
5566         struct drm_i915_private *dev_priv = dev->dev_private;
5567         bool is_enabled, enable_requested;
5568         uint32_t tmp;
5569
5570         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5571         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5572         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5573
5574         if (enable) {
5575                 if (!enable_requested)
5576                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5577                                    HSW_PWR_WELL_ENABLE_REQUEST);
5578
5579                 if (!is_enabled) {
5580                         DRM_DEBUG_KMS("Enabling power well\n");
5581                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5582                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5583                                 DRM_ERROR("Timeout enabling power well\n");
5584                 }
5585         } else {
5586                 if (enable_requested) {
5587                         unsigned long irqflags;
5588                         enum pipe p;
5589
5590                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5591                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5592                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5593
5594                         /*
5595                          * After this, the registers on the pipes that are part
5596                          * of the power well will become zero, so we have to
5597                          * adjust our counters according to that.
5598                          *
5599                          * FIXME: Should we do this in general in
5600                          * drm_vblank_post_modeset?
5601                          */
5602                         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5603                         for_each_pipe(p)
5604                                 if (p != PIPE_A)
5605                                         dev->vblank[p].last = 0;
5606                         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5607                 }
5608         }
5609 }
5610
5611 static void __intel_power_well_get(struct i915_power_well *power_well)
5612 {
5613         if (!power_well->count++)
5614                 __intel_set_power_well(power_well->device, true);
5615 }
5616
5617 static void __intel_power_well_put(struct i915_power_well *power_well)
5618 {
5619         WARN_ON(!power_well->count);
5620         if (!--power_well->count)
5621                 __intel_set_power_well(power_well->device, false);
5622 }
5623
5624 void intel_display_power_get(struct drm_device *dev,
5625                              enum intel_display_power_domain domain)
5626 {
5627         struct drm_i915_private *dev_priv = dev->dev_private;
5628         struct i915_power_well *power_well = &dev_priv->power_well;
5629
5630         if (!HAS_POWER_WELL(dev))
5631                 return;
5632
5633         if (is_always_on_power_domain(dev, domain))
5634                 return;
5635
5636         mutex_lock(&power_well->lock);
5637         __intel_power_well_get(power_well);
5638         mutex_unlock(&power_well->lock);
5639 }
5640
5641 void intel_display_power_put(struct drm_device *dev,
5642                              enum intel_display_power_domain domain)
5643 {
5644         struct drm_i915_private *dev_priv = dev->dev_private;
5645         struct i915_power_well *power_well = &dev_priv->power_well;
5646
5647         if (!HAS_POWER_WELL(dev))
5648                 return;
5649
5650         if (is_always_on_power_domain(dev, domain))
5651                 return;
5652
5653         mutex_lock(&power_well->lock);
5654         __intel_power_well_put(power_well);
5655         mutex_unlock(&power_well->lock);
5656 }
5657
5658 static struct i915_power_well *hsw_pwr;
5659
5660 /* Display audio driver power well request */
5661 void i915_request_power_well(void)
5662 {
5663         if (WARN_ON(!hsw_pwr))
5664                 return;
5665
5666         mutex_lock(&hsw_pwr->lock);
5667         __intel_power_well_get(hsw_pwr);
5668         mutex_unlock(&hsw_pwr->lock);
5669 }
5670 EXPORT_SYMBOL_GPL(i915_request_power_well);
5671
5672 /* Display audio driver power well release */
5673 void i915_release_power_well(void)
5674 {
5675         if (WARN_ON(!hsw_pwr))
5676                 return;
5677
5678         mutex_lock(&hsw_pwr->lock);
5679         __intel_power_well_put(hsw_pwr);
5680         mutex_unlock(&hsw_pwr->lock);
5681 }
5682 EXPORT_SYMBOL_GPL(i915_release_power_well);
5683
5684 int i915_init_power_well(struct drm_device *dev)
5685 {
5686         struct drm_i915_private *dev_priv = dev->dev_private;
5687
5688         hsw_pwr = &dev_priv->power_well;
5689
5690         hsw_pwr->device = dev;
5691         mutex_init(&hsw_pwr->lock);
5692         hsw_pwr->count = 0;
5693
5694         return 0;
5695 }
5696
5697 void i915_remove_power_well(struct drm_device *dev)
5698 {
5699         hsw_pwr = NULL;
5700 }
5701
5702 void intel_set_power_well(struct drm_device *dev, bool enable)
5703 {
5704         struct drm_i915_private *dev_priv = dev->dev_private;
5705         struct i915_power_well *power_well = &dev_priv->power_well;
5706
5707         if (!HAS_POWER_WELL(dev))
5708                 return;
5709
5710         if (!i915_disable_power_well && !enable)
5711                 return;
5712
5713         mutex_lock(&power_well->lock);
5714
5715         /*
5716          * This function will only ever contribute one
5717          * to the power well reference count. i915_request
5718          * is what tracks whether we have or have not
5719          * added the one to the reference count.
5720          */
5721         if (power_well->i915_request == enable)
5722                 goto out;
5723
5724         power_well->i915_request = enable;
5725
5726         if (enable)
5727                 __intel_power_well_get(power_well);
5728         else
5729                 __intel_power_well_put(power_well);
5730
5731  out:
5732         mutex_unlock(&power_well->lock);
5733 }
5734
5735 static void intel_resume_power_well(struct drm_device *dev)
5736 {
5737         struct drm_i915_private *dev_priv = dev->dev_private;
5738         struct i915_power_well *power_well = &dev_priv->power_well;
5739
5740         if (!HAS_POWER_WELL(dev))
5741                 return;
5742
5743         mutex_lock(&power_well->lock);
5744         __intel_set_power_well(dev, power_well->count > 0);
5745         mutex_unlock(&power_well->lock);
5746 }
5747
5748 /*
5749  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5750  * when not needed anymore. We have 4 registers that can request the power well
5751  * to be enabled, and it will only be disabled if none of the registers is
5752  * requesting it to be enabled.
5753  */
5754 void intel_init_power_well(struct drm_device *dev)
5755 {
5756         struct drm_i915_private *dev_priv = dev->dev_private;
5757
5758         if (!HAS_POWER_WELL(dev))
5759                 return;
5760
5761         /* For now, we need the power well to be always enabled. */
5762         intel_set_power_well(dev, true);
5763         intel_resume_power_well(dev);
5764
5765         /* We're taking over the BIOS, so clear any requests made by it since
5766          * the driver is in charge now. */
5767         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5768                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5769 }
5770
5771 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5772 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5773 {
5774         hsw_disable_package_c8(dev_priv);
5775 }
5776
5777 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5778 {
5779         hsw_enable_package_c8(dev_priv);
5780 }
5781
5782 /* Set up chip specific power management-related functions */
5783 void intel_init_pm(struct drm_device *dev)
5784 {
5785         struct drm_i915_private *dev_priv = dev->dev_private;
5786
5787         if (I915_HAS_FBC(dev)) {
5788                 if (HAS_PCH_SPLIT(dev)) {
5789                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5790                         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5791                                 dev_priv->display.enable_fbc =
5792                                         gen7_enable_fbc;
5793                         else
5794                                 dev_priv->display.enable_fbc =
5795                                         ironlake_enable_fbc;
5796                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5797                 } else if (IS_GM45(dev)) {
5798                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5799                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5800                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5801                 } else if (IS_CRESTLINE(dev)) {
5802                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5803                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5804                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5805                 }
5806                 /* 855GM needs testing */
5807         }
5808
5809         /* For cxsr */
5810         if (IS_PINEVIEW(dev))
5811                 i915_pineview_get_mem_freq(dev);
5812         else if (IS_GEN5(dev))
5813                 i915_ironlake_get_mem_freq(dev);
5814
5815         /* For FIFO watermark updates */
5816         if (HAS_PCH_SPLIT(dev)) {
5817                 intel_setup_wm_latency(dev);
5818
5819                 if (IS_GEN5(dev)) {
5820                         if (dev_priv->wm.pri_latency[1] &&
5821                             dev_priv->wm.spr_latency[1] &&
5822                             dev_priv->wm.cur_latency[1])
5823                                 dev_priv->display.update_wm = ironlake_update_wm;
5824                         else {
5825                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5826                                               "Disable CxSR\n");
5827                                 dev_priv->display.update_wm = NULL;
5828                         }
5829                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5830                 } else if (IS_GEN6(dev)) {
5831                         if (dev_priv->wm.pri_latency[0] &&
5832                             dev_priv->wm.spr_latency[0] &&
5833                             dev_priv->wm.cur_latency[0]) {
5834                                 dev_priv->display.update_wm = sandybridge_update_wm;
5835                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5836                         } else {
5837                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5838                                               "Disable CxSR\n");
5839                                 dev_priv->display.update_wm = NULL;
5840                         }
5841                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5842                 } else if (IS_IVYBRIDGE(dev)) {
5843                         if (dev_priv->wm.pri_latency[0] &&
5844                             dev_priv->wm.spr_latency[0] &&
5845                             dev_priv->wm.cur_latency[0]) {
5846                                 dev_priv->display.update_wm = ivybridge_update_wm;
5847                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5848                         } else {
5849                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5850                                               "Disable CxSR\n");
5851                                 dev_priv->display.update_wm = NULL;
5852                         }
5853                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5854                 } else if (IS_HASWELL(dev)) {
5855                         if (dev_priv->wm.pri_latency[0] &&
5856                             dev_priv->wm.spr_latency[0] &&
5857                             dev_priv->wm.cur_latency[0]) {
5858                                 dev_priv->display.update_wm = haswell_update_wm;
5859                                 dev_priv->display.update_sprite_wm =
5860                                         haswell_update_sprite_wm;
5861                         } else {
5862                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5863                                               "Disable CxSR\n");
5864                                 dev_priv->display.update_wm = NULL;
5865                         }
5866                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5867                 } else
5868                         dev_priv->display.update_wm = NULL;
5869         } else if (IS_VALLEYVIEW(dev)) {
5870                 dev_priv->display.update_wm = valleyview_update_wm;
5871                 dev_priv->display.init_clock_gating =
5872                         valleyview_init_clock_gating;
5873         } else if (IS_PINEVIEW(dev)) {
5874                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5875                                             dev_priv->is_ddr3,
5876                                             dev_priv->fsb_freq,
5877                                             dev_priv->mem_freq)) {
5878                         DRM_INFO("failed to find known CxSR latency "
5879                                  "(found ddr%s fsb freq %d, mem freq %d), "
5880                                  "disabling CxSR\n",
5881                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
5882                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5883                         /* Disable CxSR and never update its watermark again */
5884                         pineview_disable_cxsr(dev);
5885                         dev_priv->display.update_wm = NULL;
5886                 } else
5887                         dev_priv->display.update_wm = pineview_update_wm;
5888                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5889         } else if (IS_G4X(dev)) {
5890                 dev_priv->display.update_wm = g4x_update_wm;
5891                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5892         } else if (IS_GEN4(dev)) {
5893                 dev_priv->display.update_wm = i965_update_wm;
5894                 if (IS_CRESTLINE(dev))
5895                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5896                 else if (IS_BROADWATER(dev))
5897                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5898         } else if (IS_GEN3(dev)) {
5899                 dev_priv->display.update_wm = i9xx_update_wm;
5900                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5901                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5902         } else if (IS_I865G(dev)) {
5903                 dev_priv->display.update_wm = i830_update_wm;
5904                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5905                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5906         } else if (IS_I85X(dev)) {
5907                 dev_priv->display.update_wm = i9xx_update_wm;
5908                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5909                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5910         } else {
5911                 dev_priv->display.update_wm = i830_update_wm;
5912                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5913                 if (IS_845G(dev))
5914                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5915                 else
5916                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5917         }
5918 }
5919
5920 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5921 {
5922         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5923
5924         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5925                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5926                 return -EAGAIN;
5927         }
5928
5929         I915_WRITE(GEN6_PCODE_DATA, *val);
5930         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5931
5932         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5933                      500)) {
5934                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5935                 return -ETIMEDOUT;
5936         }
5937
5938         *val = I915_READ(GEN6_PCODE_DATA);
5939         I915_WRITE(GEN6_PCODE_DATA, 0);
5940
5941         return 0;
5942 }
5943
5944 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5945 {
5946         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5947
5948         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5949                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5950                 return -EAGAIN;
5951         }
5952
5953         I915_WRITE(GEN6_PCODE_DATA, val);
5954         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5955
5956         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5957                      500)) {
5958                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5959                 return -ETIMEDOUT;
5960         }
5961
5962         I915_WRITE(GEN6_PCODE_DATA, 0);
5963
5964         return 0;
5965 }
5966
5967 int vlv_gpu_freq(int ddr_freq, int val)
5968 {
5969         int mult, base;
5970
5971         switch (ddr_freq) {
5972         case 800:
5973                 mult = 20;
5974                 base = 120;
5975                 break;
5976         case 1066:
5977                 mult = 22;
5978                 base = 133;
5979                 break;
5980         case 1333:
5981                 mult = 21;
5982                 base = 125;
5983                 break;
5984         default:
5985                 return -1;
5986         }
5987
5988         return ((val - 0xbd) * mult) + base;
5989 }
5990
5991 int vlv_freq_opcode(int ddr_freq, int val)
5992 {
5993         int mult, base;
5994
5995         switch (ddr_freq) {
5996         case 800:
5997                 mult = 20;
5998                 base = 120;
5999                 break;
6000         case 1066:
6001                 mult = 22;
6002                 base = 133;
6003                 break;
6004         case 1333:
6005                 mult = 21;
6006                 base = 125;
6007                 break;
6008         default:
6009                 return -1;
6010         }
6011
6012         val /= mult;
6013         val -= base / mult;
6014         val += 0xbd;
6015
6016         if (val > 0xea)
6017                 val = 0xea;
6018
6019         return val;
6020 }
6021
6022 void intel_pm_init(struct drm_device *dev)
6023 {
6024         struct drm_i915_private *dev_priv = dev->dev_private;
6025
6026         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6027                           intel_gen6_powersave_work);
6028 }
6029