2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/interrupt.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_irq.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/spinlock.h>
24 #include <video/mipi_display.h>
29 #define MSM_DSI_VER_MAJOR_V2 0x02
30 #define MSM_DSI_VER_MAJOR_6G 0x03
31 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000
32 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000
33 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001
34 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000
35 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
37 #define DSI_6G_REG_SHIFT 4
39 #define DSI_REGULATOR_MAX 8
40 struct dsi_reg_entry {
48 struct dsi_reg_config {
50 struct dsi_reg_entry regs[DSI_REGULATOR_MAX];
57 enum msm_dsi_phy_type phy_type;
58 struct dsi_reg_config reg_cfg;
61 static const struct dsi_config dsi_cfgs[] = {
62 {MSM_DSI_VER_MAJOR_V2, 0, 0, MSM_DSI_PHY_UNKNOWN},
64 .major = MSM_DSI_VER_MAJOR_6G,
65 .minor = MSM_DSI_6G_VER_MINOR_V1_0,
66 .io_offset = DSI_6G_REG_SHIFT,
67 .phy_type = MSM_DSI_PHY_28NM,
71 {"gdsc", -1, -1, -1, -1},
72 {"vdd", 3000000, 3000000, 150000, 100},
73 {"vdda", 1200000, 1200000, 100000, 100},
74 {"vddio", 1800000, 1800000, 100000, 100},
79 .major = MSM_DSI_VER_MAJOR_6G,
80 .minor = MSM_DSI_6G_VER_MINOR_V1_1,
81 .io_offset = DSI_6G_REG_SHIFT,
82 .phy_type = MSM_DSI_PHY_28NM,
86 {"gdsc", -1, -1, -1, -1},
87 {"vdd", 3000000, 3000000, 150000, 100},
88 {"vdda", 1200000, 1200000, 100000, 100},
89 {"vddio", 1800000, 1800000, 100000, 100},
94 .major = MSM_DSI_VER_MAJOR_6G,
95 .minor = MSM_DSI_6G_VER_MINOR_V1_1_1,
96 .io_offset = DSI_6G_REG_SHIFT,
97 .phy_type = MSM_DSI_PHY_28NM,
101 {"gdsc", -1, -1, -1, -1},
102 {"vdd", 3000000, 3000000, 150000, 100},
103 {"vdda", 1200000, 1200000, 100000, 100},
104 {"vddio", 1800000, 1800000, 100000, 100},
109 .major = MSM_DSI_VER_MAJOR_6G,
110 .minor = MSM_DSI_6G_VER_MINOR_V1_2,
111 .io_offset = DSI_6G_REG_SHIFT,
112 .phy_type = MSM_DSI_PHY_28NM,
116 {"gdsc", -1, -1, -1, -1},
117 {"vdd", 3000000, 3000000, 150000, 100},
118 {"vdda", 1200000, 1200000, 100000, 100},
119 {"vddio", 1800000, 1800000, 100000, 100},
124 .major = MSM_DSI_VER_MAJOR_6G,
125 .minor = MSM_DSI_6G_VER_MINOR_V1_3_1,
126 .io_offset = DSI_6G_REG_SHIFT,
127 .phy_type = MSM_DSI_PHY_28NM,
131 {"gdsc", -1, -1, -1, -1},
132 {"vdd", 2850000, 2850000, 100000, 100},
133 {"vdda", 1200000, 1200000, 100000, 100},
134 {"vddio", 1800000, 1800000, 100000, 100},
140 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
145 if (!major || !minor)
148 /* From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
149 * makes all other registers 4-byte shifted down.
151 ver_6g = msm_readl(base + REG_DSI_6G_HW_VERSION);
153 ver = msm_readl(base + REG_DSI_VERSION);
154 ver = FIELD(ver, DSI_VERSION_MAJOR);
155 if (ver <= MSM_DSI_VER_MAJOR_V2) {
164 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
165 ver = FIELD(ver, DSI_VERSION_MAJOR);
166 if (ver == MSM_DSI_VER_MAJOR_6G) {
177 #define DSI_ERR_STATE_ACK 0x0000
178 #define DSI_ERR_STATE_TIMEOUT 0x0001
179 #define DSI_ERR_STATE_DLN0_PHY 0x0002
180 #define DSI_ERR_STATE_FIFO 0x0004
181 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
182 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
183 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
185 #define DSI_CLK_CTRL_ENABLE_CLKS \
186 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
187 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
188 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
189 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
191 struct msm_dsi_host {
192 struct mipi_dsi_host base;
194 struct platform_device *pdev;
195 struct drm_device *dev;
199 void __iomem *ctrl_base;
200 struct regulator_bulk_data supplies[DSI_REGULATOR_MAX];
201 struct clk *mdp_core_clk;
204 struct clk *mmss_misc_ahb_clk;
205 struct clk *byte_clk;
207 struct clk *pixel_clk;
210 struct gpio_desc *disp_en_gpio;
211 struct gpio_desc *te_gpio;
213 const struct dsi_config *cfg;
215 struct completion dma_comp;
216 struct completion video_comp;
217 struct mutex dev_mutex;
218 struct mutex cmd_mutex;
219 struct mutex clk_mutex;
220 spinlock_t intr_lock; /* Protect interrupt ctrl register */
223 struct work_struct err_work;
224 struct workqueue_struct *workqueue;
226 struct drm_gem_object *tx_gem_obj;
229 struct drm_display_mode *mode;
232 struct device_node *panel_node;
233 unsigned int channel;
235 enum mipi_dsi_pixel_format format;
236 unsigned long mode_flags;
238 u32 dma_cmd_ctrl_restore;
245 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
248 case MIPI_DSI_FMT_RGB565: return 16;
249 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
250 case MIPI_DSI_FMT_RGB666:
251 case MIPI_DSI_FMT_RGB888:
256 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
258 return msm_readl(msm_host->ctrl_base + msm_host->cfg->io_offset + reg);
260 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
262 msm_writel(data, msm_host->ctrl_base + msm_host->cfg->io_offset + reg);
265 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
266 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
268 static const struct dsi_config *dsi_get_config(struct msm_dsi_host *msm_host)
270 const struct dsi_config *cfg;
271 struct regulator *gdsc_reg;
273 u32 major = 0, minor = 0;
275 gdsc_reg = regulator_get(&msm_host->pdev->dev, "gdsc");
276 if (IS_ERR_OR_NULL(gdsc_reg)) {
277 pr_err("%s: cannot get gdsc\n", __func__);
280 ret = regulator_enable(gdsc_reg);
282 pr_err("%s: unable to enable gdsc\n", __func__);
283 regulator_put(gdsc_reg);
286 ret = clk_prepare_enable(msm_host->ahb_clk);
288 pr_err("%s: unable to enable ahb_clk\n", __func__);
289 regulator_disable(gdsc_reg);
290 regulator_put(gdsc_reg);
294 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
296 clk_disable_unprepare(msm_host->ahb_clk);
297 regulator_disable(gdsc_reg);
298 regulator_put(gdsc_reg);
300 pr_err("%s: Invalid version\n", __func__);
304 for (i = 0; i < ARRAY_SIZE(dsi_cfgs); i++) {
306 if ((cfg->major == major) && (cfg->minor == minor))
309 pr_err("%s: Version %x:%x not support\n", __func__, major, minor);
315 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
317 return container_of(host, struct msm_dsi_host, base);
320 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
322 struct regulator_bulk_data *s = msm_host->supplies;
323 const struct dsi_reg_entry *regs = msm_host->cfg->reg_cfg.regs;
324 int num = msm_host->cfg->reg_cfg.num;
328 for (i = num - 1; i >= 0; i--)
329 if (regs[i].disable_load >= 0)
330 regulator_set_load(s[i].consumer, regs[i].disable_load);
332 regulator_bulk_disable(num, s);
335 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
337 struct regulator_bulk_data *s = msm_host->supplies;
338 const struct dsi_reg_entry *regs = msm_host->cfg->reg_cfg.regs;
339 int num = msm_host->cfg->reg_cfg.num;
343 for (i = 0; i < num; i++) {
344 if (regs[i].enable_load >= 0) {
345 ret = regulator_set_load(s[i].consumer,
346 regs[i].enable_load);
348 pr_err("regulator %d set op mode failed, %d\n",
355 ret = regulator_bulk_enable(num, s);
357 pr_err("regulator enable failed, %d\n", ret);
364 for (i--; i >= 0; i--)
365 regulator_set_load(s[i].consumer, regs[i].disable_load);
369 static int dsi_regulator_init(struct msm_dsi_host *msm_host)
371 struct regulator_bulk_data *s = msm_host->supplies;
372 const struct dsi_reg_entry *regs = msm_host->cfg->reg_cfg.regs;
373 int num = msm_host->cfg->reg_cfg.num;
376 for (i = 0; i < num; i++)
377 s[i].supply = regs[i].name;
379 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
381 pr_err("%s: failed to init regulator, ret=%d\n",
386 for (i = 0; i < num; i++) {
387 if ((regs[i].min_voltage >= 0) && (regs[i].max_voltage >= 0)) {
388 ret = regulator_set_voltage(s[i].consumer,
389 regs[i].min_voltage, regs[i].max_voltage);
391 pr_err("regulator %d set voltage failed, %d\n",
401 static int dsi_clk_init(struct msm_dsi_host *msm_host)
403 struct device *dev = &msm_host->pdev->dev;
406 msm_host->mdp_core_clk = devm_clk_get(dev, "mdp_core_clk");
407 if (IS_ERR(msm_host->mdp_core_clk)) {
408 ret = PTR_ERR(msm_host->mdp_core_clk);
409 pr_err("%s: Unable to get mdp core clk. ret=%d\n",
414 msm_host->ahb_clk = devm_clk_get(dev, "iface_clk");
415 if (IS_ERR(msm_host->ahb_clk)) {
416 ret = PTR_ERR(msm_host->ahb_clk);
417 pr_err("%s: Unable to get mdss ahb clk. ret=%d\n",
422 msm_host->axi_clk = devm_clk_get(dev, "bus_clk");
423 if (IS_ERR(msm_host->axi_clk)) {
424 ret = PTR_ERR(msm_host->axi_clk);
425 pr_err("%s: Unable to get axi bus clk. ret=%d\n",
430 msm_host->mmss_misc_ahb_clk = devm_clk_get(dev, "core_mmss_clk");
431 if (IS_ERR(msm_host->mmss_misc_ahb_clk)) {
432 ret = PTR_ERR(msm_host->mmss_misc_ahb_clk);
433 pr_err("%s: Unable to get mmss misc ahb clk. ret=%d\n",
438 msm_host->byte_clk = devm_clk_get(dev, "byte_clk");
439 if (IS_ERR(msm_host->byte_clk)) {
440 ret = PTR_ERR(msm_host->byte_clk);
441 pr_err("%s: can't find dsi_byte_clk. ret=%d\n",
443 msm_host->byte_clk = NULL;
447 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk");
448 if (IS_ERR(msm_host->pixel_clk)) {
449 ret = PTR_ERR(msm_host->pixel_clk);
450 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n",
452 msm_host->pixel_clk = NULL;
456 msm_host->esc_clk = devm_clk_get(dev, "core_clk");
457 if (IS_ERR(msm_host->esc_clk)) {
458 ret = PTR_ERR(msm_host->esc_clk);
459 pr_err("%s: can't find dsi_esc_clk. ret=%d\n",
461 msm_host->esc_clk = NULL;
469 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
473 DBG("id=%d", msm_host->id);
475 ret = clk_prepare_enable(msm_host->mdp_core_clk);
477 pr_err("%s: failed to enable mdp_core_clock, %d\n",
482 ret = clk_prepare_enable(msm_host->ahb_clk);
484 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);
488 ret = clk_prepare_enable(msm_host->axi_clk);
490 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);
494 ret = clk_prepare_enable(msm_host->mmss_misc_ahb_clk);
496 pr_err("%s: failed to enable mmss misc ahb clk, %d\n",
498 goto misc_ahb_clk_err;
504 clk_disable_unprepare(msm_host->axi_clk);
506 clk_disable_unprepare(msm_host->ahb_clk);
508 clk_disable_unprepare(msm_host->mdp_core_clk);
513 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
516 clk_disable_unprepare(msm_host->mmss_misc_ahb_clk);
517 clk_disable_unprepare(msm_host->axi_clk);
518 clk_disable_unprepare(msm_host->ahb_clk);
519 clk_disable_unprepare(msm_host->mdp_core_clk);
522 static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
526 DBG("Set clk rates: pclk=%d, byteclk=%d",
527 msm_host->mode->clock, msm_host->byte_clk_rate);
529 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
531 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
535 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
537 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
541 ret = clk_prepare_enable(msm_host->esc_clk);
543 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
547 ret = clk_prepare_enable(msm_host->byte_clk);
549 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
553 ret = clk_prepare_enable(msm_host->pixel_clk);
555 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
562 clk_disable_unprepare(msm_host->byte_clk);
564 clk_disable_unprepare(msm_host->esc_clk);
569 static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
571 clk_disable_unprepare(msm_host->esc_clk);
572 clk_disable_unprepare(msm_host->pixel_clk);
573 clk_disable_unprepare(msm_host->byte_clk);
576 static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable)
580 mutex_lock(&msm_host->clk_mutex);
582 ret = dsi_bus_clk_enable(msm_host);
584 pr_err("%s: Can not enable bus clk, %d\n",
588 ret = dsi_link_clk_enable(msm_host);
590 pr_err("%s: Can not enable link clk, %d\n",
592 dsi_bus_clk_disable(msm_host);
596 dsi_link_clk_disable(msm_host);
597 dsi_bus_clk_disable(msm_host);
601 mutex_unlock(&msm_host->clk_mutex);
605 static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
607 struct drm_display_mode *mode = msm_host->mode;
608 u8 lanes = msm_host->lanes;
609 u32 bpp = dsi_get_bpp(msm_host->format);
613 pr_err("%s: mode not set\n", __func__);
617 pclk_rate = mode->clock * 1000;
619 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
621 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
622 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
625 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
630 static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host)
633 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
634 /* Make sure fully reset */
637 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
641 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
646 spin_lock_irqsave(&msm_host->intr_lock, flags);
647 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
654 DBG("intr=%x enable=%d", intr, enable);
656 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
657 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
660 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
662 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
664 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
665 return NON_BURST_SYNCH_PULSE;
667 return NON_BURST_SYNCH_EVENT;
670 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
671 const enum mipi_dsi_pixel_format mipi_fmt)
674 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
675 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
676 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
677 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
678 default: return VID_DST_FORMAT_RGB888;
682 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
683 const enum mipi_dsi_pixel_format mipi_fmt)
686 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
687 case MIPI_DSI_FMT_RGB666_PACKED:
688 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666;
689 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
690 default: return CMD_DST_FORMAT_RGB888;
694 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
695 u32 clk_pre, u32 clk_post)
697 u32 flags = msm_host->mode_flags;
698 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
702 dsi_write(msm_host, REG_DSI_CTRL, 0);
706 if (flags & MIPI_DSI_MODE_VIDEO) {
707 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
708 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
709 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
710 data |= DSI_VID_CFG0_HFP_POWER_STOP;
711 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
712 data |= DSI_VID_CFG0_HBP_POWER_STOP;
713 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
714 data |= DSI_VID_CFG0_HSA_POWER_STOP;
715 /* Always set low power stop mode for BLLP
716 * to let command engine send packets
718 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
719 DSI_VID_CFG0_BLLP_POWER_STOP;
720 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
721 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
722 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
723 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
725 /* Do not swap RGB colors */
726 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
727 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
729 /* Do not swap RGB colors */
730 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
731 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
732 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
734 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
735 DSI_CMD_CFG1_WR_MEM_CONTINUE(
736 MIPI_DCS_WRITE_MEMORY_CONTINUE);
737 /* Always insert DCS command */
738 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
739 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
742 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
743 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
744 DSI_CMD_DMA_CTRL_LOW_POWER);
747 /* Always assume dedicated TE pin */
748 data |= DSI_TRIG_CTRL_TE;
749 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
750 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
751 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
752 if ((msm_host->cfg->major == MSM_DSI_VER_MAJOR_6G) &&
753 (msm_host->cfg->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
754 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
755 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
757 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) |
758 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre);
759 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
762 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
763 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
764 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
766 /* allow only ack-err-status to generate interrupt */
767 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
769 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
771 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
773 data = DSI_CTRL_CLK_EN;
775 DBG("lane number=%d", msm_host->lanes);
776 if (msm_host->lanes == 2) {
777 data |= DSI_CTRL_LANE1 | DSI_CTRL_LANE2;
778 /* swap lanes for 2-lane panel for better performance */
779 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
780 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_1230));
782 /* Take 4 lanes as default */
783 data |= DSI_CTRL_LANE0 | DSI_CTRL_LANE1 | DSI_CTRL_LANE2 |
785 /* Do not swap lanes for 4-lane panel */
786 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
787 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123));
789 data |= DSI_CTRL_ENABLE;
791 dsi_write(msm_host, REG_DSI_CTRL, data);
794 static void dsi_timing_setup(struct msm_dsi_host *msm_host)
796 struct drm_display_mode *mode = msm_host->mode;
797 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
798 u32 h_total = mode->htotal;
799 u32 v_total = mode->vtotal;
800 u32 hs_end = mode->hsync_end - mode->hsync_start;
801 u32 vs_end = mode->vsync_end - mode->vsync_start;
802 u32 ha_start = h_total - mode->hsync_start;
803 u32 ha_end = ha_start + mode->hdisplay;
804 u32 va_start = v_total - mode->vsync_start;
805 u32 va_end = va_start + mode->vdisplay;
810 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
811 dsi_write(msm_host, REG_DSI_ACTIVE_H,
812 DSI_ACTIVE_H_START(ha_start) |
813 DSI_ACTIVE_H_END(ha_end));
814 dsi_write(msm_host, REG_DSI_ACTIVE_V,
815 DSI_ACTIVE_V_START(va_start) |
816 DSI_ACTIVE_V_END(va_end));
817 dsi_write(msm_host, REG_DSI_TOTAL,
818 DSI_TOTAL_H_TOTAL(h_total - 1) |
819 DSI_TOTAL_V_TOTAL(v_total - 1));
821 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
822 DSI_ACTIVE_HSYNC_START(hs_start) |
823 DSI_ACTIVE_HSYNC_END(hs_end));
824 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
825 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
826 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
827 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
828 } else { /* command mode */
829 /* image data and 1 byte write_memory_start cmd */
830 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
832 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
833 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
834 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
836 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
837 MIPI_DSI_DCS_LONG_WRITE));
839 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
840 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
841 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
845 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
847 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
848 wmb(); /* clocks need to be enabled before reset */
850 dsi_write(msm_host, REG_DSI_RESET, 1);
851 wmb(); /* make sure reset happen */
852 dsi_write(msm_host, REG_DSI_RESET, 0);
855 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
856 bool video_mode, bool enable)
860 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
863 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
864 DSI_CTRL_CMD_MODE_EN);
865 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
866 DSI_IRQ_MASK_VIDEO_DONE, 0);
869 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
870 } else { /* command mode */
871 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
872 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
874 dsi_ctrl |= DSI_CTRL_ENABLE;
877 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
880 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
884 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
887 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
889 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
891 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
894 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
896 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
898 reinit_completion(&msm_host->video_comp);
900 wait_for_completion_timeout(&msm_host->video_comp,
901 msecs_to_jiffies(70));
903 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
906 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
908 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
911 if (msm_host->power_on) {
912 dsi_wait4video_done(msm_host);
913 /* delay 4 ms to skip BLLP */
914 usleep_range(2000, 4000);
919 static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
921 struct drm_device *dev = msm_host->dev;
925 mutex_lock(&dev->struct_mutex);
926 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
927 if (IS_ERR(msm_host->tx_gem_obj)) {
928 ret = PTR_ERR(msm_host->tx_gem_obj);
929 pr_err("%s: failed to allocate gem, %d\n", __func__, ret);
930 msm_host->tx_gem_obj = NULL;
931 mutex_unlock(&dev->struct_mutex);
935 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova);
937 pr_err("%s: failed to get iova, %d\n", __func__, ret);
940 mutex_unlock(&dev->struct_mutex);
943 pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
950 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
952 struct drm_device *dev = msm_host->dev;
954 if (msm_host->tx_gem_obj) {
955 msm_gem_put_iova(msm_host->tx_gem_obj, 0);
956 mutex_lock(&dev->struct_mutex);
957 msm_gem_free_object(msm_host->tx_gem_obj);
958 msm_host->tx_gem_obj = NULL;
959 mutex_unlock(&dev->struct_mutex);
964 * prepare cmd buffer to be txed
966 static int dsi_cmd_dma_add(struct drm_gem_object *tx_gem,
967 const struct mipi_dsi_msg *msg)
969 struct mipi_dsi_packet packet;
974 ret = mipi_dsi_create_packet(&packet, msg);
976 pr_err("%s: create packet failed, %d\n", __func__, ret);
979 len = (packet.size + 3) & (~0x3);
981 if (len > tx_gem->size) {
982 pr_err("%s: packet size is too big\n", __func__);
986 data = msm_gem_vaddr(tx_gem);
990 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
994 /* MSM specific command format in memory */
995 data[0] = packet.header[1];
996 data[1] = packet.header[2];
997 data[2] = packet.header[0];
998 data[3] = BIT(7); /* Last packet */
999 if (mipi_dsi_packet_format_is_long(msg->type))
1001 if (msg->rx_buf && msg->rx_len)
1005 if (packet.payload && packet.payload_length)
1006 memcpy(data + 4, packet.payload, packet.payload_length);
1008 /* Append 0xff to the end */
1009 if (packet.size < len)
1010 memset(data + packet.size, 0xff, len - packet.size);
1016 * dsi_short_read1_resp: 1 parameter
1018 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1020 u8 *data = msg->rx_buf;
1021 if (data && (msg->rx_len >= 1)) {
1022 *data = buf[1]; /* strip out dcs type */
1025 pr_err("%s: read data does not match with rx_buf len %d\n",
1026 __func__, msg->rx_len);
1032 * dsi_short_read2_resp: 2 parameter
1034 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1036 u8 *data = msg->rx_buf;
1037 if (data && (msg->rx_len >= 2)) {
1038 data[0] = buf[1]; /* strip out dcs type */
1042 pr_err("%s: read data does not match with rx_buf len %d\n",
1043 __func__, msg->rx_len);
1048 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1050 /* strip out 4 byte dcs header */
1051 if (msg->rx_buf && msg->rx_len)
1052 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1058 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1064 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &iova);
1066 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1070 reinit_completion(&msm_host->dma_comp);
1072 dsi_wait4video_eng_busy(msm_host);
1074 triggered = msm_dsi_manager_cmd_xfer_trigger(
1075 msm_host->id, iova, len);
1077 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1078 msecs_to_jiffies(200));
1090 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1091 u8 *buf, int rx_byte, int pkt_size)
1093 u32 *lp, *temp, data;
1095 bool ack_error = false;
1098 int repeated_bytes = 0;
1099 int buf_offset = buf - msm_host->rx_buf;
1103 cnt = (rx_byte + 3) >> 2;
1105 cnt = 4; /* 4 x 32 bits registers only */
1107 /* Calculate real read data count */
1108 read_cnt = dsi_read(msm_host, 0x1d4) >> 16;
1110 ack_error = (rx_byte == 4) ?
1111 (read_cnt == 8) : /* short pkt + 4-byte error pkt */
1112 (read_cnt == (pkt_size + 6 + 4)); /* long pkt+4-byte error pkt*/
1115 read_cnt -= 4; /* Remove 4 byte error pkt */
1118 * In case of multiple reads from the panel, after the first read, there
1119 * is possibility that there are some bytes in the payload repeating in
1120 * the RDBK_DATA registers. Since we read all the parameters from the
1121 * panel right from the first byte for every pass. We need to skip the
1122 * repeating bytes and then append the new parameters to the rx buffer.
1124 if (read_cnt > 16) {
1126 /* Any data more than 16 bytes will be shifted out.
1127 * The temp read buffer should already contain these bytes.
1128 * The remaining bytes in read buffer are the repeated bytes.
1130 bytes_shifted = read_cnt - 16;
1131 repeated_bytes = buf_offset - bytes_shifted;
1134 for (i = cnt - 1; i >= 0; i--) {
1135 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1136 *temp++ = ntohl(data); /* to host byte order */
1137 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1140 for (i = repeated_bytes; i < 16; i++)
1146 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1147 const struct mipi_dsi_msg *msg)
1150 int bllp_len = msm_host->mode->hdisplay *
1151 dsi_get_bpp(msm_host->format) / 8;
1153 len = dsi_cmd_dma_add(msm_host->tx_gem_obj, msg);
1155 pr_err("%s: failed to add cmd type = 0x%x\n",
1156 __func__, msg->type);
1160 /* for video mode, do not send cmds more than
1161 * one pixel line, since it only transmit it
1164 /* TODO: if the command is sent in LP mode, the bit rate is only
1165 * half of esc clk rate. In this case, if the video is already
1166 * actively streaming, we need to check more carefully if the
1167 * command can be fit into one BLLP.
1169 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1170 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1175 ret = dsi_cmd_dma_tx(msm_host, len);
1177 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1178 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1185 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1189 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1191 data1 &= ~DSI_CTRL_ENABLE;
1192 dsi_write(msm_host, REG_DSI_CTRL, data1);
1194 * dsi controller need to be disabled before
1199 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1200 wmb(); /* make sure clocks enabled */
1202 /* dsi controller can only be reset while clocks are running */
1203 dsi_write(msm_host, REG_DSI_RESET, 1);
1204 wmb(); /* make sure reset happen */
1205 dsi_write(msm_host, REG_DSI_RESET, 0);
1206 wmb(); /* controller out of reset */
1207 dsi_write(msm_host, REG_DSI_CTRL, data0);
1208 wmb(); /* make sure dsi controller enabled again */
1211 static void dsi_err_worker(struct work_struct *work)
1213 struct msm_dsi_host *msm_host =
1214 container_of(work, struct msm_dsi_host, err_work);
1215 u32 status = msm_host->err_work_state;
1217 pr_err("%s: status=%x\n", __func__, status);
1218 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1219 dsi_sw_reset_restore(msm_host);
1221 /* It is safe to clear here because error irq is disabled. */
1222 msm_host->err_work_state = 0;
1224 /* enable dsi error interrupt */
1225 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1228 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1232 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1235 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1236 /* Writing of an extra 0 needed to clear error bits */
1237 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1238 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1242 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1246 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1249 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1250 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1254 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1258 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1261 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1262 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1266 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1270 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1272 /* fifo underflow, overflow */
1274 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1275 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1276 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1277 msm_host->err_work_state |=
1278 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1282 static void dsi_status(struct msm_dsi_host *msm_host)
1286 status = dsi_read(msm_host, REG_DSI_STATUS0);
1288 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1289 dsi_write(msm_host, REG_DSI_STATUS0, status);
1290 msm_host->err_work_state |=
1291 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1295 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1299 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1301 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1302 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1303 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1307 static void dsi_error(struct msm_dsi_host *msm_host)
1309 /* disable dsi error interrupt */
1310 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1312 dsi_clk_status(msm_host);
1313 dsi_fifo_status(msm_host);
1314 dsi_ack_err_status(msm_host);
1315 dsi_timeout_status(msm_host);
1316 dsi_status(msm_host);
1317 dsi_dln0_phy_err(msm_host);
1319 queue_work(msm_host->workqueue, &msm_host->err_work);
1322 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1324 struct msm_dsi_host *msm_host = ptr;
1326 unsigned long flags;
1328 if (!msm_host->ctrl_base)
1331 spin_lock_irqsave(&msm_host->intr_lock, flags);
1332 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1333 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1334 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1336 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1338 if (isr & DSI_IRQ_ERROR)
1339 dsi_error(msm_host);
1341 if (isr & DSI_IRQ_VIDEO_DONE)
1342 complete(&msm_host->video_comp);
1344 if (isr & DSI_IRQ_CMD_DMA_DONE)
1345 complete(&msm_host->dma_comp);
1350 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1351 struct device *panel_device)
1355 msm_host->disp_en_gpio = devm_gpiod_get(panel_device,
1357 if (IS_ERR(msm_host->disp_en_gpio)) {
1358 DBG("cannot get disp-enable-gpios %ld",
1359 PTR_ERR(msm_host->disp_en_gpio));
1360 msm_host->disp_en_gpio = NULL;
1362 if (msm_host->disp_en_gpio) {
1363 ret = gpiod_direction_output(msm_host->disp_en_gpio, 0);
1365 pr_err("cannot set dir to disp-en-gpios %d\n", ret);
1370 msm_host->te_gpio = devm_gpiod_get(panel_device, "disp-te");
1371 if (IS_ERR(msm_host->te_gpio)) {
1372 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1373 msm_host->te_gpio = NULL;
1376 if (msm_host->te_gpio) {
1377 ret = gpiod_direction_input(msm_host->te_gpio);
1379 pr_err("%s: cannot set dir to disp-te-gpios, %d\n",
1388 static int dsi_host_attach(struct mipi_dsi_host *host,
1389 struct mipi_dsi_device *dsi)
1391 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1394 msm_host->channel = dsi->channel;
1395 msm_host->lanes = dsi->lanes;
1396 msm_host->format = dsi->format;
1397 msm_host->mode_flags = dsi->mode_flags;
1399 msm_host->panel_node = dsi->dev.of_node;
1401 /* Some gpios defined in panel DT need to be controlled by host */
1402 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1406 DBG("id=%d", msm_host->id);
1408 drm_helper_hpd_irq_event(msm_host->dev);
1413 static int dsi_host_detach(struct mipi_dsi_host *host,
1414 struct mipi_dsi_device *dsi)
1416 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1418 msm_host->panel_node = NULL;
1420 DBG("id=%d", msm_host->id);
1422 drm_helper_hpd_irq_event(msm_host->dev);
1427 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1428 const struct mipi_dsi_msg *msg)
1430 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1433 if (!msg || !msm_host->power_on)
1436 mutex_lock(&msm_host->cmd_mutex);
1437 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1438 mutex_unlock(&msm_host->cmd_mutex);
1443 static struct mipi_dsi_host_ops dsi_host_ops = {
1444 .attach = dsi_host_attach,
1445 .detach = dsi_host_detach,
1446 .transfer = dsi_host_transfer,
1449 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1451 struct msm_dsi_host *msm_host = NULL;
1452 struct platform_device *pdev = msm_dsi->pdev;
1455 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1457 pr_err("%s: FAILED: cannot alloc dsi host\n",
1463 ret = of_property_read_u32(pdev->dev.of_node,
1464 "qcom,dsi-host-index", &msm_host->id);
1467 "%s: host index not specified, ret=%d\n",
1471 msm_host->pdev = pdev;
1473 ret = dsi_clk_init(msm_host);
1475 pr_err("%s: unable to initialize dsi clks\n", __func__);
1479 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1480 if (IS_ERR(msm_host->ctrl_base)) {
1481 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1482 ret = PTR_ERR(msm_host->ctrl_base);
1486 msm_host->cfg = dsi_get_config(msm_host);
1487 if (!msm_host->cfg) {
1489 pr_err("%s: get config failed\n", __func__);
1493 ret = dsi_regulator_init(msm_host);
1495 pr_err("%s: regulator init failed\n", __func__);
1499 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1500 if (!msm_host->rx_buf) {
1501 pr_err("%s: alloc rx temp buf failed\n", __func__);
1505 init_completion(&msm_host->dma_comp);
1506 init_completion(&msm_host->video_comp);
1507 mutex_init(&msm_host->dev_mutex);
1508 mutex_init(&msm_host->cmd_mutex);
1509 mutex_init(&msm_host->clk_mutex);
1510 spin_lock_init(&msm_host->intr_lock);
1512 /* setup workqueue */
1513 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1514 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1516 msm_dsi->phy = msm_dsi_phy_init(pdev, msm_host->cfg->phy_type,
1518 if (!msm_dsi->phy) {
1520 pr_err("%s: phy init failed\n", __func__);
1523 msm_dsi->host = &msm_host->base;
1524 msm_dsi->id = msm_host->id;
1526 DBG("Dsi Host %d initialized", msm_host->id);
1533 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1535 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1538 dsi_tx_buf_free(msm_host);
1539 if (msm_host->workqueue) {
1540 flush_workqueue(msm_host->workqueue);
1541 destroy_workqueue(msm_host->workqueue);
1542 msm_host->workqueue = NULL;
1545 mutex_destroy(&msm_host->clk_mutex);
1546 mutex_destroy(&msm_host->cmd_mutex);
1547 mutex_destroy(&msm_host->dev_mutex);
1550 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1551 struct drm_device *dev)
1553 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1554 struct platform_device *pdev = msm_host->pdev;
1557 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1558 if (msm_host->irq < 0) {
1559 ret = msm_host->irq;
1560 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1564 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1565 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1566 "dsi_isr", msm_host);
1568 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1569 msm_host->irq, ret);
1573 msm_host->dev = dev;
1574 ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
1576 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1583 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1585 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1586 struct device_node *node;
1589 /* Register mipi dsi host */
1590 if (!msm_host->registered) {
1591 host->dev = &msm_host->pdev->dev;
1592 host->ops = &dsi_host_ops;
1593 ret = mipi_dsi_host_register(host);
1597 msm_host->registered = true;
1599 /* If the panel driver has not been probed after host register,
1600 * we should defer the host's probe.
1601 * It makes sure panel is connected when fbcon detects
1602 * connector status and gets the proper display mode to
1603 * create framebuffer.
1606 node = of_get_child_by_name(msm_host->pdev->dev.of_node,
1609 if (!of_drm_find_panel(node))
1610 return -EPROBE_DEFER;
1618 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1620 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1622 if (msm_host->registered) {
1623 mipi_dsi_host_unregister(host);
1626 msm_host->registered = false;
1630 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1631 const struct mipi_dsi_msg *msg)
1633 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1635 /* TODO: make sure dsi_cmd_mdp is idle.
1636 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1637 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1638 * How to handle the old versions? Wait for mdp cmd done?
1642 * mdss interrupt is generated in mdp core clock domain
1643 * mdp clock need to be enabled to receive dsi interrupt
1645 dsi_clk_ctrl(msm_host, 1);
1647 /* TODO: vote for bus bandwidth */
1649 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1650 dsi_set_tx_power_mode(0, msm_host);
1652 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
1653 dsi_write(msm_host, REG_DSI_CTRL,
1654 msm_host->dma_cmd_ctrl_restore |
1655 DSI_CTRL_CMD_MODE_EN |
1657 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
1662 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
1663 const struct mipi_dsi_msg *msg)
1665 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1667 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
1668 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
1670 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1671 dsi_set_tx_power_mode(1, msm_host);
1673 /* TODO: unvote for bus bandwidth */
1675 dsi_clk_ctrl(msm_host, 0);
1678 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
1679 const struct mipi_dsi_msg *msg)
1681 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1683 return dsi_cmds2buf_tx(msm_host, msg);
1686 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
1687 const struct mipi_dsi_msg *msg)
1689 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1690 int data_byte, rx_byte, dlen, end;
1691 int short_response, diff, pkt_size, ret = 0;
1693 int rlen = msg->rx_len;
1702 data_byte = 10; /* first read */
1703 if (rlen < data_byte)
1706 pkt_size = data_byte;
1707 rx_byte = data_byte + 6; /* 4 header + 2 crc */
1710 buf = msm_host->rx_buf;
1713 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
1714 struct mipi_dsi_msg max_pkt_size_msg = {
1715 .channel = msg->channel,
1716 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
1721 DBG("rlen=%d pkt_size=%d rx_byte=%d",
1722 rlen, pkt_size, rx_byte);
1724 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
1726 pr_err("%s: Set max pkt size failed, %d\n",
1731 if ((msm_host->cfg->major == MSM_DSI_VER_MAJOR_6G) &&
1732 (msm_host->cfg->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
1733 /* Clear the RDBK_DATA registers */
1734 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
1735 DSI_RDBK_DATA_CTRL_CLR);
1736 wmb(); /* make sure the RDBK registers are cleared */
1737 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
1738 wmb(); /* release cleared status before transfer */
1741 ret = dsi_cmds2buf_tx(msm_host, msg);
1742 if (ret < msg->tx_len) {
1743 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
1748 * once cmd_dma_done interrupt received,
1749 * return data from client is ready and stored
1750 * at RDBK_DATA register already
1751 * since rx fifo is 16 bytes, dcs header is kept at first loop,
1752 * after that dcs header lost during shift into registers
1754 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
1762 if (rlen <= data_byte) {
1763 diff = data_byte - rlen;
1771 dlen -= 2; /* 2 crc */
1773 buf += dlen; /* next start position */
1774 data_byte = 14; /* NOT first read */
1775 if (rlen < data_byte)
1778 pkt_size += data_byte;
1779 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
1784 * For single Long read, if the requested rlen < 10,
1785 * we need to shift the start position of rx
1786 * data buffer to skip the bytes which are not
1789 if (pkt_size < 10 && !short_response)
1790 buf = msm_host->rx_buf + (10 - rlen);
1792 buf = msm_host->rx_buf;
1796 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1797 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
1799 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1800 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1801 ret = dsi_short_read1_resp(buf, msg);
1803 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1804 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1805 ret = dsi_short_read2_resp(buf, msg);
1807 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1808 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1809 ret = dsi_long_read_resp(buf, msg);
1812 pr_warn("%s:Invalid response cmd\n", __func__);
1819 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 iova, u32 len)
1821 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1823 dsi_write(msm_host, REG_DSI_DMA_BASE, iova);
1824 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
1825 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
1827 /* Make sure trigger happens */
1831 int msm_dsi_host_enable(struct mipi_dsi_host *host)
1833 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1835 dsi_op_mode_config(msm_host,
1836 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
1838 /* TODO: clock should be turned off for command mode,
1839 * and only turned on before MDP START.
1840 * This part of code should be enabled once mdp driver support it.
1842 /* if (msm_panel->mode == MSM_DSI_CMD_MODE)
1843 dsi_clk_ctrl(msm_host, 0); */
1848 int msm_dsi_host_disable(struct mipi_dsi_host *host)
1850 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1852 dsi_op_mode_config(msm_host,
1853 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
1855 /* Since we have disabled INTF, the video engine won't stop so that
1856 * the cmd engine will be blocked.
1857 * Reset to disable video engine so that we can send off cmd.
1859 dsi_sw_reset(msm_host);
1864 int msm_dsi_host_power_on(struct mipi_dsi_host *host)
1866 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1867 u32 clk_pre = 0, clk_post = 0;
1870 mutex_lock(&msm_host->dev_mutex);
1871 if (msm_host->power_on) {
1872 DBG("dsi host already on");
1876 ret = dsi_calc_clk_rate(msm_host);
1878 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
1882 ret = dsi_host_regulator_enable(msm_host);
1884 pr_err("%s:Failed to enable vregs.ret=%d\n",
1889 ret = dsi_bus_clk_enable(msm_host);
1891 pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret);
1892 goto fail_disable_reg;
1895 dsi_phy_sw_reset(msm_host);
1896 ret = msm_dsi_manager_phy_enable(msm_host->id,
1897 msm_host->byte_clk_rate * 8,
1898 clk_get_rate(msm_host->esc_clk),
1899 &clk_pre, &clk_post);
1900 dsi_bus_clk_disable(msm_host);
1902 pr_err("%s: failed to enable phy, %d\n", __func__, ret);
1903 goto fail_disable_reg;
1906 ret = dsi_clk_ctrl(msm_host, 1);
1908 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret);
1909 goto fail_disable_reg;
1912 dsi_timing_setup(msm_host);
1913 dsi_sw_reset(msm_host);
1914 dsi_ctrl_config(msm_host, true, clk_pre, clk_post);
1916 if (msm_host->disp_en_gpio)
1917 gpiod_set_value(msm_host->disp_en_gpio, 1);
1919 msm_host->power_on = true;
1920 mutex_unlock(&msm_host->dev_mutex);
1925 dsi_host_regulator_disable(msm_host);
1927 mutex_unlock(&msm_host->dev_mutex);
1931 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
1933 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1935 mutex_lock(&msm_host->dev_mutex);
1936 if (!msm_host->power_on) {
1937 DBG("dsi host already off");
1941 dsi_ctrl_config(msm_host, false, 0, 0);
1943 if (msm_host->disp_en_gpio)
1944 gpiod_set_value(msm_host->disp_en_gpio, 0);
1946 msm_dsi_manager_phy_disable(msm_host->id);
1948 dsi_clk_ctrl(msm_host, 0);
1950 dsi_host_regulator_disable(msm_host);
1954 msm_host->power_on = false;
1957 mutex_unlock(&msm_host->dev_mutex);
1961 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
1962 struct drm_display_mode *mode)
1964 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1966 if (msm_host->mode) {
1967 drm_mode_destroy(msm_host->dev, msm_host->mode);
1968 msm_host->mode = NULL;
1971 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
1972 if (IS_ERR(msm_host->mode)) {
1973 pr_err("%s: cannot duplicate mode\n", __func__);
1974 return PTR_ERR(msm_host->mode);
1980 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
1981 unsigned long *panel_flags)
1983 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1984 struct drm_panel *panel;
1986 panel = of_drm_find_panel(msm_host->panel_node);
1988 *panel_flags = msm_host->mode_flags;