drivers/gpu/drm/nouveau/nv50_display.c

   1         /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc_helper.h>
  29
  30 #include "nouveau_drm.h"
  31 #include "nouveau_dma.h"
  32 #include "nouveau_gem.h"
  33 #include "nouveau_connector.h"
  34 #include "nouveau_encoder.h"
  35 #include "nouveau_crtc.h"
  36 #include "nouveau_fence.h"
  37 #include "nv50_display.h"
  38
  39 #include <core/client.h>
  40 #include <core/gpuobj.h>
  41 #include <core/class.h>
  42
  43 #include <subdev/timer.h>
  44 #include <subdev/bar.h>
  45 #include <subdev/fb.h>
  46 #include <subdev/i2c.h>
  47
  48 #define EVO_DMA_NR 9
  49
  50 #define EVO_MASTER  (0x00)
  51 #define EVO_FLIP(c) (0x01 + (c))
  52 #define EVO_OVLY(c) (0x05 + (c))
  53 #define EVO_OIMM(c) (0x09 + (c))
  54 #define EVO_CURS(c) (0x0d + (c))
  55
  56 /* offsets in shared sync bo of various structures */
  57 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  58 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  59 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  60 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  61
  62 #define EVO_CORE_HANDLE      (0xd1500000)
  63 #define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
  64 #define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff))
  65 #define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) |                               \
  66                               (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
  67
  68 /******************************************************************************
  69  * EVO channel
  70  *****************************************************************************/
  71
  72 struct nv50_chan {
  73         struct nouveau_object *user;
  74         u32 handle;
  75 };
  76
  77 static int
  78 nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head,
  79                  void *data, u32 size, struct nv50_chan *chan)
  80 {
  81         struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
  82         const u32 oclass = EVO_CHAN_OCLASS(bclass, core);
  83         const u32 handle = EVO_CHAN_HANDLE(bclass, head);
  84         int ret;
  85
  86         ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle,
  87                                  oclass, data, size, &chan->user);
  88         if (ret)
  89                 return ret;
  90
  91         chan->handle = handle;
  92         return 0;
  93 }
  94
  95 static void
  96 nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan)
  97 {
  98         struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
  99         if (chan->handle)
 100                 nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle);
 101 }
 102
 103 /******************************************************************************
 104  * PIO EVO channel
 105  *****************************************************************************/
 106
 107 struct nv50_pioc {
 108         struct nv50_chan base;
 109 };
 110
 111 static void
 112 nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc)
 113 {
 114         nv50_chan_destroy(core, &pioc->base);
 115 }
 116
 117 static int
 118 nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head,
 119                  void *data, u32 size, struct nv50_pioc *pioc)
 120 {
 121         return nv50_chan_create(core, bclass, head, data, size, &pioc->base);
 122 }
 123
 124 /******************************************************************************
 125  * DMA EVO channel
 126  *****************************************************************************/
 127
 128 struct nv50_dmac {
 129         struct nv50_chan base;
 130         dma_addr_t handle;
 131         u32 *ptr;
 132
 133         /* Protects against concurrent pushbuf access to this channel, lock is
 134          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 135          * dropped again by evo_kick. */
 136         struct mutex lock;
 137 };
 138
 139 static void
 140 nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac)
 141 {
 142         if (dmac->ptr) {
 143                 struct pci_dev *pdev = nv_device(core)->pdev;
 144                 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
 145         }
 146
 147         nv50_chan_destroy(core, &dmac->base);
 148 }
 149
 150 static int
 151 nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
 152 {
 153         struct nouveau_fb *pfb = nouveau_fb(core);
 154         struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 155         struct nouveau_object *object;
 156         int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
 157                                      NV_DMA_IN_MEMORY_CLASS,
 158                                      &(struct nv_dma_class) {
 159                                         .flags = NV_DMA_TARGET_VRAM |
 160                                                  NV_DMA_ACCESS_RDWR,
 161                                         .start = 0,
 162                                         .limit = pfb->ram.size - 1,
 163                                         .conf0 = NV50_DMA_CONF0_ENABLE |
 164                                                  NV50_DMA_CONF0_PART_256,
 165                                      }, sizeof(struct nv_dma_class), &object);
 166         if (ret)
 167                 return ret;
 168
 169         ret = nouveau_object_new(client, parent, NvEvoFB16,
 170                                  NV_DMA_IN_MEMORY_CLASS,
 171                                  &(struct nv_dma_class) {
 172                                         .flags = NV_DMA_TARGET_VRAM |
 173                                                  NV_DMA_ACCESS_RDWR,
 174                                         .start = 0,
 175                                         .limit = pfb->ram.size - 1,
 176                                         .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 |
 177                                                  NV50_DMA_CONF0_PART_256,
 178                                  }, sizeof(struct nv_dma_class), &object);
 179         if (ret)
 180                 return ret;
 181
 182         ret = nouveau_object_new(client, parent, NvEvoFB32,
 183                                  NV_DMA_IN_MEMORY_CLASS,
 184                                  &(struct nv_dma_class) {
 185                                         .flags = NV_DMA_TARGET_VRAM |
 186                                                  NV_DMA_ACCESS_RDWR,
 187                                         .start = 0,
 188                                         .limit = pfb->ram.size - 1,
 189                                         .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a |
 190                                                  NV50_DMA_CONF0_PART_256,
 191                                  }, sizeof(struct nv_dma_class), &object);
 192         return ret;
 193 }
 194
 195 static int
 196 nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
 197 {
 198         struct nouveau_fb *pfb = nouveau_fb(core);
 199         struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 200         struct nouveau_object *object;
 201         int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
 202                                      NV_DMA_IN_MEMORY_CLASS,
 203                                      &(struct nv_dma_class) {
 204                                         .flags = NV_DMA_TARGET_VRAM |
 205                                                  NV_DMA_ACCESS_RDWR,
 206                                         .start = 0,
 207                                         .limit = pfb->ram.size - 1,
 208                                         .conf0 = NVC0_DMA_CONF0_ENABLE,
 209                                      }, sizeof(struct nv_dma_class), &object);
 210         if (ret)
 211                 return ret;
 212
 213         ret = nouveau_object_new(client, parent, NvEvoFB16,
 214                                  NV_DMA_IN_MEMORY_CLASS,
 215                                  &(struct nv_dma_class) {
 216                                         .flags = NV_DMA_TARGET_VRAM |
 217                                                  NV_DMA_ACCESS_RDWR,
 218                                         .start = 0,
 219                                         .limit = pfb->ram.size - 1,
 220                                         .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
 221                                  }, sizeof(struct nv_dma_class), &object);
 222         if (ret)
 223                 return ret;
 224
 225         ret = nouveau_object_new(client, parent, NvEvoFB32,
 226                                  NV_DMA_IN_MEMORY_CLASS,
 227                                  &(struct nv_dma_class) {
 228                                         .flags = NV_DMA_TARGET_VRAM |
 229                                                  NV_DMA_ACCESS_RDWR,
 230                                         .start = 0,
 231                                         .limit = pfb->ram.size - 1,
 232                                         .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
 233                                  }, sizeof(struct nv_dma_class), &object);
 234         return ret;
 235 }
 236
 237 static int
 238 nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
 239 {
 240         struct nouveau_fb *pfb = nouveau_fb(core);
 241         struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 242         struct nouveau_object *object;
 243         int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
 244                                      NV_DMA_IN_MEMORY_CLASS,
 245                                      &(struct nv_dma_class) {
 246                                         .flags = NV_DMA_TARGET_VRAM |
 247                                                  NV_DMA_ACCESS_RDWR,
 248                                         .start = 0,
 249                                         .limit = pfb->ram.size - 1,
 250                                         .conf0 = NVD0_DMA_CONF0_ENABLE |
 251                                                  NVD0_DMA_CONF0_PAGE_LP,
 252                                      }, sizeof(struct nv_dma_class), &object);
 253         if (ret)
 254                 return ret;
 255
 256         ret = nouveau_object_new(client, parent, NvEvoFB32,
 257                                  NV_DMA_IN_MEMORY_CLASS,
 258                                  &(struct nv_dma_class) {
 259                                         .flags = NV_DMA_TARGET_VRAM |
 260                                                  NV_DMA_ACCESS_RDWR,
 261                                         .start = 0,
 262                                         .limit = pfb->ram.size - 1,
 263                                         .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe |
 264                                                  NVD0_DMA_CONF0_PAGE_LP,
 265                                  }, sizeof(struct nv_dma_class), &object);
 266         return ret;
 267 }
 268
 269 static int
 270 nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head,
 271                  void *data, u32 size, u64 syncbuf,
 272                  struct nv50_dmac *dmac)
 273 {
 274         struct nouveau_fb *pfb = nouveau_fb(core);
 275         struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 276         struct nouveau_object *object;
 277         u32 pushbuf = *(u32 *)data;
 278         int ret;
 279
 280         mutex_init(&dmac->lock);
 281
 282         dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE,
 283                                         &dmac->handle);
 284         if (!dmac->ptr)
 285                 return -ENOMEM;
 286
 287         ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf,
 288                                  NV_DMA_FROM_MEMORY_CLASS,
 289                                  &(struct nv_dma_class) {
 290                                         .flags = NV_DMA_TARGET_PCI_US |
 291                                                  NV_DMA_ACCESS_RD,
 292                                         .start = dmac->handle + 0x0000,
 293                                         .limit = dmac->handle + 0x0fff,
 294                                  }, sizeof(struct nv_dma_class), &object);
 295         if (ret)
 296                 return ret;
 297
 298         ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base);
 299         if (ret)
 300                 return ret;
 301
 302         ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync,
 303                                  NV_DMA_IN_MEMORY_CLASS,
 304                                  &(struct nv_dma_class) {
 305                                         .flags = NV_DMA_TARGET_VRAM |
 306                                                  NV_DMA_ACCESS_RDWR,
 307                                         .start = syncbuf + 0x0000,
 308                                         .limit = syncbuf + 0x0fff,
 309                                  }, sizeof(struct nv_dma_class), &object);
 310         if (ret)
 311                 return ret;
 312
 313         ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM,
 314                                  NV_DMA_IN_MEMORY_CLASS,
 315                                  &(struct nv_dma_class) {
 316                                         .flags = NV_DMA_TARGET_VRAM |
 317                                                  NV_DMA_ACCESS_RDWR,
 318                                         .start = 0,
 319                                         .limit = pfb->ram.size - 1,
 320                                  }, sizeof(struct nv_dma_class), &object);
 321         if (ret)
 322                 return ret;
 323
 324         if (nv_device(core)->card_type < NV_C0)
 325                 ret = nv50_dmac_create_fbdma(core, dmac->base.handle);
 326         else
 327         if (nv_device(core)->card_type < NV_D0)
 328                 ret = nvc0_dmac_create_fbdma(core, dmac->base.handle);
 329         else
 330                 ret = nvd0_dmac_create_fbdma(core, dmac->base.handle);
 331         return ret;
 332 }
 333
 334 struct nv50_mast {
 335         struct nv50_dmac base;
 336 };
 337
 338 struct nv50_curs {
 339         struct nv50_pioc base;
 340 };
 341
 342 struct nv50_sync {
 343         struct nv50_dmac base;
 344         u32 addr;
 345         u32 data;
 346 };
 347
 348 struct nv50_ovly {
 349         struct nv50_dmac base;
 350 };
 351
 352 struct nv50_oimm {
 353         struct nv50_pioc base;
 354 };
 355
 356 struct nv50_head {
 357         struct nouveau_crtc base;
 358         struct nv50_curs curs;
 359         struct nv50_sync sync;
 360         struct nv50_ovly ovly;
 361         struct nv50_oimm oimm;
 362 };
 363
 364 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 365 #define nv50_curs(c) (&nv50_head(c)->curs)
 366 #define nv50_sync(c) (&nv50_head(c)->sync)
 367 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 368 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 369 #define nv50_chan(c) (&(c)->base.base)
 370 #define nv50_vers(c) nv_mclass(nv50_chan(c)->user)
 371
 372 struct nv50_disp {
 373         struct nouveau_object *core;
 374         struct nv50_mast mast;
 375
 376         u32 modeset;
 377
 378         struct nouveau_bo *sync;
 379 };
 380
 381 static struct nv50_disp *
 382 nv50_disp(struct drm_device *dev)
 383 {
 384         return nouveau_display(dev)->priv;
 385 }
 386
 387 #define nv50_mast(d) (&nv50_disp(d)->mast)
 388
 389 static struct drm_crtc *
 390 nv50_display_crtc_get(struct drm_encoder *encoder)
 391 {
 392         return nouveau_encoder(encoder)->crtc;
 393 }
 394
 395 /******************************************************************************
 396  * EVO channel helpers
 397  *****************************************************************************/
 398 static u32 *
 399 evo_wait(void *evoc, int nr)
 400 {
 401         struct nv50_dmac *dmac = evoc;
 402         u32 put = nv_ro32(dmac->base.user, 0x0000) / 4;
 403
 404         mutex_lock(&dmac->lock);
 405         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 406                 dmac->ptr[put] = 0x20000000;
 407
 408                 nv_wo32(dmac->base.user, 0x0000, 0x00000000);
 409                 if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) {
 410                         mutex_unlock(&dmac->lock);
 411                         NV_ERROR(dmac->base.user, "channel stalled\n");
 412                         return NULL;
 413                 }
 414
 415                 put = 0;
 416         }
 417
 418         return dmac->ptr + put;
 419 }
 420
 421 static void
 422 evo_kick(u32 *push, void *evoc)
 423 {
 424         struct nv50_dmac *dmac = evoc;
 425         nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 426         mutex_unlock(&dmac->lock);
 427 }
 428
 429 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 430 #define evo_data(p,d)   *((p)++) = (d)
 431
 432 static bool
 433 evo_sync_wait(void *data)
 434 {
 435         if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
 436                 return true;
 437         usleep_range(1, 2);
 438         return false;
 439 }
 440
 441 static int
 442 evo_sync(struct drm_device *dev)
 443 {
 444         struct nouveau_device *device = nouveau_dev(dev);
 445         struct nv50_disp *disp = nv50_disp(dev);
 446         struct nv50_mast *mast = nv50_mast(dev);
 447         u32 *push = evo_wait(mast, 8);
 448         if (push) {
 449                 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 450                 evo_mthd(push, 0x0084, 1);
 451                 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 452                 evo_mthd(push, 0x0080, 2);
 453                 evo_data(push, 0x00000000);
 454                 evo_data(push, 0x00000000);
 455                 evo_kick(push, mast);
 456                 if (nv_wait_cb(device, evo_sync_wait, disp->sync))
 457                         return 0;
 458         }
 459
 460         return -EBUSY;
 461 }
 462
 463 /******************************************************************************
 464  * Page flipping channel
 465  *****************************************************************************/
 466 struct nouveau_bo *
 467 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
 468 {
 469         return nv50_disp(dev)->sync;
 470 }
 471
 472 struct nv50_display_flip {
 473         struct nv50_disp *disp;
 474         struct nv50_sync *chan;
 475 };
 476
 477 static bool
 478 nv50_display_flip_wait(void *data)
 479 {
 480         struct nv50_display_flip *flip = data;
 481         if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
 482                                               flip->chan->data)
 483                 return true;
 484         usleep_range(1, 2);
 485         return false;
 486 }
 487
 488 void
 489 nv50_display_flip_stop(struct drm_crtc *crtc)
 490 {
 491         struct nouveau_device *device = nouveau_dev(crtc->dev);
 492         struct nv50_display_flip flip = {
 493                 .disp = nv50_disp(crtc->dev),
 494                 .chan = nv50_sync(crtc),
 495         };
 496         u32 *push;
 497
 498         push = evo_wait(flip.chan, 8);
 499         if (push) {
 500                 evo_mthd(push, 0x0084, 1);
 501                 evo_data(push, 0x00000000);
 502                 evo_mthd(push, 0x0094, 1);
 503                 evo_data(push, 0x00000000);
 504                 evo_mthd(push, 0x00c0, 1);
 505                 evo_data(push, 0x00000000);
 506                 evo_mthd(push, 0x0080, 1);
 507                 evo_data(push, 0x00000000);
 508                 evo_kick(push, flip.chan);
 509         }
 510
 511         nv_wait_cb(device, nv50_display_flip_wait, &flip);
 512 }
 513
 514 int
 515 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 516                        struct nouveau_channel *chan, u32 swap_interval)
 517 {
 518         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 519         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 520         struct nv50_sync *sync = nv50_sync(crtc);
 521         int head = nv_crtc->index, ret;
 522         u32 *push;
 523
 524         swap_interval <<= 4;
 525         if (swap_interval == 0)
 526                 swap_interval |= 0x100;
 527         if (chan == NULL)
 528                 evo_sync(crtc->dev);
 529
 530         push = evo_wait(sync, 128);
 531         if (unlikely(push == NULL))
 532                 return -EBUSY;
 533
 534         if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
 535                 ret = RING_SPACE(chan, 8);
 536                 if (ret)
 537                         return ret;
 538
 539                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
 540                 OUT_RING  (chan, NvEvoSema0 + head);
 541                 OUT_RING  (chan, sync->addr ^ 0x10);
 542                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
 543                 OUT_RING  (chan, sync->data + 1);
 544                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
 545                 OUT_RING  (chan, sync->addr);
 546                 OUT_RING  (chan, sync->data);
 547         } else
 548         if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
 549                 u64 addr = nv84_fence_crtc(chan, head) + sync->addr;
 550                 ret = RING_SPACE(chan, 12);
 551                 if (ret)
 552                         return ret;
 553
 554                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
 555                 OUT_RING  (chan, chan->vram);
 556                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 557                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 558                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 559                 OUT_RING  (chan, sync->data + 1);
 560                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
 561                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 562                 OUT_RING  (chan, upper_32_bits(addr));
 563                 OUT_RING  (chan, lower_32_bits(addr));
 564                 OUT_RING  (chan, sync->data);
 565                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
 566         } else
 567         if (chan) {
 568                 u64 addr = nv84_fence_crtc(chan, head) + sync->addr;
 569                 ret = RING_SPACE(chan, 10);
 570                 if (ret)
 571                         return ret;
 572
 573                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 574                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 575                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 576                 OUT_RING  (chan, sync->data + 1);
 577                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
 578                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 579                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 580                 OUT_RING  (chan, upper_32_bits(addr));
 581                 OUT_RING  (chan, lower_32_bits(addr));
 582                 OUT_RING  (chan, sync->data);
 583                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
 584                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 585         }
 586
 587         if (chan) {
 588                 sync->addr ^= 0x10;
 589                 sync->data++;
 590                 FIRE_RING (chan);
 591         }
 592
 593         /* queue the flip */
 594         evo_mthd(push, 0x0100, 1);
 595         evo_data(push, 0xfffe0000);
 596         evo_mthd(push, 0x0084, 1);
 597         evo_data(push, swap_interval);
 598         if (!(swap_interval & 0x00000100)) {
 599                 evo_mthd(push, 0x00e0, 1);
 600                 evo_data(push, 0x40000000);
 601         }
 602         evo_mthd(push, 0x0088, 4);
 603         evo_data(push, sync->addr);
 604         evo_data(push, sync->data++);
 605         evo_data(push, sync->data);
 606         evo_data(push, NvEvoSync);
 607         evo_mthd(push, 0x00a0, 2);
 608         evo_data(push, 0x00000000);
 609         evo_data(push, 0x00000000);
 610         evo_mthd(push, 0x00c0, 1);
 611         evo_data(push, nv_fb->r_dma);
 612         evo_mthd(push, 0x0110, 2);
 613         evo_data(push, 0x00000000);
 614         evo_data(push, 0x00000000);
 615         if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
 616                 evo_mthd(push, 0x0800, 5);
 617                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 618                 evo_data(push, 0);
 619                 evo_data(push, (fb->height << 16) | fb->width);
 620                 evo_data(push, nv_fb->r_pitch);
 621                 evo_data(push, nv_fb->r_format);
 622         } else {
 623                 evo_mthd(push, 0x0400, 5);
 624                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 625                 evo_data(push, 0);
 626                 evo_data(push, (fb->height << 16) | fb->width);
 627                 evo_data(push, nv_fb->r_pitch);
 628                 evo_data(push, nv_fb->r_format);
 629         }
 630         evo_mthd(push, 0x0080, 1);
 631         evo_data(push, 0x00000000);
 632         evo_kick(push, sync);
 633         return 0;
 634 }
 635
 636 /******************************************************************************
 637  * CRTC
 638  *****************************************************************************/
 639 static int
 640 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 641 {
 642         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 643         struct nouveau_connector *nv_connector;
 644         struct drm_connector *connector;
 645         u32 *push, mode = 0x00;
 646
 647         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 648         connector = &nv_connector->base;
 649         if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 650                 if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
 651                         mode = DITHERING_MODE_DYNAMIC2X2;
 652         } else {
 653                 mode = nv_connector->dithering_mode;
 654         }
 655
 656         if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 657                 if (connector->display_info.bpc >= 8)
 658                         mode |= DITHERING_DEPTH_8BPC;
 659         } else {
 660                 mode |= nv_connector->dithering_depth;
 661         }
 662
 663         push = evo_wait(mast, 4);
 664         if (push) {
 665                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 666                         evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
 667                         evo_data(push, mode);
 668                 } else
 669                 if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
 670                         evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
 671                         evo_data(push, mode);
 672                 } else {
 673                         evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
 674                         evo_data(push, mode);
 675                 }
 676
 677                 if (update) {
 678                         evo_mthd(push, 0x0080, 1);
 679                         evo_data(push, 0x00000000);
 680                 }
 681                 evo_kick(push, mast);
 682         }
 683
 684         return 0;
 685 }
 686
 687 static int
 688 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 689 {
 690         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 691         struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 692         struct drm_crtc *crtc = &nv_crtc->base;
 693         struct nouveau_connector *nv_connector;
 694         int mode = DRM_MODE_SCALE_NONE;
 695         u32 oX, oY, *push;
 696
 697         /* start off at the resolution we programmed the crtc for, this
 698          * effectively handles NONE/FULL scaling
 699          */
 700         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 701         if (nv_connector && nv_connector->native_mode)
 702                 mode = nv_connector->scaling_mode;
 703
 704         if (mode != DRM_MODE_SCALE_NONE)
 705                 omode = nv_connector->native_mode;
 706         else
 707                 omode = umode;
 708
 709         oX = omode->hdisplay;
 710         oY = omode->vdisplay;
 711         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 712                 oY *= 2;
 713
 714         /* add overscan compensation if necessary, will keep the aspect
 715          * ratio the same as the backend mode unless overridden by the
 716          * user setting both hborder and vborder properties.
 717          */
 718         if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 719                              (nv_connector->underscan == UNDERSCAN_AUTO &&
 720                               nv_connector->edid &&
 721                               drm_detect_hdmi_monitor(nv_connector->edid)))) {
 722                 u32 bX = nv_connector->underscan_hborder;
 723                 u32 bY = nv_connector->underscan_vborder;
 724                 u32 aspect = (oY << 19) / oX;
 725
 726                 if (bX) {
 727                         oX -= (bX * 2);
 728                         if (bY) oY -= (bY * 2);
 729                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 730                 } else {
 731                         oX -= (oX >> 4) + 32;
 732                         if (bY) oY -= (bY * 2);
 733                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 734                 }
 735         }
 736
 737         /* handle CENTER/ASPECT scaling, taking into account the areas
 738          * removed already for overscan compensation
 739          */
 740         switch (mode) {
 741         case DRM_MODE_SCALE_CENTER:
 742                 oX = min((u32)umode->hdisplay, oX);
 743                 oY = min((u32)umode->vdisplay, oY);
 744                 /* fall-through */
 745         case DRM_MODE_SCALE_ASPECT:
 746                 if (oY < oX) {
 747                         u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 748                         oX = ((oY * aspect) + (aspect / 2)) >> 19;
 749                 } else {
 750                         u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 751                         oY = ((oX * aspect) + (aspect / 2)) >> 19;
 752                 }
 753                 break;
 754         default:
 755                 break;
 756         }
 757
 758         push = evo_wait(mast, 8);
 759         if (push) {
 760                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 761                         /*XXX: SCALE_CTRL_ACTIVE??? */
 762                         evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
 763                         evo_data(push, (oY << 16) | oX);
 764                         evo_data(push, (oY << 16) | oX);
 765                         evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
 766                         evo_data(push, 0x00000000);
 767                         evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
 768                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 769                 } else {
 770                         evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 771                         evo_data(push, (oY << 16) | oX);
 772                         evo_data(push, (oY << 16) | oX);
 773                         evo_data(push, (oY << 16) | oX);
 774                         evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 775                         evo_data(push, 0x00000000);
 776                         evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 777                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 778                 }
 779
 780                 evo_kick(push, mast);
 781
 782                 if (update) {
 783                         nv50_display_flip_stop(crtc);
 784                         nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
 785                 }
 786         }
 787
 788         return 0;
 789 }
 790
 791 static int
 792 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
 793 {
 794         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 795         u32 *push, hue, vib;
 796         int adj;
 797
 798         adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
 799         vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
 800         hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
 801
 802         push = evo_wait(mast, 16);
 803         if (push) {
 804                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 805                         evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
 806                         evo_data(push, (hue << 20) | (vib << 8));
 807                 } else {
 808                         evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
 809                         evo_data(push, (hue << 20) | (vib << 8));
 810                 }
 811
 812                 if (update) {
 813                         evo_mthd(push, 0x0080, 1);
 814                         evo_data(push, 0x00000000);
 815                 }
 816                 evo_kick(push, mast);
 817         }
 818
 819         return 0;
 820 }
 821
 822 static int
 823 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 824                     int x, int y, bool update)
 825 {
 826         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 827         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 828         u32 *push;
 829
 830         push = evo_wait(mast, 16);
 831         if (push) {
 832                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 833                         evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
 834                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 835                         evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
 836                         evo_data(push, (fb->height << 16) | fb->width);
 837                         evo_data(push, nvfb->r_pitch);
 838                         evo_data(push, nvfb->r_format);
 839                         evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
 840                         evo_data(push, (y << 16) | x);
 841                         if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
 842                                 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 843                                 evo_data(push, nvfb->r_dma);
 844                         }
 845                 } else {
 846                         evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 847                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 848                         evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 849                         evo_data(push, (fb->height << 16) | fb->width);
 850                         evo_data(push, nvfb->r_pitch);
 851                         evo_data(push, nvfb->r_format);
 852                         evo_data(push, nvfb->r_dma);
 853                         evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 854                         evo_data(push, (y << 16) | x);
 855                 }
 856
 857                 if (update) {
 858                         evo_mthd(push, 0x0080, 1);
 859                         evo_data(push, 0x00000000);
 860                 }
 861                 evo_kick(push, mast);
 862         }
 863
 864         nv_crtc->fb.tile_flags = nvfb->r_dma;
 865         return 0;
 866 }
 867
 868 static void
 869 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
 870 {
 871         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 872         u32 *push = evo_wait(mast, 16);
 873         if (push) {
 874                 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 875                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 876                         evo_data(push, 0x85000000);
 877                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 878                 } else
 879                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 880                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 881                         evo_data(push, 0x85000000);
 882                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 883                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 884                         evo_data(push, NvEvoVRAM);
 885                 } else {
 886                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 887                         evo_data(push, 0x85000000);
 888                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 889                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 890                         evo_data(push, NvEvoVRAM);
 891                 }
 892                 evo_kick(push, mast);
 893         }
 894 }
 895
 896 static void
 897 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
 898 {
 899         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 900         u32 *push = evo_wait(mast, 16);
 901         if (push) {
 902                 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 903                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 904                         evo_data(push, 0x05000000);
 905                 } else
 906                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 907                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 908                         evo_data(push, 0x05000000);
 909                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 910                         evo_data(push, 0x00000000);
 911                 } else {
 912                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 913                         evo_data(push, 0x05000000);
 914                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 915                         evo_data(push, 0x00000000);
 916                 }
 917                 evo_kick(push, mast);
 918         }
 919 }
 920
 921 static void
 922 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
 923 {
 924         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 925
 926         if (show)
 927                 nv50_crtc_cursor_show(nv_crtc);
 928         else
 929                 nv50_crtc_cursor_hide(nv_crtc);
 930
 931         if (update) {
 932                 u32 *push = evo_wait(mast, 2);
 933                 if (push) {
 934                         evo_mthd(push, 0x0080, 1);
 935                         evo_data(push, 0x00000000);
 936                         evo_kick(push, mast);
 937                 }
 938         }
 939 }
 940
 941 static void
 942 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
 943 {
 944 }
 945
 946 static void
 947 nv50_crtc_prepare(struct drm_crtc *crtc)
 948 {
 949         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 950         struct nv50_mast *mast = nv50_mast(crtc->dev);
 951         u32 *push;
 952
 953         nv50_display_flip_stop(crtc);
 954
 955         push = evo_wait(mast, 2);
 956         if (push) {
 957                 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 958                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 959                         evo_data(push, 0x00000000);
 960                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
 961                         evo_data(push, 0x40000000);
 962                 } else
 963                 if (nv50_vers(mast) <  NVD0_DISP_MAST_CLASS) {
 964                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 965                         evo_data(push, 0x00000000);
 966                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
 967                         evo_data(push, 0x40000000);
 968                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
 969                         evo_data(push, 0x00000000);
 970                 } else {
 971                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 972                         evo_data(push, 0x00000000);
 973                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
 974                         evo_data(push, 0x03000000);
 975                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 976                         evo_data(push, 0x00000000);
 977                 }
 978
 979                 evo_kick(push, mast);
 980         }
 981
 982         nv50_crtc_cursor_show_hide(nv_crtc, false, false);
 983 }
 984
 985 static void
 986 nv50_crtc_commit(struct drm_crtc *crtc)
 987 {
 988         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 989         struct nv50_mast *mast = nv50_mast(crtc->dev);
 990         u32 *push;
 991
 992         push = evo_wait(mast, 32);
 993         if (push) {
 994                 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 995                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 996                         evo_data(push, NvEvoVRAM_LP);
 997                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
 998                         evo_data(push, 0xc0000000);
 999                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1000                 } else
1001                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1002                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1003                         evo_data(push, nv_crtc->fb.tile_flags);
1004                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1005                         evo_data(push, 0xc0000000);
1006                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1007                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1008                         evo_data(push, NvEvoVRAM);
1009                 } else {
1010                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1011                         evo_data(push, nv_crtc->fb.tile_flags);
1012                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1013                         evo_data(push, 0x83000000);
1014                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1015                         evo_data(push, 0x00000000);
1016                         evo_data(push, 0x00000000);
1017                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1018                         evo_data(push, NvEvoVRAM);
1019                         evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1020                         evo_data(push, 0xffffff00);
1021                 }
1022
1023                 evo_kick(push, mast);
1024         }
1025
1026         nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
1027         nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
1028 }
1029
1030 static bool
1031 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1032                      struct drm_display_mode *adjusted_mode)
1033 {
1034         return true;
1035 }
1036
1037 static int
1038 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1039 {
1040         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
1041         int ret;
1042
1043         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
1044         if (ret)
1045                 return ret;
1046
1047         if (old_fb) {
1048                 nvfb = nouveau_framebuffer(old_fb);
1049                 nouveau_bo_unpin(nvfb->nvbo);
1050         }
1051
1052         return 0;
1053 }
1054
1055 static int
1056 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1057                    struct drm_display_mode *mode, int x, int y,
1058                    struct drm_framebuffer *old_fb)
1059 {
1060         struct nv50_mast *mast = nv50_mast(crtc->dev);
1061         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1062         struct nouveau_connector *nv_connector;
1063         u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1064         u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1065         u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1066         u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1067         u32 vblan2e = 0, vblan2s = 1;
1068         u32 *push;
1069         int ret;
1070
1071         hactive = mode->htotal;
1072         hsynce  = mode->hsync_end - mode->hsync_start - 1;
1073         hbackp  = mode->htotal - mode->hsync_end;
1074         hblanke = hsynce + hbackp;
1075         hfrontp = mode->hsync_start - mode->hdisplay;
1076         hblanks = mode->htotal - hfrontp - 1;
1077
1078         vactive = mode->vtotal * vscan / ilace;
1079         vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1080         vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1081         vblanke = vsynce + vbackp;
1082         vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1083         vblanks = vactive - vfrontp - 1;
1084         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1085                 vblan2e = vactive + vsynce + vbackp;
1086                 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1087                 vactive = (vactive * 2) + 1;
1088         }
1089
1090         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1091         if (ret)
1092                 return ret;
1093
1094         push = evo_wait(mast, 64);
1095         if (push) {
1096                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1097                         evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1098                         evo_data(push, 0x00800000 | mode->clock);
1099                         evo_data(push, (ilace == 2) ? 2 : 0);
1100                         evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1101                         evo_data(push, 0x00000000);
1102                         evo_data(push, (vactive << 16) | hactive);
1103                         evo_data(push, ( vsynce << 16) | hsynce);
1104                         evo_data(push, (vblanke << 16) | hblanke);
1105                         evo_data(push, (vblanks << 16) | hblanks);
1106                         evo_data(push, (vblan2e << 16) | vblan2s);
1107                         evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1108                         evo_data(push, 0x00000000);
1109                         evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1110                         evo_data(push, 0x00000311);
1111                         evo_data(push, 0x00000100);
1112                 } else {
1113                         evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1114                         evo_data(push, 0x00000000);
1115                         evo_data(push, (vactive << 16) | hactive);
1116                         evo_data(push, ( vsynce << 16) | hsynce);
1117                         evo_data(push, (vblanke << 16) | hblanke);
1118                         evo_data(push, (vblanks << 16) | hblanks);
1119                         evo_data(push, (vblan2e << 16) | vblan2s);
1120                         evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1121                         evo_data(push, 0x00000000); /* ??? */
1122                         evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1123                         evo_data(push, mode->clock * 1000);
1124                         evo_data(push, 0x00200000); /* ??? */
1125                         evo_data(push, mode->clock * 1000);
1126                         evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1127                         evo_data(push, 0x00000311);
1128                         evo_data(push, 0x00000100);
1129                 }
1130
1131                 evo_kick(push, mast);
1132         }
1133
1134         nv_connector = nouveau_crtc_connector_get(nv_crtc);
1135         nv50_crtc_set_dither(nv_crtc, false);
1136         nv50_crtc_set_scale(nv_crtc, false);
1137         nv50_crtc_set_color_vibrance(nv_crtc, false);
1138         nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
1139         return 0;
1140 }
1141
1142 static int
1143 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1144                         struct drm_framebuffer *old_fb)
1145 {
1146         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1147         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1148         int ret;
1149
1150         if (!crtc->fb) {
1151                 NV_DEBUG(drm, "No FB bound\n");
1152                 return 0;
1153         }
1154
1155         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1156         if (ret)
1157                 return ret;
1158
1159         nv50_display_flip_stop(crtc);
1160         nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
1161         nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
1162         return 0;
1163 }
1164
1165 static int
1166 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1167                                struct drm_framebuffer *fb, int x, int y,
1168                                enum mode_set_atomic state)
1169 {
1170         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1171         nv50_display_flip_stop(crtc);
1172         nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1173         return 0;
1174 }
1175
1176 static void
1177 nv50_crtc_lut_load(struct drm_crtc *crtc)
1178 {
1179         struct nv50_disp *disp = nv50_disp(crtc->dev);
1180         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1181         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1182         int i;
1183
1184         for (i = 0; i < 256; i++) {
1185                 u16 r = nv_crtc->lut.r[i] >> 2;
1186                 u16 g = nv_crtc->lut.g[i] >> 2;
1187                 u16 b = nv_crtc->lut.b[i] >> 2;
1188
1189                 if (nv_mclass(disp->core) < NVD0_DISP_CLASS) {
1190                         writew(r + 0x0000, lut + (i * 0x08) + 0);
1191                         writew(g + 0x0000, lut + (i * 0x08) + 2);
1192                         writew(b + 0x0000, lut + (i * 0x08) + 4);
1193                 } else {
1194                         writew(r + 0x6000, lut + (i * 0x20) + 0);
1195                         writew(g + 0x6000, lut + (i * 0x20) + 2);
1196                         writew(b + 0x6000, lut + (i * 0x20) + 4);
1197                 }
1198         }
1199 }
1200
1201 static int
1202 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1203                      uint32_t handle, uint32_t width, uint32_t height)
1204 {
1205         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1206         struct drm_device *dev = crtc->dev;
1207         struct drm_gem_object *gem;
1208         struct nouveau_bo *nvbo;
1209         bool visible = (handle != 0);
1210         int i, ret = 0;
1211
1212         if (visible) {
1213                 if (width != 64 || height != 64)
1214                         return -EINVAL;
1215
1216                 gem = drm_gem_object_lookup(dev, file_priv, handle);
1217                 if (unlikely(!gem))
1218                         return -ENOENT;
1219                 nvbo = nouveau_gem_object(gem);
1220
1221                 ret = nouveau_bo_map(nvbo);
1222                 if (ret == 0) {
1223                         for (i = 0; i < 64 * 64; i++) {
1224                                 u32 v = nouveau_bo_rd32(nvbo, i);
1225                                 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1226                         }
1227                         nouveau_bo_unmap(nvbo);
1228                 }
1229
1230                 drm_gem_object_unreference_unlocked(gem);
1231         }
1232
1233         if (visible != nv_crtc->cursor.visible) {
1234                 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
1235                 nv_crtc->cursor.visible = visible;
1236         }
1237
1238         return ret;
1239 }
1240
1241 static int
1242 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1243 {
1244         struct nv50_curs *curs = nv50_curs(crtc);
1245         struct nv50_chan *chan = nv50_chan(curs);
1246         nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff));
1247         nv_wo32(chan->user, 0x0080, 0x00000000);
1248         return 0;
1249 }
1250
1251 static void
1252 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1253                     uint32_t start, uint32_t size)
1254 {
1255         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1256         u32 end = max(start + size, (u32)256);
1257         u32 i;
1258
1259         for (i = start; i < end; i++) {
1260                 nv_crtc->lut.r[i] = r[i];
1261                 nv_crtc->lut.g[i] = g[i];
1262                 nv_crtc->lut.b[i] = b[i];
1263         }
1264
1265         nv50_crtc_lut_load(crtc);
1266 }
1267
1268 static void
1269 nv50_crtc_destroy(struct drm_crtc *crtc)
1270 {
1271         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1272         struct nv50_disp *disp = nv50_disp(crtc->dev);
1273         struct nv50_head *head = nv50_head(crtc);
1274         nv50_dmac_destroy(disp->core, &head->ovly.base);
1275         nv50_pioc_destroy(disp->core, &head->oimm.base);
1276         nv50_dmac_destroy(disp->core, &head->sync.base);
1277         nv50_pioc_destroy(disp->core, &head->curs.base);
1278         nouveau_bo_unmap(nv_crtc->cursor.nvbo);
1279         if (nv_crtc->cursor.nvbo)
1280                 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1281         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1282         nouveau_bo_unmap(nv_crtc->lut.nvbo);
1283         if (nv_crtc->lut.nvbo)
1284                 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1285         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1286         drm_crtc_cleanup(crtc);
1287         kfree(crtc);
1288 }
1289
1290 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1291         .dpms = nv50_crtc_dpms,
1292         .prepare = nv50_crtc_prepare,
1293         .commit = nv50_crtc_commit,
1294         .mode_fixup = nv50_crtc_mode_fixup,
1295         .mode_set = nv50_crtc_mode_set,
1296         .mode_set_base = nv50_crtc_mode_set_base,
1297         .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1298         .load_lut = nv50_crtc_lut_load,
1299 };
1300
1301 static const struct drm_crtc_funcs nv50_crtc_func = {
1302         .cursor_set = nv50_crtc_cursor_set,
1303         .cursor_move = nv50_crtc_cursor_move,
1304         .gamma_set = nv50_crtc_gamma_set,
1305         .set_config = drm_crtc_helper_set_config,
1306         .destroy = nv50_crtc_destroy,
1307         .page_flip = nouveau_crtc_page_flip,
1308 };
1309
1310 static void
1311 nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
1312 {
1313 }
1314
1315 static void
1316 nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
1317 {
1318 }
1319
1320 static int
1321 nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index)
1322 {
1323         struct nv50_disp *disp = nv50_disp(dev);
1324         struct nv50_head *head;
1325         struct drm_crtc *crtc;
1326         int ret, i;
1327
1328         head = kzalloc(sizeof(*head), GFP_KERNEL);
1329         if (!head)
1330                 return -ENOMEM;
1331
1332         head->base.index = index;
1333         head->base.set_dither = nv50_crtc_set_dither;
1334         head->base.set_scale = nv50_crtc_set_scale;
1335         head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1336         head->base.color_vibrance = 50;
1337         head->base.vibrant_hue = 0;
1338         head->base.cursor.set_offset = nv50_cursor_set_offset;
1339         head->base.cursor.set_pos = nv50_cursor_set_pos;
1340         for (i = 0; i < 256; i++) {
1341                 head->base.lut.r[i] = i << 8;
1342                 head->base.lut.g[i] = i << 8;
1343                 head->base.lut.b[i] = i << 8;
1344         }
1345
1346         crtc = &head->base.base;
1347         drm_crtc_init(dev, crtc, &nv50_crtc_func);
1348         drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1349         drm_mode_crtc_set_gamma_size(crtc, 256);
1350
1351         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1352                              0, 0x0000, NULL, &head->base.lut.nvbo);
1353         if (!ret) {
1354                 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
1355                 if (!ret) {
1356                         ret = nouveau_bo_map(head->base.lut.nvbo);
1357                         if (ret)
1358                                 nouveau_bo_unpin(head->base.lut.nvbo);
1359                 }
1360                 if (ret)
1361                         nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1362         }
1363
1364         if (ret)
1365                 goto out;
1366
1367         nv50_crtc_lut_load(crtc);
1368
1369         /* allocate cursor resources */
1370         ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index,
1371                               &(struct nv50_display_curs_class) {
1372                                         .head = index,
1373                               }, sizeof(struct nv50_display_curs_class),
1374                               &head->curs.base);
1375         if (ret)
1376                 goto out;
1377
1378         ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
1379                              0, 0x0000, NULL, &head->base.cursor.nvbo);
1380         if (!ret) {
1381                 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
1382                 if (!ret) {
1383                         ret = nouveau_bo_map(head->base.cursor.nvbo);
1384                         if (ret)
1385                                 nouveau_bo_unpin(head->base.lut.nvbo);
1386                 }
1387                 if (ret)
1388                         nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
1389         }
1390
1391         if (ret)
1392                 goto out;
1393
1394         /* allocate page flip / sync resources */
1395         ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index,
1396                               &(struct nv50_display_sync_class) {
1397                                         .pushbuf = EVO_PUSH_HANDLE(SYNC, index),
1398                                         .head = index,
1399                               }, sizeof(struct nv50_display_sync_class),
1400                               disp->sync->bo.offset, &head->sync.base);
1401         if (ret)
1402                 goto out;
1403
1404         head->sync.addr = EVO_FLIP_SEM0(index);
1405         head->sync.data = 0x00000000;
1406
1407         /* allocate overlay resources */
1408         ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
1409                               &(struct nv50_display_oimm_class) {
1410                                         .head = index,
1411                               }, sizeof(struct nv50_display_oimm_class),
1412                               &head->oimm.base);
1413         if (ret)
1414                 goto out;
1415
1416         ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index,
1417                               &(struct nv50_display_ovly_class) {
1418                                         .pushbuf = EVO_PUSH_HANDLE(OVLY, index),
1419                                         .head = index,
1420                               }, sizeof(struct nv50_display_ovly_class),
1421                               disp->sync->bo.offset, &head->ovly.base);
1422         if (ret)
1423                 goto out;
1424
1425 out:
1426         if (ret)
1427                 nv50_crtc_destroy(crtc);
1428         return ret;
1429 }
1430
1431 /******************************************************************************
1432  * DAC
1433  *****************************************************************************/
1434 static void
1435 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1436 {
1437         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1438         struct nv50_disp *disp = nv50_disp(encoder->dev);
1439         int or = nv_encoder->or;
1440         u32 dpms_ctrl;
1441
1442         dpms_ctrl = 0x00000000;
1443         if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
1444                 dpms_ctrl |= 0x00000001;
1445         if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
1446                 dpms_ctrl |= 0x00000004;
1447
1448         nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl);
1449 }
1450
1451 static bool
1452 nv50_dac_mode_fixup(struct drm_encoder *encoder,
1453                     const struct drm_display_mode *mode,
1454                     struct drm_display_mode *adjusted_mode)
1455 {
1456         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1457         struct nouveau_connector *nv_connector;
1458
1459         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1460         if (nv_connector && nv_connector->native_mode) {
1461                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1462                         int id = adjusted_mode->base.id;
1463                         *adjusted_mode = *nv_connector->native_mode;
1464                         adjusted_mode->base.id = id;
1465                 }
1466         }
1467
1468         return true;
1469 }
1470
1471 static void
1472 nv50_dac_commit(struct drm_encoder *encoder)
1473 {
1474 }
1475
1476 static void
1477 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1478                   struct drm_display_mode *adjusted_mode)
1479 {
1480         struct nv50_mast *mast = nv50_mast(encoder->dev);
1481         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1482         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1483         u32 *push;
1484
1485         nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1486
1487         push = evo_wait(mast, 8);
1488         if (push) {
1489                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1490                         u32 syncs = 0x00000000;
1491
1492                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1493                                 syncs |= 0x00000001;
1494                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1495                                 syncs |= 0x00000002;
1496
1497                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1498                         evo_data(push, 1 << nv_crtc->index);
1499                         evo_data(push, syncs);
1500                 } else {
1501                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1502                         u32 syncs = 0x00000001;
1503
1504                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1505                                 syncs |= 0x00000008;
1506                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1507                                 syncs |= 0x00000010;
1508
1509                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1510                                 magic |= 0x00000001;
1511
1512                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1513                         evo_data(push, syncs);
1514                         evo_data(push, magic);
1515                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1516                         evo_data(push, 1 << nv_crtc->index);
1517                 }
1518
1519                 evo_kick(push, mast);
1520         }
1521
1522         nv_encoder->crtc = encoder->crtc;
1523 }
1524
1525 static void
1526 nv50_dac_disconnect(struct drm_encoder *encoder)
1527 {
1528         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1529         struct nv50_mast *mast = nv50_mast(encoder->dev);
1530         const int or = nv_encoder->or;
1531         u32 *push;
1532
1533         if (nv_encoder->crtc) {
1534                 nv50_crtc_prepare(nv_encoder->crtc);
1535
1536                 push = evo_wait(mast, 4);
1537                 if (push) {
1538                         if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1539                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1540                                 evo_data(push, 0x00000000);
1541                         } else {
1542                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1543                                 evo_data(push, 0x00000000);
1544                         }
1545                         evo_kick(push, mast);
1546                 }
1547         }
1548
1549         nv_encoder->crtc = NULL;
1550 }
1551
1552 static enum drm_connector_status
1553 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1554 {
1555         struct nv50_disp *disp = nv50_disp(encoder->dev);
1556         int ret, or = nouveau_encoder(encoder)->or;
1557         u32 load = nouveau_drm(encoder->dev)->vbios.dactestval;
1558         if (load == 0)
1559                 load = 340;
1560
1561         ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
1562         if (ret || load != 7)
1563                 return connector_status_disconnected;
1564
1565         return connector_status_connected;
1566 }
1567
1568 static void
1569 nv50_dac_destroy(struct drm_encoder *encoder)
1570 {
1571         drm_encoder_cleanup(encoder);
1572         kfree(encoder);
1573 }
1574
1575 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1576         .dpms = nv50_dac_dpms,
1577         .mode_fixup = nv50_dac_mode_fixup,
1578         .prepare = nv50_dac_disconnect,
1579         .commit = nv50_dac_commit,
1580         .mode_set = nv50_dac_mode_set,
1581         .disable = nv50_dac_disconnect,
1582         .get_crtc = nv50_display_crtc_get,
1583         .detect = nv50_dac_detect
1584 };
1585
1586 static const struct drm_encoder_funcs nv50_dac_func = {
1587         .destroy = nv50_dac_destroy,
1588 };
1589
1590 static int
1591 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1592 {
1593         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1594         struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1595         struct nouveau_encoder *nv_encoder;
1596         struct drm_encoder *encoder;
1597         int type = DRM_MODE_ENCODER_DAC;
1598
1599         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1600         if (!nv_encoder)
1601                 return -ENOMEM;
1602         nv_encoder->dcb = dcbe;
1603         nv_encoder->or = ffs(dcbe->or) - 1;
1604         nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1605
1606         encoder = to_drm_encoder(nv_encoder);
1607         encoder->possible_crtcs = dcbe->heads;
1608         encoder->possible_clones = 0;
1609         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
1610         drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1611
1612         drm_mode_connector_attach_encoder(connector, encoder);
1613         return 0;
1614 }
1615
1616 /******************************************************************************
1617  * Audio
1618  *****************************************************************************/
1619 static void
1620 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1621 {
1622         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1623         struct nouveau_connector *nv_connector;
1624         struct nv50_disp *disp = nv50_disp(encoder->dev);
1625
1626         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1627         if (!drm_detect_monitor_audio(nv_connector->edid))
1628                 return;
1629
1630         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1631
1632         nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
1633                             nv_connector->base.eld,
1634                             nv_connector->base.eld[2] * 4);
1635 }
1636
1637 static void
1638 nv50_audio_disconnect(struct drm_encoder *encoder)
1639 {
1640         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1641         struct nv50_disp *disp = nv50_disp(encoder->dev);
1642
1643         nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
1644 }
1645
1646 /******************************************************************************
1647  * HDMI
1648  *****************************************************************************/
1649 static void
1650 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1651 {
1652         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1653         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1654         struct nouveau_connector *nv_connector;
1655         struct nv50_disp *disp = nv50_disp(encoder->dev);
1656         const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1657         u32 rekey = 56; /* binary driver, and tegra constant */
1658         u32 max_ac_packet;
1659
1660         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1661         if (!drm_detect_hdmi_monitor(nv_connector->edid))
1662                 return;
1663
1664         max_ac_packet  = mode->htotal - mode->hdisplay;
1665         max_ac_packet -= rekey;
1666         max_ac_packet -= 18; /* constant from tegra */
1667         max_ac_packet /= 32;
1668
1669         nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff,
1670                             NV84_DISP_SOR_HDMI_PWR_STATE_ON |
1671                             (max_ac_packet << 16) | rekey);
1672
1673         nv50_audio_mode_set(encoder, mode);
1674 }
1675
1676 static void
1677 nv50_hdmi_disconnect(struct drm_encoder *encoder)
1678 {
1679         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1680         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1681         struct nv50_disp *disp = nv50_disp(encoder->dev);
1682         const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1683
1684         nv50_audio_disconnect(encoder);
1685
1686         nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000);
1687 }
1688
1689 /******************************************************************************
1690  * SOR
1691  *****************************************************************************/
1692 static void
1693 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1694 {
1695         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1696         struct drm_device *dev = encoder->dev;
1697         struct nv50_disp *disp = nv50_disp(dev);
1698         struct drm_encoder *partner;
1699         int or = nv_encoder->or;
1700
1701         nv_encoder->last_dpms = mode;
1702
1703         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1704                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1705
1706                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1707                         continue;
1708
1709                 if (nv_partner != nv_encoder &&
1710                     nv_partner->dcb->or == nv_encoder->dcb->or) {
1711                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1712                                 return;
1713                         break;
1714                 }
1715         }
1716
1717         nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON));
1718 }
1719
1720 static bool
1721 nv50_sor_mode_fixup(struct drm_encoder *encoder,
1722                     const struct drm_display_mode *mode,
1723                     struct drm_display_mode *adjusted_mode)
1724 {
1725         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1726         struct nouveau_connector *nv_connector;
1727
1728         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1729         if (nv_connector && nv_connector->native_mode) {
1730                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1731                         int id = adjusted_mode->base.id;
1732                         *adjusted_mode = *nv_connector->native_mode;
1733                         adjusted_mode->base.id = id;
1734                 }
1735         }
1736
1737         return true;
1738 }
1739
1740 static void
1741 nv50_sor_disconnect(struct drm_encoder *encoder)
1742 {
1743         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1744         struct nv50_mast *mast = nv50_mast(encoder->dev);
1745         const int or = nv_encoder->or;
1746         u32 *push;
1747
1748         if (nv_encoder->crtc) {
1749                 nv50_crtc_prepare(nv_encoder->crtc);
1750
1751                 push = evo_wait(mast, 4);
1752                 if (push) {
1753                         if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1754                                 evo_mthd(push, 0x0600 + (or * 0x40), 1);
1755                                 evo_data(push, 0x00000000);
1756                         } else {
1757                                 evo_mthd(push, 0x0200 + (or * 0x20), 1);
1758                                 evo_data(push, 0x00000000);
1759                         }
1760                         evo_kick(push, mast);
1761                 }
1762
1763                 nv50_hdmi_disconnect(encoder);
1764         }
1765
1766         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1767         nv_encoder->crtc = NULL;
1768 }
1769
1770 static void
1771 nv50_sor_commit(struct drm_encoder *encoder)
1772 {
1773 }
1774
1775 static void
1776 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1777                   struct drm_display_mode *mode)
1778 {
1779         struct nv50_disp *disp = nv50_disp(encoder->dev);
1780         struct nv50_mast *mast = nv50_mast(encoder->dev);
1781         struct drm_device *dev = encoder->dev;
1782         struct nouveau_drm *drm = nouveau_drm(dev);
1783         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1784         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1785         struct nouveau_connector *nv_connector;
1786         struct nvbios *bios = &drm->vbios;
1787         u32 *push, lvds = 0;
1788         u8 owner = 1 << nv_crtc->index;
1789         u8 proto = 0xf;
1790         u8 depth = 0x0;
1791
1792         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1793         switch (nv_encoder->dcb->type) {
1794         case DCB_OUTPUT_TMDS:
1795                 if (nv_encoder->dcb->sorconf.link & 1) {
1796                         if (mode->clock < 165000)
1797                                 proto = 0x1;
1798                         else
1799                                 proto = 0x5;
1800                 } else {
1801                         proto = 0x2;
1802                 }
1803
1804                 nv50_hdmi_mode_set(encoder, mode);
1805                 break;
1806         case DCB_OUTPUT_LVDS:
1807                 proto = 0x0;
1808
1809                 if (bios->fp_no_ddc) {
1810                         if (bios->fp.dual_link)
1811                                 lvds |= 0x0100;
1812                         if (bios->fp.if_is_24bit)
1813                                 lvds |= 0x0200;
1814                 } else {
1815                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1816                                 if (((u8 *)nv_connector->edid)[121] == 2)
1817                                         lvds |= 0x0100;
1818                         } else
1819                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1820                                 lvds |= 0x0100;
1821                         }
1822
1823                         if (lvds & 0x0100) {
1824                                 if (bios->fp.strapless_is_24bit & 2)
1825                                         lvds |= 0x0200;
1826                         } else {
1827                                 if (bios->fp.strapless_is_24bit & 1)
1828                                         lvds |= 0x0200;
1829                         }
1830
1831                         if (nv_connector->base.display_info.bpc == 8)
1832                                 lvds |= 0x0200;
1833                 }
1834
1835                 nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds);
1836                 break;
1837         case DCB_OUTPUT_DP:
1838                 if (nv_connector->base.display_info.bpc == 6) {
1839                         nv_encoder->dp.datarate = mode->clock * 18 / 8;
1840                         depth = 0x2;
1841                 } else
1842                 if (nv_connector->base.display_info.bpc == 8) {
1843                         nv_encoder->dp.datarate = mode->clock * 24 / 8;
1844                         depth = 0x5;
1845                 } else {
1846                         nv_encoder->dp.datarate = mode->clock * 30 / 8;
1847                         depth = 0x6;
1848                 }
1849
1850                 if (nv_encoder->dcb->sorconf.link & 1)
1851                         proto = 0x8;
1852                 else
1853                         proto = 0x9;
1854                 break;
1855         default:
1856                 BUG_ON(1);
1857                 break;
1858         }
1859
1860         nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
1861
1862         push = evo_wait(nv50_mast(dev), 8);
1863         if (push) {
1864                 if (nv50_vers(mast) < NVD0_DISP_CLASS) {
1865                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
1866                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1867                                 ctrl |= 0x00001000;
1868                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1869                                 ctrl |= 0x00002000;
1870                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1);
1871                         evo_data(push, ctrl);
1872                 } else {
1873                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1874                         u32 syncs = 0x00000001;
1875
1876                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1877                                 syncs |= 0x00000008;
1878                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1879                                 syncs |= 0x00000010;
1880
1881                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1882                                 magic |= 0x00000001;
1883
1884                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1885                         evo_data(push, syncs | (depth << 6));
1886                         evo_data(push, magic);
1887                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1);
1888                         evo_data(push, owner | (proto << 8));
1889                 }
1890
1891                 evo_kick(push, mast);
1892         }
1893
1894         nv_encoder->crtc = encoder->crtc;
1895 }
1896
1897 static void
1898 nv50_sor_destroy(struct drm_encoder *encoder)
1899 {
1900         drm_encoder_cleanup(encoder);
1901         kfree(encoder);
1902 }
1903
1904 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
1905         .dpms = nv50_sor_dpms,
1906         .mode_fixup = nv50_sor_mode_fixup,
1907         .prepare = nv50_sor_disconnect,
1908         .commit = nv50_sor_commit,
1909         .mode_set = nv50_sor_mode_set,
1910         .disable = nv50_sor_disconnect,
1911         .get_crtc = nv50_display_crtc_get,
1912 };
1913
1914 static const struct drm_encoder_funcs nv50_sor_func = {
1915         .destroy = nv50_sor_destroy,
1916 };
1917
1918 static int
1919 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1920 {
1921         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1922         struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1923         struct nouveau_encoder *nv_encoder;
1924         struct drm_encoder *encoder;
1925         int type;
1926
1927         switch (dcbe->type) {
1928         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1929         case DCB_OUTPUT_TMDS:
1930         case DCB_OUTPUT_DP:
1931         default:
1932                 type = DRM_MODE_ENCODER_TMDS;
1933                 break;
1934         }
1935
1936         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1937         if (!nv_encoder)
1938                 return -ENOMEM;
1939         nv_encoder->dcb = dcbe;
1940         nv_encoder->or = ffs(dcbe->or) - 1;
1941         nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1942         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1943
1944         encoder = to_drm_encoder(nv_encoder);
1945         encoder->possible_crtcs = dcbe->heads;
1946         encoder->possible_clones = 0;
1947         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
1948         drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
1949
1950         drm_mode_connector_attach_encoder(connector, encoder);
1951         return 0;
1952 }
1953
1954 /******************************************************************************
1955  * PIOR
1956  *****************************************************************************/
1957
1958 static void
1959 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
1960 {
1961         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1962         struct nv50_disp *disp = nv50_disp(encoder->dev);
1963         u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or;
1964         u32 ctrl = (mode == DRM_MODE_DPMS_ON);
1965         nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl);
1966 }
1967
1968 static bool
1969 nv50_pior_mode_fixup(struct drm_encoder *encoder,
1970                      const struct drm_display_mode *mode,
1971                      struct drm_display_mode *adjusted_mode)
1972 {
1973         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1974         struct nouveau_connector *nv_connector;
1975
1976         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1977         if (nv_connector && nv_connector->native_mode) {
1978                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1979                         int id = adjusted_mode->base.id;
1980                         *adjusted_mode = *nv_connector->native_mode;
1981                         adjusted_mode->base.id = id;
1982                 }
1983         }
1984
1985         adjusted_mode->clock *= 2;
1986         return true;
1987 }
1988
1989 static void
1990 nv50_pior_commit(struct drm_encoder *encoder)
1991 {
1992 }
1993
1994 static void
1995 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1996                    struct drm_display_mode *adjusted_mode)
1997 {
1998         struct nv50_mast *mast = nv50_mast(encoder->dev);
1999         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2000         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2001         struct nouveau_connector *nv_connector;
2002         u8 owner = 1 << nv_crtc->index;
2003         u8 proto, depth;
2004         u32 *push;
2005
2006         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2007         switch (nv_connector->base.display_info.bpc) {
2008         case 10: depth = 0x6; break;
2009         case  8: depth = 0x5; break;
2010         case  6: depth = 0x2; break;
2011         default: depth = 0x0; break;
2012         }
2013
2014         switch (nv_encoder->dcb->type) {
2015         case DCB_OUTPUT_TMDS:
2016         case DCB_OUTPUT_DP:
2017                 proto = 0x0;
2018                 break;
2019         default:
2020                 BUG_ON(1);
2021                 break;
2022         }
2023
2024         nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2025
2026         push = evo_wait(mast, 8);
2027         if (push) {
2028                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2029                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
2030                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2031                                 ctrl |= 0x00001000;
2032                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2033                                 ctrl |= 0x00002000;
2034                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2035                         evo_data(push, ctrl);
2036                 }
2037
2038                 evo_kick(push, mast);
2039         }
2040
2041         nv_encoder->crtc = encoder->crtc;
2042 }
2043
2044 static void
2045 nv50_pior_disconnect(struct drm_encoder *encoder)
2046 {
2047         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2048         struct nv50_mast *mast = nv50_mast(encoder->dev);
2049         const int or = nv_encoder->or;
2050         u32 *push;
2051
2052         if (nv_encoder->crtc) {
2053                 nv50_crtc_prepare(nv_encoder->crtc);
2054
2055                 push = evo_wait(mast, 4);
2056                 if (push) {
2057                         if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2058                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2059                                 evo_data(push, 0x00000000);
2060                         }
2061                         evo_kick(push, mast);
2062                 }
2063         }
2064
2065         nv_encoder->crtc = NULL;
2066 }
2067
2068 static void
2069 nv50_pior_destroy(struct drm_encoder *encoder)
2070 {
2071         drm_encoder_cleanup(encoder);
2072         kfree(encoder);
2073 }
2074
2075 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2076         .dpms = nv50_pior_dpms,
2077         .mode_fixup = nv50_pior_mode_fixup,
2078         .prepare = nv50_pior_disconnect,
2079         .commit = nv50_pior_commit,
2080         .mode_set = nv50_pior_mode_set,
2081         .disable = nv50_pior_disconnect,
2082         .get_crtc = nv50_display_crtc_get,
2083 };
2084
2085 static const struct drm_encoder_funcs nv50_pior_func = {
2086         .destroy = nv50_pior_destroy,
2087 };
2088
2089 static int
2090 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2091 {
2092         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2093         struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
2094         struct nouveau_i2c_port *ddc = NULL;
2095         struct nouveau_encoder *nv_encoder;
2096         struct drm_encoder *encoder;
2097         int type;
2098
2099         switch (dcbe->type) {
2100         case DCB_OUTPUT_TMDS:
2101                 ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2102                 type = DRM_MODE_ENCODER_TMDS;
2103                 break;
2104         case DCB_OUTPUT_DP:
2105                 ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2106                 type = DRM_MODE_ENCODER_TMDS;
2107                 break;
2108         default:
2109                 return -ENODEV;
2110         }
2111
2112         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2113         if (!nv_encoder)
2114                 return -ENOMEM;
2115         nv_encoder->dcb = dcbe;
2116         nv_encoder->or = ffs(dcbe->or) - 1;
2117         nv_encoder->i2c = ddc;
2118
2119         encoder = to_drm_encoder(nv_encoder);
2120         encoder->possible_crtcs = dcbe->heads;
2121         encoder->possible_clones = 0;
2122         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2123         drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2124
2125         drm_mode_connector_attach_encoder(connector, encoder);
2126         return 0;
2127 }
2128
2129 /******************************************************************************
2130  * Init
2131  *****************************************************************************/
2132 void
2133 nv50_display_fini(struct drm_device *dev)
2134 {
2135 }
2136
2137 int
2138 nv50_display_init(struct drm_device *dev)
2139 {
2140         struct nv50_disp *disp = nv50_disp(dev);
2141         struct drm_crtc *crtc;
2142         u32 *push;
2143
2144         push = evo_wait(nv50_mast(dev), 32);
2145         if (!push)
2146                 return -EBUSY;
2147
2148         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2149                 struct nv50_sync *sync = nv50_sync(crtc);
2150                 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2151         }
2152
2153         evo_mthd(push, 0x0088, 1);
2154         evo_data(push, NvEvoSync);
2155         evo_kick(push, nv50_mast(dev));
2156         return 0;
2157 }
2158
2159 void
2160 nv50_display_destroy(struct drm_device *dev)
2161 {
2162         struct nv50_disp *disp = nv50_disp(dev);
2163
2164         nv50_dmac_destroy(disp->core, &disp->mast.base);
2165
2166         nouveau_bo_unmap(disp->sync);
2167         if (disp->sync)
2168                 nouveau_bo_unpin(disp->sync);
2169         nouveau_bo_ref(NULL, &disp->sync);
2170
2171         nouveau_display(dev)->priv = NULL;
2172         kfree(disp);
2173 }
2174
2175 int
2176 nv50_display_create(struct drm_device *dev)
2177 {
2178         static const u16 oclass[] = {
2179                 NVF0_DISP_CLASS,
2180                 NVE0_DISP_CLASS,
2181                 NVD0_DISP_CLASS,
2182                 NVA3_DISP_CLASS,
2183                 NV94_DISP_CLASS,
2184                 NVA0_DISP_CLASS,
2185                 NV84_DISP_CLASS,
2186                 NV50_DISP_CLASS,
2187         };
2188         struct nouveau_device *device = nouveau_dev(dev);
2189         struct nouveau_drm *drm = nouveau_drm(dev);
2190         struct dcb_table *dcb = &drm->vbios.dcb;
2191         struct drm_connector *connector, *tmp;
2192         struct nv50_disp *disp;
2193         struct dcb_output *dcbe;
2194         int crtcs, ret, i;
2195
2196         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2197         if (!disp)
2198                 return -ENOMEM;
2199
2200         nouveau_display(dev)->priv = disp;
2201         nouveau_display(dev)->dtor = nv50_display_destroy;
2202         nouveau_display(dev)->init = nv50_display_init;
2203         nouveau_display(dev)->fini = nv50_display_fini;
2204
2205         /* small shared memory area we use for notifiers and semaphores */
2206         ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2207                              0, 0x0000, NULL, &disp->sync);
2208         if (!ret) {
2209                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2210                 if (!ret) {
2211                         ret = nouveau_bo_map(disp->sync);
2212                         if (ret)
2213                                 nouveau_bo_unpin(disp->sync);
2214                 }
2215                 if (ret)
2216                         nouveau_bo_ref(NULL, &disp->sync);
2217         }
2218
2219         if (ret)
2220                 goto out;
2221
2222         /* attempt to allocate a supported evo display class */
2223         ret = -ENODEV;
2224         for (i = 0; ret && i < ARRAY_SIZE(oclass); i++) {
2225                 ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE,
2226                                          0xd1500000, oclass[i], NULL, 0,
2227                                          &disp->core);
2228         }
2229
2230         if (ret)
2231                 goto out;
2232
2233         /* allocate master evo channel */
2234         ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0,
2235                               &(struct nv50_display_mast_class) {
2236                                         .pushbuf = EVO_PUSH_HANDLE(MAST, 0),
2237                               }, sizeof(struct nv50_display_mast_class),
2238                               disp->sync->bo.offset, &disp->mast.base);
2239         if (ret)
2240                 goto out;
2241
2242         /* create crtc objects to represent the hw heads */
2243         if (nv_mclass(disp->core) >= NVD0_DISP_CLASS)
2244                 crtcs = nv_rd32(device, 0x022448);
2245         else
2246                 crtcs = 2;
2247
2248         for (i = 0; i < crtcs; i++) {
2249                 ret = nv50_crtc_create(dev, disp->core, i);
2250                 if (ret)
2251                         goto out;
2252         }
2253
2254         /* create encoder/connector objects based on VBIOS DCB table */
2255         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2256                 connector = nouveau_connector_create(dev, dcbe->connector);
2257                 if (IS_ERR(connector))
2258                         continue;
2259
2260                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2261                         switch (dcbe->type) {
2262                         case DCB_OUTPUT_TMDS:
2263                         case DCB_OUTPUT_LVDS:
2264                         case DCB_OUTPUT_DP:
2265                                 ret = nv50_sor_create(connector, dcbe);
2266                                 break;
2267                         case DCB_OUTPUT_ANALOG:
2268                                 ret = nv50_dac_create(connector, dcbe);
2269                                 break;
2270                         default:
2271                                 ret = -ENODEV;
2272                                 break;
2273                         }
2274                 } else {
2275                         ret = nv50_pior_create(connector, dcbe);
2276                 }
2277
2278                 if (ret) {
2279                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2280                                      dcbe->location, dcbe->type,
2281                                      ffs(dcbe->or) - 1, ret);
2282                         ret = 0;
2283                 }
2284         }
2285
2286         /* cull any connectors we created that don't have an encoder */
2287         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2288                 if (connector->encoder_ids[0])
2289                         continue;
2290
2291                 NV_WARN(drm, "%s has no encoders, removing\n",
2292                         drm_get_connector_name(connector));
2293                 connector->funcs->destroy(connector);
2294         }
2295
2296 out:
2297         if (ret)
2298                 nv50_display_destroy(dev);
2299         return ret;
2300 }