drivers/gpu/drm/panel/panel-simple.c

   1 /*
   2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/backlight.h>
  25 #include <linux/gpio/consumer.h>
  26 #include <linux/module.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_mipi_dsi.h>
  34 #include <drm/drm_panel.h>
  35
  36 #include <video/display_timing.h>
  37 #include <video/videomode.h>
  38
  39 struct panel_desc {
  40         const struct drm_display_mode *modes;
  41         unsigned int num_modes;
  42         const struct display_timing *timings;
  43         unsigned int num_timings;
  44
  45         unsigned int bpc;
  46
  47         /**
  48          * @width: width (in millimeters) of the panel's active display area
  49          * @height: height (in millimeters) of the panel's active display area
  50          */
  51         struct {
  52                 unsigned int width;
  53                 unsigned int height;
  54         } size;
  55
  56         /**
  57          * @prepare: the time (in milliseconds) that it takes for the panel to
  58          *           become ready and start receiving video data
  59          * @enable: the time (in milliseconds) that it takes for the panel to
  60          *          display the first valid frame after starting to receive
  61          *          video data
  62          * @disable: the time (in milliseconds) that it takes for the panel to
  63          *           turn the display off (no content is visible)
  64          * @unprepare: the time (in milliseconds) that it takes for the panel
  65          *             to power itself down completely
  66          */
  67         struct {
  68                 unsigned int prepare;
  69                 unsigned int enable;
  70                 unsigned int disable;
  71                 unsigned int unprepare;
  72         } delay;
  73
  74         u32 bus_format;
  75         u32 bus_flags;
  76 };
  77
  78 struct panel_simple {
  79         struct drm_panel base;
  80         bool prepared;
  81         bool enabled;
  82
  83         const struct panel_desc *desc;
  84
  85         struct backlight_device *backlight;
  86         struct regulator *supply;
  87         struct i2c_adapter *ddc;
  88
  89         struct gpio_desc *enable_gpio;
  90
  91         u32 bus_fmt_override;
  92         u32 quirks;
  93 };
  94
  95 enum {
  96         PANEL_QUIRK_PIXDATA_NEGEDGE = BIT(0),
  97         PANEL_QUIRK_PIXDATA_POSEDGE = BIT(1),
  98 };
  99
 100 #define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
 101         .clock = freq,                                                  \
 102         .hdisplay = ha,                                                 \
 103         .hsync_start = (ha) + (hfp),                                    \
 104         .hsync_end = (ha) + (hfp) + (hs),                               \
 105         .htotal = (ha) + (hfp) + (hs) + (hbp),                          \
 106         .vdisplay = (va),                                               \
 107         .vsync_start = (va) + (vfp),                                    \
 108         .vsync_end = (va) + (vfp) + (vs),                               \
 109         .vtotal = (va) + (vfp) + (vs) + (vbp),                          \
 110         .vrefresh = vr,                                                 \
 111         .flags = flgs,                                                  \
 112 }
 113
 114 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
 115 {
 116         return container_of(panel, struct panel_simple, base);
 117 }
 118
 119 static inline void panel_simple_apply_quirks(struct panel_simple *panel,
 120                                              struct drm_display_info *info)
 121 {
 122         if (panel->quirks & PANEL_QUIRK_PIXDATA_NEGEDGE)
 123                 info->bus_flags |= DRM_BUS_FLAG_PIXDATA_NEGEDGE;
 124         if (panel->quirks & PANEL_QUIRK_PIXDATA_POSEDGE)
 125                 info->bus_flags |= DRM_BUS_FLAG_PIXDATA_POSEDGE;
 126 }
 127
 128 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
 129 {
 130         struct drm_connector *connector = panel->base.connector;
 131         struct drm_device *drm = panel->base.drm;
 132         struct drm_display_mode *mode;
 133         unsigned int i, num = 0;
 134
 135         if (!panel->desc)
 136                 return 0;
 137
 138         for (i = 0; i < panel->desc->num_timings; i++) {
 139                 const struct display_timing *dt = &panel->desc->timings[i];
 140                 struct videomode vm;
 141
 142                 videomode_from_timing(dt, &vm);
 143                 mode = drm_mode_create(drm);
 144                 if (!mode) {
 145                         dev_err(drm->dev, "failed to add mode %ux%u\n",
 146                                 dt->hactive.typ, dt->vactive.typ);
 147                         continue;
 148                 }
 149
 150                 drm_display_mode_from_videomode(&vm, mode);
 151
 152                 mode->type |= DRM_MODE_TYPE_DRIVER;
 153
 154                 if (panel->desc->num_timings == 1)
 155                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 156
 157                 drm_mode_probed_add(connector, mode);
 158                 num++;
 159         }
 160
 161         for (i = 0; i < panel->desc->num_modes; i++) {
 162                 const struct drm_display_mode *m = &panel->desc->modes[i];
 163
 164                 mode = drm_mode_duplicate(drm, m);
 165                 if (!mode) {
 166                         dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
 167                                 m->hdisplay, m->vdisplay, m->vrefresh);
 168                         continue;
 169                 }
 170
 171                 mode->type |= DRM_MODE_TYPE_DRIVER;
 172
 173                 if (panel->desc->num_modes == 1)
 174                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 175
 176                 drm_mode_set_name(mode);
 177
 178                 drm_mode_probed_add(connector, mode);
 179                 num++;
 180         }
 181
 182         connector->display_info.bpc = panel->desc->bpc;
 183         connector->display_info.width_mm = panel->desc->size.width;
 184         connector->display_info.height_mm = panel->desc->size.height;
 185
 186         if (panel->bus_fmt_override)
 187                 drm_display_info_set_bus_formats(&connector->display_info,
 188                                                  &panel->bus_fmt_override, 1);
 189         else if (panel->desc->bus_format)
 190                 drm_display_info_set_bus_formats(&connector->display_info,
 191                                                  &panel->desc->bus_format, 1);
 192         connector->display_info.bus_flags = panel->desc->bus_flags;
 193         if (panel->quirks)
 194                 panel_simple_apply_quirks(panel, &connector->display_info);
 195
 196         return num;
 197 }
 198
 199 static int panel_simple_disable(struct drm_panel *panel)
 200 {
 201         struct panel_simple *p = to_panel_simple(panel);
 202
 203         if (!p->enabled)
 204                 return 0;
 205
 206         if (p->backlight) {
 207                 p->backlight->props.power = FB_BLANK_POWERDOWN;
 208                 p->backlight->props.state |= BL_CORE_FBBLANK;
 209                 backlight_update_status(p->backlight);
 210         }
 211
 212         if (p->desc->delay.disable)
 213                 msleep(p->desc->delay.disable);
 214
 215         p->enabled = false;
 216
 217         return 0;
 218 }
 219
 220 static int panel_simple_unprepare(struct drm_panel *panel)
 221 {
 222         struct panel_simple *p = to_panel_simple(panel);
 223
 224         if (!p->prepared)
 225                 return 0;
 226
 227         if (p->enable_gpio)
 228                 gpiod_set_value_cansleep(p->enable_gpio, 0);
 229
 230         regulator_disable(p->supply);
 231
 232         if (p->desc->delay.unprepare)
 233                 msleep(p->desc->delay.unprepare);
 234
 235         p->prepared = false;
 236
 237         return 0;
 238 }
 239
 240 static int panel_simple_prepare(struct drm_panel *panel)
 241 {
 242         struct panel_simple *p = to_panel_simple(panel);
 243         int err;
 244
 245         if (p->prepared)
 246                 return 0;
 247
 248         err = regulator_enable(p->supply);
 249         if (err < 0) {
 250                 dev_err(panel->dev, "failed to enable supply: %d\n", err);
 251                 return err;
 252         }
 253
 254         if (p->enable_gpio)
 255                 gpiod_set_value_cansleep(p->enable_gpio, 1);
 256
 257         if (p->desc->delay.prepare)
 258                 msleep(p->desc->delay.prepare);
 259
 260         p->prepared = true;
 261
 262         return 0;
 263 }
 264
 265 static int panel_simple_enable(struct drm_panel *panel)
 266 {
 267         struct panel_simple *p = to_panel_simple(panel);
 268
 269         if (p->enabled)
 270                 return 0;
 271
 272         if (p->desc->delay.enable)
 273                 msleep(p->desc->delay.enable);
 274
 275         if (p->backlight) {
 276                 p->backlight->props.state &= ~BL_CORE_FBBLANK;
 277                 p->backlight->props.power = FB_BLANK_UNBLANK;
 278                 backlight_update_status(p->backlight);
 279         }
 280
 281         p->enabled = true;
 282
 283         return 0;
 284 }
 285
 286 static int panel_simple_get_modes(struct drm_panel *panel)
 287 {
 288         struct panel_simple *p = to_panel_simple(panel);
 289         int num = 0;
 290
 291         /* probe EDID if a DDC bus is available */
 292         if (p->ddc) {
 293                 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
 294                 drm_mode_connector_update_edid_property(panel->connector, edid);
 295                 if (edid) {
 296                         num += drm_add_edid_modes(panel->connector, edid);
 297                         kfree(edid);
 298                 }
 299         }
 300
 301         /* add hard-coded panel modes */
 302         num += panel_simple_get_fixed_modes(p);
 303
 304         return num;
 305 }
 306
 307 static int panel_simple_get_timings(struct drm_panel *panel,
 308                                     unsigned int num_timings,
 309                                     struct display_timing *timings)
 310 {
 311         struct panel_simple *p = to_panel_simple(panel);
 312         unsigned int i;
 313
 314         if (p->desc->num_timings < num_timings)
 315                 num_timings = p->desc->num_timings;
 316
 317         if (timings)
 318                 for (i = 0; i < num_timings; i++)
 319                         timings[i] = p->desc->timings[i];
 320
 321         return p->desc->num_timings;
 322 }
 323
 324 static inline int panel_simple_check_quirks(struct device *dev,
 325                                             struct panel_simple *p)
 326 {
 327         const char *bus_fmt;
 328         u32 clkpol;
 329
 330         if (of_property_read_string(dev->of_node, "bus-format-override",
 331                                     &bus_fmt) == 0) {
 332                 if (strcmp(bus_fmt, "rgb24") == 0)
 333                         p->bus_fmt_override = MEDIA_BUS_FMT_RGB888_1X24;
 334                 else if (strcmp(bus_fmt, "rgb666") == 0)
 335                         p->bus_fmt_override = MEDIA_BUS_FMT_RGB666_1X18;
 336                 else if (strcmp(bus_fmt, "rgb565") == 0)
 337                         p->bus_fmt_override = MEDIA_BUS_FMT_RGB565_1X16;
 338                 else if (strcmp(bus_fmt, "spwg-18") == 0)
 339                         p->bus_fmt_override = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG;
 340                 else if (strcmp(bus_fmt, "spwg-24") == 0)
 341                         p->bus_fmt_override = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG;
 342                 else if (strcmp(bus_fmt, "jeida-24") == 0)
 343                         p->bus_fmt_override = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA;
 344                 else
 345                         dev_err(dev,
 346                                 "Unsupported bus-format-override value: '%s'\n",
 347                                 bus_fmt);
 348                 return p->bus_fmt_override ? 0 : -EINVAL;
 349         }
 350
 351         if (of_property_read_u32(dev->of_node, "pixelclk-active",
 352                                  &clkpol) == 0) {
 353                 if (clkpol & ~1) {
 354                         dev_err(dev,
 355                                 "Invalid value for pixelclk-active: '%u' (should be <0> or <1>)\n",
 356                                 clkpol);
 357                         return -EINVAL;
 358                 }
 359                 p->quirks |= clkpol ? PANEL_QUIRK_PIXDATA_POSEDGE :
 360                         PANEL_QUIRK_PIXDATA_NEGEDGE;
 361         }
 362         return 0;
 363 }
 364
 365 static const struct drm_panel_funcs panel_simple_funcs = {
 366         .disable = panel_simple_disable,
 367         .unprepare = panel_simple_unprepare,
 368         .prepare = panel_simple_prepare,
 369         .enable = panel_simple_enable,
 370         .get_modes = panel_simple_get_modes,
 371         .get_timings = panel_simple_get_timings,
 372 };
 373
 374 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 375 {
 376         struct device_node *backlight, *ddc;
 377         struct panel_simple *panel;
 378         int err;
 379
 380         panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
 381         if (!panel)
 382                 return -ENOMEM;
 383
 384         panel->enabled = false;
 385         panel->prepared = false;
 386         panel->desc = desc;
 387
 388         panel->supply = devm_regulator_get(dev, "power");
 389         if (IS_ERR(panel->supply))
 390                 return PTR_ERR(panel->supply);
 391
 392         panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
 393                                                      GPIOD_OUT_LOW);
 394         if (IS_ERR(panel->enable_gpio)) {
 395                 err = PTR_ERR(panel->enable_gpio);
 396                 dev_err(dev, "failed to request GPIO: %d\n", err);
 397                 return err;
 398         }
 399
 400         backlight = of_parse_phandle(dev->of_node, "backlight", 0);
 401         if (backlight) {
 402                 panel->backlight = of_find_backlight_by_node(backlight);
 403                 of_node_put(backlight);
 404
 405                 if (!panel->backlight)
 406                         return -EPROBE_DEFER;
 407         }
 408
 409         ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
 410         if (ddc) {
 411                 panel->ddc = of_find_i2c_adapter_by_node(ddc);
 412                 of_node_put(ddc);
 413
 414                 if (!panel->ddc) {
 415                         err = -EPROBE_DEFER;
 416                         goto free_backlight;
 417                 }
 418         }
 419
 420         err = panel_simple_check_quirks(dev, panel);
 421         if (err)
 422                 goto free_ddc;
 423
 424         drm_panel_init(&panel->base);
 425         panel->base.dev = dev;
 426         panel->base.funcs = &panel_simple_funcs;
 427
 428         err = drm_panel_add(&panel->base);
 429         if (err < 0)
 430                 goto free_ddc;
 431
 432         dev_set_drvdata(dev, panel);
 433
 434         return 0;
 435
 436 free_ddc:
 437         if (panel->ddc)
 438                 put_device(&panel->ddc->dev);
 439 free_backlight:
 440         if (panel->backlight)
 441                 put_device(&panel->backlight->dev);
 442
 443         return err;
 444 }
 445
 446 static int panel_simple_remove(struct device *dev)
 447 {
 448         struct panel_simple *panel = dev_get_drvdata(dev);
 449
 450         drm_panel_detach(&panel->base);
 451         drm_panel_remove(&panel->base);
 452
 453         panel_simple_disable(&panel->base);
 454
 455         if (panel->ddc)
 456                 put_device(&panel->ddc->dev);
 457
 458         if (panel->backlight)
 459                 put_device(&panel->backlight->dev);
 460
 461         return 0;
 462 }
 463
 464 static void panel_simple_shutdown(struct device *dev)
 465 {
 466         struct panel_simple *panel = dev_get_drvdata(dev);
 467
 468         panel_simple_disable(&panel->base);
 469 }
 470
 471 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode =
 472         SP_DISPLAY_MODE(9000, 480, 2, 41, 2, 272, 2, 10, 2, 60,
 473                         DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 474
 475 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
 476         .modes = &ampire_am_480272h3tmqw_t01h_mode,
 477         .num_modes = 1,
 478         .bpc = 8,
 479         .size = {
 480                 .width = 105,
 481                 .height = 67,
 482         },
 483         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 484 };
 485
 486 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode =
 487         SP_DISPLAY_MODE(33333, 800, 0, 255, 0, 480, 2, 45, 0, 60,
 488                         DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 489
 490 static const struct panel_desc ampire_am800480r3tmqwa1h = {
 491         .modes = &ampire_am800480r3tmqwa1h_mode,
 492         .num_modes = 1,
 493         .bpc = 6,
 494         .size = {
 495                 .width = 152,
 496                 .height = 91,
 497         },
 498         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 499 };
 500
 501 static const struct drm_display_mode auo_b101aw03_mode =
 502         SP_DISPLAY_MODE(51450, 1024, 156, 8, 156, 600, 16, 6, 16, 60, 0);
 503
 504 static const struct panel_desc auo_b101aw03 = {
 505         .modes = &auo_b101aw03_mode,
 506         .num_modes = 1,
 507         .bpc = 6,
 508         .size = {
 509                 .width = 223,
 510                 .height = 125,
 511         },
 512 };
 513
 514 static const struct drm_display_mode auo_b101ean01_mode =
 515         SP_DISPLAY_MODE(72500, 1280, 119, 32, 21, 800, 4, 20, 8, 60, 0);
 516
 517 static const struct panel_desc auo_b101ean01 = {
 518         .modes = &auo_b101ean01_mode,
 519         .num_modes = 1,
 520         .bpc = 6,
 521         .size = {
 522                 .width = 217,
 523                 .height = 136,
 524         },
 525 };
 526
 527 static const struct drm_display_mode auo_b101xtn01_mode =
 528         SP_DISPLAY_MODE(72000, 1366, 20, 70, 0, 768, 14, 42, 0, 60,
 529                         DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 530
 531 static const struct panel_desc auo_b101xtn01 = {
 532         .modes = &auo_b101xtn01_mode,
 533         .num_modes = 1,
 534         .bpc = 6,
 535         .size = {
 536                 .width = 223,
 537                 .height = 125,
 538         },
 539 };
 540
 541 static const struct drm_display_mode auo_b116xw03_mode =
 542         SP_DISPLAY_MODE(70589, 1366, 40, 40, 32, 768, 10, 12, 6, 60, 0);
 543
 544 static const struct panel_desc auo_b116xw03 = {
 545         .modes = &auo_b116xw03_mode,
 546         .num_modes = 1,
 547         .bpc = 6,
 548         .size = {
 549                 .width = 256,
 550                 .height = 144,
 551         },
 552 };
 553
 554 static const struct drm_display_mode auo_b133xtn01_mode =
 555         SP_DISPLAY_MODE(69500, 1366, 48, 32, 20, 768, 3, 6, 13, 60, 0);
 556
 557 static const struct panel_desc auo_b133xtn01 = {
 558         .modes = &auo_b133xtn01_mode,
 559         .num_modes = 1,
 560         .bpc = 6,
 561         .size = {
 562                 .width = 293,
 563                 .height = 165,
 564         },
 565 };
 566
 567 static const struct drm_display_mode auo_b133htn01_mode =
 568         SP_DISPLAY_MODE(150660, 1920, 172, 80, 60, 1080, 25, 10, 10, 60, 0);
 569
 570 static const struct panel_desc auo_b133htn01 = {
 571         .modes = &auo_b133htn01_mode,
 572         .num_modes = 1,
 573         .bpc = 6,
 574         .size = {
 575                 .width = 293,
 576                 .height = 165,
 577         },
 578         .delay = {
 579                 .prepare = 105,
 580                 .enable = 20,
 581                 .unprepare = 50,
 582         },
 583 };
 584
 585 static const struct display_timing auo_g133han01_timings = {
 586         .pixelclock = { 134000000, 141200000, 149000000 },
 587         .hactive = { 1920, 1920, 1920 },
 588         .hfront_porch = { 39, 58, 77 },
 589         .hback_porch = { 59, 88, 117 },
 590         .hsync_len = { 28, 42, 56 },
 591         .vactive = { 1080, 1080, 1080 },
 592         .vfront_porch = { 3, 8, 11 },
 593         .vback_porch = { 5, 14, 19 },
 594         .vsync_len = { 4, 14, 19 },
 595 };
 596
 597 static const struct panel_desc auo_g133han01 = {
 598         .timings = &auo_g133han01_timings,
 599         .num_timings = 1,
 600         .bpc = 8,
 601         .size = {
 602                 .width = 293,
 603                 .height = 165,
 604         },
 605         .delay = {
 606                 .prepare = 200,
 607                 .enable = 50,
 608                 .disable = 50,
 609                 .unprepare = 1000,
 610         },
 611         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
 612 };
 613
 614 static const struct display_timing auo_g185han01_timings = {
 615         .pixelclock = { 120000000, 144000000, 175000000 },
 616         .hactive = { 1920, 1920, 1920 },
 617         .hfront_porch = { 18, 60, 74 },
 618         .hback_porch = { 12, 44, 54 },
 619         .hsync_len = { 10, 24, 32 },
 620         .vactive = { 1080, 1080, 1080 },
 621         .vfront_porch = { 6, 10, 40 },
 622         .vback_porch = { 2, 5, 20 },
 623         .vsync_len = { 2, 5, 20 },
 624 };
 625
 626 static const struct panel_desc auo_g185han01 = {
 627         .timings = &auo_g185han01_timings,
 628         .num_timings = 1,
 629         .bpc = 8,
 630         .size = {
 631                 .width = 409,
 632                 .height = 230,
 633         },
 634         .delay = {
 635                 .prepare = 50,
 636                 .enable = 200,
 637                 .disable = 110,
 638                 .unprepare = 1000,
 639         },
 640         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 641 };
 642
 643 static const struct display_timing auo_p320hvn03_timings = {
 644         .pixelclock = { 106000000, 148500000, 164000000 },
 645         .hactive = { 1920, 1920, 1920 },
 646         .hfront_porch = { 25, 50, 130 },
 647         .hback_porch = { 25, 50, 130 },
 648         .hsync_len = { 20, 40, 105 },
 649         .vactive = { 1080, 1080, 1080 },
 650         .vfront_porch = { 8, 17, 150 },
 651         .vback_porch = { 8, 17, 150 },
 652         .vsync_len = { 4, 11, 100 },
 653 };
 654
 655 static const struct panel_desc auo_p320hvn03 = {
 656         .timings = &auo_p320hvn03_timings,
 657         .num_timings = 1,
 658         .bpc = 8,
 659         .size = {
 660                 .width = 698,
 661                 .height = 393,
 662         },
 663         .delay = {
 664                 .prepare = 1,
 665                 .enable = 450,
 666                 .unprepare = 500,
 667         },
 668         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
 669 };
 670
 671 static const struct drm_display_mode auo_t215hvn01_mode =
 672         SP_DISPLAY_MODE(148800, 1920, 88, 44, 148, 1080, 4, 5, 36, 60, 0);
 673
 674 static const struct panel_desc auo_t215hvn01 = {
 675         .modes = &auo_t215hvn01_mode,
 676         .num_modes = 1,
 677         .bpc = 8,
 678         .size = {
 679                 .width = 430,
 680                 .height = 270,
 681         },
 682         .delay = {
 683                 .disable = 5,
 684                 .unprepare = 1000,
 685         }
 686 };
 687
 688 static const struct drm_display_mode avic_tm070ddh03_mode =
 689         SP_DISPLAY_MODE(51200, 1024, 160, 4, 156, 600, 17, 1, 17, 60, 0);
 690
 691 static const struct panel_desc avic_tm070ddh03 = {
 692         .modes = &avic_tm070ddh03_mode,
 693         .num_modes = 1,
 694         .bpc = 8,
 695         .size = {
 696                 .width = 154,
 697                 .height = 90,
 698         },
 699         .delay = {
 700                 .prepare = 20,
 701                 .enable = 200,
 702                 .disable = 200,
 703         },
 704 };
 705
 706 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
 707         SP_DISPLAY_MODE(71900, 1280, 48, 32, 80, 800, 3, 5, 24, 60, 0),
 708         SP_DISPLAY_MODE(57500, 1280, 48, 32, 80, 800, 3, 5, 24, 48, 0),
 709 };
 710
 711 static const struct panel_desc boe_nv101wxmn51 = {
 712         .modes = boe_nv101wxmn51_modes,
 713         .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
 714         .bpc = 8,
 715         .size = {
 716                 .width = 217,
 717                 .height = 136,
 718         },
 719         .delay = {
 720                 .prepare = 210,
 721                 .enable = 50,
 722                 .unprepare = 160,
 723         },
 724 };
 725
 726 static const struct drm_display_mode chunghwa_claa070wp03xg_mode =
 727         SP_DISPLAY_MODE(66770, 800, 49, 33, 17, 1280, 1, 7, 15, 60,
 728                         DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 729
 730 static const struct panel_desc chunghwa_claa070wp03xg = {
 731         .modes = &chunghwa_claa070wp03xg_mode,
 732         .num_modes = 1,
 733         .bpc = 6,
 734         .size = {
 735                 .width = 94,
 736                 .height = 150,
 737         },
 738 };
 739
 740 static const struct drm_display_mode chunghwa_claa101wa01a_mode =
 741         SP_DISPLAY_MODE(72070, 1366, 58, 58, 58, 768, 4, 4, 4, 60, 0);
 742
 743 static const struct panel_desc chunghwa_claa101wa01a = {
 744         .modes = &chunghwa_claa101wa01a_mode,
 745         .num_modes = 1,
 746         .bpc = 6,
 747         .size = {
 748                 .width = 220,
 749                 .height = 120,
 750         },
 751 };
 752
 753 static const struct drm_display_mode chunghwa_claa101wb01_mode =
 754         SP_DISPLAY_MODE(69300, 1366, 48, 32, 20, 768, 16, 8, 16, 60, 0);
 755
 756 static const struct panel_desc chunghwa_claa101wb01 = {
 757         .modes = &chunghwa_claa101wb01_mode,
 758         .num_modes = 1,
 759         .bpc = 6,
 760         .size = {
 761                 .width = 223,
 762                 .height = 125,
 763         },
 764 };
 765
 766 static const struct drm_display_mode edt_et0350g0dh6_mode =
 767         SP_DISPLAY_MODE(6500, 320, 20, 0, 68, 240, 4, 0, 18, 60,
 768                         DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 769
 770 static const struct panel_desc edt_et0350g0dh6 = {
 771         .modes = &edt_et0350g0dh6_mode,
 772         .num_modes = 1,
 773         .bpc = 6,
 774         .size = {
 775                 .width = 70,
 776                 .height = 53,
 777         },
 778         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 779         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
 780 };
 781
 782 static const struct drm_display_mode edt_et0430g0dh6_mode =
 783         SP_DISPLAY_MODE(9000, 480, 2, 41, 2, 272, 2, 10, 2, 60,
 784                         DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 785
 786 static const struct panel_desc edt_et0430g0dh6 = {
 787         .modes = &edt_et0430g0dh6_mode,
 788         .num_modes = 1,
 789         .bpc = 6,
 790         .size = {
 791                 .width = 95,
 792                 .height = 54,
 793         },
 794         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 795         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
 796 };
 797
 798 static const struct drm_display_mode edt_et057090dhu_mode =
 799         SP_DISPLAY_MODE(25175, 640, 16, 30, 114, 480, 10, 3, 32, 60,
 800                         DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
 801
 802 static const struct panel_desc edt_et057090dhu = {
 803         .modes = &edt_et057090dhu_mode,
 804         .num_modes = 1,
 805         .bpc = 6,
 806         .size = {
 807                 .width = 115,
 808                 .height = 86,
 809         },
 810         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 811         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
 812 };
 813
 814 static const struct drm_display_mode edt_etm0700g0dh6_mode =
 815         SP_DISPLAY_MODE(33260, 800, 40, 128, 88, 480, 10, 2, 33, 60,
 816                         DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
 817
 818 static const struct panel_desc edt_etm0700g0dh6 = {
 819         .modes = &edt_etm0700g0dh6_mode,
 820         .num_modes = 1,
 821         .bpc = 6,
 822         .size = {
 823                 .width = 152,
 824                 .height = 91,
 825         },
 826         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 827         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
 828 };
 829
 830 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode =
 831         SP_DISPLAY_MODE(32260, 800, 168, 64, 88, 480, 37, 2, 8, 60, 0);
 832
 833 static const struct panel_desc foxlink_fl500wvr00_a0t = {
 834         .modes = &foxlink_fl500wvr00_a0t_mode,
 835         .num_modes = 1,
 836         .bpc = 8,
 837         .size = {
 838                 .width = 108,
 839                 .height = 65,
 840         },
 841         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 842 };
 843
 844 static const struct drm_display_mode giantplus_gpg482739qs5_mode =
 845         SP_DISPLAY_MODE(9000, 480, 5, 1, 40, 272, 8, 1, 8, 60, 0);
 846
 847 static const struct panel_desc giantplus_gpg482739qs5 = {
 848         .modes = &giantplus_gpg482739qs5_mode,
 849         .num_modes = 1,
 850         .bpc = 8,
 851         .size = {
 852                 .width = 95,
 853                 .height = 54,
 854         },
 855         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 856 };
 857
 858 static const struct display_timing hannstar_hsd070pww1_timing = {
 859         .pixelclock = { 64300000, 71100000, 82000000 },
 860         .hactive = { 1280, 1280, 1280 },
 861         .hfront_porch = { 1, 1, 10 },
 862         .hback_porch = { 1, 1, 10 },
 863         /*
 864          * According to the data sheet, the minimum horizontal blanking interval
 865          * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
 866          * minimum working horizontal blanking interval to be 60 clocks.
 867          */
 868         .hsync_len = { 58, 158, 661 },
 869         .vactive = { 800, 800, 800 },
 870         .vfront_porch = { 1, 1, 10 },
 871         .vback_porch = { 1, 1, 10 },
 872         .vsync_len = { 1, 21, 203 },
 873         .flags = DISPLAY_FLAGS_DE_HIGH,
 874 };
 875
 876 static const struct panel_desc hannstar_hsd070pww1 = {
 877         .timings = &hannstar_hsd070pww1_timing,
 878         .num_timings = 1,
 879         .bpc = 6,
 880         .size = {
 881                 .width = 151,
 882                 .height = 94,
 883         },
 884         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
 885 };
 886
 887 static const struct display_timing hannstar_hsd100pxn1_timing = {
 888         .pixelclock = { 55000000, 65000000, 75000000 },
 889         .hactive = { 1024, 1024, 1024 },
 890         .hfront_porch = { 40, 40, 40 },
 891         .hback_porch = { 220, 220, 220 },
 892         .hsync_len = { 20, 60, 100 },
 893         .vactive = { 768, 768, 768 },
 894         .vfront_porch = { 7, 7, 7 },
 895         .vback_porch = { 21, 21, 21 },
 896         .vsync_len = { 10, 10, 10 },
 897         .flags = DISPLAY_FLAGS_DE_HIGH,
 898 };
 899
 900 static const struct panel_desc hannstar_hsd100pxn1 = {
 901         .timings = &hannstar_hsd100pxn1_timing,
 902         .num_timings = 1,
 903         .bpc = 6,
 904         .size = {
 905                 .width = 203,
 906                 .height = 152,
 907         },
 908         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
 909 };
 910
 911 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode =
 912         SP_DISPLAY_MODE(33333, 800, 85, 86, 85, 480, 16, 13, 16, 60, 0);
 913
 914 static const struct panel_desc hitachi_tx23d38vm0caa = {
 915         .modes = &hitachi_tx23d38vm0caa_mode,
 916         .num_modes = 1,
 917         .bpc = 6,
 918         .size = {
 919                 .width = 195,
 920                 .height = 117,
 921         },
 922 };
 923
 924 static const struct drm_display_mode innolux_at043tn24_mode =
 925         SP_DISPLAY_MODE(9000, 480, 2, 41, 2, 272, 2, 11, 2, 60,
 926                         DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
 927
 928 static const struct panel_desc innolux_at043tn24 = {
 929         .modes = &innolux_at043tn24_mode,
 930         .num_modes = 1,
 931         .bpc = 8,
 932         .size = {
 933                 .width = 95,
 934                 .height = 54,
 935         },
 936         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 937 };
 938
 939 static const struct drm_display_mode innolux_at070tn92_mode =
 940         SP_DISPLAY_MODE(33333, 800, 210, 20, 46, 480, 22, 10, 23, 60, 0);
 941
 942 static const struct panel_desc innolux_at070tn92 = {
 943         .modes = &innolux_at070tn92_mode,
 944         .num_modes = 1,
 945         .size = {
 946                 .width = 154,
 947                 .height = 86,
 948         },
 949         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 950 };
 951
 952 static const struct display_timing innolux_g101ice_l01_timing = {
 953         .pixelclock = { 60400000, 71100000, 74700000 },
 954         .hactive = { 1280, 1280, 1280 },
 955         .hfront_porch = { 41, 80, 100 },
 956         .hback_porch = { 40, 79, 99 },
 957         .hsync_len = { 1, 1, 1 },
 958         .vactive = { 800, 800, 800 },
 959         .vfront_porch = { 5, 11, 14 },
 960         .vback_porch = { 4, 11, 14 },
 961         .vsync_len = { 1, 1, 1 },
 962         .flags = DISPLAY_FLAGS_DE_HIGH,
 963 };
 964
 965 static const struct panel_desc innolux_g101ice_l01 = {
 966         .timings = &innolux_g101ice_l01_timing,
 967         .num_timings = 1,
 968         .bpc = 8,
 969         .size = {
 970                 .width = 217,
 971                 .height = 135,
 972         },
 973         .delay = {
 974                 .enable = 200,
 975                 .disable = 200,
 976         },
 977         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 978 };
 979
 980 static const struct display_timing innolux_g121i1_l01_timing = {
 981         .pixelclock = { 67450000, 71000000, 74550000 },
 982         .hactive = { 1280, 1280, 1280 },
 983         .hfront_porch = { 40, 80, 160 },
 984         .hback_porch = { 39, 79, 159 },
 985         .hsync_len = { 1, 1, 1 },
 986         .vactive = { 800, 800, 800 },
 987         .vfront_porch = { 5, 11, 100 },
 988         .vback_porch = { 4, 11, 99 },
 989         .vsync_len = { 1, 1, 1 },
 990 };
 991
 992 static const struct panel_desc innolux_g121i1_l01 = {
 993         .timings = &innolux_g121i1_l01_timing,
 994         .num_timings = 1,
 995         .bpc = 6,
 996         .size = {
 997                 .width = 261,
 998                 .height = 163,
 999         },
1000         .delay = {
1001                 .enable = 200,
1002                 .disable = 20,
1003         },
1004         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1005 };
1006
1007 static const struct drm_display_mode innolux_g121x1_l03_mode =
1008         SP_DISPLAY_MODE(65000, 1024, 0, 1, 320, 768, 38, 1, 0, 60,
1009                         DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1010
1011 static const struct panel_desc innolux_g121x1_l03 = {
1012         .modes = &innolux_g121x1_l03_mode,
1013         .num_modes = 1,
1014         .bpc = 6,
1015         .size = {
1016                 .width = 246,
1017                 .height = 185,
1018         },
1019         .delay = {
1020                 .enable = 200,
1021                 .unprepare = 200,
1022                 .disable = 400,
1023         },
1024 };
1025
1026 static const struct drm_display_mode innolux_n116bge_mode =
1027         SP_DISPLAY_MODE(76420, 1366, 136, 30, 60, 768, 8, 12, 12, 60,
1028                         DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1029
1030 static const struct panel_desc innolux_n116bge = {
1031         .modes = &innolux_n116bge_mode,
1032         .num_modes = 1,
1033         .bpc = 6,
1034         .size = {
1035                 .width = 256,
1036                 .height = 144,
1037         },
1038 };
1039
1040 static const struct drm_display_mode innolux_n156bge_l21_mode =
1041         SP_DISPLAY_MODE(69300, 1366, 16, 34, 50, 768, 2, 6, 12, 60, 0);
1042
1043 static const struct panel_desc innolux_n156bge_l21 = {
1044         .modes = &innolux_n156bge_l21_mode,
1045         .num_modes = 1,
1046         .bpc = 6,
1047         .size = {
1048                 .width = 344,
1049                 .height = 193,
1050         },
1051 };
1052
1053 static const struct drm_display_mode innolux_zj070na_01p_mode =
1054         SP_DISPLAY_MODE(51501, 1024, 128, 64, 128, 600, 16, 4, 16, 60, 0);
1055
1056 static const struct panel_desc innolux_zj070na_01p = {
1057         .modes = &innolux_zj070na_01p_mode,
1058         .num_modes = 1,
1059         .bpc = 6,
1060         .size = {
1061                 .width = 154,
1062                 .height = 90,
1063         },
1064 };
1065
1066 static const struct display_timing kyo_tcg121xglp_timing = {
1067         .pixelclock = { 52000000, 65000000, 71000000 },
1068         .hactive = { 1024, 1024, 1024 },
1069         .hfront_porch = { 2, 2, 2 },
1070         .hback_porch = { 2, 2, 2 },
1071         .hsync_len = { 86, 124, 244 },
1072         .vactive = { 768, 768, 768 },
1073         .vfront_porch = { 2, 2, 2 },
1074         .vback_porch = { 2, 2, 2 },
1075         .vsync_len = { 6, 34, 73 },
1076         .flags = DISPLAY_FLAGS_DE_HIGH,
1077 };
1078
1079 static const struct panel_desc kyo_tcg121xglp = {
1080         .timings = &kyo_tcg121xglp_timing,
1081         .num_timings = 1,
1082         .bpc = 8,
1083         .size = {
1084                 .width = 246,
1085                 .height = 184,
1086         },
1087         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1088 };
1089
1090 static const struct drm_display_mode lg_lb070wv8_mode =
1091         SP_DISPLAY_MODE(33246, 800, 88, 80, 88, 480, 10, 25, 10, 60, 0);
1092
1093 static const struct panel_desc lg_lb070wv8 = {
1094         .modes = &lg_lb070wv8_mode,
1095         .num_modes = 1,
1096         .bpc = 16,
1097         .size = {
1098                 .width = 151,
1099                 .height = 91,
1100         },
1101         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1102 };
1103
1104 static const struct drm_display_mode lg_lp079qx1_sp0v_mode =
1105         SP_DISPLAY_MODE(200000, 1536, 12, 16, 48, 2048, 8, 4, 8, 60,
1106                          DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1107
1108 static const struct panel_desc lg_lp079qx1_sp0v = {
1109         .modes = &lg_lp079qx1_sp0v_mode,
1110         .num_modes = 1,
1111         .size = {
1112                 .width = 129,
1113                 .height = 171,
1114         },
1115 };
1116
1117 static const struct drm_display_mode lg_lp097qx1_spa1_mode =
1118         SP_DISPLAY_MODE(205210, 2048, 150, 5, 5, 1536, 3, 1, 9, 60, 0);
1119
1120 static const struct panel_desc lg_lp097qx1_spa1 = {
1121         .modes = &lg_lp097qx1_spa1_mode,
1122         .num_modes = 1,
1123         .size = {
1124                 .width = 208,
1125                 .height = 147,
1126         },
1127 };
1128
1129 static const struct drm_display_mode lg_lp120up1_mode =
1130         SP_DISPLAY_MODE(162300, 1920, 40, 40, 80, 1280, 4, 4, 12, 60, 0);
1131
1132 static const struct panel_desc lg_lp120up1 = {
1133         .modes = &lg_lp120up1_mode,
1134         .num_modes = 1,
1135         .bpc = 8,
1136         .size = {
1137                 .width = 267,
1138                 .height = 183,
1139         },
1140 };
1141
1142 static const struct drm_display_mode lg_lp129qe_mode =
1143         SP_DISPLAY_MODE(285250, 2560, 48, 32, 80, 1700, 3, 10, 36, 60, 0);
1144
1145 static const struct panel_desc lg_lp129qe = {
1146         .modes = &lg_lp129qe_mode,
1147         .num_modes = 1,
1148         .bpc = 8,
1149         .size = {
1150                 .width = 272,
1151                 .height = 181,
1152         },
1153 };
1154
1155 static const struct display_timing nec_nl12880bc20_05_timing = {
1156         .pixelclock = { 67000000, 71000000, 75000000 },
1157         .hactive = { 1280, 1280, 1280 },
1158         .hfront_porch = { 2, 30, 30 },
1159         .hback_porch = { 6, 100, 100 },
1160         .hsync_len = { 2, 30, 30 },
1161         .vactive = { 800, 800, 800 },
1162         .vfront_porch = { 5, 5, 5 },
1163         .vback_porch = { 11, 11, 11 },
1164         .vsync_len = { 7, 7, 7 },
1165 };
1166
1167 static const struct panel_desc nec_nl12880bc20_05 = {
1168         .timings = &nec_nl12880bc20_05_timing,
1169         .num_timings = 1,
1170         .bpc = 8,
1171         .size = {
1172                 .width = 261,
1173                 .height = 163,
1174         },
1175         .delay = {
1176                 .enable = 50,
1177                 .disable = 50,
1178         },
1179         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1180 };
1181
1182 static const struct drm_display_mode nec_nl4827hc19_05b_mode =
1183         SP_DISPLAY_MODE(10870, 480, 2, 41, 2, 272, 2, 4, 2, 74,
1184                          DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1185
1186 static const struct panel_desc nec_nl4827hc19_05b = {
1187         .modes = &nec_nl4827hc19_05b_mode,
1188         .num_modes = 1,
1189         .bpc = 8,
1190         .size = {
1191                 .width = 95,
1192                 .height = 54,
1193         },
1194         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1195         .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1196 };
1197
1198 static const struct drm_display_mode netron_dy_e231732_mode =
1199         SP_DISPLAY_MODE(66000, 1024, 160, 70, 90, 600, 127, 20, 3, 60, 0);
1200
1201 static const struct panel_desc netron_dy_e231732 = {
1202         .modes = &netron_dy_e231732_mode,
1203         .num_modes = 1,
1204         .size = {
1205                 .width = 154,
1206                 .height = 87,
1207         },
1208         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1209 };
1210
1211 static const struct display_timing nlt_nl192108ac18_02d_timing = {
1212         .pixelclock = { 130000000, 148350000, 163000000 },
1213         .hactive = { 1920, 1920, 1920 },
1214         .hfront_porch = { 80, 100, 100 },
1215         .hback_porch = { 100, 120, 120 },
1216         .hsync_len = { 50, 60, 60 },
1217         .vactive = { 1080, 1080, 1080 },
1218         .vfront_porch = { 12, 30, 30 },
1219         .vback_porch = { 4, 10, 10 },
1220         .vsync_len = { 4, 5, 5 },
1221 };
1222
1223 static const struct panel_desc nlt_nl192108ac18_02d = {
1224         .timings = &nlt_nl192108ac18_02d_timing,
1225         .num_timings = 1,
1226         .bpc = 8,
1227         .size = {
1228                 .width = 344,
1229                 .height = 194,
1230         },
1231         .delay = {
1232                 .unprepare = 500,
1233         },
1234         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1235 };
1236
1237 static const struct drm_display_mode nlt_nl12880bc20_mode =
1238         SP_DISPLAY_MODE(71000, 1280, 50, 60, 50, 800, 5, 13, 5, 0, 0);
1239
1240 static const struct panel_desc nlt_nl12880bc20_jeida = {
1241         .modes = &nlt_nl12880bc20_mode,
1242         .num_modes = 1,
1243         .bpc = 8,
1244         .size = {
1245                 .width = 261,
1246                 .height = 163,
1247         },
1248         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1249 };
1250
1251 static const struct panel_desc nlt_nl12880bc20_spwg_18 = {
1252         .modes = &nlt_nl12880bc20_mode,
1253         .num_modes = 1,
1254         .bpc = 6,
1255         .size = {
1256                 .width = 261,
1257                 .height = 163,
1258         },
1259         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1260 };
1261
1262 static const struct panel_desc nlt_nl12880bc20_spwg_24 = {
1263         .modes = &nlt_nl12880bc20_mode,
1264         .num_modes = 1,
1265         .bpc = 8,
1266         .size = {
1267                 .width = 261,
1268                 .height = 163,
1269         },
1270         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1271 };
1272
1273 static const struct drm_display_mode nvd_9128_mode =
1274         SP_DISPLAY_MODE(29500, 800, 130, 98, 0, 480, 10, 50, 0, 0, 0);
1275
1276 static const struct panel_desc nvd_9128 = {
1277         .modes = &nvd_9128_mode,
1278         .num_modes = 1,
1279         .bpc = 8,
1280         .size = {
1281                 .width = 156,
1282                 .height = 88,
1283         },
1284         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1285 };
1286
1287 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1288         .pixelclock = { 30000000, 30000000, 40000000 },
1289         .hactive = { 800, 800, 800 },
1290         .hfront_porch = { 40, 40, 40 },
1291         .hback_porch = { 40, 40, 40 },
1292         .hsync_len = { 1, 48, 48 },
1293         .vactive = { 480, 480, 480 },
1294         .vfront_porch = { 13, 13, 13 },
1295         .vback_porch = { 29, 29, 29 },
1296         .vsync_len = { 3, 3, 3 },
1297         .flags = DISPLAY_FLAGS_DE_HIGH,
1298 };
1299
1300 static const struct panel_desc okaya_rs800480t_7x0gp = {
1301         .timings = &okaya_rs800480t_7x0gp_timing,
1302         .num_timings = 1,
1303         .bpc = 6,
1304         .size = {
1305                 .width = 154,
1306                 .height = 87,
1307         },
1308         .delay = {
1309                 .prepare = 41,
1310                 .enable = 50,
1311                 .unprepare = 41,
1312                 .disable = 50,
1313         },
1314         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1315 };
1316
1317 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode =
1318         SP_DISPLAY_MODE(9000, 480, 5, 30, 10, 272, 8, 5, 3, 60, 0);
1319
1320 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1321         .modes = &olimex_lcd_olinuxino_43ts_mode,
1322         .num_modes = 1,
1323         .size = {
1324                 .width = 105,
1325                 .height = 67,
1326         },
1327         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1328 };
1329
1330 /*
1331  * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1332  * pixel clocks, but this is the timing that was being used in the Adafruit
1333  * installation instructions.
1334  */
1335 static const struct drm_display_mode ontat_yx700wv03_mode =
1336         SP_DISPLAY_MODE(29500, 800, 24, 72, 96, 480, 3, 10, 7, 60,
1337                         DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1338
1339 /*
1340  * Specification at:
1341  * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1342  */
1343 static const struct panel_desc ontat_yx700wv03 = {
1344         .modes = &ontat_yx700wv03_mode,
1345         .num_modes = 1,
1346         .bpc = 8,
1347         .size = {
1348                 .width = 154,
1349                 .height = 83,
1350         },
1351         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1352 };
1353
1354 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  =
1355         SP_DISPLAY_MODE(25000, 480, 10, 10, 15, 800, 3, 3, 3, 60, 0);
1356
1357 static const struct panel_desc ortustech_com43h4m85ulc = {
1358         .modes = &ortustech_com43h4m85ulc_mode,
1359         .num_modes = 1,
1360         .bpc = 8,
1361         .size = {
1362                 .width = 56,
1363                 .height = 93,
1364         },
1365         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1366         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1367 };
1368
1369 static const struct drm_display_mode qd43003c0_40_mode =
1370         SP_DISPLAY_MODE(9000, 480, 8, 4, 39, 272, 4, 10, 2, 60, 0);
1371
1372 static const struct panel_desc qd43003c0_40 = {
1373         .modes = &qd43003c0_40_mode,
1374         .num_modes = 1,
1375         .bpc = 8,
1376         .size = {
1377                 .width = 95,
1378                 .height = 53,
1379         },
1380         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1381 };
1382
1383 static const struct drm_display_mode samsung_lsn122dl01_c01_mode =
1384         SP_DISPLAY_MODE(271560, 2560, 48, 32, 80, 1600, 2, 5, 57, 60, 0);
1385
1386 static const struct panel_desc samsung_lsn122dl01_c01 = {
1387         .modes = &samsung_lsn122dl01_c01_mode,
1388         .num_modes = 1,
1389         .size = {
1390                 .width = 263,
1391                 .height = 164,
1392         },
1393 };
1394
1395 static const struct drm_display_mode samsung_ltn101nt05_mode =
1396         SP_DISPLAY_MODE(54030, 1024, 24, 136, 160, 600, 3, 6, 61, 60, 0);
1397
1398 static const struct panel_desc samsung_ltn101nt05 = {
1399         .modes = &samsung_ltn101nt05_mode,
1400         .num_modes = 1,
1401         .bpc = 6,
1402         .size = {
1403                 .width = 223,
1404                 .height = 125,
1405         },
1406 };
1407
1408 static const struct drm_display_mode samsung_ltn140at29_301_mode =
1409         SP_DISPLAY_MODE(76300, 1366, 64, 48, 128, 768, 2, 5, 17, 60, 0);
1410
1411 static const struct panel_desc samsung_ltn140at29_301 = {
1412         .modes = &samsung_ltn140at29_301_mode,
1413         .num_modes = 1,
1414         .bpc = 6,
1415         .size = {
1416                 .width = 320,
1417                 .height = 187,
1418         },
1419 };
1420
1421 static const struct display_timing sharp_lq101k1ly04_timing = {
1422         .pixelclock = { 60000000, 65000000, 80000000 },
1423         .hactive = { 1280, 1280, 1280 },
1424         .hfront_porch = { 20, 20, 20 },
1425         .hback_porch = { 20, 20, 20 },
1426         .hsync_len = { 10, 10, 10 },
1427         .vactive = { 800, 800, 800 },
1428         .vfront_porch = { 4, 4, 4 },
1429         .vback_porch = { 4, 4, 4 },
1430         .vsync_len = { 4, 4, 4 },
1431         .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
1432 };
1433
1434 static const struct panel_desc sharp_lq101k1ly04 = {
1435         .timings = &sharp_lq101k1ly04_timing,
1436         .num_timings = 1,
1437         .bpc = 8,
1438         .size = {
1439                 .width = 217,
1440                 .height = 136,
1441         },
1442         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1443 };
1444
1445 static const struct drm_display_mode sharp_lq123p1jx31_mode =
1446         SP_DISPLAY_MODE(252750, 2400, 48, 32, 80, 1600, 3, 10, 33, 60,
1447                          DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1448
1449 static const struct panel_desc sharp_lq123p1jx31 = {
1450         .modes = &sharp_lq123p1jx31_mode,
1451         .num_modes = 1,
1452         .bpc = 8,
1453         .size = {
1454                 .width = 259,
1455                 .height = 173,
1456         },
1457         .delay = {
1458                 .prepare = 110,
1459                 .enable = 50,
1460                 .unprepare = 550,
1461         },
1462 };
1463
1464 static const struct drm_display_mode sharp_lq150x1lg11_mode =
1465         SP_DISPLAY_MODE(71100, 1024, 168, 64, 88, 768, 37, 2, 8, 60, 0);
1466
1467 static const struct panel_desc sharp_lq150x1lg11 = {
1468         .modes = &sharp_lq150x1lg11_mode,
1469         .num_modes = 1,
1470         .bpc = 6,
1471         .size = {
1472                 .width = 304,
1473                 .height = 228,
1474         },
1475         .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
1476 };
1477
1478 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode =
1479         SP_DISPLAY_MODE(33300, 800, 1, 64, 64, 480, 1, 23, 22, 60, 0);
1480
1481 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1482         .modes = &shelly_sca07010_bfn_lnn_mode,
1483         .num_modes = 1,
1484         .size = {
1485                 .width = 152,
1486                 .height = 91,
1487         },
1488         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1489 };
1490
1491 static const struct drm_display_mode starry_kr122ea0sra_mode =
1492         SP_DISPLAY_MODE(147000, 1920, 16, 16, 32, 1200, 15, 2, 18, 60,
1493                          DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1494
1495 static const struct panel_desc starry_kr122ea0sra = {
1496         .modes = &starry_kr122ea0sra_mode,
1497         .num_modes = 1,
1498         .size = {
1499                 .width = 263,
1500                 .height = 164,
1501         },
1502         .delay = {
1503                 .prepare = 10 + 200,
1504                 .enable = 50,
1505                 .unprepare = 10 + 500,
1506         },
1507 };
1508
1509 static const struct display_timing tianma_tm070jdhg30_timing = {
1510         .pixelclock = { 62600000, 68200000, 78100000 },
1511         .hactive = { 1280, 1280, 1280 },
1512         .hfront_porch = { 15, 64, 159 },
1513         .hback_porch = { 5, 5, 5 },
1514         .hsync_len = { 1, 1, 256 },
1515         .vactive = { 800, 800, 800 },
1516         .vfront_porch = { 3, 40, 99 },
1517         .vback_porch = { 2, 2, 2 },
1518         .vsync_len = { 1, 1, 128 },
1519         .flags = DISPLAY_FLAGS_DE_HIGH,
1520 };
1521
1522 static const struct panel_desc tianma_tm070jdhg30 = {
1523         .timings = &tianma_tm070jdhg30_timing,
1524         .num_timings = 1,
1525         .bpc = 8,
1526         .size = {
1527                 .width = 151,
1528                 .height = 95,
1529         },
1530         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1531 };
1532
1533 static const struct drm_display_mode tpk_f07a_0102_mode =
1534         SP_DISPLAY_MODE(33260, 800, 40, 128, 88, 480, 10, 2, 33, 60, 0);
1535
1536 static const struct panel_desc tpk_f07a_0102 = {
1537         .modes = &tpk_f07a_0102_mode,
1538         .num_modes = 1,
1539         .size = {
1540                 .width = 152,
1541                 .height = 91,
1542         },
1543         .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1544 };
1545
1546 static const struct drm_display_mode tpk_f10a_0102_mode =
1547         SP_DISPLAY_MODE(45000, 1024, 176, 5, 88, 600, 20, 5, 25, 60, 0);
1548
1549 static const struct panel_desc tpk_f10a_0102 = {
1550         .modes = &tpk_f10a_0102_mode,
1551         .num_modes = 1,
1552         .size = {
1553                 .width = 223,
1554                 .height = 125,
1555         },
1556 };
1557
1558 static const struct display_timing urt_umsh_8596md_timing = {
1559         .pixelclock = { 33260000, 33260000, 33260000 },
1560         .hactive = { 800, 800, 800 },
1561         .hfront_porch = { 41, 41, 41 },
1562         .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1563         .hsync_len = { 71, 128, 128 },
1564         .vactive = { 480, 480, 480 },
1565         .vfront_porch = { 10, 10, 10 },
1566         .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1567         .vsync_len = { 2, 2, 2 },
1568         .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1569                 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1570 };
1571
1572 static const struct panel_desc urt_umsh_8596md_lvds = {
1573         .timings = &urt_umsh_8596md_timing,
1574         .num_timings = 1,
1575         .bpc = 6,
1576         .size = {
1577                 .width = 152,
1578                 .height = 91,
1579         },
1580         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1581 };
1582
1583 static const struct panel_desc urt_umsh_8596md_parallel = {
1584         .timings = &urt_umsh_8596md_timing,
1585         .num_timings = 1,
1586         .bpc = 6,
1587         .size = {
1588                 .width = 152,
1589                 .height = 91,
1590         },
1591         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1592 };
1593
1594 static const struct drm_display_mode winstar_wf35ltiacd_mode =
1595         SP_DISPLAY_MODE(6410, 320, 20, 30, 38, 240, 4, 3, 15, 60,
1596                         DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1597
1598 static const struct panel_desc winstar_wf35ltiacd = {
1599         .modes = &winstar_wf35ltiacd_mode,
1600         .num_modes = 1,
1601         .bpc = 8,
1602         .size = {
1603                 .width = 70,
1604                 .height = 53,
1605         },
1606         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1607 };
1608
1609 static const struct of_device_id platform_of_match[] = {
1610         {
1611                 .compatible = "ampire,am-480272h3tmqw-t01h",
1612                 .data = &ampire_am_480272h3tmqw_t01h,
1613         }, {
1614                 .compatible = "ampire,am800480r3tmqwa1h",
1615                 .data = &ampire_am800480r3tmqwa1h,
1616         }, {
1617                 .compatible = "auo,b101aw03",
1618                 .data = &auo_b101aw03,
1619         }, {
1620                 .compatible = "auo,b101ean01",
1621                 .data = &auo_b101ean01,
1622         }, {
1623                 .compatible = "auo,b101xtn01",
1624                 .data = &auo_b101xtn01,
1625         }, {
1626                 .compatible = "auo,b116xw03",
1627                 .data = &auo_b116xw03,
1628         }, {
1629                 .compatible = "auo,b133htn01",
1630                 .data = &auo_b133htn01,
1631         }, {
1632                 .compatible = "auo,b133xtn01",
1633                 .data = &auo_b133xtn01,
1634         }, {
1635                 .compatible = "auo,g133han01",
1636                 .data = &auo_g133han01,
1637         }, {
1638                 .compatible = "auo,g185han01",
1639                 .data = &auo_g185han01,
1640         }, {
1641                 .compatible = "auo,p320hvn03",
1642                 .data = &auo_p320hvn03,
1643         }, {
1644                 .compatible = "auo,t215hvn01",
1645                 .data = &auo_t215hvn01,
1646         }, {
1647                 .compatible = "avic,tm070ddh03",
1648                 .data = &avic_tm070ddh03,
1649         }, {
1650                 .compatible = "boe,nv101wxmn51",
1651                 .data = &boe_nv101wxmn51,
1652         }, {
1653                 .compatible = "chunghwa,claa070wp03xg",
1654                 .data = &chunghwa_claa070wp03xg,
1655         }, {
1656                 .compatible = "chunghwa,claa101wa01a",
1657                 .data = &chunghwa_claa101wa01a
1658         }, {
1659                 .compatible = "chunghwa,claa101wb01",
1660                 .data = &chunghwa_claa101wb01
1661         }, {
1662                 .compatible = "edt,et0350g0dh6",
1663                 .data = &edt_et0350g0dh6,
1664         }, {
1665                 .compatible = "edt,et0430g0dh6",
1666                 .data = &edt_et0430g0dh6,
1667         }, {
1668                 .compatible = "edt,et057090dhu",
1669                 .data = &edt_et057090dhu,
1670         }, {
1671                 .compatible = "edt,et070080dh6",
1672                 .data = &edt_etm0700g0dh6,
1673         }, {
1674                 .compatible = "edt,etm0700g0dh6",
1675                 .data = &edt_etm0700g0dh6,
1676         }, {
1677                 .compatible = "foxlink,fl500wvr00-a0t",
1678                 .data = &foxlink_fl500wvr00_a0t,
1679         }, {
1680                 .compatible = "giantplus,gpg482739qs5",
1681                 .data = &giantplus_gpg482739qs5
1682         }, {
1683                 .compatible = "hannstar,hsd070pww1",
1684                 .data = &hannstar_hsd070pww1,
1685         }, {
1686                 .compatible = "hannstar,hsd100pxn1",
1687                 .data = &hannstar_hsd100pxn1,
1688         }, {
1689                 .compatible = "hit,tx23d38vm0caa",
1690                 .data = &hitachi_tx23d38vm0caa
1691         }, {
1692                 .compatible = "innolux,at043tn24",
1693                 .data = &innolux_at043tn24,
1694         }, {
1695                 .compatible = "innolux,at070tn92",
1696                 .data = &innolux_at070tn92,
1697         }, {
1698                 .compatible ="innolux,g101ice-l01",
1699                 .data = &innolux_g101ice_l01
1700         }, {
1701                 .compatible ="innolux,g121i1-l01",
1702                 .data = &innolux_g121i1_l01
1703         }, {
1704                 .compatible = "innolux,g121x1-l03",
1705                 .data = &innolux_g121x1_l03,
1706         }, {
1707                 .compatible = "innolux,n116bge",
1708                 .data = &innolux_n116bge,
1709         }, {
1710                 .compatible = "innolux,n156bge-l21",
1711                 .data = &innolux_n156bge_l21,
1712         }, {
1713                 .compatible = "innolux,zj070na-01p",
1714                 .data = &innolux_zj070na_01p,
1715         }, {
1716                 .compatible = "kyo,tcg121xglp",
1717                 .data = &kyo_tcg121xglp,
1718         }, {
1719                 .compatible = "lg,lb070wv8",
1720                 .data = &lg_lb070wv8,
1721         }, {
1722                 .compatible = "lg,lp079qx1-sp0v",
1723                 .data = &lg_lp079qx1_sp0v,
1724         }, {
1725                 .compatible = "lg,lp097qx1-spa1",
1726                 .data = &lg_lp097qx1_spa1,
1727         }, {
1728                 .compatible = "lg,lp120up1",
1729                 .data = &lg_lp120up1,
1730         }, {
1731                 .compatible = "lg,lp129qe",
1732                 .data = &lg_lp129qe,
1733         }, {
1734                 .compatible = "nec,nl12880bc20-05",
1735                 .data = &nec_nl12880bc20_05,
1736         }, {
1737                 .compatible = "nec,nl4827hc19-05b",
1738                 .data = &nec_nl4827hc19_05b,
1739         }, {
1740                 .compatible = "netron-dy,e231732",
1741                 .data = &netron_dy_e231732,
1742         }, {
1743                 .compatible = "nlt,nl192108ac18-02d",
1744                 .data = &nlt_nl192108ac18_02d,
1745         }, {
1746                 .compatible = "nlt,nl12880bc20-jeida",
1747                 .data = &nlt_nl12880bc20_jeida,
1748         }, {
1749                 .compatible = "nlt,nl12880bc20-spwg-18",
1750                 .data = &nlt_nl12880bc20_spwg_18,
1751         }, {
1752                 .compatible = "nlt,nl12880bc20-spwg-24",
1753                 .data = &nlt_nl12880bc20_spwg_24,
1754         }, {
1755                 .compatible = "nvd,9128",
1756                 .data = &nvd_9128,
1757         }, {
1758                 .compatible = "okaya,rs800480t-7x0gp",
1759                 .data = &okaya_rs800480t_7x0gp,
1760         }, {
1761                 .compatible = "olimex,lcd-olinuxino-43-ts",
1762                 .data = &olimex_lcd_olinuxino_43ts,
1763         }, {
1764                 .compatible = "ontat,yx700wv03",
1765                 .data = &ontat_yx700wv03,
1766         }, {
1767                 .compatible = "ortustech,com43h4m85ulc",
1768                 .data = &ortustech_com43h4m85ulc,
1769         }, {
1770                 .compatible = "qiaodian,qd43003c0-40",
1771                 .data = &qd43003c0_40,
1772         }, {
1773                 .compatible = "samsung,lsn122dl01-c01",
1774                 .data = &samsung_lsn122dl01_c01,
1775         }, {
1776                 .compatible = "samsung,ltn101nt05",
1777                 .data = &samsung_ltn101nt05,
1778         }, {
1779                 .compatible = "samsung,ltn140at29-301",
1780                 .data = &samsung_ltn140at29_301,
1781         }, {
1782                 .compatible = "sharp,lq101k1ly04",
1783                 .data = &sharp_lq101k1ly04,
1784         }, {
1785                 .compatible = "sharp,lq123p1jx31",
1786                 .data = &sharp_lq123p1jx31,
1787         }, {
1788                 .compatible = "sharp,lq150x1lg11",
1789                 .data = &sharp_lq150x1lg11,
1790         }, {
1791                 .compatible = "shelly,sca07010-bfn-lnn",
1792                 .data = &shelly_sca07010_bfn_lnn,
1793         }, {
1794                 .compatible = "starry,kr122ea0sra",
1795                 .data = &starry_kr122ea0sra,
1796         }, {
1797                 .compatible = "tianma,tm070jdhg30",
1798                 .data = &tianma_tm070jdhg30,
1799         }, {
1800                 .compatible = "tpk,f07a-0102",
1801                 .data = &tpk_f07a_0102,
1802         }, {
1803                 .compatible = "tpk,f10a-0102",
1804                 .data = &tpk_f10a_0102,
1805         }, {
1806                 .compatible = "urt,umsh-8596md-t",
1807                 .data = &urt_umsh_8596md_parallel,
1808         }, {
1809                 .compatible = "urt,umsh-8596md-1t",
1810                 .data = &urt_umsh_8596md_parallel,
1811         }, {
1812                 .compatible = "urt,umsh-8596md-7t",
1813                 .data = &urt_umsh_8596md_parallel,
1814         }, {
1815                 .compatible = "urt,umsh-8596md-11t",
1816                 .data = &urt_umsh_8596md_lvds,
1817         }, {
1818                 .compatible = "urt,umsh-8596md-19t",
1819                 .data = &urt_umsh_8596md_lvds,
1820         }, {
1821                 .compatible = "urt,umsh-8596md-20t",
1822                 .data = &urt_umsh_8596md_parallel,
1823         }, {
1824                 .compatible = "winstar,wf35ltiacd",
1825                 .data = &winstar_wf35ltiacd,
1826         }, {
1827                 /* sentinel */
1828         }
1829 };
1830 MODULE_DEVICE_TABLE(of, platform_of_match);
1831
1832 static int panel_simple_platform_probe(struct platform_device *pdev)
1833 {
1834         const struct of_device_id *id;
1835
1836         id = of_match_node(platform_of_match, pdev->dev.of_node);
1837         if (!id)
1838                 return -ENODEV;
1839
1840         return panel_simple_probe(&pdev->dev, id->data);
1841 }
1842
1843 static int panel_simple_platform_remove(struct platform_device *pdev)
1844 {
1845         return panel_simple_remove(&pdev->dev);
1846 }
1847
1848 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1849 {
1850         panel_simple_shutdown(&pdev->dev);
1851 }
1852
1853 static struct platform_driver panel_simple_platform_driver = {
1854         .driver = {
1855                 .name = "panel-simple",
1856                 .of_match_table = platform_of_match,
1857         },
1858         .probe = panel_simple_platform_probe,
1859         .remove = panel_simple_platform_remove,
1860         .shutdown = panel_simple_platform_shutdown,
1861 };
1862
1863 struct panel_desc_dsi {
1864         struct panel_desc desc;
1865
1866         unsigned long flags;
1867         enum mipi_dsi_pixel_format format;
1868         unsigned int lanes;
1869 };
1870
1871 static const struct drm_display_mode auo_b080uan01_mode =
1872         SP_DISPLAY_MODE(154500, 1200, 62, 4, 62, 1920, 9, 2, 8, 60, 0);
1873
1874 static const struct panel_desc_dsi auo_b080uan01 = {
1875         .desc = {
1876                 .modes = &auo_b080uan01_mode,
1877                 .num_modes = 1,
1878                 .bpc = 8,
1879                 .size = {
1880                         .width = 108,
1881                         .height = 272,
1882                 },
1883         },
1884         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1885         .format = MIPI_DSI_FMT_RGB888,
1886         .lanes = 4,
1887 };
1888
1889 static const struct drm_display_mode boe_tv080wum_nl0_mode =
1890         SP_DISPLAY_MODE(160000, 1200, 120, 20, 21, 1920, 21, 3, 18, 60,
1891                          DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
1892
1893 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1894         .desc = {
1895                 .modes = &boe_tv080wum_nl0_mode,
1896                 .num_modes = 1,
1897                 .size = {
1898                         .width = 107,
1899                         .height = 172,
1900                 },
1901         },
1902         .flags = MIPI_DSI_MODE_VIDEO |
1903                  MIPI_DSI_MODE_VIDEO_BURST |
1904                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1905         .format = MIPI_DSI_FMT_RGB888,
1906         .lanes = 4,
1907 };
1908
1909 static const struct drm_display_mode lg_ld070wx3_sl01_mode =
1910         SP_DISPLAY_MODE(71000, 800, 32, 1, 57, 1280, 28, 1, 14, 60, 0);
1911
1912 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1913         .desc = {
1914                 .modes = &lg_ld070wx3_sl01_mode,
1915                 .num_modes = 1,
1916                 .bpc = 8,
1917                 .size = {
1918                         .width = 94,
1919                         .height = 151,
1920                 },
1921         },
1922         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1923         .format = MIPI_DSI_FMT_RGB888,
1924         .lanes = 4,
1925 };
1926
1927 static const struct drm_display_mode lg_lh500wx1_sd03_mode =
1928         SP_DISPLAY_MODE(67000, 720, 12, 4, 112, 1280, 8, 4, 12, 60, 0);
1929
1930 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1931         .desc = {
1932                 .modes = &lg_lh500wx1_sd03_mode,
1933                 .num_modes = 1,
1934                 .bpc = 8,
1935                 .size = {
1936                         .width = 62,
1937                         .height = 110,
1938                 },
1939         },
1940         .flags = MIPI_DSI_MODE_VIDEO,
1941         .format = MIPI_DSI_FMT_RGB888,
1942         .lanes = 4,
1943 };
1944
1945 static const struct drm_display_mode panasonic_vvx10f004b00_mode =
1946         SP_DISPLAY_MODE(157200, 1920, 154, 16, 32, 1200, 17, 2, 16, 60, 0);
1947
1948 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1949         .desc = {
1950                 .modes = &panasonic_vvx10f004b00_mode,
1951                 .num_modes = 1,
1952                 .bpc = 8,
1953                 .size = {
1954                         .width = 217,
1955                         .height = 136,
1956                 },
1957         },
1958         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1959                  MIPI_DSI_CLOCK_NON_CONTINUOUS,
1960         .format = MIPI_DSI_FMT_RGB888,
1961         .lanes = 4,
1962 };
1963
1964 static const struct of_device_id dsi_of_match[] = {
1965         {
1966                 .compatible = "auo,b080uan01",
1967                 .data = &auo_b080uan01
1968         }, {
1969                 .compatible = "boe,tv080wum-nl0",
1970                 .data = &boe_tv080wum_nl0
1971         }, {
1972                 .compatible = "lg,ld070wx3-sl01",
1973                 .data = &lg_ld070wx3_sl01
1974         }, {
1975                 .compatible = "lg,lh500wx1-sd03",
1976                 .data = &lg_lh500wx1_sd03
1977         }, {
1978                 .compatible = "panasonic,vvx10f004b00",
1979                 .data = &panasonic_vvx10f004b00
1980         }, {
1981                 /* sentinel */
1982         }
1983 };
1984 MODULE_DEVICE_TABLE(of, dsi_of_match);
1985
1986 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1987 {
1988         const struct panel_desc_dsi *desc;
1989         const struct of_device_id *id;
1990         int err;
1991
1992         id = of_match_node(dsi_of_match, dsi->dev.of_node);
1993         if (!id)
1994                 return -ENODEV;
1995
1996         desc = id->data;
1997
1998         err = panel_simple_probe(&dsi->dev, &desc->desc);
1999         if (err < 0)
2000                 return err;
2001
2002         dsi->mode_flags = desc->flags;
2003         dsi->format = desc->format;
2004         dsi->lanes = desc->lanes;
2005
2006         return mipi_dsi_attach(dsi);
2007 }
2008
2009 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2010 {
2011         int err;
2012
2013         err = mipi_dsi_detach(dsi);
2014         if (err < 0)
2015                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2016
2017         return panel_simple_remove(&dsi->dev);
2018 }
2019
2020 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2021 {
2022         panel_simple_shutdown(&dsi->dev);
2023 }
2024
2025 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2026         .driver = {
2027                 .name = "panel-simple-dsi",
2028                 .of_match_table = dsi_of_match,
2029         },
2030         .probe = panel_simple_dsi_probe,
2031         .remove = panel_simple_dsi_remove,
2032         .shutdown = panel_simple_dsi_shutdown,
2033 };
2034
2035 static int __init panel_simple_init(void)
2036 {
2037         int err;
2038
2039         err = platform_driver_register(&panel_simple_platform_driver);
2040         if (err < 0)
2041                 return err;
2042
2043         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2044                 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2045                 if (err < 0)
2046                         return err;
2047         }
2048
2049         return 0;
2050 }
2051 module_init(panel_simple_init);
2052
2053 static void __exit panel_simple_exit(void)
2054 {
2055         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2056                 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2057
2058         platform_driver_unregister(&panel_simple_platform_driver);
2059 }
2060 module_exit(panel_simple_exit);
2061
2062 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2063 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2064 MODULE_LICENSE("GPL and additional rights");