drivers/gpu/drm/tegra/gr3d.c

   1 /*
   2  * Copyright (C) 2013 Avionic Design GmbH
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/host1x.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/tegra-powergate.h>
  15
  16 #include "drm.h"
  17 #include "gem.h"
  18 #include "gr3d.h"
  19
  20 struct gr3d {
  21         struct tegra_drm_client client;
  22         struct host1x_channel *channel;
  23         struct clk *clk_secondary;
  24         struct clk *clk;
  25
  26         DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
  27 };
  28
  29 static inline struct gr3d *to_gr3d(struct tegra_drm_client *client)
  30 {
  31         return container_of(client, struct gr3d, client);
  32 }
  33
  34 static int gr3d_init(struct host1x_client *client)
  35 {
  36         struct tegra_drm_client *drm = host1x_to_drm_client(client);
  37         struct tegra_drm *tegra = dev_get_drvdata(client->parent);
  38         struct gr3d *gr3d = to_gr3d(drm);
  39
  40         gr3d->channel = host1x_channel_request(client->dev);
  41         if (!gr3d->channel)
  42                 return -ENOMEM;
  43
  44         client->syncpts[0] = host1x_syncpt_request(client->dev, 0);
  45         if (!client->syncpts[0]) {
  46                 host1x_channel_free(gr3d->channel);
  47                 return -ENOMEM;
  48         }
  49
  50         return tegra_drm_register_client(tegra, drm);
  51 }
  52
  53 static int gr3d_exit(struct host1x_client *client)
  54 {
  55         struct tegra_drm_client *drm = host1x_to_drm_client(client);
  56         struct tegra_drm *tegra = dev_get_drvdata(client->parent);
  57         struct gr3d *gr3d = to_gr3d(drm);
  58         int err;
  59
  60         err = tegra_drm_unregister_client(tegra, drm);
  61         if (err < 0)
  62                 return err;
  63
  64         host1x_syncpt_free(client->syncpts[0]);
  65         host1x_channel_free(gr3d->channel);
  66
  67         return 0;
  68 }
  69
  70 static const struct host1x_client_ops gr3d_client_ops = {
  71         .init = gr3d_init,
  72         .exit = gr3d_exit,
  73 };
  74
  75 static int gr3d_open_channel(struct tegra_drm_client *client,
  76                              struct tegra_drm_context *context)
  77 {
  78         struct gr3d *gr3d = to_gr3d(client);
  79
  80         context->channel = host1x_channel_get(gr3d->channel);
  81         if (!context->channel)
  82                 return -ENOMEM;
  83
  84         return 0;
  85 }
  86
  87 static void gr3d_close_channel(struct tegra_drm_context *context)
  88 {
  89         host1x_channel_put(context->channel);
  90 }
  91
  92 static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset)
  93 {
  94         struct gr3d *gr3d = dev_get_drvdata(dev);
  95
  96         switch (class) {
  97         case HOST1X_CLASS_HOST1X:
  98                 if (offset == 0x2b)
  99                         return 1;
 100
 101                 break;
 102
 103         case HOST1X_CLASS_GR3D:
 104                 if (offset >= GR3D_NUM_REGS)
 105                         break;
 106
 107                 if (test_bit(offset, gr3d->addr_regs))
 108                         return 1;
 109
 110                 break;
 111         }
 112
 113         return 0;
 114 }
 115
 116 static const struct tegra_drm_client_ops gr3d_ops = {
 117         .open_channel = gr3d_open_channel,
 118         .close_channel = gr3d_close_channel,
 119         .is_addr_reg = gr3d_is_addr_reg,
 120         .submit = tegra_drm_submit,
 121 };
 122
 123 static const struct of_device_id tegra_gr3d_match[] = {
 124         { .compatible = "nvidia,tegra114-gr3d" },
 125         { .compatible = "nvidia,tegra30-gr3d" },
 126         { .compatible = "nvidia,tegra20-gr3d" },
 127         { }
 128 };
 129
 130 static const u32 gr3d_addr_regs[] = {
 131         GR3D_IDX_ATTRIBUTE( 0),
 132         GR3D_IDX_ATTRIBUTE( 1),
 133         GR3D_IDX_ATTRIBUTE( 2),
 134         GR3D_IDX_ATTRIBUTE( 3),
 135         GR3D_IDX_ATTRIBUTE( 4),
 136         GR3D_IDX_ATTRIBUTE( 5),
 137         GR3D_IDX_ATTRIBUTE( 6),
 138         GR3D_IDX_ATTRIBUTE( 7),
 139         GR3D_IDX_ATTRIBUTE( 8),
 140         GR3D_IDX_ATTRIBUTE( 9),
 141         GR3D_IDX_ATTRIBUTE(10),
 142         GR3D_IDX_ATTRIBUTE(11),
 143         GR3D_IDX_ATTRIBUTE(12),
 144         GR3D_IDX_ATTRIBUTE(13),
 145         GR3D_IDX_ATTRIBUTE(14),
 146         GR3D_IDX_ATTRIBUTE(15),
 147         GR3D_IDX_INDEX_BASE,
 148         GR3D_QR_ZTAG_ADDR,
 149         GR3D_QR_CTAG_ADDR,
 150         GR3D_QR_CZ_ADDR,
 151         GR3D_TEX_TEX_ADDR( 0),
 152         GR3D_TEX_TEX_ADDR( 1),
 153         GR3D_TEX_TEX_ADDR( 2),
 154         GR3D_TEX_TEX_ADDR( 3),
 155         GR3D_TEX_TEX_ADDR( 4),
 156         GR3D_TEX_TEX_ADDR( 5),
 157         GR3D_TEX_TEX_ADDR( 6),
 158         GR3D_TEX_TEX_ADDR( 7),
 159         GR3D_TEX_TEX_ADDR( 8),
 160         GR3D_TEX_TEX_ADDR( 9),
 161         GR3D_TEX_TEX_ADDR(10),
 162         GR3D_TEX_TEX_ADDR(11),
 163         GR3D_TEX_TEX_ADDR(12),
 164         GR3D_TEX_TEX_ADDR(13),
 165         GR3D_TEX_TEX_ADDR(14),
 166         GR3D_TEX_TEX_ADDR(15),
 167         GR3D_DW_MEMORY_OUTPUT_ADDRESS,
 168         GR3D_GLOBAL_SURFADDR( 0),
 169         GR3D_GLOBAL_SURFADDR( 1),
 170         GR3D_GLOBAL_SURFADDR( 2),
 171         GR3D_GLOBAL_SURFADDR( 3),
 172         GR3D_GLOBAL_SURFADDR( 4),
 173         GR3D_GLOBAL_SURFADDR( 5),
 174         GR3D_GLOBAL_SURFADDR( 6),
 175         GR3D_GLOBAL_SURFADDR( 7),
 176         GR3D_GLOBAL_SURFADDR( 8),
 177         GR3D_GLOBAL_SURFADDR( 9),
 178         GR3D_GLOBAL_SURFADDR(10),
 179         GR3D_GLOBAL_SURFADDR(11),
 180         GR3D_GLOBAL_SURFADDR(12),
 181         GR3D_GLOBAL_SURFADDR(13),
 182         GR3D_GLOBAL_SURFADDR(14),
 183         GR3D_GLOBAL_SURFADDR(15),
 184         GR3D_GLOBAL_SPILLSURFADDR,
 185         GR3D_GLOBAL_SURFOVERADDR( 0),
 186         GR3D_GLOBAL_SURFOVERADDR( 1),
 187         GR3D_GLOBAL_SURFOVERADDR( 2),
 188         GR3D_GLOBAL_SURFOVERADDR( 3),
 189         GR3D_GLOBAL_SURFOVERADDR( 4),
 190         GR3D_GLOBAL_SURFOVERADDR( 5),
 191         GR3D_GLOBAL_SURFOVERADDR( 6),
 192         GR3D_GLOBAL_SURFOVERADDR( 7),
 193         GR3D_GLOBAL_SURFOVERADDR( 8),
 194         GR3D_GLOBAL_SURFOVERADDR( 9),
 195         GR3D_GLOBAL_SURFOVERADDR(10),
 196         GR3D_GLOBAL_SURFOVERADDR(11),
 197         GR3D_GLOBAL_SURFOVERADDR(12),
 198         GR3D_GLOBAL_SURFOVERADDR(13),
 199         GR3D_GLOBAL_SURFOVERADDR(14),
 200         GR3D_GLOBAL_SURFOVERADDR(15),
 201         GR3D_GLOBAL_SAMP01SURFADDR( 0),
 202         GR3D_GLOBAL_SAMP01SURFADDR( 1),
 203         GR3D_GLOBAL_SAMP01SURFADDR( 2),
 204         GR3D_GLOBAL_SAMP01SURFADDR( 3),
 205         GR3D_GLOBAL_SAMP01SURFADDR( 4),
 206         GR3D_GLOBAL_SAMP01SURFADDR( 5),
 207         GR3D_GLOBAL_SAMP01SURFADDR( 6),
 208         GR3D_GLOBAL_SAMP01SURFADDR( 7),
 209         GR3D_GLOBAL_SAMP01SURFADDR( 8),
 210         GR3D_GLOBAL_SAMP01SURFADDR( 9),
 211         GR3D_GLOBAL_SAMP01SURFADDR(10),
 212         GR3D_GLOBAL_SAMP01SURFADDR(11),
 213         GR3D_GLOBAL_SAMP01SURFADDR(12),
 214         GR3D_GLOBAL_SAMP01SURFADDR(13),
 215         GR3D_GLOBAL_SAMP01SURFADDR(14),
 216         GR3D_GLOBAL_SAMP01SURFADDR(15),
 217         GR3D_GLOBAL_SAMP23SURFADDR( 0),
 218         GR3D_GLOBAL_SAMP23SURFADDR( 1),
 219         GR3D_GLOBAL_SAMP23SURFADDR( 2),
 220         GR3D_GLOBAL_SAMP23SURFADDR( 3),
 221         GR3D_GLOBAL_SAMP23SURFADDR( 4),
 222         GR3D_GLOBAL_SAMP23SURFADDR( 5),
 223         GR3D_GLOBAL_SAMP23SURFADDR( 6),
 224         GR3D_GLOBAL_SAMP23SURFADDR( 7),
 225         GR3D_GLOBAL_SAMP23SURFADDR( 8),
 226         GR3D_GLOBAL_SAMP23SURFADDR( 9),
 227         GR3D_GLOBAL_SAMP23SURFADDR(10),
 228         GR3D_GLOBAL_SAMP23SURFADDR(11),
 229         GR3D_GLOBAL_SAMP23SURFADDR(12),
 230         GR3D_GLOBAL_SAMP23SURFADDR(13),
 231         GR3D_GLOBAL_SAMP23SURFADDR(14),
 232         GR3D_GLOBAL_SAMP23SURFADDR(15),
 233 };
 234
 235 static int gr3d_probe(struct platform_device *pdev)
 236 {
 237         struct device_node *np = pdev->dev.of_node;
 238         struct host1x_syncpt **syncpts;
 239         struct gr3d *gr3d;
 240         unsigned int i;
 241         int err;
 242
 243         gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL);
 244         if (!gr3d)
 245                 return -ENOMEM;
 246
 247         syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL);
 248         if (!syncpts)
 249                 return -ENOMEM;
 250
 251         gr3d->clk = devm_clk_get(&pdev->dev, NULL);
 252         if (IS_ERR(gr3d->clk)) {
 253                 dev_err(&pdev->dev, "cannot get clock\n");
 254                 return PTR_ERR(gr3d->clk);
 255         }
 256
 257         if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) {
 258                 gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2");
 259                 if (IS_ERR(gr3d->clk)) {
 260                         dev_err(&pdev->dev, "cannot get secondary clock\n");
 261                         return PTR_ERR(gr3d->clk);
 262                 }
 263         }
 264
 265         err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk);
 266         if (err < 0) {
 267                 dev_err(&pdev->dev, "failed to power up 3D unit\n");
 268                 return err;
 269         }
 270
 271         if (gr3d->clk_secondary) {
 272                 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1,
 273                                                         gr3d->clk_secondary);
 274                 if (err < 0) {
 275                         dev_err(&pdev->dev,
 276                                 "failed to power up secondary 3D unit\n");
 277                         return err;
 278                 }
 279         }
 280
 281         INIT_LIST_HEAD(&gr3d->client.base.list);
 282         gr3d->client.base.ops = &gr3d_client_ops;
 283         gr3d->client.base.dev = &pdev->dev;
 284         gr3d->client.base.class = HOST1X_CLASS_GR3D;
 285         gr3d->client.base.syncpts = syncpts;
 286         gr3d->client.base.num_syncpts = 1;
 287
 288         INIT_LIST_HEAD(&gr3d->client.list);
 289         gr3d->client.ops = &gr3d_ops;
 290
 291         err = host1x_client_register(&gr3d->client.base);
 292         if (err < 0) {
 293                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
 294                         err);
 295                 return err;
 296         }
 297
 298         /* initialize address register map */
 299         for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++)
 300                 set_bit(gr3d_addr_regs[i], gr3d->addr_regs);
 301
 302         platform_set_drvdata(pdev, gr3d);
 303
 304         return 0;
 305 }
 306
 307 static int gr3d_remove(struct platform_device *pdev)
 308 {
 309         struct gr3d *gr3d = platform_get_drvdata(pdev);
 310         int err;
 311
 312         err = host1x_client_unregister(&gr3d->client.base);
 313         if (err < 0) {
 314                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
 315                         err);
 316                 return err;
 317         }
 318
 319         if (gr3d->clk_secondary) {
 320                 tegra_powergate_power_off(TEGRA_POWERGATE_3D1);
 321                 clk_disable_unprepare(gr3d->clk_secondary);
 322         }
 323
 324         tegra_powergate_power_off(TEGRA_POWERGATE_3D);
 325         clk_disable_unprepare(gr3d->clk);
 326
 327         return 0;
 328 }
 329
 330 struct platform_driver tegra_gr3d_driver = {
 331         .driver = {
 332                 .name = "tegra-gr3d",
 333                 .of_match_table = tegra_gr3d_match,
 334         },
 335         .probe = gr3d_probe,
 336         .remove = gr3d_remove,
 337 };