drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2013, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/clockchips.h>
  59 #include <trace/events/power.h>
  60 #include <linux/sched.h>
  61 #include <linux/notifier.h>
  62 #include <linux/cpu.h>
  63 #include <linux/module.h>
  64 #include <asm/cpu_device_id.h>
  65 #include <asm/mwait.h>
  66 #include <asm/msr.h>
  67
  68 #define INTEL_IDLE_VERSION "0.4"
  69 #define PREFIX "intel_idle: "
  70
  71 static struct cpuidle_driver intel_idle_driver = {
  72         .name = "intel_idle",
  73         .owner = THIS_MODULE,
  74 };
  75 /* intel_idle.max_cstate=0 disables driver */
  76 static int max_cstate = CPUIDLE_STATE_MAX - 1;
  77
  78 static unsigned int mwait_substates;
  79
  80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
  81 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  82 static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
  83
  84 struct idle_cpu {
  85         struct cpuidle_state *state_table;
  86
  87         /*
  88          * Hardware C-state auto-demotion may not always be optimal.
  89          * Indicate which enable bits to clear here.
  90          */
  91         unsigned long auto_demotion_disable_flags;
  92         bool disable_promotion_to_c1e;
  93 };
  94
  95 static const struct idle_cpu *icpu;
  96 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  97 static int intel_idle(struct cpuidle_device *dev,
  98                         struct cpuidle_driver *drv, int index);
  99 static int intel_idle_cpu_init(int cpu);
 100
 101 static struct cpuidle_state *cpuidle_state_table;
 102
 103 /*
 104  * Set this flag for states where the HW flushes the TLB for us
 105  * and so we don't need cross-calls to keep it consistent.
 106  * If this flag is set, SW flushes the TLB, so even if the
 107  * HW doesn't do the flushing, this flag is safe to use.
 108  */
 109 #define CPUIDLE_FLAG_TLB_FLUSHED        0x10000
 110
 111 /*
 112  * MWAIT takes an 8-bit "hint" in EAX "suggesting"
 113  * the C-state (top nibble) and sub-state (bottom nibble)
 114  * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
 115  *
 116  * We store the hint at the top of our "flags" for each state.
 117  */
 118 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
 119 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
 120
 121 /*
 122  * States are indexed by the cstate number,
 123  * which is also the index into the MWAIT hint array.
 124  * Thus C0 is a dummy.
 125  */
 126 static struct cpuidle_state nehalem_cstates[] __initdata = {
 127         {
 128                 .name = "C1-NHM",
 129                 .desc = "MWAIT 0x00",
 130                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 131                 .exit_latency = 3,
 132                 .target_residency = 6,
 133                 .enter = &intel_idle },
 134         {
 135                 .name = "C1E-NHM",
 136                 .desc = "MWAIT 0x01",
 137                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 138                 .exit_latency = 10,
 139                 .target_residency = 20,
 140                 .enter = &intel_idle },
 141         {
 142                 .name = "C3-NHM",
 143                 .desc = "MWAIT 0x10",
 144                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 145                 .exit_latency = 20,
 146                 .target_residency = 80,
 147                 .enter = &intel_idle },
 148         {
 149                 .name = "C6-NHM",
 150                 .desc = "MWAIT 0x20",
 151                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 152                 .exit_latency = 200,
 153                 .target_residency = 800,
 154                 .enter = &intel_idle },
 155         {
 156                 .enter = NULL }
 157 };
 158
 159 static struct cpuidle_state snb_cstates[] __initdata = {
 160         {
 161                 .name = "C1-SNB",
 162                 .desc = "MWAIT 0x00",
 163                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 164                 .exit_latency = 2,
 165                 .target_residency = 2,
 166                 .enter = &intel_idle },
 167         {
 168                 .name = "C1E-SNB",
 169                 .desc = "MWAIT 0x01",
 170                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 171                 .exit_latency = 10,
 172                 .target_residency = 20,
 173                 .enter = &intel_idle },
 174         {
 175                 .name = "C3-SNB",
 176                 .desc = "MWAIT 0x10",
 177                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 178                 .exit_latency = 80,
 179                 .target_residency = 211,
 180                 .enter = &intel_idle },
 181         {
 182                 .name = "C6-SNB",
 183                 .desc = "MWAIT 0x20",
 184                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 185                 .exit_latency = 104,
 186                 .target_residency = 345,
 187                 .enter = &intel_idle },
 188         {
 189                 .name = "C7-SNB",
 190                 .desc = "MWAIT 0x30",
 191                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 192                 .exit_latency = 109,
 193                 .target_residency = 345,
 194                 .enter = &intel_idle },
 195         {
 196                 .enter = NULL }
 197 };
 198
 199 static struct cpuidle_state ivb_cstates[] __initdata = {
 200         {
 201                 .name = "C1-IVB",
 202                 .desc = "MWAIT 0x00",
 203                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 204                 .exit_latency = 1,
 205                 .target_residency = 1,
 206                 .enter = &intel_idle },
 207         {
 208                 .name = "C1E-IVB",
 209                 .desc = "MWAIT 0x01",
 210                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 211                 .exit_latency = 10,
 212                 .target_residency = 20,
 213                 .enter = &intel_idle },
 214         {
 215                 .name = "C3-IVB",
 216                 .desc = "MWAIT 0x10",
 217                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 218                 .exit_latency = 59,
 219                 .target_residency = 156,
 220                 .enter = &intel_idle },
 221         {
 222                 .name = "C6-IVB",
 223                 .desc = "MWAIT 0x20",
 224                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 225                 .exit_latency = 80,
 226                 .target_residency = 300,
 227                 .enter = &intel_idle },
 228         {
 229                 .name = "C7-IVB",
 230                 .desc = "MWAIT 0x30",
 231                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 232                 .exit_latency = 87,
 233                 .target_residency = 300,
 234                 .enter = &intel_idle },
 235         {
 236                 .enter = NULL }
 237 };
 238
 239 static struct cpuidle_state hsw_cstates[] __initdata = {
 240         {
 241                 .name = "C1-HSW",
 242                 .desc = "MWAIT 0x00",
 243                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 244                 .exit_latency = 2,
 245                 .target_residency = 2,
 246                 .enter = &intel_idle },
 247         {
 248                 .name = "C1E-HSW",
 249                 .desc = "MWAIT 0x01",
 250                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 251                 .exit_latency = 10,
 252                 .target_residency = 20,
 253                 .enter = &intel_idle },
 254         {
 255                 .name = "C3-HSW",
 256                 .desc = "MWAIT 0x10",
 257                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 258                 .exit_latency = 33,
 259                 .target_residency = 100,
 260                 .enter = &intel_idle },
 261         {
 262                 .name = "C6-HSW",
 263                 .desc = "MWAIT 0x20",
 264                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 265                 .exit_latency = 133,
 266                 .target_residency = 400,
 267                 .enter = &intel_idle },
 268         {
 269                 .name = "C7s-HSW",
 270                 .desc = "MWAIT 0x32",
 271                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 272                 .exit_latency = 166,
 273                 .target_residency = 500,
 274                 .enter = &intel_idle },
 275         {
 276                 .name = "C8-HSW",
 277                 .desc = "MWAIT 0x40",
 278                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 279                 .exit_latency = 300,
 280                 .target_residency = 900,
 281                 .enter = &intel_idle },
 282         {
 283                 .name = "C9-HSW",
 284                 .desc = "MWAIT 0x50",
 285                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 286                 .exit_latency = 600,
 287                 .target_residency = 1800,
 288                 .enter = &intel_idle },
 289         {
 290                 .name = "C10-HSW",
 291                 .desc = "MWAIT 0x60",
 292                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 293                 .exit_latency = 2600,
 294                 .target_residency = 7700,
 295                 .enter = &intel_idle },
 296         {
 297                 .enter = NULL }
 298 };
 299
 300 static struct cpuidle_state atom_cstates[] __initdata = {
 301         {
 302                 .name = "C1E-ATM",
 303                 .desc = "MWAIT 0x00",
 304                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 305                 .exit_latency = 10,
 306                 .target_residency = 20,
 307                 .enter = &intel_idle },
 308         {
 309                 .name = "C2-ATM",
 310                 .desc = "MWAIT 0x10",
 311                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,
 312                 .exit_latency = 20,
 313                 .target_residency = 80,
 314                 .enter = &intel_idle },
 315         {
 316                 .name = "C4-ATM",
 317                 .desc = "MWAIT 0x30",
 318                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 319                 .exit_latency = 100,
 320                 .target_residency = 400,
 321                 .enter = &intel_idle },
 322         {
 323                 .name = "C6-ATM",
 324                 .desc = "MWAIT 0x52",
 325                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 326                 .exit_latency = 140,
 327                 .target_residency = 560,
 328                 .enter = &intel_idle },
 329         {
 330                 .enter = NULL }
 331 };
 332 static struct cpuidle_state avn_cstates[CPUIDLE_STATE_MAX] = {
 333         {
 334                 .name = "C1-AVN",
 335                 .desc = "MWAIT 0x00",
 336                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 337                 .exit_latency = 1,
 338                 .target_residency = 1,
 339                 .enter = &intel_idle },
 340         {
 341                 .name = "C1E-AVN",
 342                 .desc = "MWAIT 0x01",
 343                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 344                 .exit_latency = 5,
 345                 .target_residency = 10,
 346                 .enter = &intel_idle },
 347         {
 348                 .name = "C6NS-AVN",     /* No Cache Shrink */
 349                 .desc = "MWAIT 0x51",
 350                 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 351                 .exit_latency = 15,
 352                 .target_residency = 45,
 353                 .enter = &intel_idle },
 354         {
 355                 .name = "C6FS-AVN",     /* Full Cache shrink */
 356                 .desc = "MWAIT 0x52",
 357                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 358                 .exit_latency = 150,            /* fake penalty added due to cold cache */
 359                 .target_residency = 100000,     /* fake penalty added due to cold cache */
 360                 .enter = &intel_idle },
 361 };
 362
 363 /**
 364  * intel_idle
 365  * @dev: cpuidle_device
 366  * @drv: cpuidle driver
 367  * @index: index of cpuidle state
 368  *
 369  * Must be called under local_irq_disable().
 370  */
 371 static int intel_idle(struct cpuidle_device *dev,
 372                 struct cpuidle_driver *drv, int index)
 373 {
 374         unsigned long ecx = 1; /* break on interrupt flag */
 375         struct cpuidle_state *state = &drv->states[index];
 376         unsigned long eax = flg2MWAIT(state->flags);
 377         unsigned int cstate;
 378         int cpu = smp_processor_id();
 379
 380         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 381
 382         /*
 383          * leave_mm() to avoid costly and often unnecessary wakeups
 384          * for flushing the user TLB's associated with the active mm.
 385          */
 386         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 387                 leave_mm(cpu);
 388
 389         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 390                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 391
 392         if (!current_set_polling_and_test()) {
 393
 394                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 395                 smp_mb();
 396                 if (!need_resched())
 397                         __mwait(eax, ecx);
 398         }
 399
 400         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 401                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 402
 403         return index;
 404 }
 405
 406 static void __setup_broadcast_timer(void *arg)
 407 {
 408         unsigned long reason = (unsigned long)arg;
 409         int cpu = smp_processor_id();
 410
 411         reason = reason ?
 412                 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
 413
 414         clockevents_notify(reason, &cpu);
 415 }
 416
 417 static int cpu_hotplug_notify(struct notifier_block *n,
 418                               unsigned long action, void *hcpu)
 419 {
 420         int hotcpu = (unsigned long)hcpu;
 421         struct cpuidle_device *dev;
 422
 423         switch (action & 0xf) {
 424         case CPU_ONLINE:
 425
 426                 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 427                         smp_call_function_single(hotcpu, __setup_broadcast_timer,
 428                                                  (void *)true, 1);
 429
 430                 /*
 431                  * Some systems can hotplug a cpu at runtime after
 432                  * the kernel has booted, we have to initialize the
 433                  * driver in this case
 434                  */
 435                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
 436                 if (!dev->registered)
 437                         intel_idle_cpu_init(hotcpu);
 438
 439                 break;
 440         }
 441         return NOTIFY_OK;
 442 }
 443
 444 static struct notifier_block cpu_hotplug_notifier = {
 445         .notifier_call = cpu_hotplug_notify,
 446 };
 447
 448 static void auto_demotion_disable(void *dummy)
 449 {
 450         unsigned long long msr_bits;
 451
 452         rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 453         msr_bits &= ~(icpu->auto_demotion_disable_flags);
 454         wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 455 }
 456 static void c1e_promotion_disable(void *dummy)
 457 {
 458         unsigned long long msr_bits;
 459
 460         rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
 461         msr_bits &= ~0x2;
 462         wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
 463 }
 464
 465 static const struct idle_cpu idle_cpu_nehalem = {
 466         .state_table = nehalem_cstates,
 467         .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
 468         .disable_promotion_to_c1e = true,
 469 };
 470
 471 static const struct idle_cpu idle_cpu_atom = {
 472         .state_table = atom_cstates,
 473 };
 474
 475 static const struct idle_cpu idle_cpu_lincroft = {
 476         .state_table = atom_cstates,
 477         .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
 478 };
 479
 480 static const struct idle_cpu idle_cpu_snb = {
 481         .state_table = snb_cstates,
 482         .disable_promotion_to_c1e = true,
 483 };
 484
 485 static const struct idle_cpu idle_cpu_ivb = {
 486         .state_table = ivb_cstates,
 487         .disable_promotion_to_c1e = true,
 488 };
 489
 490 static const struct idle_cpu idle_cpu_hsw = {
 491         .state_table = hsw_cstates,
 492         .disable_promotion_to_c1e = true,
 493 };
 494
 495 static const struct idle_cpu idle_cpu_avn = {
 496         .state_table = avn_cstates,
 497         .disable_promotion_to_c1e = true,
 498 };
 499
 500 #define ICPU(model, cpu) \
 501         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
 502
 503 static const struct x86_cpu_id intel_idle_ids[] = {
 504         ICPU(0x1a, idle_cpu_nehalem),
 505         ICPU(0x1e, idle_cpu_nehalem),
 506         ICPU(0x1f, idle_cpu_nehalem),
 507         ICPU(0x25, idle_cpu_nehalem),
 508         ICPU(0x2c, idle_cpu_nehalem),
 509         ICPU(0x2e, idle_cpu_nehalem),
 510         ICPU(0x1c, idle_cpu_atom),
 511         ICPU(0x26, idle_cpu_lincroft),
 512         ICPU(0x2f, idle_cpu_nehalem),
 513         ICPU(0x2a, idle_cpu_snb),
 514         ICPU(0x2d, idle_cpu_snb),
 515         ICPU(0x3a, idle_cpu_ivb),
 516         ICPU(0x3e, idle_cpu_ivb),
 517         ICPU(0x3c, idle_cpu_hsw),
 518         ICPU(0x3f, idle_cpu_hsw),
 519         ICPU(0x45, idle_cpu_hsw),
 520         ICPU(0x46, idle_cpu_hsw),
 521         ICPU(0x4D, idle_cpu_avn),
 522         {}
 523 };
 524 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
 525
 526 /*
 527  * intel_idle_probe()
 528  */
 529 static int __init intel_idle_probe(void)
 530 {
 531         unsigned int eax, ebx, ecx;
 532         const struct x86_cpu_id *id;
 533
 534         if (max_cstate == 0) {
 535                 pr_debug(PREFIX "disabled\n");
 536                 return -EPERM;
 537         }
 538
 539         id = x86_match_cpu(intel_idle_ids);
 540         if (!id) {
 541                 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 542                     boot_cpu_data.x86 == 6)
 543                         pr_debug(PREFIX "does not run on family %d model %d\n",
 544                                 boot_cpu_data.x86, boot_cpu_data.x86_model);
 545                 return -ENODEV;
 546         }
 547
 548         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 549                 return -ENODEV;
 550
 551         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 552
 553         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 554             !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
 555             !mwait_substates)
 556                         return -ENODEV;
 557
 558         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 559
 560         icpu = (const struct idle_cpu *)id->driver_data;
 561         cpuidle_state_table = icpu->state_table;
 562
 563         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
 564                 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 565         else
 566                 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
 567
 568         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
 569                 " model 0x%X\n", boot_cpu_data.x86_model);
 570
 571         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
 572                 lapic_timer_reliable_states);
 573         return 0;
 574 }
 575
 576 /*
 577  * intel_idle_cpuidle_devices_uninit()
 578  * unregister, free cpuidle_devices
 579  */
 580 static void intel_idle_cpuidle_devices_uninit(void)
 581 {
 582         int i;
 583         struct cpuidle_device *dev;
 584
 585         for_each_online_cpu(i) {
 586                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 587                 cpuidle_unregister_device(dev);
 588         }
 589
 590         free_percpu(intel_idle_cpuidle_devices);
 591         return;
 592 }
 593 /*
 594  * intel_idle_cpuidle_driver_init()
 595  * allocate, initialize cpuidle_states
 596  */
 597 static int __init intel_idle_cpuidle_driver_init(void)
 598 {
 599         int cstate;
 600         struct cpuidle_driver *drv = &intel_idle_driver;
 601
 602         drv->state_count = 1;
 603
 604         for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
 605                 int num_substates, mwait_hint, mwait_cstate, mwait_substate;
 606
 607                 if (cpuidle_state_table[cstate].enter == NULL)
 608                         break;
 609
 610                 if (cstate + 1 > max_cstate) {
 611                         printk(PREFIX "max_cstate %d reached\n",
 612                                 max_cstate);
 613                         break;
 614                 }
 615
 616                 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
 617                 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
 618                 mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint);
 619
 620                 /* does the state exist in CPUID.MWAIT? */
 621                 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
 622                                         & MWAIT_SUBSTATE_MASK;
 623
 624                 /* if sub-state in table is not enumerated by CPUID */
 625                 if ((mwait_substate + 1) > num_substates)
 626                         continue;
 627
 628                 if (((mwait_cstate + 1) > 2) &&
 629                         !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 630                         mark_tsc_unstable("TSC halts in idle"
 631                                         " states deeper than C2");
 632
 633                 drv->states[drv->state_count] = /* structure copy */
 634                         cpuidle_state_table[cstate];
 635
 636                 drv->state_count += 1;
 637         }
 638
 639         if (icpu->auto_demotion_disable_flags)
 640                 on_each_cpu(auto_demotion_disable, NULL, 1);
 641
 642         if (icpu->disable_promotion_to_c1e)     /* each-cpu is redundant */
 643                 on_each_cpu(c1e_promotion_disable, NULL, 1);
 644
 645         return 0;
 646 }
 647
 648
 649 /*
 650  * intel_idle_cpu_init()
 651  * allocate, initialize, register cpuidle_devices
 652  * @cpu: cpu/core to initialize
 653  */
 654 static int intel_idle_cpu_init(int cpu)
 655 {
 656         int cstate;
 657         struct cpuidle_device *dev;
 658
 659         dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
 660
 661         dev->state_count = 1;
 662
 663         for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
 664                 int num_substates, mwait_hint, mwait_cstate, mwait_substate;
 665
 666                 if (cpuidle_state_table[cstate].enter == NULL)
 667                         break;
 668
 669                 if (cstate + 1 > max_cstate) {
 670                         printk(PREFIX "max_cstate %d reached\n", max_cstate);
 671                         break;
 672                 }
 673
 674                 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
 675                 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
 676                 mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint);
 677
 678                 /* does the state exist in CPUID.MWAIT? */
 679                 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
 680                                         & MWAIT_SUBSTATE_MASK;
 681
 682                 /* if sub-state in table is not enumerated by CPUID */
 683                 if ((mwait_substate + 1) > num_substates)
 684                         continue;
 685
 686                 dev->state_count += 1;
 687         }
 688
 689         dev->cpu = cpu;
 690
 691         if (cpuidle_register_device(dev)) {
 692                 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
 693                 intel_idle_cpuidle_devices_uninit();
 694                 return -EIO;
 695         }
 696
 697         if (icpu->auto_demotion_disable_flags)
 698                 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
 699
 700         return 0;
 701 }
 702
 703 static int __init intel_idle_init(void)
 704 {
 705         int retval, i;
 706
 707         /* Do not load intel_idle at all for now if idle= is passed */
 708         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
 709                 return -ENODEV;
 710
 711         retval = intel_idle_probe();
 712         if (retval)
 713                 return retval;
 714
 715         intel_idle_cpuidle_driver_init();
 716         retval = cpuidle_register_driver(&intel_idle_driver);
 717         if (retval) {
 718                 struct cpuidle_driver *drv = cpuidle_get_driver();
 719                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
 720                         drv ? drv->name : "none");
 721                 return retval;
 722         }
 723
 724         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
 725         if (intel_idle_cpuidle_devices == NULL)
 726                 return -ENOMEM;
 727
 728         for_each_online_cpu(i) {
 729                 retval = intel_idle_cpu_init(i);
 730                 if (retval) {
 731                         cpuidle_unregister_driver(&intel_idle_driver);
 732                         return retval;
 733                 }
 734         }
 735         register_cpu_notifier(&cpu_hotplug_notifier);
 736
 737         return 0;
 738 }
 739
 740 static void __exit intel_idle_exit(void)
 741 {
 742         intel_idle_cpuidle_devices_uninit();
 743         cpuidle_unregister_driver(&intel_idle_driver);
 744
 745
 746         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 747                 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
 748         unregister_cpu_notifier(&cpu_hotplug_notifier);
 749
 750         return;
 751 }
 752
 753 module_init(intel_idle_init);
 754 module_exit(intel_idle_exit);
 755
 756 module_param(max_cstate, int, 0444);
 757
 758 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
 759 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
 760 MODULE_LICENSE("GPL");