drivers/infiniband/hw/hfi1/chip.c

   1 /*
   2  * Copyright(c) 2015 - 2017 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 /*
  49  * This file contains all of the code that is specific to the HFI chip
  50  */
  51
  52 #include <linux/pci.h>
  53 #include <linux/delay.h>
  54 #include <linux/interrupt.h>
  55 #include <linux/module.h>
  56
  57 #include "hfi.h"
  58 #include "trace.h"
  59 #include "mad.h"
  60 #include "pio.h"
  61 #include "sdma.h"
  62 #include "eprom.h"
  63 #include "efivar.h"
  64 #include "platform.h"
  65 #include "aspm.h"
  66 #include "affinity.h"
  67 #include "debugfs.h"
  68
  69 #define NUM_IB_PORTS 1
  70
  71 uint kdeth_qp;
  72 module_param_named(kdeth_qp, kdeth_qp, uint, S_IRUGO);
  73 MODULE_PARM_DESC(kdeth_qp, "Set the KDETH queue pair prefix");
  74
  75 uint num_vls = HFI1_MAX_VLS_SUPPORTED;
  76 module_param(num_vls, uint, S_IRUGO);
  77 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
  78
  79 /*
  80  * Default time to aggregate two 10K packets from the idle state
  81  * (timer not running). The timer starts at the end of the first packet,
  82  * so only the time for one 10K packet and header plus a bit extra is needed.
  83  * 10 * 1024 + 64 header byte = 10304 byte
  84  * 10304 byte / 12.5 GB/s = 824.32ns
  85  */
  86 uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */
  87 module_param(rcv_intr_timeout, uint, S_IRUGO);
  88 MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns");
  89
  90 uint rcv_intr_count = 16; /* same as qib */
  91 module_param(rcv_intr_count, uint, S_IRUGO);
  92 MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count");
  93
  94 ushort link_crc_mask = SUPPORTED_CRCS;
  95 module_param(link_crc_mask, ushort, S_IRUGO);
  96 MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link");
  97
  98 uint loopback;
  99 module_param_named(loopback, loopback, uint, S_IRUGO);
 100 MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable");
 101
 102 /* Other driver tunables */
 103 uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/
 104 static ushort crc_14b_sideband = 1;
 105 static uint use_flr = 1;
 106 uint quick_linkup; /* skip LNI */
 107
 108 struct flag_table {
 109         u64 flag;       /* the flag */
 110         char *str;      /* description string */
 111         u16 extra;      /* extra information */
 112         u16 unused0;
 113         u32 unused1;
 114 };
 115
 116 /* str must be a string constant */
 117 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
 118 #define FLAG_ENTRY0(str, flag) {flag, str, 0}
 119
 120 /* Send Error Consequences */
 121 #define SEC_WRITE_DROPPED       0x1
 122 #define SEC_PACKET_DROPPED      0x2
 123 #define SEC_SC_HALTED           0x4     /* per-context only */
 124 #define SEC_SPC_FREEZE          0x8     /* per-HFI only */
 125
 126 #define DEFAULT_KRCVQS            2
 127 #define MIN_KERNEL_KCTXTS         2
 128 #define FIRST_KERNEL_KCTXT        1
 129
 130 /*
 131  * RSM instance allocation
 132  *   0 - Verbs
 133  *   1 - User Fecn Handling
 134  *   2 - Vnic
 135  */
 136 #define RSM_INS_VERBS             0
 137 #define RSM_INS_FECN              1
 138 #define RSM_INS_VNIC              2
 139
 140 /* Bit offset into the GUID which carries HFI id information */
 141 #define GUID_HFI_INDEX_SHIFT     39
 142
 143 /* extract the emulation revision */
 144 #define emulator_rev(dd) ((dd)->irev >> 8)
 145 /* parallel and serial emulation versions are 3 and 4 respectively */
 146 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
 147 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
 148
 149 /* RSM fields for Verbs */
 150 /* packet type */
 151 #define IB_PACKET_TYPE         2ull
 152 #define QW_SHIFT               6ull
 153 /* QPN[7..1] */
 154 #define QPN_WIDTH              7ull
 155
 156 /* LRH.BTH: QW 0, OFFSET 48 - for match */
 157 #define LRH_BTH_QW             0ull
 158 #define LRH_BTH_BIT_OFFSET     48ull
 159 #define LRH_BTH_OFFSET(off)    ((LRH_BTH_QW << QW_SHIFT) | (off))
 160 #define LRH_BTH_MATCH_OFFSET   LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
 161 #define LRH_BTH_SELECT
 162 #define LRH_BTH_MASK           3ull
 163 #define LRH_BTH_VALUE          2ull
 164
 165 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
 166 #define LRH_SC_QW              0ull
 167 #define LRH_SC_BIT_OFFSET      56ull
 168 #define LRH_SC_OFFSET(off)     ((LRH_SC_QW << QW_SHIFT) | (off))
 169 #define LRH_SC_MATCH_OFFSET    LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
 170 #define LRH_SC_MASK            128ull
 171 #define LRH_SC_VALUE           0ull
 172
 173 /* SC[n..0] QW 0, OFFSET 60 - for select */
 174 #define LRH_SC_SELECT_OFFSET  ((LRH_SC_QW << QW_SHIFT) | (60ull))
 175
 176 /* QPN[m+n:1] QW 1, OFFSET 1 */
 177 #define QPN_SELECT_OFFSET      ((1ull << QW_SHIFT) | (1ull))
 178
 179 /* RSM fields for Vnic */
 180 /* L2_TYPE: QW 0, OFFSET 61 - for match */
 181 #define L2_TYPE_QW             0ull
 182 #define L2_TYPE_BIT_OFFSET     61ull
 183 #define L2_TYPE_OFFSET(off)    ((L2_TYPE_QW << QW_SHIFT) | (off))
 184 #define L2_TYPE_MATCH_OFFSET   L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET)
 185 #define L2_TYPE_MASK           3ull
 186 #define L2_16B_VALUE           2ull
 187
 188 /* L4_TYPE QW 1, OFFSET 0 - for match */
 189 #define L4_TYPE_QW              1ull
 190 #define L4_TYPE_BIT_OFFSET      0ull
 191 #define L4_TYPE_OFFSET(off)     ((L4_TYPE_QW << QW_SHIFT) | (off))
 192 #define L4_TYPE_MATCH_OFFSET    L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET)
 193 #define L4_16B_TYPE_MASK        0xFFull
 194 #define L4_16B_ETH_VALUE        0x78ull
 195
 196 /* 16B VESWID - for select */
 197 #define L4_16B_HDR_VESWID_OFFSET  ((2 << QW_SHIFT) | (16ull))
 198 /* 16B ENTROPY - for select */
 199 #define L2_16B_ENTROPY_OFFSET     ((1 << QW_SHIFT) | (32ull))
 200
 201 /* defines to build power on SC2VL table */
 202 #define SC2VL_VAL( \
 203         num, \
 204         sc0, sc0val, \
 205         sc1, sc1val, \
 206         sc2, sc2val, \
 207         sc3, sc3val, \
 208         sc4, sc4val, \
 209         sc5, sc5val, \
 210         sc6, sc6val, \
 211         sc7, sc7val) \
 212 ( \
 213         ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
 214         ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
 215         ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
 216         ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
 217         ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
 218         ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
 219         ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
 220         ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT)   \
 221 )
 222
 223 #define DC_SC_VL_VAL( \
 224         range, \
 225         e0, e0val, \
 226         e1, e1val, \
 227         e2, e2val, \
 228         e3, e3val, \
 229         e4, e4val, \
 230         e5, e5val, \
 231         e6, e6val, \
 232         e7, e7val, \
 233         e8, e8val, \
 234         e9, e9val, \
 235         e10, e10val, \
 236         e11, e11val, \
 237         e12, e12val, \
 238         e13, e13val, \
 239         e14, e14val, \
 240         e15, e15val) \
 241 ( \
 242         ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
 243         ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
 244         ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
 245         ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
 246         ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
 247         ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
 248         ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
 249         ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
 250         ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
 251         ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
 252         ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
 253         ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
 254         ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
 255         ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
 256         ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
 257         ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
 258 )
 259
 260 /* all CceStatus sub-block freeze bits */
 261 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
 262                         | CCE_STATUS_RXE_FROZE_SMASK \
 263                         | CCE_STATUS_TXE_FROZE_SMASK \
 264                         | CCE_STATUS_TXE_PIO_FROZE_SMASK)
 265 /* all CceStatus sub-block TXE pause bits */
 266 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
 267                         | CCE_STATUS_TXE_PAUSED_SMASK \
 268                         | CCE_STATUS_SDMA_PAUSED_SMASK)
 269 /* all CceStatus sub-block RXE pause bits */
 270 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
 271
 272 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
 273 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF
 274
 275 /*
 276  * CCE Error flags.
 277  */
 278 static struct flag_table cce_err_status_flags[] = {
 279 /* 0*/  FLAG_ENTRY0("CceCsrParityErr",
 280                 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
 281 /* 1*/  FLAG_ENTRY0("CceCsrReadBadAddrErr",
 282                 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
 283 /* 2*/  FLAG_ENTRY0("CceCsrWriteBadAddrErr",
 284                 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
 285 /* 3*/  FLAG_ENTRY0("CceTrgtAsyncFifoParityErr",
 286                 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
 287 /* 4*/  FLAG_ENTRY0("CceTrgtAccessErr",
 288                 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
 289 /* 5*/  FLAG_ENTRY0("CceRspdDataParityErr",
 290                 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
 291 /* 6*/  FLAG_ENTRY0("CceCli0AsyncFifoParityErr",
 292                 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
 293 /* 7*/  FLAG_ENTRY0("CceCsrCfgBusParityErr",
 294                 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
 295 /* 8*/  FLAG_ENTRY0("CceCli2AsyncFifoParityErr",
 296                 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
 297 /* 9*/  FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
 298             CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
 299 /*10*/  FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
 300             CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
 301 /*11*/  FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError",
 302             CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
 303 /*12*/  FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError",
 304                 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
 305 /*13*/  FLAG_ENTRY0("PcicRetryMemCorErr",
 306                 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
 307 /*14*/  FLAG_ENTRY0("PcicRetryMemCorErr",
 308                 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
 309 /*15*/  FLAG_ENTRY0("PcicPostHdQCorErr",
 310                 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
 311 /*16*/  FLAG_ENTRY0("PcicPostHdQCorErr",
 312                 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
 313 /*17*/  FLAG_ENTRY0("PcicPostHdQCorErr",
 314                 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
 315 /*18*/  FLAG_ENTRY0("PcicCplDatQCorErr",
 316                 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
 317 /*19*/  FLAG_ENTRY0("PcicNPostHQParityErr",
 318                 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
 319 /*20*/  FLAG_ENTRY0("PcicNPostDatQParityErr",
 320                 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
 321 /*21*/  FLAG_ENTRY0("PcicRetryMemUncErr",
 322                 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
 323 /*22*/  FLAG_ENTRY0("PcicRetrySotMemUncErr",
 324                 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
 325 /*23*/  FLAG_ENTRY0("PcicPostHdQUncErr",
 326                 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
 327 /*24*/  FLAG_ENTRY0("PcicPostDatQUncErr",
 328                 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
 329 /*25*/  FLAG_ENTRY0("PcicCplHdQUncErr",
 330                 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
 331 /*26*/  FLAG_ENTRY0("PcicCplDatQUncErr",
 332                 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
 333 /*27*/  FLAG_ENTRY0("PcicTransmitFrontParityErr",
 334                 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
 335 /*28*/  FLAG_ENTRY0("PcicTransmitBackParityErr",
 336                 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
 337 /*29*/  FLAG_ENTRY0("PcicReceiveParityErr",
 338                 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
 339 /*30*/  FLAG_ENTRY0("CceTrgtCplTimeoutErr",
 340                 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
 341 /*31*/  FLAG_ENTRY0("LATriggered",
 342                 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
 343 /*32*/  FLAG_ENTRY0("CceSegReadBadAddrErr",
 344                 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
 345 /*33*/  FLAG_ENTRY0("CceSegWriteBadAddrErr",
 346                 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
 347 /*34*/  FLAG_ENTRY0("CceRcplAsyncFifoParityErr",
 348                 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
 349 /*35*/  FLAG_ENTRY0("CceRxdmaConvFifoParityErr",
 350                 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
 351 /*36*/  FLAG_ENTRY0("CceMsixTableCorErr",
 352                 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
 353 /*37*/  FLAG_ENTRY0("CceMsixTableUncErr",
 354                 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
 355 /*38*/  FLAG_ENTRY0("CceIntMapCorErr",
 356                 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
 357 /*39*/  FLAG_ENTRY0("CceIntMapUncErr",
 358                 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
 359 /*40*/  FLAG_ENTRY0("CceMsixCsrParityErr",
 360                 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
 361 /*41-63 reserved*/
 362 };
 363
 364 /*
 365  * Misc Error flags
 366  */
 367 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
 368 static struct flag_table misc_err_status_flags[] = {
 369 /* 0*/  FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
 370 /* 1*/  FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
 371 /* 2*/  FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
 372 /* 3*/  FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)),
 373 /* 4*/  FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)),
 374 /* 5*/  FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)),
 375 /* 6*/  FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)),
 376 /* 7*/  FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)),
 377 /* 8*/  FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)),
 378 /* 9*/  FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)),
 379 /*10*/  FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)),
 380 /*11*/  FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)),
 381 /*12*/  FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL))
 382 };
 383
 384 /*
 385  * TXE PIO Error flags and consequences
 386  */
 387 static struct flag_table pio_err_status_flags[] = {
 388 /* 0*/  FLAG_ENTRY("PioWriteBadCtxt",
 389         SEC_WRITE_DROPPED,
 390         SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
 391 /* 1*/  FLAG_ENTRY("PioWriteAddrParity",
 392         SEC_SPC_FREEZE,
 393         SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
 394 /* 2*/  FLAG_ENTRY("PioCsrParity",
 395         SEC_SPC_FREEZE,
 396         SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
 397 /* 3*/  FLAG_ENTRY("PioSbMemFifo0",
 398         SEC_SPC_FREEZE,
 399         SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
 400 /* 4*/  FLAG_ENTRY("PioSbMemFifo1",
 401         SEC_SPC_FREEZE,
 402         SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
 403 /* 5*/  FLAG_ENTRY("PioPccFifoParity",
 404         SEC_SPC_FREEZE,
 405         SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
 406 /* 6*/  FLAG_ENTRY("PioPecFifoParity",
 407         SEC_SPC_FREEZE,
 408         SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
 409 /* 7*/  FLAG_ENTRY("PioSbrdctlCrrelParity",
 410         SEC_SPC_FREEZE,
 411         SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
 412 /* 8*/  FLAG_ENTRY("PioSbrdctrlCrrelFifoParity",
 413         SEC_SPC_FREEZE,
 414         SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
 415 /* 9*/  FLAG_ENTRY("PioPktEvictFifoParityErr",
 416         SEC_SPC_FREEZE,
 417         SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
 418 /*10*/  FLAG_ENTRY("PioSmPktResetParity",
 419         SEC_SPC_FREEZE,
 420         SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
 421 /*11*/  FLAG_ENTRY("PioVlLenMemBank0Unc",
 422         SEC_SPC_FREEZE,
 423         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
 424 /*12*/  FLAG_ENTRY("PioVlLenMemBank1Unc",
 425         SEC_SPC_FREEZE,
 426         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
 427 /*13*/  FLAG_ENTRY("PioVlLenMemBank0Cor",
 428         0,
 429         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
 430 /*14*/  FLAG_ENTRY("PioVlLenMemBank1Cor",
 431         0,
 432         SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
 433 /*15*/  FLAG_ENTRY("PioCreditRetFifoParity",
 434         SEC_SPC_FREEZE,
 435         SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
 436 /*16*/  FLAG_ENTRY("PioPpmcPblFifo",
 437         SEC_SPC_FREEZE,
 438         SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
 439 /*17*/  FLAG_ENTRY("PioInitSmIn",
 440         0,
 441         SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
 442 /*18*/  FLAG_ENTRY("PioPktEvictSmOrArbSm",
 443         SEC_SPC_FREEZE,
 444         SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
 445 /*19*/  FLAG_ENTRY("PioHostAddrMemUnc",
 446         SEC_SPC_FREEZE,
 447         SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
 448 /*20*/  FLAG_ENTRY("PioHostAddrMemCor",
 449         0,
 450         SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
 451 /*21*/  FLAG_ENTRY("PioWriteDataParity",
 452         SEC_SPC_FREEZE,
 453         SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
 454 /*22*/  FLAG_ENTRY("PioStateMachine",
 455         SEC_SPC_FREEZE,
 456         SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
 457 /*23*/  FLAG_ENTRY("PioWriteQwValidParity",
 458         SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
 459         SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
 460 /*24*/  FLAG_ENTRY("PioBlockQwCountParity",
 461         SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
 462         SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
 463 /*25*/  FLAG_ENTRY("PioVlfVlLenParity",
 464         SEC_SPC_FREEZE,
 465         SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
 466 /*26*/  FLAG_ENTRY("PioVlfSopParity",
 467         SEC_SPC_FREEZE,
 468         SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
 469 /*27*/  FLAG_ENTRY("PioVlFifoParity",
 470         SEC_SPC_FREEZE,
 471         SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
 472 /*28*/  FLAG_ENTRY("PioPpmcBqcMemParity",
 473         SEC_SPC_FREEZE,
 474         SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
 475 /*29*/  FLAG_ENTRY("PioPpmcSopLen",
 476         SEC_SPC_FREEZE,
 477         SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
 478 /*30-31 reserved*/
 479 /*32*/  FLAG_ENTRY("PioCurrentFreeCntParity",
 480         SEC_SPC_FREEZE,
 481         SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
 482 /*33*/  FLAG_ENTRY("PioLastReturnedCntParity",
 483         SEC_SPC_FREEZE,
 484         SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
 485 /*34*/  FLAG_ENTRY("PioPccSopHeadParity",
 486         SEC_SPC_FREEZE,
 487         SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
 488 /*35*/  FLAG_ENTRY("PioPecSopHeadParityErr",
 489         SEC_SPC_FREEZE,
 490         SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
 491 /*36-63 reserved*/
 492 };
 493
 494 /* TXE PIO errors that cause an SPC freeze */
 495 #define ALL_PIO_FREEZE_ERR \
 496         (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
 497         | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
 498         | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
 499         | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
 500         | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
 501         | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
 502         | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
 503         | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
 504         | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
 505         | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
 506         | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
 507         | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
 508         | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
 509         | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
 510         | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
 511         | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
 512         | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
 513         | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
 514         | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
 515         | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
 516         | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
 517         | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
 518         | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
 519         | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
 520         | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
 521         | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
 522         | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
 523         | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
 524         | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
 525
 526 /*
 527  * TXE SDMA Error flags
 528  */
 529 static struct flag_table sdma_err_status_flags[] = {
 530 /* 0*/  FLAG_ENTRY0("SDmaRpyTagErr",
 531                 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
 532 /* 1*/  FLAG_ENTRY0("SDmaCsrParityErr",
 533                 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
 534 /* 2*/  FLAG_ENTRY0("SDmaPcieReqTrackingUncErr",
 535                 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
 536 /* 3*/  FLAG_ENTRY0("SDmaPcieReqTrackingCorErr",
 537                 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
 538 /*04-63 reserved*/
 539 };
 540
 541 /* TXE SDMA errors that cause an SPC freeze */
 542 #define ALL_SDMA_FREEZE_ERR  \
 543                 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
 544                 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
 545                 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
 546
 547 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
 548 #define PORT_DISCARD_EGRESS_ERRS \
 549         (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
 550         | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
 551         | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
 552
 553 /*
 554  * TXE Egress Error flags
 555  */
 556 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
 557 static struct flag_table egress_err_status_flags[] = {
 558 /* 0*/  FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)),
 559 /* 1*/  FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)),
 560 /* 2 reserved */
 561 /* 3*/  FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr",
 562                 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)),
 563 /* 4*/  FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)),
 564 /* 5*/  FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)),
 565 /* 6 reserved */
 566 /* 7*/  FLAG_ENTRY0("TxPioLaunchIntfParityErr",
 567                 SEES(TX_PIO_LAUNCH_INTF_PARITY)),
 568 /* 8*/  FLAG_ENTRY0("TxSdmaLaunchIntfParityErr",
 569                 SEES(TX_SDMA_LAUNCH_INTF_PARITY)),
 570 /* 9-10 reserved */
 571 /*11*/  FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr",
 572                 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)),
 573 /*12*/  FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)),
 574 /*13*/  FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)),
 575 /*14*/  FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)),
 576 /*15*/  FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)),
 577 /*16*/  FLAG_ENTRY0("TxSdma0DisallowedPacketErr",
 578                 SEES(TX_SDMA0_DISALLOWED_PACKET)),
 579 /*17*/  FLAG_ENTRY0("TxSdma1DisallowedPacketErr",
 580                 SEES(TX_SDMA1_DISALLOWED_PACKET)),
 581 /*18*/  FLAG_ENTRY0("TxSdma2DisallowedPacketErr",
 582                 SEES(TX_SDMA2_DISALLOWED_PACKET)),
 583 /*19*/  FLAG_ENTRY0("TxSdma3DisallowedPacketErr",
 584                 SEES(TX_SDMA3_DISALLOWED_PACKET)),
 585 /*20*/  FLAG_ENTRY0("TxSdma4DisallowedPacketErr",
 586                 SEES(TX_SDMA4_DISALLOWED_PACKET)),
 587 /*21*/  FLAG_ENTRY0("TxSdma5DisallowedPacketErr",
 588                 SEES(TX_SDMA5_DISALLOWED_PACKET)),
 589 /*22*/  FLAG_ENTRY0("TxSdma6DisallowedPacketErr",
 590                 SEES(TX_SDMA6_DISALLOWED_PACKET)),
 591 /*23*/  FLAG_ENTRY0("TxSdma7DisallowedPacketErr",
 592                 SEES(TX_SDMA7_DISALLOWED_PACKET)),
 593 /*24*/  FLAG_ENTRY0("TxSdma8DisallowedPacketErr",
 594                 SEES(TX_SDMA8_DISALLOWED_PACKET)),
 595 /*25*/  FLAG_ENTRY0("TxSdma9DisallowedPacketErr",
 596                 SEES(TX_SDMA9_DISALLOWED_PACKET)),
 597 /*26*/  FLAG_ENTRY0("TxSdma10DisallowedPacketErr",
 598                 SEES(TX_SDMA10_DISALLOWED_PACKET)),
 599 /*27*/  FLAG_ENTRY0("TxSdma11DisallowedPacketErr",
 600                 SEES(TX_SDMA11_DISALLOWED_PACKET)),
 601 /*28*/  FLAG_ENTRY0("TxSdma12DisallowedPacketErr",
 602                 SEES(TX_SDMA12_DISALLOWED_PACKET)),
 603 /*29*/  FLAG_ENTRY0("TxSdma13DisallowedPacketErr",
 604                 SEES(TX_SDMA13_DISALLOWED_PACKET)),
 605 /*30*/  FLAG_ENTRY0("TxSdma14DisallowedPacketErr",
 606                 SEES(TX_SDMA14_DISALLOWED_PACKET)),
 607 /*31*/  FLAG_ENTRY0("TxSdma15DisallowedPacketErr",
 608                 SEES(TX_SDMA15_DISALLOWED_PACKET)),
 609 /*32*/  FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr",
 610                 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)),
 611 /*33*/  FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr",
 612                 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)),
 613 /*34*/  FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr",
 614                 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)),
 615 /*35*/  FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr",
 616                 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)),
 617 /*36*/  FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr",
 618                 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)),
 619 /*37*/  FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr",
 620                 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)),
 621 /*38*/  FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr",
 622                 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)),
 623 /*39*/  FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr",
 624                 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)),
 625 /*40*/  FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr",
 626                 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)),
 627 /*41*/  FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)),
 628 /*42*/  FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)),
 629 /*43*/  FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)),
 630 /*44*/  FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)),
 631 /*45*/  FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)),
 632 /*46*/  FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)),
 633 /*47*/  FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)),
 634 /*48*/  FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)),
 635 /*49*/  FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)),
 636 /*50*/  FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)),
 637 /*51*/  FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)),
 638 /*52*/  FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)),
 639 /*53*/  FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)),
 640 /*54*/  FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)),
 641 /*55*/  FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)),
 642 /*56*/  FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)),
 643 /*57*/  FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)),
 644 /*58*/  FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)),
 645 /*59*/  FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)),
 646 /*60*/  FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)),
 647 /*61*/  FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)),
 648 /*62*/  FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr",
 649                 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)),
 650 /*63*/  FLAG_ENTRY0("TxReadPioMemoryCsrUncErr",
 651                 SEES(TX_READ_PIO_MEMORY_CSR_UNC)),
 652 };
 653
 654 /*
 655  * TXE Egress Error Info flags
 656  */
 657 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
 658 static struct flag_table egress_err_info_flags[] = {
 659 /* 0*/  FLAG_ENTRY0("Reserved", 0ull),
 660 /* 1*/  FLAG_ENTRY0("VLErr", SEEI(VL)),
 661 /* 2*/  FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
 662 /* 3*/  FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
 663 /* 4*/  FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)),
 664 /* 5*/  FLAG_ENTRY0("SLIDErr", SEEI(SLID)),
 665 /* 6*/  FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)),
 666 /* 7*/  FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)),
 667 /* 8*/  FLAG_ENTRY0("RawErr", SEEI(RAW)),
 668 /* 9*/  FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)),
 669 /*10*/  FLAG_ENTRY0("GRHErr", SEEI(GRH)),
 670 /*11*/  FLAG_ENTRY0("BypassErr", SEEI(BYPASS)),
 671 /*12*/  FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)),
 672 /*13*/  FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)),
 673 /*14*/  FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)),
 674 /*15*/  FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)),
 675 /*16*/  FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)),
 676 /*17*/  FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)),
 677 /*18*/  FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)),
 678 /*19*/  FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)),
 679 /*20*/  FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)),
 680 /*21*/  FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)),
 681 };
 682
 683 /* TXE Egress errors that cause an SPC freeze */
 684 #define ALL_TXE_EGRESS_FREEZE_ERR \
 685         (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
 686         | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
 687         | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
 688         | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
 689         | SEES(TX_LAUNCH_CSR_PARITY) \
 690         | SEES(TX_SBRD_CTL_CSR_PARITY) \
 691         | SEES(TX_CONFIG_PARITY) \
 692         | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
 693         | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
 694         | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
 695         | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
 696         | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
 697         | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
 698         | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
 699         | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
 700         | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
 701         | SEES(TX_CREDIT_RETURN_PARITY))
 702
 703 /*
 704  * TXE Send error flags
 705  */
 706 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
 707 static struct flag_table send_err_status_flags[] = {
 708 /* 0*/  FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)),
 709 /* 1*/  FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)),
 710 /* 2*/  FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR))
 711 };
 712
 713 /*
 714  * TXE Send Context Error flags and consequences
 715  */
 716 static struct flag_table sc_err_status_flags[] = {
 717 /* 0*/  FLAG_ENTRY("InconsistentSop",
 718                 SEC_PACKET_DROPPED | SEC_SC_HALTED,
 719                 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
 720 /* 1*/  FLAG_ENTRY("DisallowedPacket",
 721                 SEC_PACKET_DROPPED | SEC_SC_HALTED,
 722                 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
 723 /* 2*/  FLAG_ENTRY("WriteCrossesBoundary",
 724                 SEC_WRITE_DROPPED | SEC_SC_HALTED,
 725                 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
 726 /* 3*/  FLAG_ENTRY("WriteOverflow",
 727                 SEC_WRITE_DROPPED | SEC_SC_HALTED,
 728                 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
 729 /* 4*/  FLAG_ENTRY("WriteOutOfBounds",
 730                 SEC_WRITE_DROPPED | SEC_SC_HALTED,
 731                 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
 732 /* 5-63 reserved*/
 733 };
 734
 735 /*
 736  * RXE Receive Error flags
 737  */
 738 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
 739 static struct flag_table rxe_err_status_flags[] = {
 740 /* 0*/  FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)),
 741 /* 1*/  FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)),
 742 /* 2*/  FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)),
 743 /* 3*/  FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)),
 744 /* 4*/  FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)),
 745 /* 5*/  FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)),
 746 /* 6*/  FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)),
 747 /* 7*/  FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)),
 748 /* 8*/  FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)),
 749 /* 9*/  FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)),
 750 /*10*/  FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)),
 751 /*11*/  FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)),
 752 /*12*/  FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)),
 753 /*13*/  FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)),
 754 /*14*/  FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)),
 755 /*15*/  FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)),
 756 /*16*/  FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr",
 757                 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)),
 758 /*17*/  FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)),
 759 /*18*/  FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)),
 760 /*19*/  FLAG_ENTRY0("RxRbufBlockListReadUncErr",
 761                 RXES(RBUF_BLOCK_LIST_READ_UNC)),
 762 /*20*/  FLAG_ENTRY0("RxRbufBlockListReadCorErr",
 763                 RXES(RBUF_BLOCK_LIST_READ_COR)),
 764 /*21*/  FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr",
 765                 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)),
 766 /*22*/  FLAG_ENTRY0("RxRbufCsrQEntCntParityErr",
 767                 RXES(RBUF_CSR_QENT_CNT_PARITY)),
 768 /*23*/  FLAG_ENTRY0("RxRbufCsrQNextBufParityErr",
 769                 RXES(RBUF_CSR_QNEXT_BUF_PARITY)),
 770 /*24*/  FLAG_ENTRY0("RxRbufCsrQVldBitParityErr",
 771                 RXES(RBUF_CSR_QVLD_BIT_PARITY)),
 772 /*25*/  FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)),
 773 /*26*/  FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)),
 774 /*27*/  FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr",
 775                 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)),
 776 /*28*/  FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)),
 777 /*29*/  FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)),
 778 /*30*/  FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)),
 779 /*31*/  FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)),
 780 /*32*/  FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)),
 781 /*33*/  FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)),
 782 /*34*/  FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)),
 783 /*35*/  FLAG_ENTRY0("RxRbufFlInitdoneParityErr",
 784                 RXES(RBUF_FL_INITDONE_PARITY)),
 785 /*36*/  FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr",
 786                 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)),
 787 /*37*/  FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)),
 788 /*38*/  FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)),
 789 /*39*/  FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)),
 790 /*40*/  FLAG_ENTRY0("RxLookupDesPart1UncCorErr",
 791                 RXES(LOOKUP_DES_PART1_UNC_COR)),
 792 /*41*/  FLAG_ENTRY0("RxLookupDesPart2ParityErr",
 793                 RXES(LOOKUP_DES_PART2_PARITY)),
 794 /*42*/  FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)),
 795 /*43*/  FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)),
 796 /*44*/  FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)),
 797 /*45*/  FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)),
 798 /*46*/  FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)),
 799 /*47*/  FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)),
 800 /*48*/  FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)),
 801 /*49*/  FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)),
 802 /*50*/  FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)),
 803 /*51*/  FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)),
 804 /*52*/  FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)),
 805 /*53*/  FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)),
 806 /*54*/  FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)),
 807 /*55*/  FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)),
 808 /*56*/  FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)),
 809 /*57*/  FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)),
 810 /*58*/  FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)),
 811 /*59*/  FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)),
 812 /*60*/  FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)),
 813 /*61*/  FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)),
 814 /*62*/  FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)),
 815 /*63*/  FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY))
 816 };
 817
 818 /* RXE errors that will trigger an SPC freeze */
 819 #define ALL_RXE_FREEZE_ERR  \
 820         (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
 821         | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
 822         | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
 823         | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
 824         | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
 825         | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
 826         | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
 827         | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
 828         | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
 829         | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
 830         | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
 831         | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
 832         | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
 833         | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
 834         | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
 835         | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
 836         | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
 837         | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
 838         | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
 839         | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
 840         | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
 841         | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
 842         | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
 843         | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
 844         | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
 845         | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
 846         | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
 847         | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
 848         | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
 849         | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
 850         | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
 851         | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
 852         | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
 853         | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
 854         | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
 855         | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
 856         | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
 857         | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
 858         | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
 859         | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
 860         | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
 861         | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
 862         | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
 863         | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
 864
 865 #define RXE_FREEZE_ABORT_MASK \
 866         (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
 867         RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
 868         RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
 869
 870 /*
 871  * DCC Error Flags
 872  */
 873 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK
 874 static struct flag_table dcc_err_flags[] = {
 875         FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)),
 876         FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)),
 877         FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)),
 878         FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)),
 879         FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)),
 880         FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)),
 881         FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)),
 882         FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)),
 883         FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)),
 884         FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)),
 885         FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)),
 886         FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)),
 887         FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)),
 888         FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)),
 889         FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)),
 890         FLAG_ENTRY0("link_err", DCCE(LINK_ERR)),
 891         FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)),
 892         FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)),
 893         FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)),
 894         FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)),
 895         FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)),
 896         FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)),
 897         FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)),
 898         FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)),
 899         FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)),
 900         FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)),
 901         FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)),
 902         FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)),
 903         FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)),
 904         FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)),
 905         FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)),
 906         FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)),
 907         FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)),
 908         FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)),
 909         FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)),
 910         FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)),
 911         FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)),
 912         FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)),
 913         FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)),
 914         FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)),
 915         FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)),
 916         FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)),
 917         FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)),
 918         FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)),
 919         FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)),
 920         FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)),
 921 };
 922
 923 /*
 924  * LCB error flags
 925  */
 926 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
 927 static struct flag_table lcb_err_flags[] = {
 928 /* 0*/  FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)),
 929 /* 1*/  FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)),
 930 /* 2*/  FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)),
 931 /* 3*/  FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST",
 932                 LCBE(ALL_LNS_FAILED_REINIT_TEST)),
 933 /* 4*/  FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)),
 934 /* 5*/  FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)),
 935 /* 6*/  FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)),
 936 /* 7*/  FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)),
 937 /* 8*/  FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)),
 938 /* 9*/  FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)),
 939 /*10*/  FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)),
 940 /*11*/  FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)),
 941 /*12*/  FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)),
 942 /*13*/  FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER",
 943                 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)),
 944 /*14*/  FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)),
 945 /*15*/  FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)),
 946 /*16*/  FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)),
 947 /*17*/  FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)),
 948 /*18*/  FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)),
 949 /*19*/  FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE",
 950                 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)),
 951 /*20*/  FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)),
 952 /*21*/  FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)),
 953 /*22*/  FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)),
 954 /*23*/  FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)),
 955 /*24*/  FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)),
 956 /*25*/  FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)),
 957 /*26*/  FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP",
 958                 LCBE(RST_FOR_INCOMPLT_RND_TRIP)),
 959 /*27*/  FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)),
 960 /*28*/  FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE",
 961                 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)),
 962 /*29*/  FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR",
 963                 LCBE(REDUNDANT_FLIT_PARITY_ERR))
 964 };
 965
 966 /*
 967  * DC8051 Error Flags
 968  */
 969 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
 970 static struct flag_table dc8051_err_flags[] = {
 971         FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)),
 972         FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)),
 973         FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)),
 974         FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)),
 975         FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)),
 976         FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)),
 977         FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)),
 978         FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)),
 979         FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES",
 980                     D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)),
 981         FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)),
 982 };
 983
 984 /*
 985  * DC8051 Information Error flags
 986  *
 987  * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
 988  */
 989 static struct flag_table dc8051_info_err_flags[] = {
 990         FLAG_ENTRY0("Spico ROM check failed",  SPICO_ROM_FAILED),
 991         FLAG_ENTRY0("Unknown frame received",  UNKNOWN_FRAME),
 992         FLAG_ENTRY0("Target BER not met",      TARGET_BER_NOT_MET),
 993         FLAG_ENTRY0("Serdes internal loopback failure",
 994                     FAILED_SERDES_INTERNAL_LOOPBACK),
 995         FLAG_ENTRY0("Failed SerDes init",      FAILED_SERDES_INIT),
 996         FLAG_ENTRY0("Failed LNI(Polling)",     FAILED_LNI_POLLING),
 997         FLAG_ENTRY0("Failed LNI(Debounce)",    FAILED_LNI_DEBOUNCE),
 998         FLAG_ENTRY0("Failed LNI(EstbComm)",    FAILED_LNI_ESTBCOMM),
 999         FLAG_ENTRY0("Failed LNI(OptEq)",       FAILED_LNI_OPTEQ),
1000         FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1),
1001         FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2),
1002         FLAG_ENTRY0("Failed LNI(ConfigLT)",    FAILED_LNI_CONFIGLT),
1003         FLAG_ENTRY0("Host Handshake Timeout",  HOST_HANDSHAKE_TIMEOUT),
1004         FLAG_ENTRY0("External Device Request Timeout",
1005                     EXTERNAL_DEVICE_REQ_TIMEOUT),
1006 };
1007
1008 /*
1009  * DC8051 Information Host Information flags
1010  *
1011  * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
1012  */
1013 static struct flag_table dc8051_info_host_msg_flags[] = {
1014         FLAG_ENTRY0("Host request done", 0x0001),
1015         FLAG_ENTRY0("BC SMA message", 0x0002),
1016         FLAG_ENTRY0("BC PWR_MGM message", 0x0004),
1017         FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008),
1018         FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010),
1019         FLAG_ENTRY0("External device config request", 0x0020),
1020         FLAG_ENTRY0("VerifyCap all frames received", 0x0040),
1021         FLAG_ENTRY0("LinkUp achieved", 0x0080),
1022         FLAG_ENTRY0("Link going down", 0x0100),
1023 };
1024
1025 static u32 encoded_size(u32 size);
1026 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate);
1027 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state);
1028 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
1029                                u8 *continuous);
1030 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
1031                                   u8 *vcu, u16 *vl15buf, u8 *crc_sizes);
1032 static void read_vc_remote_link_width(struct hfi1_devdata *dd,
1033                                       u8 *remote_tx_rate, u16 *link_widths);
1034 static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
1035                                      u8 *flag_bits, u16 *link_widths);
1036 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
1037                                   u8 *device_rev);
1038 static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed);
1039 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx);
1040 static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx,
1041                             u8 *tx_polarity_inversion,
1042                             u8 *rx_polarity_inversion, u8 *max_rate);
1043 static void handle_sdma_eng_err(struct hfi1_devdata *dd,
1044                                 unsigned int context, u64 err_status);
1045 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg);
1046 static void handle_dcc_err(struct hfi1_devdata *dd,
1047                            unsigned int context, u64 err_status);
1048 static void handle_lcb_err(struct hfi1_devdata *dd,
1049                            unsigned int context, u64 err_status);
1050 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg);
1051 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1052 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1053 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1054 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1055 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1056 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1057 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1058 static void set_partition_keys(struct hfi1_pportdata *ppd);
1059 static const char *link_state_name(u32 state);
1060 static const char *link_state_reason_name(struct hfi1_pportdata *ppd,
1061                                           u32 state);
1062 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
1063                            u64 *out_data);
1064 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data);
1065 static int thermal_init(struct hfi1_devdata *dd);
1066
1067 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
1068                                   int msecs);
1069 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc);
1070 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr);
1071 static void handle_temp_err(struct hfi1_devdata *dd);
1072 static void dc_shutdown(struct hfi1_devdata *dd);
1073 static void dc_start(struct hfi1_devdata *dd);
1074 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
1075                            unsigned int *np);
1076 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd);
1077 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms);
1078 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index);
1079
1080 /*
1081  * Error interrupt table entry.  This is used as input to the interrupt
1082  * "clear down" routine used for all second tier error interrupt register.
1083  * Second tier interrupt registers have a single bit representing them
1084  * in the top-level CceIntStatus.
1085  */
1086 struct err_reg_info {
1087         u32 status;             /* status CSR offset */
1088         u32 clear;              /* clear CSR offset */
1089         u32 mask;               /* mask CSR offset */
1090         void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg);
1091         const char *desc;
1092 };
1093
1094 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START)
1095 #define NUM_DC_ERRS (IS_DC_END - IS_DC_START)
1096 #define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START)
1097
1098 /*
1099  * Helpers for building HFI and DC error interrupt table entries.  Different
1100  * helpers are needed because of inconsistent register names.
1101  */
1102 #define EE(reg, handler, desc) \
1103         { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1104                 handler, desc }
1105 #define DC_EE1(reg, handler, desc) \
1106         { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1107 #define DC_EE2(reg, handler, desc) \
1108         { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1109
1110 /*
1111  * Table of the "misc" grouping of error interrupts.  Each entry refers to
1112  * another register containing more information.
1113  */
1114 static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = {
1115 /* 0*/  EE(CCE_ERR,             handle_cce_err,    "CceErr"),
1116 /* 1*/  EE(RCV_ERR,             handle_rxe_err,    "RxeErr"),
1117 /* 2*/  EE(MISC_ERR,    handle_misc_err,   "MiscErr"),
1118 /* 3*/  { 0, 0, 0, NULL }, /* reserved */
1119 /* 4*/  EE(SEND_PIO_ERR,    handle_pio_err,    "PioErr"),
1120 /* 5*/  EE(SEND_DMA_ERR,    handle_sdma_err,   "SDmaErr"),
1121 /* 6*/  EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"),
1122 /* 7*/  EE(SEND_ERR,    handle_txe_err,    "TxeErr")
1123         /* the rest are reserved */
1124 };
1125
1126 /*
1127  * Index into the Various section of the interrupt sources
1128  * corresponding to the Critical Temperature interrupt.
1129  */
1130 #define TCRIT_INT_SOURCE 4
1131
1132 /*
1133  * SDMA error interrupt entry - refers to another register containing more
1134  * information.
1135  */
1136 static const struct err_reg_info sdma_eng_err =
1137         EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr");
1138
1139 static const struct err_reg_info various_err[NUM_VARIOUS] = {
1140 /* 0*/  { 0, 0, 0, NULL }, /* PbcInt */
1141 /* 1*/  { 0, 0, 0, NULL }, /* GpioAssertInt */
1142 /* 2*/  EE(ASIC_QSFP1,  handle_qsfp_int,        "QSFP1"),
1143 /* 3*/  EE(ASIC_QSFP2,  handle_qsfp_int,        "QSFP2"),
1144 /* 4*/  { 0, 0, 0, NULL }, /* TCritInt */
1145         /* rest are reserved */
1146 };
1147
1148 /*
1149  * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1150  * register can not be derived from the MTU value because 10K is not
1151  * a power of 2. Therefore, we need a constant. Everything else can
1152  * be calculated.
1153  */
1154 #define DCC_CFG_PORT_MTU_CAP_10240 7
1155
1156 /*
1157  * Table of the DC grouping of error interrupts.  Each entry refers to
1158  * another register containing more information.
1159  */
1160 static const struct err_reg_info dc_errs[NUM_DC_ERRS] = {
1161 /* 0*/  DC_EE1(DCC_ERR,         handle_dcc_err,        "DCC Err"),
1162 /* 1*/  DC_EE2(DC_LCB_ERR,      handle_lcb_err,        "LCB Err"),
1163 /* 2*/  DC_EE2(DC_DC8051_ERR,   handle_8051_interrupt, "DC8051 Interrupt"),
1164 /* 3*/  /* dc_lbm_int - special, see is_dc_int() */
1165         /* the rest are reserved */
1166 };
1167
1168 struct cntr_entry {
1169         /*
1170          * counter name
1171          */
1172         char *name;
1173
1174         /*
1175          * csr to read for name (if applicable)
1176          */
1177         u64 csr;
1178
1179         /*
1180          * offset into dd or ppd to store the counter's value
1181          */
1182         int offset;
1183
1184         /*
1185          * flags
1186          */
1187         u8 flags;
1188
1189         /*
1190          * accessor for stat element, context either dd or ppd
1191          */
1192         u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl,
1193                        int mode, u64 data);
1194 };
1195
1196 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1197 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1198
1199 #define CNTR_ELEM(name, csr, offset, flags, accessor) \
1200 { \
1201         name, \
1202         csr, \
1203         offset, \
1204         flags, \
1205         accessor \
1206 }
1207
1208 /* 32bit RXE */
1209 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1210 CNTR_ELEM(#name, \
1211           (counter * 8 + RCV_COUNTER_ARRAY32), \
1212           0, flags | CNTR_32BIT, \
1213           port_access_u32_csr)
1214
1215 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1216 CNTR_ELEM(#name, \
1217           (counter * 8 + RCV_COUNTER_ARRAY32), \
1218           0, flags | CNTR_32BIT, \
1219           dev_access_u32_csr)
1220
1221 /* 64bit RXE */
1222 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1223 CNTR_ELEM(#name, \
1224           (counter * 8 + RCV_COUNTER_ARRAY64), \
1225           0, flags, \
1226           port_access_u64_csr)
1227
1228 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1229 CNTR_ELEM(#name, \
1230           (counter * 8 + RCV_COUNTER_ARRAY64), \
1231           0, flags, \
1232           dev_access_u64_csr)
1233
1234 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1235 #define OVR_ELM(ctx) \
1236 CNTR_ELEM("RcvHdrOvr" #ctx, \
1237           (RCV_HDR_OVFL_CNT + ctx * 0x100), \
1238           0, CNTR_NORMAL, port_access_u64_csr)
1239
1240 /* 32bit TXE */
1241 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1242 CNTR_ELEM(#name, \
1243           (counter * 8 + SEND_COUNTER_ARRAY32), \
1244           0, flags | CNTR_32BIT, \
1245           port_access_u32_csr)
1246
1247 /* 64bit TXE */
1248 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1249 CNTR_ELEM(#name, \
1250           (counter * 8 + SEND_COUNTER_ARRAY64), \
1251           0, flags, \
1252           port_access_u64_csr)
1253
1254 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1255 CNTR_ELEM(#name,\
1256           counter * 8 + SEND_COUNTER_ARRAY64, \
1257           0, \
1258           flags, \
1259           dev_access_u64_csr)
1260
1261 /* CCE */
1262 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1263 CNTR_ELEM(#name, \
1264           (counter * 8 + CCE_COUNTER_ARRAY32), \
1265           0, flags | CNTR_32BIT, \
1266           dev_access_u32_csr)
1267
1268 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1269 CNTR_ELEM(#name, \
1270           (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1271           0, flags | CNTR_32BIT, \
1272           dev_access_u32_csr)
1273
1274 /* DC */
1275 #define DC_PERF_CNTR(name, counter, flags) \
1276 CNTR_ELEM(#name, \
1277           counter, \
1278           0, \
1279           flags, \
1280           dev_access_u64_csr)
1281
1282 #define DC_PERF_CNTR_LCB(name, counter, flags) \
1283 CNTR_ELEM(#name, \
1284           counter, \
1285           0, \
1286           flags, \
1287           dc_access_lcb_cntr)
1288
1289 /* ibp counters */
1290 #define SW_IBP_CNTR(name, cntr) \
1291 CNTR_ELEM(#name, \
1292           0, \
1293           0, \
1294           CNTR_SYNTH, \
1295           access_ibp_##cntr)
1296
1297 u64 read_csr(const struct hfi1_devdata *dd, u32 offset)
1298 {
1299         if (dd->flags & HFI1_PRESENT) {
1300                 return readq((void __iomem *)dd->kregbase + offset);
1301         }
1302         return -1;
1303 }
1304
1305 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value)
1306 {
1307         if (dd->flags & HFI1_PRESENT)
1308                 writeq(value, (void __iomem *)dd->kregbase + offset);
1309 }
1310
1311 void __iomem *get_csr_addr(
1312         struct hfi1_devdata *dd,
1313         u32 offset)
1314 {
1315         return (void __iomem *)dd->kregbase + offset;
1316 }
1317
1318 static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr,
1319                                  int mode, u64 value)
1320 {
1321         u64 ret;
1322
1323         if (mode == CNTR_MODE_R) {
1324                 ret = read_csr(dd, csr);
1325         } else if (mode == CNTR_MODE_W) {
1326                 write_csr(dd, csr, value);
1327                 ret = value;
1328         } else {
1329                 dd_dev_err(dd, "Invalid cntr register access mode");
1330                 return 0;
1331         }
1332
1333         hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);
1334         return ret;
1335 }
1336
1337 /* Dev Access */
1338 static u64 dev_access_u32_csr(const struct cntr_entry *entry,
1339                               void *context, int vl, int mode, u64 data)
1340 {
1341         struct hfi1_devdata *dd = context;
1342         u64 csr = entry->csr;
1343
1344         if (entry->flags & CNTR_SDMA) {
1345                 if (vl == CNTR_INVALID_VL)
1346                         return 0;
1347                 csr += 0x100 * vl;
1348         } else {
1349                 if (vl != CNTR_INVALID_VL)
1350                         return 0;
1351         }
1352         return read_write_csr(dd, csr, mode, data);
1353 }
1354
1355 static u64 access_sde_err_cnt(const struct cntr_entry *entry,
1356                               void *context, int idx, int mode, u64 data)
1357 {
1358         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1359
1360         if (dd->per_sdma && idx < dd->num_sdma)
1361                 return dd->per_sdma[idx].err_cnt;
1362         return 0;
1363 }
1364
1365 static u64 access_sde_int_cnt(const struct cntr_entry *entry,
1366                               void *context, int idx, int mode, u64 data)
1367 {
1368         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1369
1370         if (dd->per_sdma && idx < dd->num_sdma)
1371                 return dd->per_sdma[idx].sdma_int_cnt;
1372         return 0;
1373 }
1374
1375 static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry,
1376                                    void *context, int idx, int mode, u64 data)
1377 {
1378         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1379
1380         if (dd->per_sdma && idx < dd->num_sdma)
1381                 return dd->per_sdma[idx].idle_int_cnt;
1382         return 0;
1383 }
1384
1385 static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry,
1386                                        void *context, int idx, int mode,
1387                                        u64 data)
1388 {
1389         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1390
1391         if (dd->per_sdma && idx < dd->num_sdma)
1392                 return dd->per_sdma[idx].progress_int_cnt;
1393         return 0;
1394 }
1395
1396 static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context,
1397                               int vl, int mode, u64 data)
1398 {
1399         struct hfi1_devdata *dd = context;
1400
1401         u64 val = 0;
1402         u64 csr = entry->csr;
1403
1404         if (entry->flags & CNTR_VL) {
1405                 if (vl == CNTR_INVALID_VL)
1406                         return 0;
1407                 csr += 8 * vl;
1408         } else {
1409                 if (vl != CNTR_INVALID_VL)
1410                         return 0;
1411         }
1412
1413         val = read_write_csr(dd, csr, mode, data);
1414         return val;
1415 }
1416
1417 static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context,
1418                               int vl, int mode, u64 data)
1419 {
1420         struct hfi1_devdata *dd = context;
1421         u32 csr = entry->csr;
1422         int ret = 0;
1423
1424         if (vl != CNTR_INVALID_VL)
1425                 return 0;
1426         if (mode == CNTR_MODE_R)
1427                 ret = read_lcb_csr(dd, csr, &data);
1428         else if (mode == CNTR_MODE_W)
1429                 ret = write_lcb_csr(dd, csr, data);
1430
1431         if (ret) {
1432                 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr);
1433                 return 0;
1434         }
1435
1436         hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);
1437         return data;
1438 }
1439
1440 /* Port Access */
1441 static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context,
1442                                int vl, int mode, u64 data)
1443 {
1444         struct hfi1_pportdata *ppd = context;
1445
1446         if (vl != CNTR_INVALID_VL)
1447                 return 0;
1448         return read_write_csr(ppd->dd, entry->csr, mode, data);
1449 }
1450
1451 static u64 port_access_u64_csr(const struct cntr_entry *entry,
1452                                void *context, int vl, int mode, u64 data)
1453 {
1454         struct hfi1_pportdata *ppd = context;
1455         u64 val;
1456         u64 csr = entry->csr;
1457
1458         if (entry->flags & CNTR_VL) {
1459                 if (vl == CNTR_INVALID_VL)
1460                         return 0;
1461                 csr += 8 * vl;
1462         } else {
1463                 if (vl != CNTR_INVALID_VL)
1464                         return 0;
1465         }
1466         val = read_write_csr(ppd->dd, csr, mode, data);
1467         return val;
1468 }
1469
1470 /* Software defined */
1471 static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode,
1472                                 u64 data)
1473 {
1474         u64 ret;
1475
1476         if (mode == CNTR_MODE_R) {
1477                 ret = *cntr;
1478         } else if (mode == CNTR_MODE_W) {
1479                 *cntr = data;
1480                 ret = data;
1481         } else {
1482                 dd_dev_err(dd, "Invalid cntr sw access mode");
1483                 return 0;
1484         }
1485
1486         hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);
1487
1488         return ret;
1489 }
1490
1491 static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context,
1492                                  int vl, int mode, u64 data)
1493 {
1494         struct hfi1_pportdata *ppd = context;
1495
1496         if (vl != CNTR_INVALID_VL)
1497                 return 0;
1498         return read_write_sw(ppd->dd, &ppd->link_downed, mode, data);
1499 }
1500
1501 static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context,
1502                                  int vl, int mode, u64 data)
1503 {
1504         struct hfi1_pportdata *ppd = context;
1505
1506         if (vl != CNTR_INVALID_VL)
1507                 return 0;
1508         return read_write_sw(ppd->dd, &ppd->link_up, mode, data);
1509 }
1510
1511 static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry,
1512                                        void *context, int vl, int mode,
1513                                        u64 data)
1514 {
1515         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1516
1517         if (vl != CNTR_INVALID_VL)
1518                 return 0;
1519         return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data);
1520 }
1521
1522 static u64 access_sw_xmit_discards(const struct cntr_entry *entry,
1523                                    void *context, int vl, int mode, u64 data)
1524 {
1525         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1526         u64 zero = 0;
1527         u64 *counter;
1528
1529         if (vl == CNTR_INVALID_VL)
1530                 counter = &ppd->port_xmit_discards;
1531         else if (vl >= 0 && vl < C_VL_COUNT)
1532                 counter = &ppd->port_xmit_discards_vl[vl];
1533         else
1534                 counter = &zero;
1535
1536         return read_write_sw(ppd->dd, counter, mode, data);
1537 }
1538
1539 static u64 access_xmit_constraint_errs(const struct cntr_entry *entry,
1540                                        void *context, int vl, int mode,
1541                                        u64 data)
1542 {
1543         struct hfi1_pportdata *ppd = context;
1544
1545         if (vl != CNTR_INVALID_VL)
1546                 return 0;
1547
1548         return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors,
1549                              mode, data);
1550 }
1551
1552 static u64 access_rcv_constraint_errs(const struct cntr_entry *entry,
1553                                       void *context, int vl, int mode, u64 data)
1554 {
1555         struct hfi1_pportdata *ppd = context;
1556
1557         if (vl != CNTR_INVALID_VL)
1558                 return 0;
1559
1560         return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors,
1561                              mode, data);
1562 }
1563
1564 u64 get_all_cpu_total(u64 __percpu *cntr)
1565 {
1566         int cpu;
1567         u64 counter = 0;
1568
1569         for_each_possible_cpu(cpu)
1570                 counter += *per_cpu_ptr(cntr, cpu);
1571         return counter;
1572 }
1573
1574 static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val,
1575                           u64 __percpu *cntr,
1576                           int vl, int mode, u64 data)
1577 {
1578         u64 ret = 0;
1579
1580         if (vl != CNTR_INVALID_VL)
1581                 return 0;
1582
1583         if (mode == CNTR_MODE_R) {
1584                 ret = get_all_cpu_total(cntr) - *z_val;
1585         } else if (mode == CNTR_MODE_W) {
1586                 /* A write can only zero the counter */
1587                 if (data == 0)
1588                         *z_val = get_all_cpu_total(cntr);
1589                 else
1590                         dd_dev_err(dd, "Per CPU cntrs can only be zeroed");
1591         } else {
1592                 dd_dev_err(dd, "Invalid cntr sw cpu access mode");
1593                 return 0;
1594         }
1595
1596         return ret;
1597 }
1598
1599 static u64 access_sw_cpu_intr(const struct cntr_entry *entry,
1600                               void *context, int vl, int mode, u64 data)
1601 {
1602         struct hfi1_devdata *dd = context;
1603
1604         return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl,
1605                               mode, data);
1606 }
1607
1608 static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry,
1609                                    void *context, int vl, int mode, u64 data)
1610 {
1611         struct hfi1_devdata *dd = context;
1612
1613         return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl,
1614                               mode, data);
1615 }
1616
1617 static u64 access_sw_pio_wait(const struct cntr_entry *entry,
1618                               void *context, int vl, int mode, u64 data)
1619 {
1620         struct hfi1_devdata *dd = context;
1621
1622         return dd->verbs_dev.n_piowait;
1623 }
1624
1625 static u64 access_sw_pio_drain(const struct cntr_entry *entry,
1626                                void *context, int vl, int mode, u64 data)
1627 {
1628         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1629
1630         return dd->verbs_dev.n_piodrain;
1631 }
1632
1633 static u64 access_sw_vtx_wait(const struct cntr_entry *entry,
1634                               void *context, int vl, int mode, u64 data)
1635 {
1636         struct hfi1_devdata *dd = context;
1637
1638         return dd->verbs_dev.n_txwait;
1639 }
1640
1641 static u64 access_sw_kmem_wait(const struct cntr_entry *entry,
1642                                void *context, int vl, int mode, u64 data)
1643 {
1644         struct hfi1_devdata *dd = context;
1645
1646         return dd->verbs_dev.n_kmem_wait;
1647 }
1648
1649 static u64 access_sw_send_schedule(const struct cntr_entry *entry,
1650                                    void *context, int vl, int mode, u64 data)
1651 {
1652         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1653
1654         return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl,
1655                               mode, data);
1656 }
1657
1658 /* Software counters for the error status bits within MISC_ERR_STATUS */
1659 static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry,
1660                                              void *context, int vl, int mode,
1661                                              u64 data)
1662 {
1663         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1664
1665         return dd->misc_err_status_cnt[12];
1666 }
1667
1668 static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry,
1669                                           void *context, int vl, int mode,
1670                                           u64 data)
1671 {
1672         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1673
1674         return dd->misc_err_status_cnt[11];
1675 }
1676
1677 static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry,
1678                                                void *context, int vl, int mode,
1679                                                u64 data)
1680 {
1681         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1682
1683         return dd->misc_err_status_cnt[10];
1684 }
1685
1686 static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry,
1687                                                  void *context, int vl,
1688                                                  int mode, u64 data)
1689 {
1690         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1691
1692         return dd->misc_err_status_cnt[9];
1693 }
1694
1695 static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry,
1696                                            void *context, int vl, int mode,
1697                                            u64 data)
1698 {
1699         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1700
1701         return dd->misc_err_status_cnt[8];
1702 }
1703
1704 static u64 access_misc_efuse_read_bad_addr_err_cnt(
1705                                 const struct cntr_entry *entry,
1706                                 void *context, int vl, int mode, u64 data)
1707 {
1708         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1709
1710         return dd->misc_err_status_cnt[7];
1711 }
1712
1713 static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry,
1714                                                 void *context, int vl,
1715                                                 int mode, u64 data)
1716 {
1717         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1718
1719         return dd->misc_err_status_cnt[6];
1720 }
1721
1722 static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry,
1723                                               void *context, int vl, int mode,
1724                                               u64 data)
1725 {
1726         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1727
1728         return dd->misc_err_status_cnt[5];
1729 }
1730
1731 static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry,
1732                                             void *context, int vl, int mode,
1733                                             u64 data)
1734 {
1735         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1736
1737         return dd->misc_err_status_cnt[4];
1738 }
1739
1740 static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry,
1741                                                  void *context, int vl,
1742                                                  int mode, u64 data)
1743 {
1744         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1745
1746         return dd->misc_err_status_cnt[3];
1747 }
1748
1749 static u64 access_misc_csr_write_bad_addr_err_cnt(
1750                                 const struct cntr_entry *entry,
1751                                 void *context, int vl, int mode, u64 data)
1752 {
1753         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1754
1755         return dd->misc_err_status_cnt[2];
1756 }
1757
1758 static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1759                                                  void *context, int vl,
1760                                                  int mode, u64 data)
1761 {
1762         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1763
1764         return dd->misc_err_status_cnt[1];
1765 }
1766
1767 static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry,
1768                                           void *context, int vl, int mode,
1769                                           u64 data)
1770 {
1771         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1772
1773         return dd->misc_err_status_cnt[0];
1774 }
1775
1776 /*
1777  * Software counter for the aggregate of
1778  * individual CceErrStatus counters
1779  */
1780 static u64 access_sw_cce_err_status_aggregated_cnt(
1781                                 const struct cntr_entry *entry,
1782                                 void *context, int vl, int mode, u64 data)
1783 {
1784         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1785
1786         return dd->sw_cce_err_status_aggregate;
1787 }
1788
1789 /*
1790  * Software counters corresponding to each of the
1791  * error status bits within CceErrStatus
1792  */
1793 static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry,
1794                                               void *context, int vl, int mode,
1795                                               u64 data)
1796 {
1797         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1798
1799         return dd->cce_err_status_cnt[40];
1800 }
1801
1802 static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry,
1803                                           void *context, int vl, int mode,
1804                                           u64 data)
1805 {
1806         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1807
1808         return dd->cce_err_status_cnt[39];
1809 }
1810
1811 static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry,
1812                                           void *context, int vl, int mode,
1813                                           u64 data)
1814 {
1815         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1816
1817         return dd->cce_err_status_cnt[38];
1818 }
1819
1820 static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry,
1821                                              void *context, int vl, int mode,
1822                                              u64 data)
1823 {
1824         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1825
1826         return dd->cce_err_status_cnt[37];
1827 }
1828
1829 static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry,
1830                                              void *context, int vl, int mode,
1831                                              u64 data)
1832 {
1833         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1834
1835         return dd->cce_err_status_cnt[36];
1836 }
1837
1838 static u64 access_cce_rxdma_conv_fifo_parity_err_cnt(
1839                                 const struct cntr_entry *entry,
1840                                 void *context, int vl, int mode, u64 data)
1841 {
1842         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1843
1844         return dd->cce_err_status_cnt[35];
1845 }
1846
1847 static u64 access_cce_rcpl_async_fifo_parity_err_cnt(
1848                                 const struct cntr_entry *entry,
1849                                 void *context, int vl, int mode, u64 data)
1850 {
1851         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1852
1853         return dd->cce_err_status_cnt[34];
1854 }
1855
1856 static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry,
1857                                                  void *context, int vl,
1858                                                  int mode, u64 data)
1859 {
1860         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1861
1862         return dd->cce_err_status_cnt[33];
1863 }
1864
1865 static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1866                                                 void *context, int vl, int mode,
1867                                                 u64 data)
1868 {
1869         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1870
1871         return dd->cce_err_status_cnt[32];
1872 }
1873
1874 static u64 access_la_triggered_cnt(const struct cntr_entry *entry,
1875                                    void *context, int vl, int mode, u64 data)
1876 {
1877         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1878
1879         return dd->cce_err_status_cnt[31];
1880 }
1881
1882 static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry,
1883                                                void *context, int vl, int mode,
1884                                                u64 data)
1885 {
1886         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1887
1888         return dd->cce_err_status_cnt[30];
1889 }
1890
1891 static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry,
1892                                               void *context, int vl, int mode,
1893                                               u64 data)
1894 {
1895         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1896
1897         return dd->cce_err_status_cnt[29];
1898 }
1899
1900 static u64 access_pcic_transmit_back_parity_err_cnt(
1901                                 const struct cntr_entry *entry,
1902                                 void *context, int vl, int mode, u64 data)
1903 {
1904         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1905
1906         return dd->cce_err_status_cnt[28];
1907 }
1908
1909 static u64 access_pcic_transmit_front_parity_err_cnt(
1910                                 const struct cntr_entry *entry,
1911                                 void *context, int vl, int mode, u64 data)
1912 {
1913         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1914
1915         return dd->cce_err_status_cnt[27];
1916 }
1917
1918 static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1919                                              void *context, int vl, int mode,
1920                                              u64 data)
1921 {
1922         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1923
1924         return dd->cce_err_status_cnt[26];
1925 }
1926
1927 static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1928                                             void *context, int vl, int mode,
1929                                             u64 data)
1930 {
1931         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1932
1933         return dd->cce_err_status_cnt[25];
1934 }
1935
1936 static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry,
1937                                               void *context, int vl, int mode,
1938                                               u64 data)
1939 {
1940         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1941
1942         return dd->cce_err_status_cnt[24];
1943 }
1944
1945 static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry,
1946                                              void *context, int vl, int mode,
1947                                              u64 data)
1948 {
1949         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1950
1951         return dd->cce_err_status_cnt[23];
1952 }
1953
1954 static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry,
1955                                                  void *context, int vl,
1956                                                  int mode, u64 data)
1957 {
1958         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1959
1960         return dd->cce_err_status_cnt[22];
1961 }
1962
1963 static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry,
1964                                          void *context, int vl, int mode,
1965                                          u64 data)
1966 {
1967         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1968
1969         return dd->cce_err_status_cnt[21];
1970 }
1971
1972 static u64 access_pcic_n_post_dat_q_parity_err_cnt(
1973                                 const struct cntr_entry *entry,
1974                                 void *context, int vl, int mode, u64 data)
1975 {
1976         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1977
1978         return dd->cce_err_status_cnt[20];
1979 }
1980
1981 static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry,
1982                                                  void *context, int vl,
1983                                                  int mode, u64 data)
1984 {
1985         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1986
1987         return dd->cce_err_status_cnt[19];
1988 }
1989
1990 static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry,
1991                                              void *context, int vl, int mode,
1992                                              u64 data)
1993 {
1994         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1995
1996         return dd->cce_err_status_cnt[18];
1997 }
1998
1999 static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry,
2000                                             void *context, int vl, int mode,
2001                                             u64 data)
2002 {
2003         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2004
2005         return dd->cce_err_status_cnt[17];
2006 }
2007
2008 static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry,
2009                                               void *context, int vl, int mode,
2010                                               u64 data)
2011 {
2012         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2013
2014         return dd->cce_err_status_cnt[16];
2015 }
2016
2017 static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry,
2018                                              void *context, int vl, int mode,
2019                                              u64 data)
2020 {
2021         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2022
2023         return dd->cce_err_status_cnt[15];
2024 }
2025
2026 static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry,
2027                                                  void *context, int vl,
2028                                                  int mode, u64 data)
2029 {
2030         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2031
2032         return dd->cce_err_status_cnt[14];
2033 }
2034
2035 static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry,
2036                                              void *context, int vl, int mode,
2037                                              u64 data)
2038 {
2039         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2040
2041         return dd->cce_err_status_cnt[13];
2042 }
2043
2044 static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt(
2045                                 const struct cntr_entry *entry,
2046                                 void *context, int vl, int mode, u64 data)
2047 {
2048         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2049
2050         return dd->cce_err_status_cnt[12];
2051 }
2052
2053 static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt(
2054                                 const struct cntr_entry *entry,
2055                                 void *context, int vl, int mode, u64 data)
2056 {
2057         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2058
2059         return dd->cce_err_status_cnt[11];
2060 }
2061
2062 static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt(
2063                                 const struct cntr_entry *entry,
2064                                 void *context, int vl, int mode, u64 data)
2065 {
2066         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2067
2068         return dd->cce_err_status_cnt[10];
2069 }
2070
2071 static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt(
2072                                 const struct cntr_entry *entry,
2073                                 void *context, int vl, int mode, u64 data)
2074 {
2075         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2076
2077         return dd->cce_err_status_cnt[9];
2078 }
2079
2080 static u64 access_cce_cli2_async_fifo_parity_err_cnt(
2081                                 const struct cntr_entry *entry,
2082                                 void *context, int vl, int mode, u64 data)
2083 {
2084         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2085
2086         return dd->cce_err_status_cnt[8];
2087 }
2088
2089 static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry,
2090                                                  void *context, int vl,
2091                                                  int mode, u64 data)
2092 {
2093         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2094
2095         return dd->cce_err_status_cnt[7];
2096 }
2097
2098 static u64 access_cce_cli0_async_fifo_parity_err_cnt(
2099                                 const struct cntr_entry *entry,
2100                                 void *context, int vl, int mode, u64 data)
2101 {
2102         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2103
2104         return dd->cce_err_status_cnt[6];
2105 }
2106
2107 static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry,
2108                                                void *context, int vl, int mode,
2109                                                u64 data)
2110 {
2111         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2112
2113         return dd->cce_err_status_cnt[5];
2114 }
2115
2116 static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry,
2117                                           void *context, int vl, int mode,
2118                                           u64 data)
2119 {
2120         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2121
2122         return dd->cce_err_status_cnt[4];
2123 }
2124
2125 static u64 access_cce_trgt_async_fifo_parity_err_cnt(
2126                                 const struct cntr_entry *entry,
2127                                 void *context, int vl, int mode, u64 data)
2128 {
2129         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2130
2131         return dd->cce_err_status_cnt[3];
2132 }
2133
2134 static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2135                                                  void *context, int vl,
2136                                                  int mode, u64 data)
2137 {
2138         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2139
2140         return dd->cce_err_status_cnt[2];
2141 }
2142
2143 static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2144                                                 void *context, int vl,
2145                                                 int mode, u64 data)
2146 {
2147         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2148
2149         return dd->cce_err_status_cnt[1];
2150 }
2151
2152 static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry,
2153                                          void *context, int vl, int mode,
2154                                          u64 data)
2155 {
2156         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2157
2158         return dd->cce_err_status_cnt[0];
2159 }
2160
2161 /*
2162  * Software counters corresponding to each of the
2163  * error status bits within RcvErrStatus
2164  */
2165 static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry,
2166                                         void *context, int vl, int mode,
2167                                         u64 data)
2168 {
2169         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2170
2171         return dd->rcv_err_status_cnt[63];
2172 }
2173
2174 static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2175                                                 void *context, int vl,
2176                                                 int mode, u64 data)
2177 {
2178         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2179
2180         return dd->rcv_err_status_cnt[62];
2181 }
2182
2183 static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2184                                                void *context, int vl, int mode,
2185                                                u64 data)
2186 {
2187         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2188
2189         return dd->rcv_err_status_cnt[61];
2190 }
2191
2192 static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry,
2193                                          void *context, int vl, int mode,
2194                                          u64 data)
2195 {
2196         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2197
2198         return dd->rcv_err_status_cnt[60];
2199 }
2200
2201 static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2202                                                  void *context, int vl,
2203                                                  int mode, u64 data)
2204 {
2205         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2206
2207         return dd->rcv_err_status_cnt[59];
2208 }
2209
2210 static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2211                                                  void *context, int vl,
2212                                                  int mode, u64 data)
2213 {
2214         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2215
2216         return dd->rcv_err_status_cnt[58];
2217 }
2218
2219 static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry,
2220                                             void *context, int vl, int mode,
2221                                             u64 data)
2222 {
2223         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2224
2225         return dd->rcv_err_status_cnt[57];
2226 }
2227
2228 static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry,
2229                                            void *context, int vl, int mode,
2230                                            u64 data)
2231 {
2232         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2233
2234         return dd->rcv_err_status_cnt[56];
2235 }
2236
2237 static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry,
2238                                            void *context, int vl, int mode,
2239                                            u64 data)
2240 {
2241         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2242
2243         return dd->rcv_err_status_cnt[55];
2244 }
2245
2246 static u64 access_rx_dma_data_fifo_rd_cor_err_cnt(
2247                                 const struct cntr_entry *entry,
2248                                 void *context, int vl, int mode, u64 data)
2249 {
2250         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2251
2252         return dd->rcv_err_status_cnt[54];
2253 }
2254
2255 static u64 access_rx_dma_data_fifo_rd_unc_err_cnt(
2256                                 const struct cntr_entry *entry,
2257                                 void *context, int vl, int mode, u64 data)
2258 {
2259         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2260
2261         return dd->rcv_err_status_cnt[53];
2262 }
2263
2264 static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry,
2265                                                  void *context, int vl,
2266                                                  int mode, u64 data)
2267 {
2268         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2269
2270         return dd->rcv_err_status_cnt[52];
2271 }
2272
2273 static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry,
2274                                                  void *context, int vl,
2275                                                  int mode, u64 data)
2276 {
2277         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2278
2279         return dd->rcv_err_status_cnt[51];
2280 }
2281
2282 static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry,
2283                                                  void *context, int vl,
2284                                                  int mode, u64 data)
2285 {
2286         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2287
2288         return dd->rcv_err_status_cnt[50];
2289 }
2290
2291 static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry,
2292                                                  void *context, int vl,
2293                                                  int mode, u64 data)
2294 {
2295         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2296
2297         return dd->rcv_err_status_cnt[49];
2298 }
2299
2300 static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry,
2301                                                  void *context, int vl,
2302                                                  int mode, u64 data)
2303 {
2304         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2305
2306         return dd->rcv_err_status_cnt[48];
2307 }
2308
2309 static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry,
2310                                                  void *context, int vl,
2311                                                  int mode, u64 data)
2312 {
2313         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2314
2315         return dd->rcv_err_status_cnt[47];
2316 }
2317
2318 static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry,
2319                                          void *context, int vl, int mode,
2320                                          u64 data)
2321 {
2322         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2323
2324         return dd->rcv_err_status_cnt[46];
2325 }
2326
2327 static u64 access_rx_hq_intr_csr_parity_err_cnt(
2328                                 const struct cntr_entry *entry,
2329                                 void *context, int vl, int mode, u64 data)
2330 {
2331         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2332
2333         return dd->rcv_err_status_cnt[45];
2334 }
2335
2336 static u64 access_rx_lookup_csr_parity_err_cnt(
2337                                 const struct cntr_entry *entry,
2338                                 void *context, int vl, int mode, u64 data)
2339 {
2340         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2341
2342         return dd->rcv_err_status_cnt[44];
2343 }
2344
2345 static u64 access_rx_lookup_rcv_array_cor_err_cnt(
2346                                 const struct cntr_entry *entry,
2347                                 void *context, int vl, int mode, u64 data)
2348 {
2349         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2350
2351         return dd->rcv_err_status_cnt[43];
2352 }
2353
2354 static u64 access_rx_lookup_rcv_array_unc_err_cnt(
2355                                 const struct cntr_entry *entry,
2356                                 void *context, int vl, int mode, u64 data)
2357 {
2358         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2359
2360         return dd->rcv_err_status_cnt[42];
2361 }
2362
2363 static u64 access_rx_lookup_des_part2_parity_err_cnt(
2364                                 const struct cntr_entry *entry,
2365                                 void *context, int vl, int mode, u64 data)
2366 {
2367         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2368
2369         return dd->rcv_err_status_cnt[41];
2370 }
2371
2372 static u64 access_rx_lookup_des_part1_unc_cor_err_cnt(
2373                                 const struct cntr_entry *entry,
2374                                 void *context, int vl, int mode, u64 data)
2375 {
2376         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2377
2378         return dd->rcv_err_status_cnt[40];
2379 }
2380
2381 static u64 access_rx_lookup_des_part1_unc_err_cnt(
2382                                 const struct cntr_entry *entry,
2383                                 void *context, int vl, int mode, u64 data)
2384 {
2385         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2386
2387         return dd->rcv_err_status_cnt[39];
2388 }
2389
2390 static u64 access_rx_rbuf_next_free_buf_cor_err_cnt(
2391                                 const struct cntr_entry *entry,
2392                                 void *context, int vl, int mode, u64 data)
2393 {
2394         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2395
2396         return dd->rcv_err_status_cnt[38];
2397 }
2398
2399 static u64 access_rx_rbuf_next_free_buf_unc_err_cnt(
2400                                 const struct cntr_entry *entry,
2401                                 void *context, int vl, int mode, u64 data)
2402 {
2403         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2404
2405         return dd->rcv_err_status_cnt[37];
2406 }
2407
2408 static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt(
2409                                 const struct cntr_entry *entry,
2410                                 void *context, int vl, int mode, u64 data)
2411 {
2412         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2413
2414         return dd->rcv_err_status_cnt[36];
2415 }
2416
2417 static u64 access_rx_rbuf_fl_initdone_parity_err_cnt(
2418                                 const struct cntr_entry *entry,
2419                                 void *context, int vl, int mode, u64 data)
2420 {
2421         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2422
2423         return dd->rcv_err_status_cnt[35];
2424 }
2425
2426 static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt(
2427                                 const struct cntr_entry *entry,
2428                                 void *context, int vl, int mode, u64 data)
2429 {
2430         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2431
2432         return dd->rcv_err_status_cnt[34];
2433 }
2434
2435 static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt(
2436                                 const struct cntr_entry *entry,
2437                                 void *context, int vl, int mode, u64 data)
2438 {
2439         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2440
2441         return dd->rcv_err_status_cnt[33];
2442 }
2443
2444 static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry,
2445                                         void *context, int vl, int mode,
2446                                         u64 data)
2447 {
2448         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2449
2450         return dd->rcv_err_status_cnt[32];
2451 }
2452
2453 static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry,
2454                                        void *context, int vl, int mode,
2455                                        u64 data)
2456 {
2457         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2458
2459         return dd->rcv_err_status_cnt[31];
2460 }
2461
2462 static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry,
2463                                           void *context, int vl, int mode,
2464                                           u64 data)
2465 {
2466         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2467
2468         return dd->rcv_err_status_cnt[30];
2469 }
2470
2471 static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry,
2472                                              void *context, int vl, int mode,
2473                                              u64 data)
2474 {
2475         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2476
2477         return dd->rcv_err_status_cnt[29];
2478 }
2479
2480 static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry,
2481                                                  void *context, int vl,
2482                                                  int mode, u64 data)
2483 {
2484         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2485
2486         return dd->rcv_err_status_cnt[28];
2487 }
2488
2489 static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt(
2490                                 const struct cntr_entry *entry,
2491                                 void *context, int vl, int mode, u64 data)
2492 {
2493         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2494
2495         return dd->rcv_err_status_cnt[27];
2496 }
2497
2498 static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt(
2499                                 const struct cntr_entry *entry,
2500                                 void *context, int vl, int mode, u64 data)
2501 {
2502         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2503
2504         return dd->rcv_err_status_cnt[26];
2505 }
2506
2507 static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt(
2508                                 const struct cntr_entry *entry,
2509                                 void *context, int vl, int mode, u64 data)
2510 {
2511         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2512
2513         return dd->rcv_err_status_cnt[25];
2514 }
2515
2516 static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt(
2517                                 const struct cntr_entry *entry,
2518                                 void *context, int vl, int mode, u64 data)
2519 {
2520         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2521
2522         return dd->rcv_err_status_cnt[24];
2523 }
2524
2525 static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt(
2526                                 const struct cntr_entry *entry,
2527                                 void *context, int vl, int mode, u64 data)
2528 {
2529         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2530
2531         return dd->rcv_err_status_cnt[23];
2532 }
2533
2534 static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt(
2535                                 const struct cntr_entry *entry,
2536                                 void *context, int vl, int mode, u64 data)
2537 {
2538         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2539
2540         return dd->rcv_err_status_cnt[22];
2541 }
2542
2543 static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt(
2544                                 const struct cntr_entry *entry,
2545                                 void *context, int vl, int mode, u64 data)
2546 {
2547         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2548
2549         return dd->rcv_err_status_cnt[21];
2550 }
2551
2552 static u64 access_rx_rbuf_block_list_read_cor_err_cnt(
2553                                 const struct cntr_entry *entry,
2554                                 void *context, int vl, int mode, u64 data)
2555 {
2556         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2557
2558         return dd->rcv_err_status_cnt[20];
2559 }
2560
2561 static u64 access_rx_rbuf_block_list_read_unc_err_cnt(
2562                                 const struct cntr_entry *entry,
2563                                 void *context, int vl, int mode, u64 data)
2564 {
2565         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2566
2567         return dd->rcv_err_status_cnt[19];
2568 }
2569
2570 static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry,
2571                                                  void *context, int vl,
2572                                                  int mode, u64 data)
2573 {
2574         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2575
2576         return dd->rcv_err_status_cnt[18];
2577 }
2578
2579 static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry,
2580                                                  void *context, int vl,
2581                                                  int mode, u64 data)
2582 {
2583         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2584
2585         return dd->rcv_err_status_cnt[17];
2586 }
2587
2588 static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt(
2589                                 const struct cntr_entry *entry,
2590                                 void *context, int vl, int mode, u64 data)
2591 {
2592         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2593
2594         return dd->rcv_err_status_cnt[16];
2595 }
2596
2597 static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt(
2598                                 const struct cntr_entry *entry,
2599                                 void *context, int vl, int mode, u64 data)
2600 {
2601         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2602
2603         return dd->rcv_err_status_cnt[15];
2604 }
2605
2606 static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry,
2607                                                 void *context, int vl,
2608                                                 int mode, u64 data)
2609 {
2610         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2611
2612         return dd->rcv_err_status_cnt[14];
2613 }
2614
2615 static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry,
2616                                                 void *context, int vl,
2617                                                 int mode, u64 data)
2618 {
2619         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2620
2621         return dd->rcv_err_status_cnt[13];
2622 }
2623
2624 static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2625                                               void *context, int vl, int mode,
2626                                               u64 data)
2627 {
2628         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2629
2630         return dd->rcv_err_status_cnt[12];
2631 }
2632
2633 static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry,
2634                                           void *context, int vl, int mode,
2635                                           u64 data)
2636 {
2637         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2638
2639         return dd->rcv_err_status_cnt[11];
2640 }
2641
2642 static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry,
2643                                           void *context, int vl, int mode,
2644                                           u64 data)
2645 {
2646         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2647
2648         return dd->rcv_err_status_cnt[10];
2649 }
2650
2651 static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry,
2652                                                void *context, int vl, int mode,
2653                                                u64 data)
2654 {
2655         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2656
2657         return dd->rcv_err_status_cnt[9];
2658 }
2659
2660 static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry,
2661                                             void *context, int vl, int mode,
2662                                             u64 data)
2663 {
2664         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2665
2666         return dd->rcv_err_status_cnt[8];
2667 }
2668
2669 static u64 access_rx_rcv_qp_map_table_cor_err_cnt(
2670                                 const struct cntr_entry *entry,
2671                                 void *context, int vl, int mode, u64 data)
2672 {
2673         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2674
2675         return dd->rcv_err_status_cnt[7];
2676 }
2677
2678 static u64 access_rx_rcv_qp_map_table_unc_err_cnt(
2679                                 const struct cntr_entry *entry,
2680                                 void *context, int vl, int mode, u64 data)
2681 {
2682         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2683
2684         return dd->rcv_err_status_cnt[6];
2685 }
2686
2687 static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry,
2688                                           void *context, int vl, int mode,
2689                                           u64 data)
2690 {
2691         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2692
2693         return dd->rcv_err_status_cnt[5];
2694 }
2695
2696 static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry,
2697                                           void *context, int vl, int mode,
2698                                           u64 data)
2699 {
2700         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2701
2702         return dd->rcv_err_status_cnt[4];
2703 }
2704
2705 static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry,
2706                                          void *context, int vl, int mode,
2707                                          u64 data)
2708 {
2709         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2710
2711         return dd->rcv_err_status_cnt[3];
2712 }
2713
2714 static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry,
2715                                          void *context, int vl, int mode,
2716                                          u64 data)
2717 {
2718         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2719
2720         return dd->rcv_err_status_cnt[2];
2721 }
2722
2723 static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry,
2724                                             void *context, int vl, int mode,
2725                                             u64 data)
2726 {
2727         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2728
2729         return dd->rcv_err_status_cnt[1];
2730 }
2731
2732 static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry,
2733                                          void *context, int vl, int mode,
2734                                          u64 data)
2735 {
2736         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2737
2738         return dd->rcv_err_status_cnt[0];
2739 }
2740
2741 /*
2742  * Software counters corresponding to each of the
2743  * error status bits within SendPioErrStatus
2744  */
2745 static u64 access_pio_pec_sop_head_parity_err_cnt(
2746                                 const struct cntr_entry *entry,
2747                                 void *context, int vl, int mode, u64 data)
2748 {
2749         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2750
2751         return dd->send_pio_err_status_cnt[35];
2752 }
2753
2754 static u64 access_pio_pcc_sop_head_parity_err_cnt(
2755                                 const struct cntr_entry *entry,
2756                                 void *context, int vl, int mode, u64 data)
2757 {
2758         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2759
2760         return dd->send_pio_err_status_cnt[34];
2761 }
2762
2763 static u64 access_pio_last_returned_cnt_parity_err_cnt(
2764                                 const struct cntr_entry *entry,
2765                                 void *context, int vl, int mode, u64 data)
2766 {
2767         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2768
2769         return dd->send_pio_err_status_cnt[33];
2770 }
2771
2772 static u64 access_pio_current_free_cnt_parity_err_cnt(
2773                                 const struct cntr_entry *entry,
2774                                 void *context, int vl, int mode, u64 data)
2775 {
2776         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2777
2778         return dd->send_pio_err_status_cnt[32];
2779 }
2780
2781 static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry,
2782                                           void *context, int vl, int mode,
2783                                           u64 data)
2784 {
2785         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2786
2787         return dd->send_pio_err_status_cnt[31];
2788 }
2789
2790 static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry,
2791                                           void *context, int vl, int mode,
2792                                           u64 data)
2793 {
2794         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2795
2796         return dd->send_pio_err_status_cnt[30];
2797 }
2798
2799 static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry,
2800                                            void *context, int vl, int mode,
2801                                            u64 data)
2802 {
2803         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2804
2805         return dd->send_pio_err_status_cnt[29];
2806 }
2807
2808 static u64 access_pio_ppmc_bqc_mem_parity_err_cnt(
2809                                 const struct cntr_entry *entry,
2810                                 void *context, int vl, int mode, u64 data)
2811 {
2812         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2813
2814         return dd->send_pio_err_status_cnt[28];
2815 }
2816
2817 static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry,
2818                                              void *context, int vl, int mode,
2819                                              u64 data)
2820 {
2821         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2822
2823         return dd->send_pio_err_status_cnt[27];
2824 }
2825
2826 static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry,
2827                                              void *context, int vl, int mode,
2828                                              u64 data)
2829 {
2830         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2831
2832         return dd->send_pio_err_status_cnt[26];
2833 }
2834
2835 static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry,
2836                                                 void *context, int vl,
2837                                                 int mode, u64 data)
2838 {
2839         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2840
2841         return dd->send_pio_err_status_cnt[25];
2842 }
2843
2844 static u64 access_pio_block_qw_count_parity_err_cnt(
2845                                 const struct cntr_entry *entry,
2846                                 void *context, int vl, int mode, u64 data)
2847 {
2848         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2849
2850         return dd->send_pio_err_status_cnt[24];
2851 }
2852
2853 static u64 access_pio_write_qw_valid_parity_err_cnt(
2854                                 const struct cntr_entry *entry,
2855                                 void *context, int vl, int mode, u64 data)
2856 {
2857         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2858
2859         return dd->send_pio_err_status_cnt[23];
2860 }
2861
2862 static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry,
2863                                             void *context, int vl, int mode,
2864                                             u64 data)
2865 {
2866         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2867
2868         return dd->send_pio_err_status_cnt[22];
2869 }
2870
2871 static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry,
2872                                                 void *context, int vl,
2873                                                 int mode, u64 data)
2874 {
2875         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2876
2877         return dd->send_pio_err_status_cnt[21];
2878 }
2879
2880 static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry,
2881                                                 void *context, int vl,
2882                                                 int mode, u64 data)
2883 {
2884         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2885
2886         return dd->send_pio_err_status_cnt[20];
2887 }
2888
2889 static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry,
2890                                                 void *context, int vl,
2891                                                 int mode, u64 data)
2892 {
2893         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2894
2895         return dd->send_pio_err_status_cnt[19];
2896 }
2897
2898 static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt(
2899                                 const struct cntr_entry *entry,
2900                                 void *context, int vl, int mode, u64 data)
2901 {
2902         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2903
2904         return dd->send_pio_err_status_cnt[18];
2905 }
2906
2907 static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry,
2908                                          void *context, int vl, int mode,
2909                                          u64 data)
2910 {
2911         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2912
2913         return dd->send_pio_err_status_cnt[17];
2914 }
2915
2916 static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry,
2917                                             void *context, int vl, int mode,
2918                                             u64 data)
2919 {
2920         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2921
2922         return dd->send_pio_err_status_cnt[16];
2923 }
2924
2925 static u64 access_pio_credit_ret_fifo_parity_err_cnt(
2926                                 const struct cntr_entry *entry,
2927                                 void *context, int vl, int mode, u64 data)
2928 {
2929         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2930
2931         return dd->send_pio_err_status_cnt[15];
2932 }
2933
2934 static u64 access_pio_v1_len_mem_bank1_cor_err_cnt(
2935                                 const struct cntr_entry *entry,
2936                                 void *context, int vl, int mode, u64 data)
2937 {
2938         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2939
2940         return dd->send_pio_err_status_cnt[14];
2941 }
2942
2943 static u64 access_pio_v1_len_mem_bank0_cor_err_cnt(
2944                                 const struct cntr_entry *entry,
2945                                 void *context, int vl, int mode, u64 data)
2946 {
2947         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2948
2949         return dd->send_pio_err_status_cnt[13];
2950 }
2951
2952 static u64 access_pio_v1_len_mem_bank1_unc_err_cnt(
2953                                 const struct cntr_entry *entry,
2954                                 void *context, int vl, int mode, u64 data)
2955 {
2956         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2957
2958         return dd->send_pio_err_status_cnt[12];
2959 }
2960
2961 static u64 access_pio_v1_len_mem_bank0_unc_err_cnt(
2962                                 const struct cntr_entry *entry,
2963                                 void *context, int vl, int mode, u64 data)
2964 {
2965         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2966
2967         return dd->send_pio_err_status_cnt[11];
2968 }
2969
2970 static u64 access_pio_sm_pkt_reset_parity_err_cnt(
2971                                 const struct cntr_entry *entry,
2972                                 void *context, int vl, int mode, u64 data)
2973 {
2974         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2975
2976         return dd->send_pio_err_status_cnt[10];
2977 }
2978
2979 static u64 access_pio_pkt_evict_fifo_parity_err_cnt(
2980                                 const struct cntr_entry *entry,
2981                                 void *context, int vl, int mode, u64 data)
2982 {
2983         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2984
2985         return dd->send_pio_err_status_cnt[9];
2986 }
2987
2988 static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt(
2989                                 const struct cntr_entry *entry,
2990                                 void *context, int vl, int mode, u64 data)
2991 {
2992         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2993
2994         return dd->send_pio_err_status_cnt[8];
2995 }
2996
2997 static u64 access_pio_sbrdctl_crrel_parity_err_cnt(
2998                                 const struct cntr_entry *entry,
2999                                 void *context, int vl, int mode, u64 data)
3000 {
3001         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3002
3003         return dd->send_pio_err_status_cnt[7];
3004 }
3005
3006 static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry,
3007                                               void *context, int vl, int mode,
3008                                               u64 data)
3009 {
3010         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3011
3012         return dd->send_pio_err_status_cnt[6];
3013 }
3014
3015 static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry,
3016                                               void *context, int vl, int mode,
3017                                               u64 data)
3018 {
3019         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3020
3021         return dd->send_pio_err_status_cnt[5];
3022 }
3023
3024 static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry,
3025                                            void *context, int vl, int mode,
3026                                            u64 data)
3027 {
3028         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3029
3030         return dd->send_pio_err_status_cnt[4];
3031 }
3032
3033 static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry,
3034                                            void *context, int vl, int mode,
3035                                            u64 data)
3036 {
3037         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3038
3039         return dd->send_pio_err_status_cnt[3];
3040 }
3041
3042 static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry,
3043                                          void *context, int vl, int mode,
3044                                          u64 data)
3045 {
3046         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3047
3048         return dd->send_pio_err_status_cnt[2];
3049 }
3050
3051 static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry,
3052                                                 void *context, int vl,
3053                                                 int mode, u64 data)
3054 {
3055         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3056
3057         return dd->send_pio_err_status_cnt[1];
3058 }
3059
3060 static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry,
3061                                              void *context, int vl, int mode,
3062                                              u64 data)
3063 {
3064         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3065
3066         return dd->send_pio_err_status_cnt[0];
3067 }
3068
3069 /*
3070  * Software counters corresponding to each of the
3071  * error status bits within SendDmaErrStatus
3072  */
3073 static u64 access_sdma_pcie_req_tracking_cor_err_cnt(
3074                                 const struct cntr_entry *entry,
3075                                 void *context, int vl, int mode, u64 data)
3076 {
3077         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3078
3079         return dd->send_dma_err_status_cnt[3];
3080 }
3081
3082 static u64 access_sdma_pcie_req_tracking_unc_err_cnt(
3083                                 const struct cntr_entry *entry,
3084                                 void *context, int vl, int mode, u64 data)
3085 {
3086         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3087
3088         return dd->send_dma_err_status_cnt[2];
3089 }
3090
3091 static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry,
3092                                           void *context, int vl, int mode,
3093                                           u64 data)
3094 {
3095         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3096
3097         return dd->send_dma_err_status_cnt[1];
3098 }
3099
3100 static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry,
3101                                        void *context, int vl, int mode,
3102                                        u64 data)
3103 {
3104         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3105
3106         return dd->send_dma_err_status_cnt[0];
3107 }
3108
3109 /*
3110  * Software counters corresponding to each of the
3111  * error status bits within SendEgressErrStatus
3112  */
3113 static u64 access_tx_read_pio_memory_csr_unc_err_cnt(
3114                                 const struct cntr_entry *entry,
3115                                 void *context, int vl, int mode, u64 data)
3116 {
3117         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3118
3119         return dd->send_egress_err_status_cnt[63];
3120 }
3121
3122 static u64 access_tx_read_sdma_memory_csr_err_cnt(
3123                                 const struct cntr_entry *entry,
3124                                 void *context, int vl, int mode, u64 data)
3125 {
3126         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3127
3128         return dd->send_egress_err_status_cnt[62];
3129 }
3130
3131 static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry,
3132                                              void *context, int vl, int mode,
3133                                              u64 data)
3134 {
3135         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3136
3137         return dd->send_egress_err_status_cnt[61];
3138 }
3139
3140 static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry,
3141                                                  void *context, int vl,
3142                                                  int mode, u64 data)
3143 {
3144         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3145
3146         return dd->send_egress_err_status_cnt[60];
3147 }
3148
3149 static u64 access_tx_read_sdma_memory_cor_err_cnt(
3150                                 const struct cntr_entry *entry,
3151                                 void *context, int vl, int mode, u64 data)
3152 {
3153         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3154
3155         return dd->send_egress_err_status_cnt[59];
3156 }
3157
3158 static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry,
3159                                         void *context, int vl, int mode,
3160                                         u64 data)
3161 {
3162         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3163
3164         return dd->send_egress_err_status_cnt[58];
3165 }
3166
3167 static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry,
3168                                             void *context, int vl, int mode,
3169                                             u64 data)
3170 {
3171         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3172
3173         return dd->send_egress_err_status_cnt[57];
3174 }
3175
3176 static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry,
3177                                               void *context, int vl, int mode,
3178                                               u64 data)
3179 {
3180         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3181
3182         return dd->send_egress_err_status_cnt[56];
3183 }
3184
3185 static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry,
3186                                               void *context, int vl, int mode,
3187                                               u64 data)
3188 {
3189         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3190
3191         return dd->send_egress_err_status_cnt[55];
3192 }
3193
3194 static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry,
3195                                               void *context, int vl, int mode,
3196                                               u64 data)
3197 {
3198         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3199
3200         return dd->send_egress_err_status_cnt[54];
3201 }
3202
3203 static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry,
3204                                               void *context, int vl, int mode,
3205                                               u64 data)
3206 {
3207         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3208
3209         return dd->send_egress_err_status_cnt[53];
3210 }
3211
3212 static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry,
3213                                               void *context, int vl, int mode,
3214                                               u64 data)
3215 {
3216         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3217
3218         return dd->send_egress_err_status_cnt[52];
3219 }
3220
3221 static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry,
3222                                               void *context, int vl, int mode,
3223                                               u64 data)
3224 {
3225         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3226
3227         return dd->send_egress_err_status_cnt[51];
3228 }
3229
3230 static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry,
3231                                               void *context, int vl, int mode,
3232                                               u64 data)
3233 {
3234         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3235
3236         return dd->send_egress_err_status_cnt[50];
3237 }
3238
3239 static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry,
3240                                               void *context, int vl, int mode,
3241                                               u64 data)
3242 {
3243         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3244
3245         return dd->send_egress_err_status_cnt[49];
3246 }
3247
3248 static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry,
3249                                               void *context, int vl, int mode,
3250                                               u64 data)
3251 {
3252         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3253
3254         return dd->send_egress_err_status_cnt[48];
3255 }
3256
3257 static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry,
3258                                               void *context, int vl, int mode,
3259                                               u64 data)
3260 {
3261         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3262
3263         return dd->send_egress_err_status_cnt[47];
3264 }
3265
3266 static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry,
3267                                             void *context, int vl, int mode,
3268                                             u64 data)
3269 {
3270         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3271
3272         return dd->send_egress_err_status_cnt[46];
3273 }
3274
3275 static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry,
3276                                              void *context, int vl, int mode,
3277                                              u64 data)
3278 {
3279         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3280
3281         return dd->send_egress_err_status_cnt[45];
3282 }
3283
3284 static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry,
3285                                                  void *context, int vl,
3286                                                  int mode, u64 data)
3287 {
3288         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3289
3290         return dd->send_egress_err_status_cnt[44];
3291 }
3292
3293 static u64 access_tx_read_sdma_memory_unc_err_cnt(
3294                                 const struct cntr_entry *entry,
3295                                 void *context, int vl, int mode, u64 data)
3296 {
3297         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3298
3299         return dd->send_egress_err_status_cnt[43];
3300 }
3301
3302 static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry,
3303                                         void *context, int vl, int mode,
3304                                         u64 data)
3305 {
3306         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3307
3308         return dd->send_egress_err_status_cnt[42];
3309 }
3310
3311 static u64 access_tx_credit_return_partiy_err_cnt(
3312                                 const struct cntr_entry *entry,
3313                                 void *context, int vl, int mode, u64 data)
3314 {
3315         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3316
3317         return dd->send_egress_err_status_cnt[41];
3318 }
3319
3320 static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt(
3321                                 const struct cntr_entry *entry,
3322                                 void *context, int vl, int mode, u64 data)
3323 {
3324         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3325
3326         return dd->send_egress_err_status_cnt[40];
3327 }
3328
3329 static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt(
3330                                 const struct cntr_entry *entry,
3331                                 void *context, int vl, int mode, u64 data)
3332 {
3333         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3334
3335         return dd->send_egress_err_status_cnt[39];
3336 }
3337
3338 static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt(
3339                                 const struct cntr_entry *entry,
3340                                 void *context, int vl, int mode, u64 data)
3341 {
3342         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3343
3344         return dd->send_egress_err_status_cnt[38];
3345 }
3346
3347 static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt(
3348                                 const struct cntr_entry *entry,
3349                                 void *context, int vl, int mode, u64 data)
3350 {
3351         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3352
3353         return dd->send_egress_err_status_cnt[37];
3354 }
3355
3356 static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt(
3357                                 const struct cntr_entry *entry,
3358                                 void *context, int vl, int mode, u64 data)
3359 {
3360         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3361
3362         return dd->send_egress_err_status_cnt[36];
3363 }
3364
3365 static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt(
3366                                 const struct cntr_entry *entry,
3367                                 void *context, int vl, int mode, u64 data)
3368 {
3369         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3370
3371         return dd->send_egress_err_status_cnt[35];
3372 }
3373
3374 static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt(
3375                                 const struct cntr_entry *entry,
3376                                 void *context, int vl, int mode, u64 data)
3377 {
3378         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3379
3380         return dd->send_egress_err_status_cnt[34];
3381 }
3382
3383 static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt(
3384                                 const struct cntr_entry *entry,
3385                                 void *context, int vl, int mode, u64 data)
3386 {
3387         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3388
3389         return dd->send_egress_err_status_cnt[33];
3390 }
3391
3392 static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt(
3393                                 const struct cntr_entry *entry,
3394                                 void *context, int vl, int mode, u64 data)
3395 {
3396         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3397
3398         return dd->send_egress_err_status_cnt[32];
3399 }
3400
3401 static u64 access_tx_sdma15_disallowed_packet_err_cnt(
3402                                 const struct cntr_entry *entry,
3403                                 void *context, int vl, int mode, u64 data)
3404 {
3405         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3406
3407         return dd->send_egress_err_status_cnt[31];
3408 }
3409
3410 static u64 access_tx_sdma14_disallowed_packet_err_cnt(
3411                                 const struct cntr_entry *entry,
3412                                 void *context, int vl, int mode, u64 data)
3413 {
3414         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3415
3416         return dd->send_egress_err_status_cnt[30];
3417 }
3418
3419 static u64 access_tx_sdma13_disallowed_packet_err_cnt(
3420                                 const struct cntr_entry *entry,
3421                                 void *context, int vl, int mode, u64 data)
3422 {
3423         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3424
3425         return dd->send_egress_err_status_cnt[29];
3426 }
3427
3428 static u64 access_tx_sdma12_disallowed_packet_err_cnt(
3429                                 const struct cntr_entry *entry,
3430                                 void *context, int vl, int mode, u64 data)
3431 {
3432         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3433
3434         return dd->send_egress_err_status_cnt[28];
3435 }
3436
3437 static u64 access_tx_sdma11_disallowed_packet_err_cnt(
3438                                 const struct cntr_entry *entry,
3439                                 void *context, int vl, int mode, u64 data)
3440 {
3441         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3442
3443         return dd->send_egress_err_status_cnt[27];
3444 }
3445
3446 static u64 access_tx_sdma10_disallowed_packet_err_cnt(
3447                                 const struct cntr_entry *entry,
3448                                 void *context, int vl, int mode, u64 data)
3449 {
3450         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3451
3452         return dd->send_egress_err_status_cnt[26];
3453 }
3454
3455 static u64 access_tx_sdma9_disallowed_packet_err_cnt(
3456                                 const struct cntr_entry *entry,
3457                                 void *context, int vl, int mode, u64 data)
3458 {
3459         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3460
3461         return dd->send_egress_err_status_cnt[25];
3462 }
3463
3464 static u64 access_tx_sdma8_disallowed_packet_err_cnt(
3465                                 const struct cntr_entry *entry,
3466                                 void *context, int vl, int mode, u64 data)
3467 {
3468         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3469
3470         return dd->send_egress_err_status_cnt[24];
3471 }
3472
3473 static u64 access_tx_sdma7_disallowed_packet_err_cnt(
3474                                 const struct cntr_entry *entry,
3475                                 void *context, int vl, int mode, u64 data)
3476 {
3477         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3478
3479         return dd->send_egress_err_status_cnt[23];
3480 }
3481
3482 static u64 access_tx_sdma6_disallowed_packet_err_cnt(
3483                                 const struct cntr_entry *entry,
3484                                 void *context, int vl, int mode, u64 data)
3485 {
3486         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3487
3488         return dd->send_egress_err_status_cnt[22];
3489 }
3490
3491 static u64 access_tx_sdma5_disallowed_packet_err_cnt(
3492                                 const struct cntr_entry *entry,
3493                                 void *context, int vl, int mode, u64 data)
3494 {
3495         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3496
3497         return dd->send_egress_err_status_cnt[21];
3498 }
3499
3500 static u64 access_tx_sdma4_disallowed_packet_err_cnt(
3501                                 const struct cntr_entry *entry,
3502                                 void *context, int vl, int mode, u64 data)
3503 {
3504         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3505
3506         return dd->send_egress_err_status_cnt[20];
3507 }
3508
3509 static u64 access_tx_sdma3_disallowed_packet_err_cnt(
3510                                 const struct cntr_entry *entry,
3511                                 void *context, int vl, int mode, u64 data)
3512 {
3513         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3514
3515         return dd->send_egress_err_status_cnt[19];
3516 }
3517
3518 static u64 access_tx_sdma2_disallowed_packet_err_cnt(
3519                                 const struct cntr_entry *entry,
3520                                 void *context, int vl, int mode, u64 data)
3521 {
3522         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3523
3524         return dd->send_egress_err_status_cnt[18];
3525 }
3526
3527 static u64 access_tx_sdma1_disallowed_packet_err_cnt(
3528                                 const struct cntr_entry *entry,
3529                                 void *context, int vl, int mode, u64 data)
3530 {
3531         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3532
3533         return dd->send_egress_err_status_cnt[17];
3534 }
3535
3536 static u64 access_tx_sdma0_disallowed_packet_err_cnt(
3537                                 const struct cntr_entry *entry,
3538                                 void *context, int vl, int mode, u64 data)
3539 {
3540         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3541
3542         return dd->send_egress_err_status_cnt[16];
3543 }
3544
3545 static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry,
3546                                            void *context, int vl, int mode,
3547                                            u64 data)
3548 {
3549         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3550
3551         return dd->send_egress_err_status_cnt[15];
3552 }
3553
3554 static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry,
3555                                                  void *context, int vl,
3556                                                  int mode, u64 data)
3557 {
3558         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3559
3560         return dd->send_egress_err_status_cnt[14];
3561 }
3562
3563 static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry,
3564                                                void *context, int vl, int mode,
3565                                                u64 data)
3566 {
3567         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3568
3569         return dd->send_egress_err_status_cnt[13];
3570 }
3571
3572 static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry,
3573                                         void *context, int vl, int mode,
3574                                         u64 data)
3575 {
3576         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3577
3578         return dd->send_egress_err_status_cnt[12];
3579 }
3580
3581 static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt(
3582                                 const struct cntr_entry *entry,
3583                                 void *context, int vl, int mode, u64 data)
3584 {
3585         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3586
3587         return dd->send_egress_err_status_cnt[11];
3588 }
3589
3590 static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry,
3591                                              void *context, int vl, int mode,
3592                                              u64 data)
3593 {
3594         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3595
3596         return dd->send_egress_err_status_cnt[10];
3597 }
3598
3599 static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry,
3600                                             void *context, int vl, int mode,
3601                                             u64 data)
3602 {
3603         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3604
3605         return dd->send_egress_err_status_cnt[9];
3606 }
3607
3608 static u64 access_tx_sdma_launch_intf_parity_err_cnt(
3609                                 const struct cntr_entry *entry,
3610                                 void *context, int vl, int mode, u64 data)
3611 {
3612         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3613
3614         return dd->send_egress_err_status_cnt[8];
3615 }
3616
3617 static u64 access_tx_pio_launch_intf_parity_err_cnt(
3618                                 const struct cntr_entry *entry,
3619                                 void *context, int vl, int mode, u64 data)
3620 {
3621         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3622
3623         return dd->send_egress_err_status_cnt[7];
3624 }
3625
3626 static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry,
3627                                             void *context, int vl, int mode,
3628                                             u64 data)
3629 {
3630         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3631
3632         return dd->send_egress_err_status_cnt[6];
3633 }
3634
3635 static u64 access_tx_incorrect_link_state_err_cnt(
3636                                 const struct cntr_entry *entry,
3637                                 void *context, int vl, int mode, u64 data)
3638 {
3639         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3640
3641         return dd->send_egress_err_status_cnt[5];
3642 }
3643
3644 static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry,
3645                                       void *context, int vl, int mode,
3646                                       u64 data)
3647 {
3648         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3649
3650         return dd->send_egress_err_status_cnt[4];
3651 }
3652
3653 static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt(
3654                                 const struct cntr_entry *entry,
3655                                 void *context, int vl, int mode, u64 data)
3656 {
3657         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3658
3659         return dd->send_egress_err_status_cnt[3];
3660 }
3661
3662 static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry,
3663                                             void *context, int vl, int mode,
3664                                             u64 data)
3665 {
3666         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3667
3668         return dd->send_egress_err_status_cnt[2];
3669 }
3670
3671 static u64 access_tx_pkt_integrity_mem_unc_err_cnt(
3672                                 const struct cntr_entry *entry,
3673                                 void *context, int vl, int mode, u64 data)
3674 {
3675         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3676
3677         return dd->send_egress_err_status_cnt[1];
3678 }
3679
3680 static u64 access_tx_pkt_integrity_mem_cor_err_cnt(
3681                                 const struct cntr_entry *entry,
3682                                 void *context, int vl, int mode, u64 data)
3683 {
3684         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3685
3686         return dd->send_egress_err_status_cnt[0];
3687 }
3688
3689 /*
3690  * Software counters corresponding to each of the
3691  * error status bits within SendErrStatus
3692  */
3693 static u64 access_send_csr_write_bad_addr_err_cnt(
3694                                 const struct cntr_entry *entry,
3695                                 void *context, int vl, int mode, u64 data)
3696 {
3697         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3698
3699         return dd->send_err_status_cnt[2];
3700 }
3701
3702 static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
3703                                                  void *context, int vl,
3704                                                  int mode, u64 data)
3705 {
3706         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3707
3708         return dd->send_err_status_cnt[1];
3709 }
3710
3711 static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry,
3712                                       void *context, int vl, int mode,
3713                                       u64 data)
3714 {
3715         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3716
3717         return dd->send_err_status_cnt[0];
3718 }
3719
3720 /*
3721  * Software counters corresponding to each of the
3722  * error status bits within SendCtxtErrStatus
3723  */
3724 static u64 access_pio_write_out_of_bounds_err_cnt(
3725                                 const struct cntr_entry *entry,
3726                                 void *context, int vl, int mode, u64 data)
3727 {
3728         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3729
3730         return dd->sw_ctxt_err_status_cnt[4];
3731 }
3732
3733 static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry,
3734                                              void *context, int vl, int mode,
3735                                              u64 data)
3736 {
3737         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3738
3739         return dd->sw_ctxt_err_status_cnt[3];
3740 }
3741
3742 static u64 access_pio_write_crosses_boundary_err_cnt(
3743                                 const struct cntr_entry *entry,
3744                                 void *context, int vl, int mode, u64 data)
3745 {
3746         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3747
3748         return dd->sw_ctxt_err_status_cnt[2];
3749 }
3750
3751 static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry,
3752                                                 void *context, int vl,
3753                                                 int mode, u64 data)
3754 {
3755         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3756
3757         return dd->sw_ctxt_err_status_cnt[1];
3758 }
3759
3760 static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry,
3761                                                void *context, int vl, int mode,
3762                                                u64 data)
3763 {
3764         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3765
3766         return dd->sw_ctxt_err_status_cnt[0];
3767 }
3768
3769 /*
3770  * Software counters corresponding to each of the
3771  * error status bits within SendDmaEngErrStatus
3772  */
3773 static u64 access_sdma_header_request_fifo_cor_err_cnt(
3774                                 const struct cntr_entry *entry,
3775                                 void *context, int vl, int mode, u64 data)
3776 {
3777         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3778
3779         return dd->sw_send_dma_eng_err_status_cnt[23];
3780 }
3781
3782 static u64 access_sdma_header_storage_cor_err_cnt(
3783                                 const struct cntr_entry *entry,
3784                                 void *context, int vl, int mode, u64 data)
3785 {
3786         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3787
3788         return dd->sw_send_dma_eng_err_status_cnt[22];
3789 }
3790
3791 static u64 access_sdma_packet_tracking_cor_err_cnt(
3792                                 const struct cntr_entry *entry,
3793                                 void *context, int vl, int mode, u64 data)
3794 {
3795         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3796
3797         return dd->sw_send_dma_eng_err_status_cnt[21];
3798 }
3799
3800 static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry,
3801                                             void *context, int vl, int mode,
3802                                             u64 data)
3803 {
3804         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3805
3806         return dd->sw_send_dma_eng_err_status_cnt[20];
3807 }
3808
3809 static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry,
3810                                               void *context, int vl, int mode,
3811                                               u64 data)
3812 {
3813         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3814
3815         return dd->sw_send_dma_eng_err_status_cnt[19];
3816 }
3817
3818 static u64 access_sdma_header_request_fifo_unc_err_cnt(
3819                                 const struct cntr_entry *entry,
3820                                 void *context, int vl, int mode, u64 data)
3821 {
3822         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3823
3824         return dd->sw_send_dma_eng_err_status_cnt[18];
3825 }
3826
3827 static u64 access_sdma_header_storage_unc_err_cnt(
3828                                 const struct cntr_entry *entry,
3829                                 void *context, int vl, int mode, u64 data)
3830 {
3831         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3832
3833         return dd->sw_send_dma_eng_err_status_cnt[17];
3834 }
3835
3836 static u64 access_sdma_packet_tracking_unc_err_cnt(
3837                                 const struct cntr_entry *entry,
3838                                 void *context, int vl, int mode, u64 data)
3839 {
3840         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3841
3842         return dd->sw_send_dma_eng_err_status_cnt[16];
3843 }
3844
3845 static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry,
3846                                             void *context, int vl, int mode,
3847                                             u64 data)
3848 {
3849         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3850
3851         return dd->sw_send_dma_eng_err_status_cnt[15];
3852 }
3853
3854 static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry,
3855                                               void *context, int vl, int mode,
3856                                               u64 data)
3857 {
3858         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3859
3860         return dd->sw_send_dma_eng_err_status_cnt[14];
3861 }
3862
3863 static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry,
3864                                        void *context, int vl, int mode,
3865                                        u64 data)
3866 {
3867         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3868
3869         return dd->sw_send_dma_eng_err_status_cnt[13];
3870 }
3871
3872 static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry,
3873                                              void *context, int vl, int mode,
3874                                              u64 data)
3875 {
3876         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3877
3878         return dd->sw_send_dma_eng_err_status_cnt[12];
3879 }
3880
3881 static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry,
3882                                               void *context, int vl, int mode,
3883                                               u64 data)
3884 {
3885         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3886
3887         return dd->sw_send_dma_eng_err_status_cnt[11];
3888 }
3889
3890 static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry,
3891                                              void *context, int vl, int mode,
3892                                              u64 data)
3893 {
3894         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3895
3896         return dd->sw_send_dma_eng_err_status_cnt[10];
3897 }
3898
3899 static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry,
3900                                           void *context, int vl, int mode,
3901                                           u64 data)
3902 {
3903         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3904
3905         return dd->sw_send_dma_eng_err_status_cnt[9];
3906 }
3907
3908 static u64 access_sdma_packet_desc_overflow_err_cnt(
3909                                 const struct cntr_entry *entry,
3910                                 void *context, int vl, int mode, u64 data)
3911 {
3912         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3913
3914         return dd->sw_send_dma_eng_err_status_cnt[8];
3915 }
3916
3917 static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry,
3918                                                void *context, int vl,
3919                                                int mode, u64 data)
3920 {
3921         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3922
3923         return dd->sw_send_dma_eng_err_status_cnt[7];
3924 }
3925
3926 static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry,
3927                                     void *context, int vl, int mode, u64 data)
3928 {
3929         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3930
3931         return dd->sw_send_dma_eng_err_status_cnt[6];
3932 }
3933
3934 static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry,
3935                                         void *context, int vl, int mode,
3936                                         u64 data)
3937 {
3938         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3939
3940         return dd->sw_send_dma_eng_err_status_cnt[5];
3941 }
3942
3943 static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry,
3944                                           void *context, int vl, int mode,
3945                                           u64 data)
3946 {
3947         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3948
3949         return dd->sw_send_dma_eng_err_status_cnt[4];
3950 }
3951
3952 static u64 access_sdma_tail_out_of_bounds_err_cnt(
3953                                 const struct cntr_entry *entry,
3954                                 void *context, int vl, int mode, u64 data)
3955 {
3956         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3957
3958         return dd->sw_send_dma_eng_err_status_cnt[3];
3959 }
3960
3961 static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry,
3962                                         void *context, int vl, int mode,
3963                                         u64 data)
3964 {
3965         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3966
3967         return dd->sw_send_dma_eng_err_status_cnt[2];
3968 }
3969
3970 static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry,
3971                                             void *context, int vl, int mode,
3972                                             u64 data)
3973 {
3974         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3975
3976         return dd->sw_send_dma_eng_err_status_cnt[1];
3977 }
3978
3979 static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry,
3980                                         void *context, int vl, int mode,
3981                                         u64 data)
3982 {
3983         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3984
3985         return dd->sw_send_dma_eng_err_status_cnt[0];
3986 }
3987
3988 static u64 access_dc_rcv_err_cnt(const struct cntr_entry *entry,
3989                                  void *context, int vl, int mode,
3990                                  u64 data)
3991 {
3992         struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3993
3994         u64 val = 0;
3995         u64 csr = entry->csr;
3996
3997         val = read_write_csr(dd, csr, mode, data);
3998         if (mode == CNTR_MODE_R) {
3999                 val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ?
4000                         CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors;
4001         } else if (mode == CNTR_MODE_W) {
4002                 dd->sw_rcv_bypass_packet_errors = 0;
4003         } else {
4004                 dd_dev_err(dd, "Invalid cntr register access mode");
4005                 return 0;
4006         }
4007         return val;
4008 }
4009
4010 #define def_access_sw_cpu(cntr) \
4011 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry,               \
4012                               void *context, int vl, int mode, u64 data)      \
4013 {                                                                             \
4014         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;        \
4015         return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr,       \
4016                               ppd->ibport_data.rvp.cntr, vl,                  \
4017                               mode, data);                                    \
4018 }
4019
4020 def_access_sw_cpu(rc_acks);
4021 def_access_sw_cpu(rc_qacks);
4022 def_access_sw_cpu(rc_delayed_comp);
4023
4024 #define def_access_ibp_counter(cntr) \
4025 static u64 access_ibp_##cntr(const struct cntr_entry *entry,                  \
4026                                 void *context, int vl, int mode, u64 data)    \
4027 {                                                                             \
4028         struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;        \
4029                                                                               \
4030         if (vl != CNTR_INVALID_VL)                                            \
4031                 return 0;                                                     \
4032                                                                               \
4033         return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr,        \
4034                              mode, data);                                     \
4035 }
4036
4037 def_access_ibp_counter(loop_pkts);
4038 def_access_ibp_counter(rc_resends);
4039 def_access_ibp_counter(rnr_naks);
4040 def_access_ibp_counter(other_naks);
4041 def_access_ibp_counter(rc_timeouts);
4042 def_access_ibp_counter(pkt_drops);
4043 def_access_ibp_counter(dmawait);
4044 def_access_ibp_counter(rc_seqnak);
4045 def_access_ibp_counter(rc_dupreq);
4046 def_access_ibp_counter(rdma_seq);
4047 def_access_ibp_counter(unaligned);
4048 def_access_ibp_counter(seq_naks);
4049
4050 static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = {
4051 [C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH),
4052 [C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT,
4053                         CNTR_NORMAL),
4054 [C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT,
4055                         CNTR_NORMAL),
4056 [C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs,
4057                         RCV_TID_FLOW_GEN_MISMATCH_CNT,
4058                         CNTR_NORMAL),
4059 [C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL,
4060                         CNTR_NORMAL),
4061 [C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs,
4062                         RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL),
4063 [C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt,
4064                         CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL),
4065 [C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT,
4066                         CNTR_NORMAL),
4067 [C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT,
4068                         CNTR_NORMAL),
4069 [C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT,
4070                         CNTR_NORMAL),
4071 [C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT,
4072                         CNTR_NORMAL),
4073 [C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT,
4074                         CNTR_NORMAL),
4075 [C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT,
4076                         CNTR_NORMAL),
4077 [C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt,
4078                         CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL),
4079 [C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt,
4080                         CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL),
4081 [C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT,
4082                               CNTR_SYNTH),
4083 [C_DC_RCV_ERR] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT, 0, CNTR_SYNTH,
4084                             access_dc_rcv_err_cnt),
4085 [C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT,
4086                                  CNTR_SYNTH),
4087 [C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT,
4088                                   CNTR_SYNTH),
4089 [C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT,
4090                                   CNTR_SYNTH),
4091 [C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts,
4092                                    DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH),
4093 [C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts,
4094                                   DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4095                                   CNTR_SYNTH),
4096 [C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr,
4097                                 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH),
4098 [C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT,
4099                                CNTR_SYNTH),
4100 [C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT,
4101                               CNTR_SYNTH),
4102 [C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT,
4103                                CNTR_SYNTH),
4104 [C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT,
4105                                  CNTR_SYNTH),
4106 [C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT,
4107                                 CNTR_SYNTH),
4108 [C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT,
4109                                 CNTR_SYNTH),
4110 [C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT,
4111                                CNTR_SYNTH),
4112 [C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT,
4113                                  CNTR_SYNTH | CNTR_VL),
4114 [C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT,
4115                                 CNTR_SYNTH | CNTR_VL),
4116 [C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH),
4117 [C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT,
4118                                  CNTR_SYNTH | CNTR_VL),
4119 [C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH),
4120 [C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT,
4121                                  CNTR_SYNTH | CNTR_VL),
4122 [C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT,
4123                               CNTR_SYNTH),
4124 [C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT,
4125                                  CNTR_SYNTH | CNTR_VL),
4126 [C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT,
4127                                 CNTR_SYNTH),
4128 [C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT,
4129                                    CNTR_SYNTH | CNTR_VL),
4130 [C_DC_TOTAL_CRC] =
4131         DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR,
4132                          CNTR_SYNTH),
4133 [C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0,
4134                                   CNTR_SYNTH),
4135 [C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1,
4136                                   CNTR_SYNTH),
4137 [C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2,
4138                                   CNTR_SYNTH),
4139 [C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3,
4140                                   CNTR_SYNTH),
4141 [C_DC_CRC_MULT_LN] =
4142         DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN,
4143                          CNTR_SYNTH),
4144 [C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT,
4145                                     CNTR_SYNTH),
4146 [C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT,
4147                                     CNTR_SYNTH),
4148 [C_DC_SEQ_CRC_CNT] =
4149         DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT,
4150                          CNTR_SYNTH),
4151 [C_DC_ESC0_ONLY_CNT] =
4152         DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT,
4153                          CNTR_SYNTH),
4154 [C_DC_ESC0_PLUS1_CNT] =
4155         DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT,
4156                          CNTR_SYNTH),
4157 [C_DC_ESC0_PLUS2_CNT] =
4158         DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT,
4159                          CNTR_SYNTH),
4160 [C_DC_REINIT_FROM_PEER_CNT] =
4161         DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT,
4162                          CNTR_SYNTH),
4163 [C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT,
4164                                   CNTR_SYNTH),
4165 [C_DC_MISC_FLG_CNT] =
4166         DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT,
4167                          CNTR_SYNTH),
4168 [C_DC_PRF_GOOD_LTP_CNT] =
4169         DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH),
4170 [C_DC_PRF_ACCEPTED_LTP_CNT] =
4171         DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT,
4172                          CNTR_SYNTH),
4173 [C_DC_PRF_RX_FLIT_CNT] =
4174         DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH),
4175 [C_DC_PRF_TX_FLIT_CNT] =
4176         DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH),
4177 [C_DC_PRF_CLK_CNTR] =
4178         DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH),
4179 [C_DC_PG_DBG_FLIT_CRDTS_CNT] =
4180         DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH),
4181 [C_DC_PG_STS_PAUSE_COMPLETE_CNT] =
4182         DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT,
4183                          CNTR_SYNTH),
4184 [C_DC_PG_STS_TX_SBE_CNT] =
4185         DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH),
4186 [C_DC_PG_STS_TX_MBE_CNT] =
4187         DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT,
4188                          CNTR_SYNTH),
4189 [C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL,
4190                             access_sw_cpu_intr),
4191 [C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL,
4192                             access_sw_cpu_rcv_limit),
4193 [C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL,
4194                             access_sw_vtx_wait),
4195 [C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL,
4196                             access_sw_pio_wait),
4197 [C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL,
4198                             access_sw_pio_drain),
4199 [C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL,
4200                             access_sw_kmem_wait),
4201 [C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL,
4202                             access_sw_send_schedule),
4203 [C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn",
4204                                       SEND_DMA_DESC_FETCHED_CNT, 0,
4205                                       CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4206                                       dev_access_u32_csr),
4207 [C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0,
4208                              CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4209                              access_sde_int_cnt),
4210 [C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0,
4211                              CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4212                              access_sde_err_cnt),
4213 [C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0,
4214                                   CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4215                                   access_sde_idle_int_cnt),
4216 [C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0,
4217                                       CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4218                                       access_sde_progress_int_cnt),
4219 /* MISC_ERR_STATUS */
4220 [C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0,
4221                                 CNTR_NORMAL,
4222                                 access_misc_pll_lock_fail_err_cnt),
4223 [C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0,
4224                                 CNTR_NORMAL,
4225                                 access_misc_mbist_fail_err_cnt),
4226 [C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0,
4227                                 CNTR_NORMAL,
4228                                 access_misc_invalid_eep_cmd_err_cnt),
4229 [C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0,
4230                                 CNTR_NORMAL,
4231                                 access_misc_efuse_done_parity_err_cnt),
4232 [C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0,
4233                                 CNTR_NORMAL,
4234                                 access_misc_efuse_write_err_cnt),
4235 [C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0,
4236                                 0, CNTR_NORMAL,
4237                                 access_misc_efuse_read_bad_addr_err_cnt),
4238 [C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0,
4239                                 CNTR_NORMAL,
4240                                 access_misc_efuse_csr_parity_err_cnt),
4241 [C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0,
4242                                 CNTR_NORMAL,
4243                                 access_misc_fw_auth_failed_err_cnt),
4244 [C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0,
4245                                 CNTR_NORMAL,
4246                                 access_misc_key_mismatch_err_cnt),
4247 [C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0,
4248                                 CNTR_NORMAL,
4249                                 access_misc_sbus_write_failed_err_cnt),
4250 [C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0,
4251                                 CNTR_NORMAL,
4252                                 access_misc_csr_write_bad_addr_err_cnt),
4253 [C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0,
4254                                 CNTR_NORMAL,
4255                                 access_misc_csr_read_bad_addr_err_cnt),
4256 [C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0,
4257                                 CNTR_NORMAL,
4258                                 access_misc_csr_parity_err_cnt),
4259 /* CceErrStatus */
4260 [C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0,
4261                                 CNTR_NORMAL,
4262                                 access_sw_cce_err_status_aggregated_cnt),
4263 [C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0,
4264                                 CNTR_NORMAL,
4265                                 access_cce_msix_csr_parity_err_cnt),
4266 [C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0,
4267                                 CNTR_NORMAL,
4268                                 access_cce_int_map_unc_err_cnt),
4269 [C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0,
4270                                 CNTR_NORMAL,
4271                                 access_cce_int_map_cor_err_cnt),
4272 [C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0,
4273                                 CNTR_NORMAL,
4274                                 access_cce_msix_table_unc_err_cnt),
4275 [C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0,
4276                                 CNTR_NORMAL,
4277                                 access_cce_msix_table_cor_err_cnt),
4278 [C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0,
4279                                 0, CNTR_NORMAL,
4280                                 access_cce_rxdma_conv_fifo_parity_err_cnt),
4281 [C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0,
4282                                 0, CNTR_NORMAL,
4283                                 access_cce_rcpl_async_fifo_parity_err_cnt),
4284 [C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0,
4285                                 CNTR_NORMAL,
4286                                 access_cce_seg_write_bad_addr_err_cnt),
4287 [C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0,
4288                                 CNTR_NORMAL,
4289                                 access_cce_seg_read_bad_addr_err_cnt),
4290 [C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0,
4291                                 CNTR_NORMAL,
4292                                 access_la_triggered_cnt),
4293 [C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0,
4294                                 CNTR_NORMAL,
4295                                 access_cce_trgt_cpl_timeout_err_cnt),
4296 [C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0,
4297                                 CNTR_NORMAL,
4298                                 access_pcic_receive_parity_err_cnt),
4299 [C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0,
4300                                 CNTR_NORMAL,
4301                                 access_pcic_transmit_back_parity_err_cnt),
4302 [C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0,
4303                                 0, CNTR_NORMAL,
4304                                 access_pcic_transmit_front_parity_err_cnt),
4305 [C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0,
4306                                 CNTR_NORMAL,
4307                                 access_pcic_cpl_dat_q_unc_err_cnt),
4308 [C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0,
4309                                 CNTR_NORMAL,
4310                                 access_pcic_cpl_hd_q_unc_err_cnt),
4311 [C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0,
4312                                 CNTR_NORMAL,
4313                                 access_pcic_post_dat_q_unc_err_cnt),
4314 [C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0,
4315                                 CNTR_NORMAL,
4316                                 access_pcic_post_hd_q_unc_err_cnt),
4317 [C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0,
4318                                 CNTR_NORMAL,
4319                                 access_pcic_retry_sot_mem_unc_err_cnt),
4320 [C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0,
4321                                 CNTR_NORMAL,
4322                                 access_pcic_retry_mem_unc_err),
4323 [C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0,
4324                                 CNTR_NORMAL,
4325                                 access_pcic_n_post_dat_q_parity_err_cnt),
4326 [C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0,
4327                                 CNTR_NORMAL,
4328                                 access_pcic_n_post_h_q_parity_err_cnt),
4329 [C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0,
4330                                 CNTR_NORMAL,
4331                                 access_pcic_cpl_dat_q_cor_err_cnt),
4332 [C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0,
4333                                 CNTR_NORMAL,
4334                                 access_pcic_cpl_hd_q_cor_err_cnt),
4335 [C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0,
4336                                 CNTR_NORMAL,
4337                                 access_pcic_post_dat_q_cor_err_cnt),
4338 [C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0,
4339                                 CNTR_NORMAL,
4340                                 access_pcic_post_hd_q_cor_err_cnt),
4341 [C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0,
4342                                 CNTR_NORMAL,
4343                                 access_pcic_retry_sot_mem_cor_err_cnt),
4344 [C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0,
4345                                 CNTR_NORMAL,
4346                                 access_pcic_retry_mem_cor_err_cnt),
4347 [C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM(
4348                                 "CceCli1AsyncFifoDbgParityError", 0, 0,
4349                                 CNTR_NORMAL,
4350                                 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4351 [C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM(
4352                                 "CceCli1AsyncFifoRxdmaParityError", 0, 0,
4353                                 CNTR_NORMAL,
4354                                 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4355                                 ),
4356 [C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM(
4357                         "CceCli1AsyncFifoSdmaHdParityErr", 0, 0,
4358                         CNTR_NORMAL,
4359                         access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4360 [C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM(
4361                         "CceCli1AsyncFifoPioCrdtParityErr", 0, 0,
4362                         CNTR_NORMAL,
4363                         access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4364 [C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0,
4365                         0, CNTR_NORMAL,
4366                         access_cce_cli2_async_fifo_parity_err_cnt),
4367 [C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0,
4368                         CNTR_NORMAL,
4369                         access_cce_csr_cfg_bus_parity_err_cnt),
4370 [C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0,
4371                         0, CNTR_NORMAL,
4372                         access_cce_cli0_async_fifo_parity_err_cnt),
4373 [C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0,
4374                         CNTR_NORMAL,
4375                         access_cce_rspd_data_parity_err_cnt),
4376 [C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0,
4377                         CNTR_NORMAL,
4378                         access_cce_trgt_access_err_cnt),
4379 [C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0,
4380                         0, CNTR_NORMAL,
4381                         access_cce_trgt_async_fifo_parity_err_cnt),
4382 [C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0,
4383                         CNTR_NORMAL,
4384                         access_cce_csr_write_bad_addr_err_cnt),
4385 [C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0,
4386                         CNTR_NORMAL,
4387                         access_cce_csr_read_bad_addr_err_cnt),
4388 [C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0,
4389                         CNTR_NORMAL,
4390                         access_ccs_csr_parity_err_cnt),
4391
4392 /* RcvErrStatus */
4393 [C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0,
4394                         CNTR_NORMAL,
4395                         access_rx_csr_parity_err_cnt),
4396 [C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0,
4397                         CNTR_NORMAL,
4398                         access_rx_csr_write_bad_addr_err_cnt),
4399 [C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0,
4400                         CNTR_NORMAL,
4401                         access_rx_csr_read_bad_addr_err_cnt),
4402 [C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0,
4403                         CNTR_NORMAL,
4404                         access_rx_dma_csr_unc_err_cnt),
4405 [C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0,
4406                         CNTR_NORMAL,
4407                         access_rx_dma_dq_fsm_encoding_err_cnt),
4408 [C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0,
4409                         CNTR_NORMAL,
4410                         access_rx_dma_eq_fsm_encoding_err_cnt),
4411 [C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0,
4412                         CNTR_NORMAL,
4413                         access_rx_dma_csr_parity_err_cnt),
4414 [C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0,
4415                         CNTR_NORMAL,
4416                         access_rx_rbuf_data_cor_err_cnt),
4417 [C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0,
4418                         CNTR_NORMAL,
4419                         access_rx_rbuf_data_unc_err_cnt),
4420 [C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0,
4421                         CNTR_NORMAL,
4422                         access_rx_dma_data_fifo_rd_cor_err_cnt),
4423 [C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0,
4424                         CNTR_NORMAL,
4425                         access_rx_dma_data_fifo_rd_unc_err_cnt),
4426 [C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0,
4427                         CNTR_NORMAL,
4428                         access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4429 [C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0,
4430                         CNTR_NORMAL,
4431                         access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4432 [C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0,
4433                         CNTR_NORMAL,
4434                         access_rx_rbuf_desc_part2_cor_err_cnt),
4435 [C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0,
4436                         CNTR_NORMAL,
4437                         access_rx_rbuf_desc_part2_unc_err_cnt),
4438 [C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0,
4439                         CNTR_NORMAL,
4440                         access_rx_rbuf_desc_part1_cor_err_cnt),
4441 [C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0,
4442                         CNTR_NORMAL,
4443                         access_rx_rbuf_desc_part1_unc_err_cnt),
4444 [C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0,
4445                         CNTR_NORMAL,
4446                         access_rx_hq_intr_fsm_err_cnt),
4447 [C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0,
4448                         CNTR_NORMAL,
4449                         access_rx_hq_intr_csr_parity_err_cnt),
4450 [C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0,
4451                         CNTR_NORMAL,
4452                         access_rx_lookup_csr_parity_err_cnt),
4453 [C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0,
4454                         CNTR_NORMAL,
4455                         access_rx_lookup_rcv_array_cor_err_cnt),
4456 [C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0,
4457                         CNTR_NORMAL,
4458                         access_rx_lookup_rcv_array_unc_err_cnt),
4459 [C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0,
4460                         0, CNTR_NORMAL,
4461                         access_rx_lookup_des_part2_parity_err_cnt),
4462 [C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0,
4463                         0, CNTR_NORMAL,
4464                         access_rx_lookup_des_part1_unc_cor_err_cnt),
4465 [C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0,
4466                         CNTR_NORMAL,
4467                         access_rx_lookup_des_part1_unc_err_cnt),
4468 [C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0,
4469                         CNTR_NORMAL,
4470                         access_rx_rbuf_next_free_buf_cor_err_cnt),
4471 [C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0,
4472                         CNTR_NORMAL,
4473                         access_rx_rbuf_next_free_buf_unc_err_cnt),
4474 [C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM(
4475                         "RxRbufFlInitWrAddrParityErr", 0, 0,
4476                         CNTR_NORMAL,
4477                         access_rbuf_fl_init_wr_addr_parity_err_cnt),
4478 [C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0,
4479                         0, CNTR_NORMAL,
4480                         access_rx_rbuf_fl_initdone_parity_err_cnt),
4481 [C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0,
4482                         0, CNTR_NORMAL,
4483                         access_rx_rbuf_fl_write_addr_parity_err_cnt),
4484 [C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0,
4485                         CNTR_NORMAL,
4486                         access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4487 [C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0,
4488                         CNTR_NORMAL,
4489                         access_rx_rbuf_empty_err_cnt),
4490 [C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0,
4491                         CNTR_NORMAL,
4492                         access_rx_rbuf_full_err_cnt),
4493 [C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0,
4494                         CNTR_NORMAL,
4495                         access_rbuf_bad_lookup_err_cnt),
4496 [C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0,
4497                         CNTR_NORMAL,
4498                         access_rbuf_ctx_id_parity_err_cnt),
4499 [C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0,
4500                         CNTR_NORMAL,
4501                         access_rbuf_csr_qeopdw_parity_err_cnt),
4502 [C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM(
4503                         "RxRbufCsrQNumOfPktParityErr", 0, 0,
4504                         CNTR_NORMAL,
4505                         access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4506 [C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM(
4507                         "RxRbufCsrQTlPtrParityErr", 0, 0,
4508                         CNTR_NORMAL,
4509                         access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4510 [C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0,
4511                         0, CNTR_NORMAL,
4512                         access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4513 [C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0,
4514                         0, CNTR_NORMAL,
4515                         access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4516 [C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr",
4517                         0, 0, CNTR_NORMAL,
4518                         access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4519 [C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0,
4520                         0, CNTR_NORMAL,
4521                         access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4522 [C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM(
4523                         "RxRbufCsrQHeadBufNumParityErr", 0, 0,
4524                         CNTR_NORMAL,
4525                         access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4526 [C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0,
4527                         0, CNTR_NORMAL,
4528                         access_rx_rbuf_block_list_read_cor_err_cnt),
4529 [C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0,
4530                         0, CNTR_NORMAL,
4531                         access_rx_rbuf_block_list_read_unc_err_cnt),
4532 [C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0,
4533                         CNTR_NORMAL,
4534                         access_rx_rbuf_lookup_des_cor_err_cnt),
4535 [C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0,
4536                         CNTR_NORMAL,
4537                         access_rx_rbuf_lookup_des_unc_err_cnt),
4538 [C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM(
4539                         "RxRbufLookupDesRegUncCorErr", 0, 0,
4540                         CNTR_NORMAL,
4541                         access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4542 [C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0,
4543                         CNTR_NORMAL,
4544                         access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4545 [C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0,
4546                         CNTR_NORMAL,
4547                         access_rx_rbuf_free_list_cor_err_cnt),
4548 [C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0,
4549                         CNTR_NORMAL,
4550                         access_rx_rbuf_free_list_unc_err_cnt),
4551 [C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0,
4552                         CNTR_NORMAL,
4553                         access_rx_rcv_fsm_encoding_err_cnt),
4554 [C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0,
4555                         CNTR_NORMAL,
4556                         access_rx_dma_flag_cor_err_cnt),
4557 [C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0,
4558                         CNTR_NORMAL,
4559                         access_rx_dma_flag_unc_err_cnt),
4560 [C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0,
4561                         CNTR_NORMAL,
4562                         access_rx_dc_sop_eop_parity_err_cnt),
4563 [C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0,
4564                         CNTR_NORMAL,
4565                         access_rx_rcv_csr_parity_err_cnt),
4566 [C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0,
4567                         CNTR_NORMAL,
4568                         access_rx_rcv_qp_map_table_cor_err_cnt),
4569 [C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0,
4570                         CNTR_NORMAL,
4571                         access_rx_rcv_qp_map_table_unc_err_cnt),
4572 [C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0,
4573                         CNTR_NORMAL,
4574                         access_rx_rcv_data_cor_err_cnt),
4575 [C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0,
4576                         CNTR_NORMAL,
4577                         access_rx_rcv_data_unc_err_cnt),
4578 [C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0,
4579                         CNTR_NORMAL,
4580                         access_rx_rcv_hdr_cor_err_cnt),
4581 [C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0,
4582                         CNTR_NORMAL,
4583                         access_rx_rcv_hdr_unc_err_cnt),
4584 [C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0,
4585                         CNTR_NORMAL,
4586                         access_rx_dc_intf_parity_err_cnt),
4587 [C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0,
4588                         CNTR_NORMAL,
4589                         access_rx_dma_csr_cor_err_cnt),
4590 /* SendPioErrStatus */
4591 [C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0,
4592                         CNTR_NORMAL,
4593                         access_pio_pec_sop_head_parity_err_cnt),
4594 [C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0,
4595                         CNTR_NORMAL,
4596                         access_pio_pcc_sop_head_parity_err_cnt),
4597 [C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr",
4598                         0, 0, CNTR_NORMAL,
4599                         access_pio_last_returned_cnt_parity_err_cnt),
4600 [C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0,
4601                         0, CNTR_NORMAL,
4602                         access_pio_current_free_cnt_parity_err_cnt),
4603 [C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0,
4604                         CNTR_NORMAL,
4605                         access_pio_reserved_31_err_cnt),
4606 [C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0,
4607                         CNTR_NORMAL,
4608                         access_pio_reserved_30_err_cnt),
4609 [C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0,
4610                         CNTR_NORMAL,
4611                         access_pio_ppmc_sop_len_err_cnt),
4612 [C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0,
4613                         CNTR_NORMAL,
4614                         access_pio_ppmc_bqc_mem_parity_err_cnt),
4615 [C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0,
4616                         CNTR_NORMAL,
4617                         access_pio_vl_fifo_parity_err_cnt),
4618 [C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0,
4619                         CNTR_NORMAL,
4620                         access_pio_vlf_sop_parity_err_cnt),
4621 [C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0,
4622                         CNTR_NORMAL,
4623                         access_pio_vlf_v1_len_parity_err_cnt),
4624 [C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0,
4625                         CNTR_NORMAL,
4626                         access_pio_block_qw_count_parity_err_cnt),
4627 [C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0,
4628                         CNTR_NORMAL,
4629                         access_pio_write_qw_valid_parity_err_cnt),
4630 [C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0,
4631                         CNTR_NORMAL,
4632                         access_pio_state_machine_err_cnt),
4633 [C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0,
4634                         CNTR_NORMAL,
4635                         access_pio_write_data_parity_err_cnt),
4636 [C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0,
4637                         CNTR_NORMAL,
4638                         access_pio_host_addr_mem_cor_err_cnt),
4639 [C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0,
4640                         CNTR_NORMAL,
4641                         access_pio_host_addr_mem_unc_err_cnt),
4642 [C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0,
4643                         CNTR_NORMAL,
4644                         access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4645 [C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0,
4646                         CNTR_NORMAL,
4647                         access_pio_init_sm_in_err_cnt),
4648 [C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0,
4649                         CNTR_NORMAL,
4650                         access_pio_ppmc_pbl_fifo_err_cnt),
4651 [C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0,
4652                         0, CNTR_NORMAL,
4653                         access_pio_credit_ret_fifo_parity_err_cnt),
4654 [C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0,
4655                         CNTR_NORMAL,
4656                         access_pio_v1_len_mem_bank1_cor_err_cnt),
4657 [C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0,
4658                         CNTR_NORMAL,
4659                         access_pio_v1_len_mem_bank0_cor_err_cnt),
4660 [C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0,
4661                         CNTR_NORMAL,
4662                         access_pio_v1_len_mem_bank1_unc_err_cnt),
4663 [C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0,
4664                         CNTR_NORMAL,
4665                         access_pio_v1_len_mem_bank0_unc_err_cnt),
4666 [C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0,
4667                         CNTR_NORMAL,
4668                         access_pio_sm_pkt_reset_parity_err_cnt),
4669 [C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0,
4670                         CNTR_NORMAL,
4671                         access_pio_pkt_evict_fifo_parity_err_cnt),
4672 [C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM(
4673                         "PioSbrdctrlCrrelFifoParityErr", 0, 0,
4674                         CNTR_NORMAL,
4675                         access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4676 [C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0,
4677                         CNTR_NORMAL,
4678                         access_pio_sbrdctl_crrel_parity_err_cnt),
4679 [C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0,
4680                         CNTR_NORMAL,
4681                         access_pio_pec_fifo_parity_err_cnt),
4682 [C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0,
4683                         CNTR_NORMAL,
4684                         access_pio_pcc_fifo_parity_err_cnt),
4685 [C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0,
4686                         CNTR_NORMAL,
4687                         access_pio_sb_mem_fifo1_err_cnt),
4688 [C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0,
4689                         CNTR_NORMAL,
4690                         access_pio_sb_mem_fifo0_err_cnt),
4691 [C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0,
4692                         CNTR_NORMAL,
4693                         access_pio_csr_parity_err_cnt),
4694 [C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0,
4695                         CNTR_NORMAL,
4696                         access_pio_write_addr_parity_err_cnt),
4697 [C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0,
4698                         CNTR_NORMAL,
4699                         access_pio_write_bad_ctxt_err_cnt),
4700 /* SendDmaErrStatus */
4701 [C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0,
4702                         0, CNTR_NORMAL,
4703                         access_sdma_pcie_req_tracking_cor_err_cnt),
4704 [C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0,
4705                         0, CNTR_NORMAL,
4706                         access_sdma_pcie_req_tracking_unc_err_cnt),
4707 [C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0,
4708                         CNTR_NORMAL,
4709                         access_sdma_csr_parity_err_cnt),
4710 [C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0,
4711                         CNTR_NORMAL,
4712                         access_sdma_rpy_tag_err_cnt),
4713 /* SendEgressErrStatus */
4714 [C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0,
4715                         CNTR_NORMAL,
4716                         access_tx_read_pio_memory_csr_unc_err_cnt),
4717 [C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0,
4718                         0, CNTR_NORMAL,
4719                         access_tx_read_sdma_memory_csr_err_cnt),
4720 [C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0,
4721                         CNTR_NORMAL,
4722                         access_tx_egress_fifo_cor_err_cnt),
4723 [C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0,
4724                         CNTR_NORMAL,
4725                         access_tx_read_pio_memory_cor_err_cnt),
4726 [C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0,
4727                         CNTR_NORMAL,
4728                         access_tx_read_sdma_memory_cor_err_cnt),
4729 [C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0,
4730                         CNTR_NORMAL,
4731                         access_tx_sb_hdr_cor_err_cnt),
4732 [C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0,
4733                         CNTR_NORMAL,
4734                         access_tx_credit_overrun_err_cnt),
4735 [C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0,
4736                         CNTR_NORMAL,
4737                         access_tx_launch_fifo8_cor_err_cnt),
4738 [C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0,
4739                         CNTR_NORMAL,
4740                         access_tx_launch_fifo7_cor_err_cnt),
4741 [C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0,
4742                         CNTR_NORMAL,
4743                         access_tx_launch_fifo6_cor_err_cnt),
4744 [C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0,
4745                         CNTR_NORMAL,
4746                         access_tx_launch_fifo5_cor_err_cnt),
4747 [C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0,
4748                         CNTR_NORMAL,
4749                         access_tx_launch_fifo4_cor_err_cnt),
4750 [C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0,
4751                         CNTR_NORMAL,
4752                         access_tx_launch_fifo3_cor_err_cnt),
4753 [C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0,
4754                         CNTR_NORMAL,
4755                         access_tx_launch_fifo2_cor_err_cnt),
4756 [C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0,
4757                         CNTR_NORMAL,
4758                         access_tx_launch_fifo1_cor_err_cnt),
4759 [C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0,
4760                         CNTR_NORMAL,
4761                         access_tx_launch_fifo0_cor_err_cnt),
4762 [C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0,
4763                         CNTR_NORMAL,
4764                         access_tx_credit_return_vl_err_cnt),
4765 [C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0,
4766                         CNTR_NORMAL,
4767                         access_tx_hcrc_insertion_err_cnt),
4768 [C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0,
4769                         CNTR_NORMAL,
4770                         access_tx_egress_fifo_unc_err_cnt),
4771 [C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0,
4772                         CNTR_NORMAL,
4773                         access_tx_read_pio_memory_unc_err_cnt),
4774 [C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0,
4775                         CNTR_NORMAL,
4776                         access_tx_read_sdma_memory_unc_err_cnt),
4777 [C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0,
4778                         CNTR_NORMAL,
4779                         access_tx_sb_hdr_unc_err_cnt),
4780 [C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0,
4781                         CNTR_NORMAL,
4782                         access_tx_credit_return_partiy_err_cnt),
4783 [C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr",
4784                         0, 0, CNTR_NORMAL,
4785                         access_tx_launch_fifo8_unc_or_parity_err_cnt),
4786 [C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr",
4787                         0, 0, CNTR_NORMAL,
4788                         access_tx_launch_fifo7_unc_or_parity_err_cnt),
4789 [C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr",
4790                         0, 0, CNTR_NORMAL,
4791                         access_tx_launch_fifo6_unc_or_parity_err_cnt),
4792 [C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr",
4793                         0, 0, CNTR_NORMAL,
4794                         access_tx_launch_fifo5_unc_or_parity_err_cnt),
4795 [C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr",
4796                         0, 0, CNTR_NORMAL,
4797                         access_tx_launch_fifo4_unc_or_parity_err_cnt),
4798 [C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr",
4799                         0, 0, CNTR_NORMAL,
4800                         access_tx_launch_fifo3_unc_or_parity_err_cnt),
4801 [C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr",
4802                         0, 0, CNTR_NORMAL,
4803                         access_tx_launch_fifo2_unc_or_parity_err_cnt),
4804 [C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr",
4805                         0, 0, CNTR_NORMAL,
4806                         access_tx_launch_fifo1_unc_or_parity_err_cnt),
4807 [C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr",
4808                         0, 0, CNTR_NORMAL,
4809                         access_tx_launch_fifo0_unc_or_parity_err_cnt),
4810 [C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr",
4811                         0, 0, CNTR_NORMAL,
4812                         access_tx_sdma15_disallowed_packet_err_cnt),
4813 [C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr",
4814                         0, 0, CNTR_NORMAL,
4815                         access_tx_sdma14_disallowed_packet_err_cnt),
4816 [C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr",
4817                         0, 0, CNTR_NORMAL,
4818                         access_tx_sdma13_disallowed_packet_err_cnt),
4819 [C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr",
4820                         0, 0, CNTR_NORMAL,
4821                         access_tx_sdma12_disallowed_packet_err_cnt),
4822 [C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr",
4823                         0, 0, CNTR_NORMAL,
4824                         access_tx_sdma11_disallowed_packet_err_cnt),
4825 [C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr",
4826                         0, 0, CNTR_NORMAL,
4827                         access_tx_sdma10_disallowed_packet_err_cnt),
4828 [C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr",
4829                         0, 0, CNTR_NORMAL,
4830                         access_tx_sdma9_disallowed_packet_err_cnt),
4831 [C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr",
4832                         0, 0, CNTR_NORMAL,
4833                         access_tx_sdma8_disallowed_packet_err_cnt),
4834 [C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr",
4835                         0, 0, CNTR_NORMAL,
4836                         access_tx_sdma7_disallowed_packet_err_cnt),
4837 [C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr",
4838                         0, 0, CNTR_NORMAL,
4839                         access_tx_sdma6_disallowed_packet_err_cnt),
4840 [C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr",
4841                         0, 0, CNTR_NORMAL,
4842                         access_tx_sdma5_disallowed_packet_err_cnt),
4843 [C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr",
4844                         0, 0, CNTR_NORMAL,
4845                         access_tx_sdma4_disallowed_packet_err_cnt),
4846 [C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr",
4847                         0, 0, CNTR_NORMAL,
4848                         access_tx_sdma3_disallowed_packet_err_cnt),
4849 [C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr",
4850                         0, 0, CNTR_NORMAL,
4851                         access_tx_sdma2_disallowed_packet_err_cnt),
4852 [C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr",
4853                         0, 0, CNTR_NORMAL,
4854                         access_tx_sdma1_disallowed_packet_err_cnt),
4855 [C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr",
4856                         0, 0, CNTR_NORMAL,
4857                         access_tx_sdma0_disallowed_packet_err_cnt),
4858 [C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0,
4859                         CNTR_NORMAL,
4860                         access_tx_config_parity_err_cnt),
4861 [C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0,
4862                         CNTR_NORMAL,
4863                         access_tx_sbrd_ctl_csr_parity_err_cnt),
4864 [C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0,
4865                         CNTR_NORMAL,
4866                         access_tx_launch_csr_parity_err_cnt),
4867 [C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0,
4868                         CNTR_NORMAL,
4869                         access_tx_illegal_vl_err_cnt),
4870 [C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM(
4871                         "TxSbrdCtlStateMachineParityErr", 0, 0,
4872                         CNTR_NORMAL,
4873                         access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4874 [C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0,
4875                         CNTR_NORMAL,
4876                         access_egress_reserved_10_err_cnt),
4877 [C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0,
4878                         CNTR_NORMAL,
4879                         access_egress_reserved_9_err_cnt),
4880 [C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr",
4881                         0, 0, CNTR_NORMAL,
4882                         access_tx_sdma_launch_intf_parity_err_cnt),
4883 [C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0,
4884                         CNTR_NORMAL,
4885                         access_tx_pio_launch_intf_parity_err_cnt),
4886 [C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0,
4887                         CNTR_NORMAL,
4888                         access_egress_reserved_6_err_cnt),
4889 [C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0,
4890                         CNTR_NORMAL,
4891                         access_tx_incorrect_link_state_err_cnt),
4892 [C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0,
4893                         CNTR_NORMAL,
4894                         access_tx_linkdown_err_cnt),
4895 [C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM(
4896                         "EgressFifoUnderrunOrParityErr", 0, 0,
4897                         CNTR_NORMAL,
4898                         access_tx_egress_fifi_underrun_or_parity_err_cnt),
4899 [C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0,
4900                         CNTR_NORMAL,
4901                         access_egress_reserved_2_err_cnt),
4902 [C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0,
4903                         CNTR_NORMAL,
4904                         access_tx_pkt_integrity_mem_unc_err_cnt),
4905 [C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0,
4906                         CNTR_NORMAL,
4907                         access_tx_pkt_integrity_mem_cor_err_cnt),
4908 /* SendErrStatus */
4909 [C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0,
4910                         CNTR_NORMAL,
4911                         access_send_csr_write_bad_addr_err_cnt),
4912 [C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0,
4913                         CNTR_NORMAL,
4914                         access_send_csr_read_bad_addr_err_cnt),
4915 [C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0,
4916                         CNTR_NORMAL,
4917                         access_send_csr_parity_cnt),
4918 /* SendCtxtErrStatus */
4919 [C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0,
4920                         CNTR_NORMAL,
4921                         access_pio_write_out_of_bounds_err_cnt),
4922 [C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0,
4923                         CNTR_NORMAL,
4924                         access_pio_write_overflow_err_cnt),
4925 [C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr",
4926                         0, 0, CNTR_NORMAL,
4927                         access_pio_write_crosses_boundary_err_cnt),
4928 [C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0,
4929                         CNTR_NORMAL,
4930                         access_pio_disallowed_packet_err_cnt),
4931 [C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0,
4932                         CNTR_NORMAL,
4933                         access_pio_inconsistent_sop_err_cnt),
4934 /* SendDmaEngErrStatus */
4935 [C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr",
4936                         0, 0, CNTR_NORMAL,
4937                         access_sdma_header_request_fifo_cor_err_cnt),
4938 [C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0,
4939                         CNTR_NORMAL,
4940                         access_sdma_header_storage_cor_err_cnt),
4941 [C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0,
4942                         CNTR_NORMAL,
4943                         access_sdma_packet_tracking_cor_err_cnt),
4944 [C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0,
4945                         CNTR_NORMAL,
4946                         access_sdma_assembly_cor_err_cnt),
4947 [C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0,
4948                         CNTR_NORMAL,
4949                         access_sdma_desc_table_cor_err_cnt),
4950 [C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr",
4951                         0, 0, CNTR_NORMAL,
4952                         access_sdma_header_request_fifo_unc_err_cnt),
4953 [C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0,
4954                         CNTR_NORMAL,
4955                         access_sdma_header_storage_unc_err_cnt),
4956 [C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0,
4957                         CNTR_NORMAL,
4958                         access_sdma_packet_tracking_unc_err_cnt),
4959 [C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0,
4960                         CNTR_NORMAL,
4961                         access_sdma_assembly_unc_err_cnt),
4962 [C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0,
4963                         CNTR_NORMAL,
4964                         access_sdma_desc_table_unc_err_cnt),
4965 [C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0,
4966                         CNTR_NORMAL,
4967                         access_sdma_timeout_err_cnt),
4968 [C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0,
4969                         CNTR_NORMAL,
4970                         access_sdma_header_length_err_cnt),
4971 [C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0,
4972                         CNTR_NORMAL,
4973                         access_sdma_header_address_err_cnt),
4974 [C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0,
4975                         CNTR_NORMAL,
4976                         access_sdma_header_select_err_cnt),
4977 [C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0,
4978                         CNTR_NORMAL,
4979                         access_sdma_reserved_9_err_cnt),
4980 [C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0,
4981                         CNTR_NORMAL,
4982                         access_sdma_packet_desc_overflow_err_cnt),
4983 [C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0,
4984                         CNTR_NORMAL,
4985                         access_sdma_length_mismatch_err_cnt),
4986 [C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0,
4987                         CNTR_NORMAL,
4988                         access_sdma_halt_err_cnt),
4989 [C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0,
4990                         CNTR_NORMAL,
4991                         access_sdma_mem_read_err_cnt),
4992 [C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0,
4993                         CNTR_NORMAL,
4994                         access_sdma_first_desc_err_cnt),
4995 [C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0,
4996                         CNTR_NORMAL,
4997                         access_sdma_tail_out_of_bounds_err_cnt),
4998 [C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0,
4999                         CNTR_NORMAL,
5000                         access_sdma_too_long_err_cnt),
5001 [C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0,
5002                         CNTR_NORMAL,
5003                         access_sdma_gen_mismatch_err_cnt),
5004 [C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0,
5005                         CNTR_NORMAL,
5006                         access_sdma_wrong_dw_err_cnt),
5007 };
5008
5009 static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = {
5010 [C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT,
5011                         CNTR_NORMAL),
5012 [C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT,
5013                         CNTR_NORMAL),
5014 [C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT,
5015                         CNTR_NORMAL),
5016 [C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT,
5017                         CNTR_NORMAL),
5018 [C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT,
5019                         CNTR_NORMAL),
5020 [C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT,
5021                         CNTR_NORMAL),
5022 [C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT,
5023                         CNTR_NORMAL),
5024 [C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL),
5025 [C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL),
5026 [C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH),
5027 [C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT,
5028                                       CNTR_SYNTH | CNTR_VL),
5029 [C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT,
5030                                      CNTR_SYNTH | CNTR_VL),
5031 [C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT,
5032                                       CNTR_SYNTH | CNTR_VL),
5033 [C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL),
5034 [C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL),
5035 [C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT,
5036                              access_sw_link_dn_cnt),
5037 [C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT,
5038                            access_sw_link_up_cnt),
5039 [C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL,
5040                                  access_sw_unknown_frame_cnt),
5041 [C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT,
5042                              access_sw_xmit_discards),
5043 [C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0,
5044                                 CNTR_SYNTH | CNTR_32BIT | CNTR_VL,
5045                                 access_sw_xmit_discards),
5046 [C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH,
5047                                  access_xmit_constraint_errs),
5048 [C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH,
5049                                 access_rcv_constraint_errs),
5050 [C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts),
5051 [C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends),
5052 [C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks),
5053 [C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks),
5054 [C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts),
5055 [C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops),
5056 [C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait),
5057 [C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak),
5058 [C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq),
5059 [C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq),
5060 [C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned),
5061 [C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks),
5062 [C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL,
5063                                access_sw_cpu_rc_acks),
5064 [C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL,
5065                                 access_sw_cpu_rc_qacks),
5066 [C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL,
5067                                        access_sw_cpu_rc_delayed_comp),
5068 [OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1),
5069 [OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3),
5070 [OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5),
5071 [OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7),
5072 [OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9),
5073 [OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11),
5074 [OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13),
5075 [OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15),
5076 [OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17),
5077 [OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19),
5078 [OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21),
5079 [OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23),
5080 [OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25),
5081 [OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27),
5082 [OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29),
5083 [OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31),
5084 [OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33),
5085 [OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35),
5086 [OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37),
5087 [OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39),
5088 [OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41),
5089 [OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43),
5090 [OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45),
5091 [OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47),
5092 [OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49),
5093 [OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51),
5094 [OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53),
5095 [OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55),
5096 [OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57),
5097 [OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59),
5098 [OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61),
5099 [OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63),
5100 [OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65),
5101 [OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67),
5102 [OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69),
5103 [OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71),
5104 [OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73),
5105 [OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75),
5106 [OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77),
5107 [OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79),
5108 [OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81),
5109 [OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83),
5110 [OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85),
5111 [OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87),
5112 [OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89),
5113 [OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91),
5114 [OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93),
5115 [OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95),
5116 [OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97),
5117 [OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99),
5118 [OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101),
5119 [OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103),
5120 [OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105),
5121 [OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107),
5122 [OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109),
5123 [OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111),
5124 [OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113),
5125 [OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115),
5126 [OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117),
5127 [OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119),
5128 [OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121),
5129 [OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123),
5130 [OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125),
5131 [OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127),
5132 [OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129),
5133 [OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131),
5134 [OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133),
5135 [OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135),
5136 [OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137),
5137 [OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139),
5138 [OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141),
5139 [OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143),
5140 [OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145),
5141 [OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147),
5142 [OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149),
5143 [OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151),
5144 [OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153),
5145 [OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155),
5146 [OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157),
5147 [OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159),
5148 };
5149
5150 /* ======================================================================== */
5151
5152 /* return true if this is chip revision revision a */
5153 int is_ax(struct hfi1_devdata *dd)
5154 {
5155         u8 chip_rev_minor =
5156                 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5157                         & CCE_REVISION_CHIP_REV_MINOR_MASK;
5158         return (chip_rev_minor & 0xf0) == 0;
5159 }
5160
5161 /* return true if this is chip revision revision b */
5162 int is_bx(struct hfi1_devdata *dd)
5163 {
5164         u8 chip_rev_minor =
5165                 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5166                         & CCE_REVISION_CHIP_REV_MINOR_MASK;
5167         return (chip_rev_minor & 0xF0) == 0x10;
5168 }
5169
5170 /*
5171  * Append string s to buffer buf.  Arguments curp and len are the current
5172  * position and remaining length, respectively.
5173  *
5174  * return 0 on success, 1 on out of room
5175  */
5176 static int append_str(char *buf, char **curp, int *lenp, const char *s)
5177 {
5178         char *p = *curp;
5179         int len = *lenp;
5180         int result = 0; /* success */
5181         char c;
5182
5183         /* add a comma, if first in the buffer */
5184         if (p != buf) {
5185                 if (len == 0) {
5186                         result = 1; /* out of room */
5187                         goto done;
5188                 }
5189                 *p++ = ',';
5190                 len--;
5191         }
5192
5193         /* copy the string */
5194         while ((c = *s++) != 0) {
5195                 if (len == 0) {
5196                         result = 1; /* out of room */
5197                         goto done;
5198                 }
5199                 *p++ = c;
5200                 len--;
5201         }
5202
5203 done:
5204         /* write return values */
5205         *curp = p;
5206         *lenp = len;
5207
5208         return result;
5209 }
5210
5211 /*
5212  * Using the given flag table, print a comma separated string into
5213  * the buffer.  End in '*' if the buffer is too short.
5214  */
5215 static char *flag_string(char *buf, int buf_len, u64 flags,
5216                          struct flag_table *table, int table_size)
5217 {
5218         char extra[32];
5219         char *p = buf;
5220         int len = buf_len;
5221         int no_room = 0;
5222         int i;
5223
5224         /* make sure there is at least 2 so we can form "*" */
5225         if (len < 2)
5226                 return "";
5227
5228         len--;  /* leave room for a nul */
5229         for (i = 0; i < table_size; i++) {
5230                 if (flags & table[i].flag) {
5231                         no_room = append_str(buf, &p, &len, table[i].str);
5232                         if (no_room)
5233                                 break;
5234                         flags &= ~table[i].flag;
5235                 }
5236         }
5237
5238         /* any undocumented bits left? */
5239         if (!no_room && flags) {
5240                 snprintf(extra, sizeof(extra), "bits 0x%llx", flags);
5241                 no_room = append_str(buf, &p, &len, extra);
5242         }
5243
5244         /* add * if ran out of room */
5245         if (no_room) {
5246                 /* may need to back up to add space for a '*' */
5247                 if (len == 0)
5248                         --p;
5249                 *p++ = '*';
5250         }
5251
5252         /* add final nul - space already allocated above */
5253         *p = 0;
5254         return buf;
5255 }
5256
5257 /* first 8 CCE error interrupt source names */
5258 static const char * const cce_misc_names[] = {
5259         "CceErrInt",            /* 0 */
5260         "RxeErrInt",            /* 1 */
5261         "MiscErrInt",           /* 2 */
5262         "Reserved3",            /* 3 */
5263         "PioErrInt",            /* 4 */
5264         "SDmaErrInt",           /* 5 */
5265         "EgressErrInt",         /* 6 */
5266         "TxeErrInt"             /* 7 */
5267 };
5268
5269 /*
5270  * Return the miscellaneous error interrupt name.
5271  */
5272 static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source)
5273 {
5274         if (source < ARRAY_SIZE(cce_misc_names))
5275                 strncpy(buf, cce_misc_names[source], bsize);
5276         else
5277                 snprintf(buf, bsize, "Reserved%u",
5278                          source + IS_GENERAL_ERR_START);
5279
5280         return buf;
5281 }
5282
5283 /*
5284  * Return the SDMA engine error interrupt name.
5285  */
5286 static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source)
5287 {
5288         snprintf(buf, bsize, "SDmaEngErrInt%u", source);
5289         return buf;
5290 }
5291
5292 /*
5293  * Return the send context error interrupt name.
5294  */
5295 static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source)
5296 {
5297         snprintf(buf, bsize, "SendCtxtErrInt%u", source);
5298         return buf;
5299 }
5300
5301 static const char * const various_names[] = {
5302         "PbcInt",
5303         "GpioAssertInt",
5304         "Qsfp1Int",
5305         "Qsfp2Int",
5306         "TCritInt"
5307 };
5308
5309 /*
5310  * Return the various interrupt name.
5311  */
5312 static char *is_various_name(char *buf, size_t bsize, unsigned int source)
5313 {
5314         if (source < ARRAY_SIZE(various_names))
5315                 strncpy(buf, various_names[source], bsize);
5316         else
5317                 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START);
5318         return buf;
5319 }
5320
5321 /*
5322  * Return the DC interrupt name.
5323  */
5324 static char *is_dc_name(char *buf, size_t bsize, unsigned int source)
5325 {
5326         static const char * const dc_int_names[] = {
5327                 "common",
5328                 "lcb",
5329                 "8051",
5330                 "lbm"   /* local block merge */
5331         };
5332
5333         if (source < ARRAY_SIZE(dc_int_names))
5334                 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]);
5335         else
5336                 snprintf(buf, bsize, "DCInt%u", source);
5337         return buf;
5338 }
5339
5340 static const char * const sdma_int_names[] = {
5341         "SDmaInt",
5342         "SdmaIdleInt",
5343         "SdmaProgressInt",
5344 };
5345
5346 /*
5347  * Return the SDMA engine interrupt name.
5348  */
5349 static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source)
5350 {
5351         /* what interrupt */
5352         unsigned int what  = source / TXE_NUM_SDMA_ENGINES;
5353         /* which engine */
5354         unsigned int which = source % TXE_NUM_SDMA_ENGINES;
5355
5356         if (likely(what < 3))
5357                 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which);
5358         else
5359                 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source);
5360         return buf;
5361 }
5362
5363 /*
5364  * Return the receive available interrupt name.
5365  */
5366 static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source)
5367 {
5368         snprintf(buf, bsize, "RcvAvailInt%u", source);
5369         return buf;
5370 }
5371
5372 /*
5373  * Return the receive urgent interrupt name.
5374  */
5375 static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source)
5376 {
5377         snprintf(buf, bsize, "RcvUrgentInt%u", source);
5378         return buf;
5379 }
5380
5381 /*
5382  * Return the send credit interrupt name.
5383  */
5384 static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source)
5385 {
5386         snprintf(buf, bsize, "SendCreditInt%u", source);
5387         return buf;
5388 }
5389
5390 /*
5391  * Return the reserved interrupt name.
5392  */
5393 static char *is_reserved_name(char *buf, size_t bsize, unsigned int source)
5394 {
5395         snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START);
5396         return buf;
5397 }
5398
5399 static char *cce_err_status_string(char *buf, int buf_len, u64 flags)
5400 {
5401         return flag_string(buf, buf_len, flags,
5402                            cce_err_status_flags,
5403                            ARRAY_SIZE(cce_err_status_flags));
5404 }
5405
5406 static char *rxe_err_status_string(char *buf, int buf_len, u64 flags)
5407 {
5408         return flag_string(buf, buf_len, flags,
5409                            rxe_err_status_flags,
5410                            ARRAY_SIZE(rxe_err_status_flags));
5411 }
5412
5413 static char *misc_err_status_string(char *buf, int buf_len, u64 flags)
5414 {
5415         return flag_string(buf, buf_len, flags, misc_err_status_flags,
5416                            ARRAY_SIZE(misc_err_status_flags));
5417 }
5418
5419 static char *pio_err_status_string(char *buf, int buf_len, u64 flags)
5420 {
5421         return flag_string(buf, buf_len, flags,
5422                            pio_err_status_flags,
5423                            ARRAY_SIZE(pio_err_status_flags));
5424 }
5425
5426 static char *sdma_err_status_string(char *buf, int buf_len, u64 flags)
5427 {
5428         return flag_string(buf, buf_len, flags,
5429                            sdma_err_status_flags,
5430                            ARRAY_SIZE(sdma_err_status_flags));
5431 }
5432
5433 static char *egress_err_status_string(char *buf, int buf_len, u64 flags)
5434 {
5435         return flag_string(buf, buf_len, flags,
5436                            egress_err_status_flags,
5437                            ARRAY_SIZE(egress_err_status_flags));
5438 }
5439
5440 static char *egress_err_info_string(char *buf, int buf_len, u64 flags)
5441 {
5442         return flag_string(buf, buf_len, flags,
5443                            egress_err_info_flags,
5444                            ARRAY_SIZE(egress_err_info_flags));
5445 }
5446
5447 static char *send_err_status_string(char *buf, int buf_len, u64 flags)
5448 {
5449         return flag_string(buf, buf_len, flags,
5450                            send_err_status_flags,
5451                            ARRAY_SIZE(send_err_status_flags));
5452 }
5453
5454 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5455 {
5456         char buf[96];
5457         int i = 0;
5458
5459         /*
5460          * For most these errors, there is nothing that can be done except
5461          * report or record it.
5462          */
5463         dd_dev_info(dd, "CCE Error: %s\n",
5464                     cce_err_status_string(buf, sizeof(buf), reg));
5465
5466         if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) &&
5467             is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) {
5468                 /* this error requires a manual drop into SPC freeze mode */
5469                 /* then a fix up */
5470                 start_freeze_handling(dd->pport, FREEZE_SELF);
5471         }
5472
5473         for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) {
5474                 if (reg & (1ull << i)) {
5475                         incr_cntr64(&dd->cce_err_status_cnt[i]);
5476                         /* maintain a counter over all cce_err_status errors */
5477                         incr_cntr64(&dd->sw_cce_err_status_aggregate);
5478                 }
5479         }
5480 }
5481
5482 /*
5483  * Check counters for receive errors that do not have an interrupt
5484  * associated with them.
5485  */
5486 #define RCVERR_CHECK_TIME 10
5487 static void update_rcverr_timer(unsigned long opaque)
5488 {
5489         struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
5490         struct hfi1_pportdata *ppd = dd->pport;
5491         u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);
5492
5493         if (dd->rcv_ovfl_cnt < cur_ovfl_cnt &&
5494             ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) {
5495                 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
5496                 set_link_down_reason(
5497                 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0,
5498                 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
5499                 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
5500         }
5501         dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt;
5502
5503         mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5504 }
5505
5506 static int init_rcverr(struct hfi1_devdata *dd)
5507 {
5508         setup_timer(&dd->rcverr_timer, update_rcverr_timer, (unsigned long)dd);
5509         /* Assume the hardware counter has been reset */
5510         dd->rcv_ovfl_cnt = 0;
5511         return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5512 }
5513
5514 static void free_rcverr(struct hfi1_devdata *dd)
5515 {
5516         if (dd->rcverr_timer.data)
5517                 del_timer_sync(&dd->rcverr_timer);
5518         dd->rcverr_timer.data = 0;
5519 }
5520
5521 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5522 {
5523         char buf[96];
5524         int i = 0;
5525
5526         dd_dev_info(dd, "Receive Error: %s\n",
5527                     rxe_err_status_string(buf, sizeof(buf), reg));
5528
5529         if (reg & ALL_RXE_FREEZE_ERR) {
5530                 int flags = 0;
5531
5532                 /*
5533                  * Freeze mode recovery is disabled for the errors
5534                  * in RXE_FREEZE_ABORT_MASK
5535                  */
5536                 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK))
5537                         flags = FREEZE_ABORT;
5538
5539                 start_freeze_handling(dd->pport, flags);
5540         }
5541
5542         for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) {
5543                 if (reg & (1ull << i))
5544                         incr_cntr64(&dd->rcv_err_status_cnt[i]);
5545         }
5546 }
5547
5548 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5549 {
5550         char buf[96];
5551         int i = 0;
5552
5553         dd_dev_info(dd, "Misc Error: %s",
5554                     misc_err_status_string(buf, sizeof(buf), reg));
5555         for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) {
5556                 if (reg & (1ull << i))
5557                         incr_cntr64(&dd->misc_err_status_cnt[i]);
5558         }
5559 }
5560
5561 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5562 {
5563         char buf[96];
5564         int i = 0;
5565
5566         dd_dev_info(dd, "PIO Error: %s\n",
5567                     pio_err_status_string(buf, sizeof(buf), reg));
5568
5569         if (reg & ALL_PIO_FREEZE_ERR)
5570                 start_freeze_handling(dd->pport, 0);
5571
5572         for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) {
5573                 if (reg & (1ull << i))
5574                         incr_cntr64(&dd->send_pio_err_status_cnt[i]);
5575         }
5576 }
5577
5578 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5579 {
5580         char buf[96];
5581         int i = 0;
5582
5583         dd_dev_info(dd, "SDMA Error: %s\n",
5584                     sdma_err_status_string(buf, sizeof(buf), reg));
5585
5586         if (reg & ALL_SDMA_FREEZE_ERR)
5587                 start_freeze_handling(dd->pport, 0);
5588
5589         for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) {
5590                 if (reg & (1ull << i))
5591                         incr_cntr64(&dd->send_dma_err_status_cnt[i]);
5592         }
5593 }
5594
5595 static inline void __count_port_discards(struct hfi1_pportdata *ppd)
5596 {
5597         incr_cntr64(&ppd->port_xmit_discards);
5598 }
5599
5600 static void count_port_inactive(struct hfi1_devdata *dd)
5601 {
5602         __count_port_discards(dd->pport);
5603 }
5604
5605 /*
5606  * We have had a "disallowed packet" error during egress. Determine the
5607  * integrity check which failed, and update relevant error counter, etc.
5608  *
5609  * Note that the SEND_EGRESS_ERR_INFO register has only a single
5610  * bit of state per integrity check, and so we can miss the reason for an
5611  * egress error if more than one packet fails the same integrity check
5612  * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5613  */
5614 static void handle_send_egress_err_info(struct hfi1_devdata *dd,
5615                                         int vl)
5616 {
5617         struct hfi1_pportdata *ppd = dd->pport;
5618         u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
5619         u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
5620         char buf[96];
5621
5622         /* clear down all observed info as quickly as possible after read */
5623         write_csr(dd, SEND_EGRESS_ERR_INFO, info);
5624
5625         dd_dev_info(dd,
5626                     "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n",
5627                     info, egress_err_info_string(buf, sizeof(buf), info), src);
5628
5629         /* Eventually add other counters for each bit */
5630         if (info & PORT_DISCARD_EGRESS_ERRS) {
5631                 int weight, i;
5632
5633                 /*
5634                  * Count all applicable bits as individual errors and
5635                  * attribute them to the packet that triggered this handler.
5636                  * This may not be completely accurate due to limitations
5637                  * on the available hardware error information.  There is
5638                  * a single information register and any number of error
5639                  * packets may have occurred and contributed to it before
5640                  * this routine is called.  This means that:
5641                  * a) If multiple packets with the same error occur before
5642                  *    this routine is called, earlier packets are missed.
5643                  *    There is only a single bit for each error type.
5644                  * b) Errors may not be attributed to the correct VL.
5645                  *    The driver is attributing all bits in the info register
5646                  *    to the packet that triggered this call, but bits
5647                  *    could be an accumulation of different packets with
5648                  *    different VLs.
5649                  * c) A single error packet may have multiple counts attached
5650                  *    to it.  There is no way for the driver to know if
5651                  *    multiple bits set in the info register are due to a
5652                  *    single packet or multiple packets.  The driver assumes
5653                  *    multiple packets.
5654                  */
5655                 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS);
5656                 for (i = 0; i < weight; i++) {
5657                         __count_port_discards(ppd);
5658                         if (vl >= 0 && vl < TXE_NUM_DATA_VL)
5659                                 incr_cntr64(&ppd->port_xmit_discards_vl[vl]);
5660                         else if (vl == 15)
5661                                 incr_cntr64(&ppd->port_xmit_discards_vl
5662                                             [C_VL_15]);
5663                 }
5664         }
5665 }
5666
5667 /*
5668  * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5669  * register. Does it represent a 'port inactive' error?
5670  */
5671 static inline int port_inactive_err(u64 posn)
5672 {
5673         return (posn >= SEES(TX_LINKDOWN) &&
5674                 posn <= SEES(TX_INCORRECT_LINK_STATE));
5675 }
5676
5677 /*
5678  * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5679  * register. Does it represent a 'disallowed packet' error?
5680  */
5681 static inline int disallowed_pkt_err(int posn)
5682 {
5683         return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) &&
5684                 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET));
5685 }
5686
5687 /*
5688  * Input value is a bit position of one of the SDMA engine disallowed
5689  * packet errors.  Return which engine.  Use of this must be guarded by
5690  * disallowed_pkt_err().
5691  */
5692 static inline int disallowed_pkt_engine(int posn)
5693 {
5694         return posn - SEES(TX_SDMA0_DISALLOWED_PACKET);
5695 }
5696
5697 /*
5698  * Translate an SDMA engine to a VL.  Return -1 if the tranlation cannot
5699  * be done.
5700  */
5701 static int engine_to_vl(struct hfi1_devdata *dd, int engine)
5702 {
5703         struct sdma_vl_map *m;
5704         int vl;
5705
5706         /* range check */
5707         if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES)
5708                 return -1;
5709
5710         rcu_read_lock();
5711         m = rcu_dereference(dd->sdma_map);
5712         vl = m->engine_to_vl[engine];
5713         rcu_read_unlock();
5714
5715         return vl;
5716 }
5717
5718 /*
5719  * Translate the send context (sofware index) into a VL.  Return -1 if the
5720  * translation cannot be done.
5721  */
5722 static int sc_to_vl(struct hfi1_devdata *dd, int sw_index)
5723 {
5724         struct send_context_info *sci;
5725         struct send_context *sc;
5726         int i;
5727
5728         sci = &dd->send_contexts[sw_index];
5729
5730         /* there is no information for user (PSM) and ack contexts */
5731         if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15))
5732                 return -1;
5733
5734         sc = sci->sc;
5735         if (!sc)
5736                 return -1;
5737         if (dd->vld[15].sc == sc)
5738                 return 15;
5739         for (i = 0; i < num_vls; i++)
5740                 if (dd->vld[i].sc == sc)
5741                         return i;
5742
5743         return -1;
5744 }
5745
5746 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5747 {
5748         u64 reg_copy = reg, handled = 0;
5749         char buf[96];
5750         int i = 0;
5751
5752         if (reg & ALL_TXE_EGRESS_FREEZE_ERR)
5753                 start_freeze_handling(dd->pport, 0);
5754         else if (is_ax(dd) &&
5755                  (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) &&
5756                  (dd->icode != ICODE_FUNCTIONAL_SIMULATOR))
5757                 start_freeze_handling(dd->pport, 0);
5758
5759         while (reg_copy) {
5760                 int posn = fls64(reg_copy);
5761                 /* fls64() returns a 1-based offset, we want it zero based */
5762                 int shift = posn - 1;
5763                 u64 mask = 1ULL << shift;
5764
5765                 if (port_inactive_err(shift)) {
5766                         count_port_inactive(dd);
5767                         handled |= mask;
5768                 } else if (disallowed_pkt_err(shift)) {
5769                         int vl = engine_to_vl(dd, disallowed_pkt_engine(shift));
5770
5771                         handle_send_egress_err_info(dd, vl);
5772                         handled |= mask;
5773                 }
5774                 reg_copy &= ~mask;
5775         }
5776
5777         reg &= ~handled;
5778
5779         if (reg)
5780                 dd_dev_info(dd, "Egress Error: %s\n",
5781                             egress_err_status_string(buf, sizeof(buf), reg));
5782
5783         for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) {
5784                 if (reg & (1ull << i))
5785                         incr_cntr64(&dd->send_egress_err_status_cnt[i]);
5786         }
5787 }
5788
5789 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5790 {
5791         char buf[96];
5792         int i = 0;
5793
5794         dd_dev_info(dd, "Send Error: %s\n",
5795                     send_err_status_string(buf, sizeof(buf), reg));
5796
5797         for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) {
5798                 if (reg & (1ull << i))
5799                         incr_cntr64(&dd->send_err_status_cnt[i]);
5800         }
5801 }
5802
5803 /*
5804  * The maximum number of times the error clear down will loop before
5805  * blocking a repeating error.  This value is arbitrary.
5806  */
5807 #define MAX_CLEAR_COUNT 20
5808
5809 /*
5810  * Clear and handle an error register.  All error interrupts are funneled
5811  * through here to have a central location to correctly handle single-
5812  * or multi-shot errors.
5813  *
5814  * For non per-context registers, call this routine with a context value
5815  * of 0 so the per-context offset is zero.
5816  *
5817  * If the handler loops too many times, assume that something is wrong
5818  * and can't be fixed, so mask the error bits.
5819  */
5820 static void interrupt_clear_down(struct hfi1_devdata *dd,
5821                                  u32 context,
5822                                  const struct err_reg_info *eri)
5823 {
5824         u64 reg;
5825         u32 count;
5826
5827         /* read in a loop until no more errors are seen */
5828         count = 0;
5829         while (1) {
5830                 reg = read_kctxt_csr(dd, context, eri->status);
5831                 if (reg == 0)
5832                         break;
5833                 write_kctxt_csr(dd, context, eri->clear, reg);
5834                 if (likely(eri->handler))
5835                         eri->handler(dd, context, reg);
5836                 count++;
5837                 if (count > MAX_CLEAR_COUNT) {
5838                         u64 mask;
5839
5840                         dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n",
5841                                    eri->desc, reg);
5842                         /*
5843                          * Read-modify-write so any other masked bits
5844                          * remain masked.
5845                          */
5846                         mask = read_kctxt_csr(dd, context, eri->mask);
5847                         mask &= ~reg;
5848                         write_kctxt_csr(dd, context, eri->mask, mask);
5849                         break;
5850                 }
5851         }
5852 }
5853
5854 /*
5855  * CCE block "misc" interrupt.  Source is < 16.
5856  */
5857 static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source)
5858 {
5859         const struct err_reg_info *eri = &misc_errs[source];
5860
5861         if (eri->handler) {
5862                 interrupt_clear_down(dd, 0, eri);
5863         } else {
5864                 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n",
5865                            source);
5866         }
5867 }
5868
5869 static char *send_context_err_status_string(char *buf, int buf_len, u64 flags)
5870 {
5871         return flag_string(buf, buf_len, flags,
5872                            sc_err_status_flags,
5873                            ARRAY_SIZE(sc_err_status_flags));
5874 }
5875
5876 /*
5877  * Send context error interrupt.  Source (hw_context) is < 160.
5878  *
5879  * All send context errors cause the send context to halt.  The normal
5880  * clear-down mechanism cannot be used because we cannot clear the
5881  * error bits until several other long-running items are done first.
5882  * This is OK because with the context halted, nothing else is going
5883  * to happen on it anyway.
5884  */
5885 static void is_sendctxt_err_int(struct hfi1_devdata *dd,
5886                                 unsigned int hw_context)
5887 {
5888         struct send_context_info *sci;
5889         struct send_context *sc;
5890         char flags[96];
5891         u64 status;
5892         u32 sw_index;
5893         int i = 0;
5894
5895         sw_index = dd->hw_to_sw[hw_context];
5896         if (sw_index >= dd->num_send_contexts) {
5897                 dd_dev_err(dd,
5898                            "out of range sw index %u for send context %u\n",
5899                            sw_index, hw_context);
5900                 return;
5901         }
5902         sci = &dd->send_contexts[sw_index];
5903         sc = sci->sc;
5904         if (!sc) {
5905                 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__,
5906                            sw_index, hw_context);
5907                 return;
5908         }
5909
5910         /* tell the software that a halt has begun */
5911         sc_stop(sc, SCF_HALTED);
5912
5913         status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS);
5914
5915         dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context,
5916                     send_context_err_status_string(flags, sizeof(flags),
5917                                                    status));
5918
5919         if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK)
5920                 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index));
5921
5922         /*
5923          * Automatically restart halted kernel contexts out of interrupt
5924          * context.  User contexts must ask the driver to restart the context.
5925          */
5926         if (sc->type != SC_USER)
5927                 queue_work(dd->pport->hfi1_wq, &sc->halt_work);
5928
5929         /*
5930          * Update the counters for the corresponding status bits.
5931          * Note that these particular counters are aggregated over all
5932          * 160 contexts.
5933          */
5934         for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) {
5935                 if (status & (1ull << i))
5936                         incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]);
5937         }
5938 }
5939
5940 static void handle_sdma_eng_err(struct hfi1_devdata *dd,
5941                                 unsigned int source, u64 status)
5942 {
5943         struct sdma_engine *sde;
5944         int i = 0;
5945
5946         sde = &dd->per_sdma[source];
5947 #ifdef CONFIG_SDMA_VERBOSITY
5948         dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5949                    slashstrip(__FILE__), __LINE__, __func__);
5950         dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n",
5951                    sde->this_idx, source, (unsigned long long)status);
5952 #endif
5953         sde->err_cnt++;
5954         sdma_engine_error(sde, status);
5955
5956         /*
5957         * Update the counters for the corresponding status bits.
5958         * Note that these particular counters are aggregated over
5959         * all 16 DMA engines.
5960         */
5961         for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) {
5962                 if (status & (1ull << i))
5963                         incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]);
5964         }
5965 }
5966
5967 /*
5968  * CCE block SDMA error interrupt.  Source is < 16.
5969  */
5970 static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source)
5971 {
5972 #ifdef CONFIG_SDMA_VERBOSITY
5973         struct sdma_engine *sde = &dd->per_sdma[source];
5974
5975         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
5976                    slashstrip(__FILE__), __LINE__, __func__);
5977         dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx,
5978                    source);
5979         sdma_dumpstate(sde);
5980 #endif
5981         interrupt_clear_down(dd, source, &sdma_eng_err);
5982 }
5983
5984 /*
5985  * CCE block "various" interrupt.  Source is < 8.
5986  */
5987 static void is_various_int(struct hfi1_devdata *dd, unsigned int source)
5988 {
5989         const struct err_reg_info *eri = &various_err[source];
5990
5991         /*
5992          * TCritInt cannot go through interrupt_clear_down()
5993          * because it is not a second tier interrupt. The handler
5994          * should be called directly.
5995          */
5996         if (source == TCRIT_INT_SOURCE)
5997                 handle_temp_err(dd);
5998         else if (eri->handler)
5999                 interrupt_clear_down(dd, 0, eri);
6000         else
6001                 dd_dev_info(dd,
6002                             "%s: Unimplemented/reserved interrupt %d\n",
6003                             __func__, source);
6004 }
6005
6006 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg)
6007 {
6008         /* src_ctx is always zero */
6009         struct hfi1_pportdata *ppd = dd->pport;
6010         unsigned long flags;
6011         u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
6012
6013         if (reg & QSFP_HFI0_MODPRST_N) {
6014                 if (!qsfp_mod_present(ppd)) {
6015                         dd_dev_info(dd, "%s: QSFP module removed\n",
6016                                     __func__);
6017
6018                         ppd->driver_link_ready = 0;
6019                         /*
6020                          * Cable removed, reset all our information about the
6021                          * cache and cable capabilities
6022                          */
6023
6024                         spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6025                         /*
6026                          * We don't set cache_refresh_required here as we expect
6027                          * an interrupt when a cable is inserted
6028                          */
6029                         ppd->qsfp_info.cache_valid = 0;
6030                         ppd->qsfp_info.reset_needed = 0;
6031                         ppd->qsfp_info.limiting_active = 0;
6032                         spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
6033                                                flags);
6034                         /* Invert the ModPresent pin now to detect plug-in */
6035                         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6036                                   ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6037
6038                         if ((ppd->offline_disabled_reason >
6039                           HFI1_ODR_MASK(
6040                           OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
6041                           (ppd->offline_disabled_reason ==
6042                           HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)))
6043                                 ppd->offline_disabled_reason =
6044                                 HFI1_ODR_MASK(
6045                                 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
6046
6047                         if (ppd->host_link_state == HLS_DN_POLL) {
6048                                 /*
6049                                  * The link is still in POLL. This means
6050                                  * that the normal link down processing
6051                                  * will not happen. We have to do it here
6052                                  * before turning the DC off.
6053                                  */
6054                                 queue_work(ppd->hfi1_wq, &ppd->link_down_work);
6055                         }
6056                 } else {
6057                         dd_dev_info(dd, "%s: QSFP module inserted\n",
6058                                     __func__);
6059
6060                         spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6061                         ppd->qsfp_info.cache_valid = 0;
6062                         ppd->qsfp_info.cache_refresh_required = 1;
6063                         spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
6064                                                flags);
6065
6066                         /*
6067                          * Stop inversion of ModPresent pin to detect
6068                          * removal of the cable
6069                          */
6070                         qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N;
6071                         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6072                                   ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6073
6074                         ppd->offline_disabled_reason =
6075                                 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
6076                 }
6077         }
6078
6079         if (reg & QSFP_HFI0_INT_N) {
6080                 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n",
6081                             __func__);
6082                 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6083                 ppd->qsfp_info.check_interrupt_flags = 1;
6084                 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags);
6085         }
6086
6087         /* Schedule the QSFP work only if there is a cable attached. */
6088         if (qsfp_mod_present(ppd))
6089                 queue_work(ppd->hfi1_wq, &ppd->qsfp_info.qsfp_work);
6090 }
6091
6092 static int request_host_lcb_access(struct hfi1_devdata *dd)
6093 {
6094         int ret;
6095
6096         ret = do_8051_command(dd, HCMD_MISC,
6097                               (u64)HCMD_MISC_REQUEST_LCB_ACCESS <<
6098                               LOAD_DATA_FIELD_ID_SHIFT, NULL);
6099         if (ret != HCMD_SUCCESS) {
6100                 dd_dev_err(dd, "%s: command failed with error %d\n",
6101                            __func__, ret);
6102         }
6103         return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6104 }
6105
6106 static int request_8051_lcb_access(struct hfi1_devdata *dd)
6107 {
6108         int ret;
6109
6110         ret = do_8051_command(dd, HCMD_MISC,
6111                               (u64)HCMD_MISC_GRANT_LCB_ACCESS <<
6112                               LOAD_DATA_FIELD_ID_SHIFT, NULL);
6113         if (ret != HCMD_SUCCESS) {
6114                 dd_dev_err(dd, "%s: command failed with error %d\n",
6115                            __func__, ret);
6116         }
6117         return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6118 }
6119
6120 /*
6121  * Set the LCB selector - allow host access.  The DCC selector always
6122  * points to the host.
6123  */
6124 static inline void set_host_lcb_access(struct hfi1_devdata *dd)
6125 {
6126         write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6127                   DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6128                   DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
6129 }
6130
6131 /*
6132  * Clear the LCB selector - allow 8051 access.  The DCC selector always
6133  * points to the host.
6134  */
6135 static inline void set_8051_lcb_access(struct hfi1_devdata *dd)
6136 {
6137         write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6138                   DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
6139 }
6140
6141 /*
6142  * Acquire LCB access from the 8051.  If the host already has access,
6143  * just increment a counter.  Otherwise, inform the 8051 that the
6144  * host is taking access.
6145  *
6146  * Returns:
6147  *      0 on success
6148  *      -EBUSY if the 8051 has control and cannot be disturbed
6149  *      -errno if unable to acquire access from the 8051
6150  */
6151 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6152 {
6153         struct hfi1_pportdata *ppd = dd->pport;
6154         int ret = 0;
6155
6156         /*
6157          * Use the host link state lock so the operation of this routine
6158          * { link state check, selector change, count increment } can occur
6159          * as a unit against a link state change.  Otherwise there is a
6160          * race between the state change and the count increment.
6161          */
6162         if (sleep_ok) {
6163                 mutex_lock(&ppd->hls_lock);
6164         } else {
6165                 while (!mutex_trylock(&ppd->hls_lock))
6166                         udelay(1);
6167         }
6168
6169         /* this access is valid only when the link is up */
6170         if (ppd->host_link_state & HLS_DOWN) {
6171                 dd_dev_info(dd, "%s: link state %s not up\n",
6172                             __func__, link_state_name(ppd->host_link_state));
6173                 ret = -EBUSY;
6174                 goto done;
6175         }
6176
6177         if (dd->lcb_access_count == 0) {
6178                 ret = request_host_lcb_access(dd);
6179                 if (ret) {
6180                         dd_dev_err(dd,
6181                                    "%s: unable to acquire LCB access, err %d\n",
6182                                    __func__, ret);
6183                         goto done;
6184                 }
6185                 set_host_lcb_access(dd);
6186         }
6187         dd->lcb_access_count++;
6188 done:
6189         mutex_unlock(&ppd->hls_lock);
6190         return ret;
6191 }
6192
6193 /*
6194  * Release LCB access by decrementing the use count.  If the count is moving
6195  * from 1 to 0, inform 8051 that it has control back.
6196  *
6197  * Returns:
6198  *      0 on success
6199  *      -errno if unable to release access to the 8051
6200  */
6201 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6202 {
6203         int ret = 0;
6204
6205         /*
6206          * Use the host link state lock because the acquire needed it.
6207          * Here, we only need to keep { selector change, count decrement }
6208          * as a unit.
6209          */
6210         if (sleep_ok) {
6211                 mutex_lock(&dd->pport->hls_lock);
6212         } else {
6213                 while (!mutex_trylock(&dd->pport->hls_lock))
6214                         udelay(1);
6215         }
6216
6217         if (dd->lcb_access_count == 0) {
6218                 dd_dev_err(dd, "%s: LCB access count is zero.  Skipping.\n",
6219                            __func__);
6220                 goto done;
6221         }
6222
6223         if (dd->lcb_access_count == 1) {
6224                 set_8051_lcb_access(dd);
6225                 ret = request_8051_lcb_access(dd);
6226                 if (ret) {
6227                         dd_dev_err(dd,
6228                                    "%s: unable to release LCB access, err %d\n",
6229                                    __func__, ret);
6230                         /* restore host access if the grant didn't work */
6231                         set_host_lcb_access(dd);
6232                         goto done;
6233                 }
6234         }
6235         dd->lcb_access_count--;
6236 done:
6237         mutex_unlock(&dd->pport->hls_lock);
6238         return ret;
6239 }
6240
6241 /*
6242  * Initialize LCB access variables and state.  Called during driver load,
6243  * after most of the initialization is finished.
6244  *
6245  * The DC default is LCB access on for the host.  The driver defaults to
6246  * leaving access to the 8051.  Assign access now - this constrains the call
6247  * to this routine to be after all LCB set-up is done.  In particular, after
6248  * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6249  */
6250 static void init_lcb_access(struct hfi1_devdata *dd)
6251 {
6252         dd->lcb_access_count = 0;
6253 }
6254
6255 /*
6256  * Write a response back to a 8051 request.
6257  */
6258 static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data)
6259 {
6260         write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
6261                   DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6262                   (u64)return_code <<
6263                   DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6264                   (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
6265 }
6266
6267 /*
6268  * Handle host requests from the 8051.
6269  */
6270 static void handle_8051_request(struct hfi1_pportdata *ppd)
6271 {
6272         struct hfi1_devdata *dd = ppd->dd;
6273         u64 reg;
6274         u16 data = 0;
6275         u8 type;
6276
6277         reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
6278         if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0)
6279                 return; /* no request */
6280
6281         /* zero out COMPLETED so the response is seen */
6282         write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
6283
6284         /* extract request details */
6285         type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT)
6286                         & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK;
6287         data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT)
6288                         & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK;
6289
6290         switch (type) {
6291         case HREQ_LOAD_CONFIG:
6292         case HREQ_SAVE_CONFIG:
6293         case HREQ_READ_CONFIG:
6294         case HREQ_SET_TX_EQ_ABS:
6295         case HREQ_SET_TX_EQ_REL:
6296         case HREQ_ENABLE:
6297                 dd_dev_info(dd, "8051 request: request 0x%x not supported\n",
6298                             type);
6299                 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6300                 break;
6301         case HREQ_CONFIG_DONE:
6302                 hreq_response(dd, HREQ_SUCCESS, 0);
6303                 break;
6304
6305         case HREQ_INTERFACE_TEST:
6306                 hreq_response(dd, HREQ_SUCCESS, data);
6307                 break;
6308         default:
6309                 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type);
6310                 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6311                 break;
6312         }
6313 }
6314
6315 static void write_global_credit(struct hfi1_devdata *dd,
6316                                 u8 vau, u16 total, u16 shared)
6317 {
6318         write_csr(dd, SEND_CM_GLOBAL_CREDIT,
6319                   ((u64)total <<
6320                    SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT) |
6321                   ((u64)shared <<
6322                    SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) |
6323                   ((u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT));
6324 }
6325
6326 /*
6327  * Set up initial VL15 credits of the remote.  Assumes the rest of
6328  * the CM credit registers are zero from a previous global or credit reset .
6329  */
6330 void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf)
6331 {
6332         /* leave shared count at zero for both global and VL15 */
6333         write_global_credit(dd, vau, vl15buf, 0);
6334
6335         write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6336                   << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6337 }
6338
6339 /*
6340  * Zero all credit details from the previous connection and
6341  * reset the CM manager's internal counters.
6342  */
6343 void reset_link_credits(struct hfi1_devdata *dd)
6344 {
6345         int i;
6346
6347         /* remove all previous VL credit limits */
6348         for (i = 0; i < TXE_NUM_DATA_VL; i++)
6349                 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
6350         write_csr(dd, SEND_CM_CREDIT_VL15, 0);
6351         write_global_credit(dd, 0, 0, 0);
6352         /* reset the CM block */
6353         pio_send_control(dd, PSC_CM_RESET);
6354 }
6355
6356 /* convert a vCU to a CU */
6357 static u32 vcu_to_cu(u8 vcu)
6358 {
6359         return 1 << vcu;
6360 }
6361
6362 /* convert a CU to a vCU */
6363 static u8 cu_to_vcu(u32 cu)
6364 {
6365         return ilog2(cu);
6366 }
6367
6368 /* convert a vAU to an AU */
6369 static u32 vau_to_au(u8 vau)
6370 {
6371         return 8 * (1 << vau);
6372 }
6373
6374 static void set_linkup_defaults(struct hfi1_pportdata *ppd)
6375 {
6376         ppd->sm_trap_qp = 0x0;
6377         ppd->sa_qp = 0x1;
6378 }
6379
6380 /*
6381  * Graceful LCB shutdown.  This leaves the LCB FIFOs in reset.
6382  */
6383 static void lcb_shutdown(struct hfi1_devdata *dd, int abort)
6384 {
6385         u64 reg;
6386
6387         /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6388         write_csr(dd, DC_LCB_CFG_RUN, 0);
6389         /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6390         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
6391                   1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT);
6392         /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6393         dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
6394         reg = read_csr(dd, DCC_CFG_RESET);
6395         write_csr(dd, DCC_CFG_RESET, reg |
6396                   (1ull << DCC_CFG_RESET_RESET_LCB_SHIFT) |
6397                   (1ull << DCC_CFG_RESET_RESET_RX_FPE_SHIFT));
6398         (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
6399         if (!abort) {
6400                 udelay(1);    /* must hold for the longer of 16cclks or 20ns */
6401                 write_csr(dd, DCC_CFG_RESET, reg);
6402                 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6403         }
6404 }
6405
6406 /*
6407  * This routine should be called after the link has been transitioned to
6408  * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6409  * reset).
6410  *
6411  * The expectation is that the caller of this routine would have taken
6412  * care of properly transitioning the link into the correct state.
6413  * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6414  *       before calling this function.
6415  */
6416 static void _dc_shutdown(struct hfi1_devdata *dd)
6417 {
6418         lockdep_assert_held(&dd->dc8051_lock);
6419
6420         if (dd->dc_shutdown)
6421                 return;
6422
6423         dd->dc_shutdown = 1;
6424         /* Shutdown the LCB */
6425         lcb_shutdown(dd, 1);
6426         /*
6427          * Going to OFFLINE would have causes the 8051 to put the
6428          * SerDes into reset already. Just need to shut down the 8051,
6429          * itself.
6430          */
6431         write_csr(dd, DC_DC8051_CFG_RST, 0x1);
6432 }
6433
6434 static void dc_shutdown(struct hfi1_devdata *dd)
6435 {
6436         mutex_lock(&dd->dc8051_lock);
6437         _dc_shutdown(dd);
6438         mutex_unlock(&dd->dc8051_lock);
6439 }
6440
6441 /*
6442  * Calling this after the DC has been brought out of reset should not
6443  * do any damage.
6444  * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6445  *       before calling this function.
6446  */
6447 static void _dc_start(struct hfi1_devdata *dd)
6448 {
6449         lockdep_assert_held(&dd->dc8051_lock);
6450
6451         if (!dd->dc_shutdown)
6452                 return;
6453
6454         /* Take the 8051 out of reset */
6455         write_csr(dd, DC_DC8051_CFG_RST, 0ull);
6456         /* Wait until 8051 is ready */
6457         if (wait_fm_ready(dd, TIMEOUT_8051_START))
6458                 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n",
6459                            __func__);
6460
6461         /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6462         write_csr(dd, DCC_CFG_RESET, 0x10);
6463         /* lcb_shutdown() with abort=1 does not restore these */
6464         write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6465         dd->dc_shutdown = 0;
6466 }
6467
6468 static void dc_start(struct hfi1_devdata *dd)
6469 {
6470         mutex_lock(&dd->dc8051_lock);
6471         _dc_start(dd);
6472         mutex_unlock(&dd->dc8051_lock);
6473 }
6474
6475 /*
6476  * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6477  */
6478 static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd)
6479 {
6480         u64 rx_radr, tx_radr;
6481         u32 version;
6482
6483         if (dd->icode != ICODE_FPGA_EMULATION)
6484                 return;
6485
6486         /*
6487          * These LCB defaults on emulator _s are good, nothing to do here:
6488          *      LCB_CFG_TX_FIFOS_RADR
6489          *      LCB_CFG_RX_FIFOS_RADR
6490          *      LCB_CFG_LN_DCLK
6491          *      LCB_CFG_IGNORE_LOST_RCLK
6492          */
6493         if (is_emulator_s(dd))
6494                 return;
6495         /* else this is _p */
6496
6497         version = emulator_rev(dd);
6498         if (!is_ax(dd))
6499                 version = 0x2d; /* all B0 use 0x2d or higher settings */
6500
6501         if (version <= 0x12) {
6502                 /* release 0x12 and below */
6503
6504                 /*
6505                  * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6506                  * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6507                  * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6508                  */
6509                 rx_radr =
6510                       0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6511                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6512                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6513                 /*
6514                  * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6515                  * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6516                  */
6517                 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6518         } else if (version <= 0x18) {
6519                 /* release 0x13 up to 0x18 */
6520                 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6521                 rx_radr =
6522                       0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6523                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6524                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6525                 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6526         } else if (version == 0x19) {
6527                 /* release 0x19 */
6528                 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6529                 rx_radr =
6530                       0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6531                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6532                     | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6533                 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6534         } else if (version == 0x1a) {
6535                 /* release 0x1a */
6536                 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6537                 rx_radr =
6538                       0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6539                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6540                     | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6541                 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6542                 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
6543         } else {
6544                 /* release 0x1b and higher */
6545                 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6546                 rx_radr =
6547                       0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6548                     | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6549                     | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6550                 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6551         }
6552
6553         write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
6554         /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6555         write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
6556                   DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
6557         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
6558 }
6559
6560 /*
6561  * Handle a SMA idle message
6562  *
6563  * This is a work-queue function outside of the interrupt.
6564  */
6565 void handle_sma_message(struct work_struct *work)
6566 {
6567         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6568                                                         sma_message_work);
6569         struct hfi1_devdata *dd = ppd->dd;
6570         u64 msg;
6571         int ret;
6572
6573         /*
6574          * msg is bytes 1-4 of the 40-bit idle message - the command code
6575          * is stripped off
6576          */
6577         ret = read_idle_sma(dd, &msg);
6578         if (ret)
6579                 return;
6580         dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg);
6581         /*
6582          * React to the SMA message.  Byte[1] (0 for us) is the command.
6583          */
6584         switch (msg & 0xff) {
6585         case SMA_IDLE_ARM:
6586                 /*
6587                  * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6588                  * State Transitions
6589                  *
6590                  * Only expected in INIT or ARMED, discard otherwise.
6591                  */
6592                 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED))
6593                         ppd->neighbor_normal = 1;
6594                 break;
6595         case SMA_IDLE_ACTIVE:
6596                 /*
6597                  * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6598                  * State Transitions
6599                  *
6600                  * Can activate the node.  Discard otherwise.
6601                  */
6602                 if (ppd->host_link_state == HLS_UP_ARMED &&
6603                     ppd->is_active_optimize_enabled) {
6604                         ppd->neighbor_normal = 1;
6605                         ret = set_link_state(ppd, HLS_UP_ACTIVE);
6606                         if (ret)
6607                                 dd_dev_err(
6608                                         dd,
6609                                         "%s: received Active SMA idle message, couldn't set link to Active\n",
6610                                         __func__);
6611                 }
6612                 break;
6613         default:
6614                 dd_dev_err(dd,
6615                            "%s: received unexpected SMA idle message 0x%llx\n",
6616                            __func__, msg);
6617                 break;
6618         }
6619 }
6620
6621 static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear)
6622 {
6623         u64 rcvctrl;
6624         unsigned long flags;
6625
6626         spin_lock_irqsave(&dd->rcvctrl_lock, flags);
6627         rcvctrl = read_csr(dd, RCV_CTRL);
6628         rcvctrl |= add;
6629         rcvctrl &= ~clear;
6630         write_csr(dd, RCV_CTRL, rcvctrl);
6631         spin_unlock_irqrestore(&dd->rcvctrl_lock, flags);
6632 }
6633
6634 static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add)
6635 {
6636         adjust_rcvctrl(dd, add, 0);
6637 }
6638
6639 static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear)
6640 {
6641         adjust_rcvctrl(dd, 0, clear);
6642 }
6643
6644 /*
6645  * Called from all interrupt handlers to start handling an SPC freeze.
6646  */
6647 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags)
6648 {
6649         struct hfi1_devdata *dd = ppd->dd;
6650         struct send_context *sc;
6651         int i;
6652
6653         if (flags & FREEZE_SELF)
6654                 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6655
6656         /* enter frozen mode */
6657         dd->flags |= HFI1_FROZEN;
6658
6659         /* notify all SDMA engines that they are going into a freeze */
6660         sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN));
6661
6662         /* do halt pre-handling on all enabled send contexts */
6663         for (i = 0; i < dd->num_send_contexts; i++) {
6664                 sc = dd->send_contexts[i].sc;
6665                 if (sc && (sc->flags & SCF_ENABLED))
6666                         sc_stop(sc, SCF_FROZEN | SCF_HALTED);
6667         }
6668
6669         /* Send context are frozen. Notify user space */
6670         hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT);
6671
6672         if (flags & FREEZE_ABORT) {
6673                 dd_dev_err(dd,
6674                            "Aborted freeze recovery. Please REBOOT system\n");
6675                 return;
6676         }
6677         /* queue non-interrupt handler */
6678         queue_work(ppd->hfi1_wq, &ppd->freeze_work);
6679 }
6680
6681 /*
6682  * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6683  * depending on the "freeze" parameter.
6684  *
6685  * No need to return an error if it times out, our only option
6686  * is to proceed anyway.
6687  */
6688 static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze)
6689 {
6690         unsigned long timeout;
6691         u64 reg;
6692
6693         timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT);
6694         while (1) {
6695                 reg = read_csr(dd, CCE_STATUS);
6696                 if (freeze) {
6697                         /* waiting until all indicators are set */
6698                         if ((reg & ALL_FROZE) == ALL_FROZE)
6699                                 return; /* all done */
6700                 } else {
6701                         /* waiting until all indicators are clear */
6702                         if ((reg & ALL_FROZE) == 0)
6703                                 return; /* all done */
6704                 }
6705
6706                 if (time_after(jiffies, timeout)) {
6707                         dd_dev_err(dd,
6708                                    "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing",
6709                                    freeze ? "" : "un", reg & ALL_FROZE,
6710                                    freeze ? ALL_FROZE : 0ull);
6711                         return;
6712                 }
6713                 usleep_range(80, 120);
6714         }
6715 }
6716
6717 /*
6718  * Do all freeze handling for the RXE block.
6719  */
6720 static void rxe_freeze(struct hfi1_devdata *dd)
6721 {
6722         int i;
6723
6724         /* disable port */
6725         clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6726
6727         /* disable all receive contexts */
6728         for (i = 0; i < dd->num_rcv_contexts; i++)
6729                 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, i);
6730 }
6731
6732 /*
6733  * Unfreeze handling for the RXE block - kernel contexts only.
6734  * This will also enable the port.  User contexts will do unfreeze
6735  * handling on a per-context basis as they call into the driver.
6736  *
6737  */
6738 static void rxe_kernel_unfreeze(struct hfi1_devdata *dd)
6739 {
6740         u32 rcvmask;
6741         int i;
6742
6743         /* enable all kernel contexts */
6744         for (i = 0; i < dd->num_rcv_contexts; i++) {
6745                 struct hfi1_ctxtdata *rcd = dd->rcd[i];
6746
6747                 /* Ensure all non-user contexts(including vnic) are enabled */
6748                 if (!rcd || !rcd->sc || (rcd->sc->type == SC_USER))
6749                         continue;
6750
6751                 rcvmask = HFI1_RCVCTRL_CTXT_ENB;
6752                 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6753                 rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ?
6754                         HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
6755                 hfi1_rcvctrl(dd, rcvmask, i);
6756         }
6757
6758         /* enable port */
6759         add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6760 }
6761
6762 /*
6763  * Non-interrupt SPC freeze handling.
6764  *
6765  * This is a work-queue function outside of the triggering interrupt.
6766  */
6767 void handle_freeze(struct work_struct *work)
6768 {
6769         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6770                                                                 freeze_work);
6771         struct hfi1_devdata *dd = ppd->dd;
6772
6773         /* wait for freeze indicators on all affected blocks */
6774         wait_for_freeze_status(dd, 1);
6775
6776         /* SPC is now frozen */
6777
6778         /* do send PIO freeze steps */
6779         pio_freeze(dd);
6780
6781         /* do send DMA freeze steps */
6782         sdma_freeze(dd);
6783
6784         /* do send egress freeze steps - nothing to do */
6785
6786         /* do receive freeze steps */
6787         rxe_freeze(dd);
6788
6789         /*
6790          * Unfreeze the hardware - clear the freeze, wait for each
6791          * block's frozen bit to clear, then clear the frozen flag.
6792          */
6793         write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6794         wait_for_freeze_status(dd, 0);
6795
6796         if (is_ax(dd)) {
6797                 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6798                 wait_for_freeze_status(dd, 1);
6799                 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6800                 wait_for_freeze_status(dd, 0);
6801         }
6802
6803         /* do send PIO unfreeze steps for kernel contexts */
6804         pio_kernel_unfreeze(dd);
6805
6806         /* do send DMA unfreeze steps */
6807         sdma_unfreeze(dd);
6808
6809         /* do send egress unfreeze steps - nothing to do */
6810
6811         /* do receive unfreeze steps for kernel contexts */
6812         rxe_kernel_unfreeze(dd);
6813
6814         /*
6815          * The unfreeze procedure touches global device registers when
6816          * it disables and re-enables RXE. Mark the device unfrozen
6817          * after all that is done so other parts of the driver waiting
6818          * for the device to unfreeze don't do things out of order.
6819          *
6820          * The above implies that the meaning of HFI1_FROZEN flag is
6821          * "Device has gone into freeze mode and freeze mode handling
6822          * is still in progress."
6823          *
6824          * The flag will be removed when freeze mode processing has
6825          * completed.
6826          */
6827         dd->flags &= ~HFI1_FROZEN;
6828         wake_up(&dd->event_queue);
6829
6830         /* no longer frozen */
6831 }
6832
6833 /*
6834  * Handle a link up interrupt from the 8051.
6835  *
6836  * This is a work-queue function outside of the interrupt.
6837  */
6838 void handle_link_up(struct work_struct *work)
6839 {
6840         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6841                                                   link_up_work);
6842         set_link_state(ppd, HLS_UP_INIT);
6843
6844         /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6845         read_ltp_rtt(ppd->dd);
6846         /*
6847          * OPA specifies that certain counters are cleared on a transition
6848          * to link up, so do that.
6849          */
6850         clear_linkup_counters(ppd->dd);
6851         /*
6852          * And (re)set link up default values.
6853          */
6854         set_linkup_defaults(ppd);
6855
6856         /* enforce link speed enabled */
6857         if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) {
6858                 /* oops - current speed is not enabled, bounce */
6859                 dd_dev_err(ppd->dd,
6860                            "Link speed active 0x%x is outside enabled 0x%x, downing link\n",
6861                            ppd->link_speed_active, ppd->link_speed_enabled);
6862                 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0,
6863                                      OPA_LINKDOWN_REASON_SPEED_POLICY);
6864                 set_link_state(ppd, HLS_DN_OFFLINE);
6865                 start_link(ppd);
6866         }
6867 }
6868
6869 /*
6870  * Several pieces of LNI information were cached for SMA in ppd.
6871  * Reset these on link down
6872  */
6873 static void reset_neighbor_info(struct hfi1_pportdata *ppd)
6874 {
6875         ppd->neighbor_guid = 0;
6876         ppd->neighbor_port_number = 0;
6877         ppd->neighbor_type = 0;
6878         ppd->neighbor_fm_security = 0;
6879 }
6880
6881 static const char * const link_down_reason_strs[] = {
6882         [OPA_LINKDOWN_REASON_NONE] = "None",
6883         [OPA_LINKDOWN_REASON_RCV_ERROR_0] = "Recive error 0",
6884         [OPA_LINKDOWN_REASON_BAD_PKT_LEN] = "Bad packet length",
6885         [OPA_LINKDOWN_REASON_PKT_TOO_LONG] = "Packet too long",
6886         [OPA_LINKDOWN_REASON_PKT_TOO_SHORT] = "Packet too short",
6887         [OPA_LINKDOWN_REASON_BAD_SLID] = "Bad SLID",
6888         [OPA_LINKDOWN_REASON_BAD_DLID] = "Bad DLID",
6889         [OPA_LINKDOWN_REASON_BAD_L2] = "Bad L2",
6890         [OPA_LINKDOWN_REASON_BAD_SC] = "Bad SC",
6891         [OPA_LINKDOWN_REASON_RCV_ERROR_8] = "Receive error 8",
6892         [OPA_LINKDOWN_REASON_BAD_MID_TAIL] = "Bad mid tail",
6893         [OPA_LINKDOWN_REASON_RCV_ERROR_10] = "Receive error 10",
6894         [OPA_LINKDOWN_REASON_PREEMPT_ERROR] = "Preempt error",
6895         [OPA_LINKDOWN_REASON_PREEMPT_VL15] = "Preempt vl15",
6896         [OPA_LINKDOWN_REASON_BAD_VL_MARKER] = "Bad VL marker",
6897         [OPA_LINKDOWN_REASON_RCV_ERROR_14] = "Receive error 14",
6898         [OPA_LINKDOWN_REASON_RCV_ERROR_15] = "Receive error 15",
6899         [OPA_LINKDOWN_REASON_BAD_HEAD_DIST] = "Bad head distance",
6900         [OPA_LINKDOWN_REASON_BAD_TAIL_DIST] = "Bad tail distance",
6901         [OPA_LINKDOWN_REASON_BAD_CTRL_DIST] = "Bad control distance",
6902         [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK] = "Bad credit ack",
6903         [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER] = "Unsupported VL marker",
6904         [OPA_LINKDOWN_REASON_BAD_PREEMPT] = "Bad preempt",
6905         [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT] = "Bad control flit",
6906         [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT] = "Exceed multicast limit",
6907         [OPA_LINKDOWN_REASON_RCV_ERROR_24] = "Receive error 24",
6908         [OPA_LINKDOWN_REASON_RCV_ERROR_25] = "Receive error 25",
6909         [OPA_LINKDOWN_REASON_RCV_ERROR_26] = "Receive error 26",
6910         [OPA_LINKDOWN_REASON_RCV_ERROR_27] = "Receive error 27",
6911         [OPA_LINKDOWN_REASON_RCV_ERROR_28] = "Receive error 28",
6912         [OPA_LINKDOWN_REASON_RCV_ERROR_29] = "Receive error 29",
6913         [OPA_LINKDOWN_REASON_RCV_ERROR_30] = "Receive error 30",
6914         [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN] =
6915                                         "Excessive buffer overrun",
6916         [OPA_LINKDOWN_REASON_UNKNOWN] = "Unknown",
6917         [OPA_LINKDOWN_REASON_REBOOT] = "Reboot",
6918         [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN] = "Neighbor unknown",
6919         [OPA_LINKDOWN_REASON_FM_BOUNCE] = "FM bounce",
6920         [OPA_LINKDOWN_REASON_SPEED_POLICY] = "Speed policy",
6921         [OPA_LINKDOWN_REASON_WIDTH_POLICY] = "Width policy",
6922         [OPA_LINKDOWN_REASON_DISCONNECTED] = "Disconnected",
6923         [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED] =
6924                                         "Local media not installed",
6925         [OPA_LINKDOWN_REASON_NOT_INSTALLED] = "Not installed",
6926         [OPA_LINKDOWN_REASON_CHASSIS_CONFIG] = "Chassis config",
6927         [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED] =
6928                                         "End to end not installed",
6929         [OPA_LINKDOWN_REASON_POWER_POLICY] = "Power policy",
6930         [OPA_LINKDOWN_REASON_LINKSPEED_POLICY] = "Link speed policy",
6931         [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY] = "Link width policy",
6932         [OPA_LINKDOWN_REASON_SWITCH_MGMT] = "Switch management",
6933         [OPA_LINKDOWN_REASON_SMA_DISABLED] = "SMA disabled",
6934         [OPA_LINKDOWN_REASON_TRANSIENT] = "Transient"
6935 };
6936
6937 /* return the neighbor link down reason string */
6938 static const char *link_down_reason_str(u8 reason)
6939 {
6940         const char *str = NULL;
6941
6942         if (reason < ARRAY_SIZE(link_down_reason_strs))
6943                 str = link_down_reason_strs[reason];
6944         if (!str)
6945                 str = "(invalid)";
6946
6947         return str;
6948 }
6949
6950 /*
6951  * Handle a link down interrupt from the 8051.
6952  *
6953  * This is a work-queue function outside of the interrupt.
6954  */
6955 void handle_link_down(struct work_struct *work)
6956 {
6957         u8 lcl_reason, neigh_reason = 0;
6958         u8 link_down_reason;
6959         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6960                                                   link_down_work);
6961         int was_up;
6962         static const char ldr_str[] = "Link down reason: ";
6963
6964         if ((ppd->host_link_state &
6965              (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) &&
6966              ppd->port_type == PORT_TYPE_FIXED)
6967                 ppd->offline_disabled_reason =
6968                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED);
6969
6970         /* Go offline first, then deal with reading/writing through 8051 */
6971         was_up = !!(ppd->host_link_state & HLS_UP);
6972         set_link_state(ppd, HLS_DN_OFFLINE);
6973
6974         if (was_up) {
6975                 lcl_reason = 0;
6976                 /* link down reason is only valid if the link was up */
6977                 read_link_down_reason(ppd->dd, &link_down_reason);
6978                 switch (link_down_reason) {
6979                 case LDR_LINK_TRANSFER_ACTIVE_LOW:
6980                         /* the link went down, no idle message reason */
6981                         dd_dev_info(ppd->dd, "%sUnexpected link down\n",
6982                                     ldr_str);
6983                         break;
6984                 case LDR_RECEIVED_LINKDOWN_IDLE_MSG:
6985                         /*
6986                          * The neighbor reason is only valid if an idle message
6987                          * was received for it.
6988                          */
6989                         read_planned_down_reason_code(ppd->dd, &neigh_reason);
6990                         dd_dev_info(ppd->dd,
6991                                     "%sNeighbor link down message %d, %s\n",
6992                                     ldr_str, neigh_reason,
6993                                     link_down_reason_str(neigh_reason));
6994                         break;
6995                 case LDR_RECEIVED_HOST_OFFLINE_REQ:
6996                         dd_dev_info(ppd->dd,
6997                                     "%sHost requested link to go offline\n",
6998                                     ldr_str);
6999                         break;
7000                 default:
7001                         dd_dev_info(ppd->dd, "%sUnknown reason 0x%x\n",
7002                                     ldr_str, link_down_reason);
7003                         break;
7004                 }
7005
7006                 /*
7007                  * If no reason, assume peer-initiated but missed
7008                  * LinkGoingDown idle flits.
7009                  */
7010                 if (neigh_reason == 0)
7011                         lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN;
7012         } else {
7013                 /* went down while polling or going up */
7014                 lcl_reason = OPA_LINKDOWN_REASON_TRANSIENT;
7015         }
7016
7017         set_link_down_reason(ppd, lcl_reason, neigh_reason, 0);
7018
7019         /* inform the SMA when the link transitions from up to down */
7020         if (was_up && ppd->local_link_down_reason.sma == 0 &&
7021             ppd->neigh_link_down_reason.sma == 0) {
7022                 ppd->local_link_down_reason.sma =
7023                                         ppd->local_link_down_reason.latest;
7024                 ppd->neigh_link_down_reason.sma =
7025                                         ppd->neigh_link_down_reason.latest;
7026         }
7027
7028         reset_neighbor_info(ppd);
7029
7030         /* disable the port */
7031         clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
7032
7033         /*
7034          * If there is no cable attached, turn the DC off. Otherwise,
7035          * start the link bring up.
7036          */
7037         if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd))
7038                 dc_shutdown(ppd->dd);
7039         else
7040                 start_link(ppd);
7041 }
7042
7043 void handle_link_bounce(struct work_struct *work)
7044 {
7045         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7046                                                         link_bounce_work);
7047
7048         /*
7049          * Only do something if the link is currently up.
7050          */
7051         if (ppd->host_link_state & HLS_UP) {
7052                 set_link_state(ppd, HLS_DN_OFFLINE);
7053                 start_link(ppd);
7054         } else {
7055                 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n",
7056                             __func__, link_state_name(ppd->host_link_state));
7057         }
7058 }
7059
7060 /*
7061  * Mask conversion: Capability exchange to Port LTP.  The capability
7062  * exchange has an implicit 16b CRC that is mandatory.
7063  */
7064 static int cap_to_port_ltp(int cap)
7065 {
7066         int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */
7067
7068         if (cap & CAP_CRC_14B)
7069                 port_ltp |= PORT_LTP_CRC_MODE_14;
7070         if (cap & CAP_CRC_48B)
7071                 port_ltp |= PORT_LTP_CRC_MODE_48;
7072         if (cap & CAP_CRC_12B_16B_PER_LANE)
7073                 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE;
7074
7075         return port_ltp;
7076 }
7077
7078 /*
7079  * Convert an OPA Port LTP mask to capability mask
7080  */
7081 int port_ltp_to_cap(int port_ltp)
7082 {
7083         int cap_mask = 0;
7084
7085         if (port_ltp & PORT_LTP_CRC_MODE_14)
7086                 cap_mask |= CAP_CRC_14B;
7087         if (port_ltp & PORT_LTP_CRC_MODE_48)
7088                 cap_mask |= CAP_CRC_48B;
7089         if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE)
7090                 cap_mask |= CAP_CRC_12B_16B_PER_LANE;
7091
7092         return cap_mask;
7093 }
7094
7095 /*
7096  * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7097  */
7098 static int lcb_to_port_ltp(int lcb_crc)
7099 {
7100         int port_ltp = 0;
7101
7102         if (lcb_crc == LCB_CRC_12B_16B_PER_LANE)
7103                 port_ltp = PORT_LTP_CRC_MODE_PER_LANE;
7104         else if (lcb_crc == LCB_CRC_48B)
7105                 port_ltp = PORT_LTP_CRC_MODE_48;
7106         else if (lcb_crc == LCB_CRC_14B)
7107                 port_ltp = PORT_LTP_CRC_MODE_14;
7108         else
7109                 port_ltp = PORT_LTP_CRC_MODE_16;
7110
7111         return port_ltp;
7112 }
7113
7114 /*
7115  * Our neighbor has indicated that we are allowed to act as a fabric
7116  * manager, so place the full management partition key in the second
7117  * (0-based) pkey array position (see OPAv1, section 20.2.2.6.8). Note
7118  * that we should already have the limited management partition key in
7119  * array element 1, and also that the port is not yet up when
7120  * add_full_mgmt_pkey() is invoked.
7121  */
7122 static void add_full_mgmt_pkey(struct hfi1_pportdata *ppd)
7123 {
7124         struct hfi1_devdata *dd = ppd->dd;
7125
7126         /* Sanity check - ppd->pkeys[2] should be 0, or already initialized */
7127         if (!((ppd->pkeys[2] == 0) || (ppd->pkeys[2] == FULL_MGMT_P_KEY)))
7128                 dd_dev_warn(dd, "%s pkey[2] already set to 0x%x, resetting it to 0x%x\n",
7129                             __func__, ppd->pkeys[2], FULL_MGMT_P_KEY);
7130         ppd->pkeys[2] = FULL_MGMT_P_KEY;
7131         (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
7132         hfi1_event_pkey_change(ppd->dd, ppd->port);
7133 }
7134
7135 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd)
7136 {
7137         if (ppd->pkeys[2] != 0) {
7138                 ppd->pkeys[2] = 0;
7139                 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
7140                 hfi1_event_pkey_change(ppd->dd, ppd->port);
7141         }
7142 }
7143
7144 /*
7145  * Convert the given link width to the OPA link width bitmask.
7146  */
7147 static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width)
7148 {
7149         switch (width) {
7150         case 0:
7151                 /*
7152                  * Simulator and quick linkup do not set the width.
7153                  * Just set it to 4x without complaint.
7154                  */
7155                 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup)
7156                         return OPA_LINK_WIDTH_4X;
7157                 return 0; /* no lanes up */
7158         case 1: return OPA_LINK_WIDTH_1X;
7159         case 2: return OPA_LINK_WIDTH_2X;
7160         case 3: return OPA_LINK_WIDTH_3X;
7161         default:
7162                 dd_dev_info(dd, "%s: invalid width %d, using 4\n",
7163                             __func__, width);
7164                 /* fall through */
7165         case 4: return OPA_LINK_WIDTH_4X;
7166         }
7167 }
7168
7169 /*
7170  * Do a population count on the bottom nibble.
7171  */
7172 static const u8 bit_counts[16] = {
7173         0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
7174 };
7175
7176 static inline u8 nibble_to_count(u8 nibble)
7177 {
7178         return bit_counts[nibble & 0xf];
7179 }
7180
7181 /*
7182  * Read the active lane information from the 8051 registers and return
7183  * their widths.
7184  *
7185  * Active lane information is found in these 8051 registers:
7186  *      enable_lane_tx
7187  *      enable_lane_rx
7188  */
7189 static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width,
7190                             u16 *rx_width)
7191 {
7192         u16 tx, rx;
7193         u8 enable_lane_rx;
7194         u8 enable_lane_tx;
7195         u8 tx_polarity_inversion;
7196         u8 rx_polarity_inversion;
7197         u8 max_rate;
7198
7199         /* read the active lanes */
7200         read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
7201                          &rx_polarity_inversion, &max_rate);
7202         read_local_lni(dd, &enable_lane_rx);
7203
7204         /* convert to counts */
7205         tx = nibble_to_count(enable_lane_tx);
7206         rx = nibble_to_count(enable_lane_rx);
7207
7208         /*
7209          * Set link_speed_active here, overriding what was set in
7210          * handle_verify_cap().  The ASIC 8051 firmware does not correctly
7211          * set the max_rate field in handle_verify_cap until v0.19.
7212          */
7213         if ((dd->icode == ICODE_RTL_SILICON) &&
7214             (dd->dc8051_ver < dc8051_ver(0, 19, 0))) {
7215                 /* max_rate: 0 = 12.5G, 1 = 25G */
7216                 switch (max_rate) {
7217                 case 0:
7218                         dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G;
7219                         break;
7220                 default:
7221                         dd_dev_err(dd,
7222                                    "%s: unexpected max rate %d, using 25Gb\n",
7223                                    __func__, (int)max_rate);
7224                         /* fall through */
7225                 case 1:
7226                         dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G;
7227                         break;
7228                 }
7229         }
7230
7231         dd_dev_info(dd,
7232                     "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n",
7233                     enable_lane_tx, tx, enable_lane_rx, rx);
7234         *tx_width = link_width_to_bits(dd, tx);
7235         *rx_width = link_width_to_bits(dd, rx);
7236 }
7237
7238 /*
7239  * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7240  * Valid after the end of VerifyCap and during LinkUp.  Does not change
7241  * after link up.  I.e. look elsewhere for downgrade information.
7242  *
7243  * Bits are:
7244  *      + bits [7:4] contain the number of active transmitters
7245  *      + bits [3:0] contain the number of active receivers
7246  * These are numbers 1 through 4 and can be different values if the
7247  * link is asymmetric.
7248  *
7249  * verify_cap_local_fm_link_width[0] retains its original value.
7250  */
7251 static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width,
7252                               u16 *rx_width)
7253 {
7254         u16 widths, tx, rx;
7255         u8 misc_bits, local_flags;
7256         u16 active_tx, active_rx;
7257
7258         read_vc_local_link_width(dd, &misc_bits, &local_flags, &widths);
7259         tx = widths >> 12;
7260         rx = (widths >> 8) & 0xf;
7261
7262         *tx_width = link_width_to_bits(dd, tx);
7263         *rx_width = link_width_to_bits(dd, rx);
7264
7265         /* print the active widths */
7266         get_link_widths(dd, &active_tx, &active_rx);
7267 }
7268
7269 /*
7270  * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7271  * hardware information when the link first comes up.
7272  *
7273  * The link width is not available until after VerifyCap.AllFramesReceived
7274  * (the trigger for handle_verify_cap), so this is outside that routine
7275  * and should be called when the 8051 signals linkup.
7276  */
7277 void get_linkup_link_widths(struct hfi1_pportdata *ppd)
7278 {
7279         u16 tx_width, rx_width;
7280
7281         /* get end-of-LNI link widths */
7282         get_linkup_widths(ppd->dd, &tx_width, &rx_width);
7283
7284         /* use tx_width as the link is supposed to be symmetric on link up */
7285         ppd->link_width_active = tx_width;
7286         /* link width downgrade active (LWD.A) starts out matching LW.A */
7287         ppd->link_width_downgrade_tx_active = ppd->link_width_active;
7288         ppd->link_width_downgrade_rx_active = ppd->link_width_active;
7289         /* per OPA spec, on link up LWD.E resets to LWD.S */
7290         ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported;
7291         /* cache the active egress rate (units {10^6 bits/sec]) */
7292         ppd->current_egress_rate = active_egress_rate(ppd);
7293 }
7294
7295 /*
7296  * Handle a verify capabilities interrupt from the 8051.
7297  *
7298  * This is a work-queue function outside of the interrupt.
7299  */
7300 void handle_verify_cap(struct work_struct *work)
7301 {
7302         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7303                                                                 link_vc_work);
7304         struct hfi1_devdata *dd = ppd->dd;
7305         u64 reg;
7306         u8 power_management;
7307         u8 continious;
7308         u8 vcu;
7309         u8 vau;
7310         u8 z;
7311         u16 vl15buf;
7312         u16 link_widths;
7313         u16 crc_mask;
7314         u16 crc_val;
7315         u16 device_id;
7316         u16 active_tx, active_rx;
7317         u8 partner_supported_crc;
7318         u8 remote_tx_rate;
7319         u8 device_rev;
7320
7321         set_link_state(ppd, HLS_VERIFY_CAP);
7322
7323         lcb_shutdown(dd, 0);
7324         adjust_lcb_for_fpga_serdes(dd);
7325
7326         read_vc_remote_phy(dd, &power_management, &continious);
7327         read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf,
7328                               &partner_supported_crc);
7329         read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths);
7330         read_remote_device_id(dd, &device_id, &device_rev);
7331         /*
7332          * And the 'MgmtAllowed' information, which is exchanged during
7333          * LNI, is also be available at this point.
7334          */
7335         read_mgmt_allowed(dd, &ppd->mgmt_allowed);
7336         /* print the active widths */
7337         get_link_widths(dd, &active_tx, &active_rx);
7338         dd_dev_info(dd,
7339                     "Peer PHY: power management 0x%x, continuous updates 0x%x\n",
7340                     (int)power_management, (int)continious);
7341         dd_dev_info(dd,
7342                     "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n",
7343                     (int)vau, (int)z, (int)vcu, (int)vl15buf,
7344                     (int)partner_supported_crc);
7345         dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n",
7346                     (u32)remote_tx_rate, (u32)link_widths);
7347         dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n",
7348                     (u32)device_id, (u32)device_rev);
7349         /*
7350          * The peer vAU value just read is the peer receiver value.  HFI does
7351          * not support a transmit vAU of 0 (AU == 8).  We advertised that
7352          * with Z=1 in the fabric capabilities sent to the peer.  The peer
7353          * will see our Z=1, and, if it advertised a vAU of 0, will move its
7354          * receive to vAU of 1 (AU == 16).  Do the same here.  We do not care
7355          * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7356          * subject to the Z value exception.
7357          */
7358         if (vau == 0)
7359                 vau = 1;
7360         set_up_vl15(dd, vau, vl15buf);
7361
7362         /* set up the LCB CRC mode */
7363         crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc;
7364
7365         /* order is important: use the lowest bit in common */
7366         if (crc_mask & CAP_CRC_14B)
7367                 crc_val = LCB_CRC_14B;
7368         else if (crc_mask & CAP_CRC_48B)
7369                 crc_val = LCB_CRC_48B;
7370         else if (crc_mask & CAP_CRC_12B_16B_PER_LANE)
7371                 crc_val = LCB_CRC_12B_16B_PER_LANE;
7372         else
7373                 crc_val = LCB_CRC_16B;
7374
7375         dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val);
7376         write_csr(dd, DC_LCB_CFG_CRC_MODE,
7377                   (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT);
7378
7379         /* set (14b only) or clear sideband credit */
7380         reg = read_csr(dd, SEND_CM_CTRL);
7381         if (crc_val == LCB_CRC_14B && crc_14b_sideband) {
7382                 write_csr(dd, SEND_CM_CTRL,
7383                           reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
7384         } else {
7385                 write_csr(dd, SEND_CM_CTRL,
7386                           reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
7387         }
7388
7389         ppd->link_speed_active = 0;     /* invalid value */
7390         if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) {
7391                 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7392                 switch (remote_tx_rate) {
7393                 case 0:
7394                         ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7395                         break;
7396                 case 1:
7397                         ppd->link_speed_active = OPA_LINK_SPEED_25G;
7398                         break;
7399                 }
7400         } else {
7401                 /* actual rate is highest bit of the ANDed rates */
7402                 u8 rate = remote_tx_rate & ppd->local_tx_rate;
7403
7404                 if (rate & 2)
7405                         ppd->link_speed_active = OPA_LINK_SPEED_25G;
7406                 else if (rate & 1)
7407                         ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7408         }
7409         if (ppd->link_speed_active == 0) {
7410                 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n",
7411                            __func__, (int)remote_tx_rate);
7412                 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7413         }
7414
7415         /*
7416          * Cache the values of the supported, enabled, and active
7417          * LTP CRC modes to return in 'portinfo' queries. But the bit
7418          * flags that are returned in the portinfo query differ from
7419          * what's in the link_crc_mask, crc_sizes, and crc_val
7420          * variables. Convert these here.
7421          */
7422         ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
7423                 /* supported crc modes */
7424         ppd->port_ltp_crc_mode |=
7425                 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4;
7426                 /* enabled crc modes */
7427         ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val);
7428                 /* active crc mode */
7429
7430         /* set up the remote credit return table */
7431         assign_remote_cm_au_table(dd, vcu);
7432
7433         /*
7434          * The LCB is reset on entry to handle_verify_cap(), so this must
7435          * be applied on every link up.
7436          *
7437          * Adjust LCB error kill enable to kill the link if
7438          * these RBUF errors are seen:
7439          *      REPLAY_BUF_MBE_SMASK
7440          *      FLIT_INPUT_BUF_MBE_SMASK
7441          */
7442         if (is_ax(dd)) {                        /* fixed in B0 */
7443                 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
7444                 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7445                         | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK;
7446                 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
7447         }
7448
7449         /* pull LCB fifos out of reset - all fifo clocks must be stable */
7450         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
7451
7452         /* give 8051 access to the LCB CSRs */
7453         write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7454         set_8051_lcb_access(dd);
7455
7456         if (ppd->mgmt_allowed)
7457                 add_full_mgmt_pkey(ppd);
7458
7459         /* tell the 8051 to go to LinkUp */
7460         set_link_state(ppd, HLS_GOING_UP);
7461 }
7462
7463 /*
7464  * Apply the link width downgrade enabled policy against the current active
7465  * link widths.
7466  *
7467  * Called when the enabled policy changes or the active link widths change.
7468  */
7469 void apply_link_downgrade_policy(struct hfi1_pportdata *ppd, int refresh_widths)
7470 {
7471         int do_bounce = 0;
7472         int tries;
7473         u16 lwde;
7474         u16 tx, rx;
7475
7476         /* use the hls lock to avoid a race with actual link up */
7477         tries = 0;
7478 retry:
7479         mutex_lock(&ppd->hls_lock);
7480         /* only apply if the link is up */
7481         if (ppd->host_link_state & HLS_DOWN) {
7482                 /* still going up..wait and retry */
7483                 if (ppd->host_link_state & HLS_GOING_UP) {
7484                         if (++tries < 1000) {
7485                                 mutex_unlock(&ppd->hls_lock);
7486                                 usleep_range(100, 120); /* arbitrary */
7487                                 goto retry;
7488                         }
7489                         dd_dev_err(ppd->dd,
7490                                    "%s: giving up waiting for link state change\n",
7491                                    __func__);
7492                 }
7493                 goto done;
7494         }
7495
7496         lwde = ppd->link_width_downgrade_enabled;
7497
7498         if (refresh_widths) {
7499                 get_link_widths(ppd->dd, &tx, &rx);
7500                 ppd->link_width_downgrade_tx_active = tx;
7501                 ppd->link_width_downgrade_rx_active = rx;
7502         }
7503
7504         if (ppd->link_width_downgrade_tx_active == 0 ||
7505             ppd->link_width_downgrade_rx_active == 0) {
7506                 /* the 8051 reported a dead link as a downgrade */
7507                 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n");
7508         } else if (lwde == 0) {
7509                 /* downgrade is disabled */
7510
7511                 /* bounce if not at starting active width */
7512                 if ((ppd->link_width_active !=
7513                      ppd->link_width_downgrade_tx_active) ||
7514                     (ppd->link_width_active !=
7515                      ppd->link_width_downgrade_rx_active)) {
7516                         dd_dev_err(ppd->dd,
7517                                    "Link downgrade is disabled and link has downgraded, downing link\n");
7518                         dd_dev_err(ppd->dd,
7519                                    "  original 0x%x, tx active 0x%x, rx active 0x%x\n",
7520                                    ppd->link_width_active,
7521                                    ppd->link_width_downgrade_tx_active,
7522                                    ppd->link_width_downgrade_rx_active);
7523                         do_bounce = 1;
7524                 }
7525         } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 ||
7526                    (lwde & ppd->link_width_downgrade_rx_active) == 0) {
7527                 /* Tx or Rx is outside the enabled policy */
7528                 dd_dev_err(ppd->dd,
7529                            "Link is outside of downgrade allowed, downing link\n");
7530                 dd_dev_err(ppd->dd,
7531                            "  enabled 0x%x, tx active 0x%x, rx active 0x%x\n",
7532                            lwde, ppd->link_width_downgrade_tx_active,
7533                            ppd->link_width_downgrade_rx_active);
7534                 do_bounce = 1;
7535         }
7536
7537 done:
7538         mutex_unlock(&ppd->hls_lock);
7539
7540         if (do_bounce) {
7541                 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0,
7542                                      OPA_LINKDOWN_REASON_WIDTH_POLICY);
7543                 set_link_state(ppd, HLS_DN_OFFLINE);
7544                 start_link(ppd);
7545         }
7546 }
7547
7548 /*
7549  * Handle a link downgrade interrupt from the 8051.
7550  *
7551  * This is a work-queue function outside of the interrupt.
7552  */
7553 void handle_link_downgrade(struct work_struct *work)
7554 {
7555         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7556                                                         link_downgrade_work);
7557
7558         dd_dev_info(ppd->dd, "8051: Link width downgrade\n");
7559         apply_link_downgrade_policy(ppd, 1);
7560 }
7561
7562 static char *dcc_err_string(char *buf, int buf_len, u64 flags)
7563 {
7564         return flag_string(buf, buf_len, flags, dcc_err_flags,
7565                 ARRAY_SIZE(dcc_err_flags));
7566 }
7567
7568 static char *lcb_err_string(char *buf, int buf_len, u64 flags)
7569 {
7570         return flag_string(buf, buf_len, flags, lcb_err_flags,
7571                 ARRAY_SIZE(lcb_err_flags));
7572 }
7573
7574 static char *dc8051_err_string(char *buf, int buf_len, u64 flags)
7575 {
7576         return flag_string(buf, buf_len, flags, dc8051_err_flags,
7577                 ARRAY_SIZE(dc8051_err_flags));
7578 }
7579
7580 static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags)
7581 {
7582         return flag_string(buf, buf_len, flags, dc8051_info_err_flags,
7583                 ARRAY_SIZE(dc8051_info_err_flags));
7584 }
7585
7586 static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags)
7587 {
7588         return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags,
7589                 ARRAY_SIZE(dc8051_info_host_msg_flags));
7590 }
7591
7592 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg)
7593 {
7594         struct hfi1_pportdata *ppd = dd->pport;
7595         u64 info, err, host_msg;
7596         int queue_link_down = 0;
7597         char buf[96];
7598
7599         /* look at the flags */
7600         if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) {
7601                 /* 8051 information set by firmware */
7602                 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7603                 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
7604                 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT)
7605                         & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK;
7606                 host_msg = (info >>
7607                         DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7608                         & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK;
7609
7610                 /*
7611                  * Handle error flags.
7612                  */
7613                 if (err & FAILED_LNI) {
7614                         /*
7615                          * LNI error indications are cleared by the 8051
7616                          * only when starting polling.  Only pay attention
7617                          * to them when in the states that occur during
7618                          * LNI.
7619                          */
7620                         if (ppd->host_link_state
7621                             & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
7622                                 queue_link_down = 1;
7623                                 dd_dev_info(dd, "Link error: %s\n",
7624                                             dc8051_info_err_string(buf,
7625                                                                    sizeof(buf),
7626                                                                    err &
7627                                                                    FAILED_LNI));
7628                         }
7629                         err &= ~(u64)FAILED_LNI;
7630                 }
7631                 /* unknown frames can happen durning LNI, just count */
7632                 if (err & UNKNOWN_FRAME) {
7633                         ppd->unknown_frame_count++;
7634                         err &= ~(u64)UNKNOWN_FRAME;
7635                 }
7636                 if (err) {
7637                         /* report remaining errors, but do not do anything */
7638                         dd_dev_err(dd, "8051 info error: %s\n",
7639                                    dc8051_info_err_string(buf, sizeof(buf),
7640                                                           err));
7641                 }
7642
7643                 /*
7644                  * Handle host message flags.
7645                  */
7646                 if (host_msg & HOST_REQ_DONE) {
7647                         /*
7648                          * Presently, the driver does a busy wait for
7649                          * host requests to complete.  This is only an
7650                          * informational message.
7651                          * NOTE: The 8051 clears the host message
7652                          * information *on the next 8051 command*.
7653                          * Therefore, when linkup is achieved,
7654                          * this flag will still be set.
7655                          */
7656                         host_msg &= ~(u64)HOST_REQ_DONE;
7657                 }
7658                 if (host_msg & BC_SMA_MSG) {
7659                         queue_work(ppd->hfi1_wq, &ppd->sma_message_work);
7660                         host_msg &= ~(u64)BC_SMA_MSG;
7661                 }
7662                 if (host_msg & LINKUP_ACHIEVED) {
7663                         dd_dev_info(dd, "8051: Link up\n");
7664                         queue_work(ppd->hfi1_wq, &ppd->link_up_work);
7665                         host_msg &= ~(u64)LINKUP_ACHIEVED;
7666                 }
7667                 if (host_msg & EXT_DEVICE_CFG_REQ) {
7668                         handle_8051_request(ppd);
7669                         host_msg &= ~(u64)EXT_DEVICE_CFG_REQ;
7670                 }
7671                 if (host_msg & VERIFY_CAP_FRAME) {
7672                         queue_work(ppd->hfi1_wq, &ppd->link_vc_work);
7673                         host_msg &= ~(u64)VERIFY_CAP_FRAME;
7674                 }
7675                 if (host_msg & LINK_GOING_DOWN) {
7676                         const char *extra = "";
7677                         /* no downgrade action needed if going down */
7678                         if (host_msg & LINK_WIDTH_DOWNGRADED) {
7679                                 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7680                                 extra = " (ignoring downgrade)";
7681                         }
7682                         dd_dev_info(dd, "8051: Link down%s\n", extra);
7683                         queue_link_down = 1;
7684                         host_msg &= ~(u64)LINK_GOING_DOWN;
7685                 }
7686                 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7687                         queue_work(ppd->hfi1_wq, &ppd->link_downgrade_work);
7688                         host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7689                 }
7690                 if (host_msg) {
7691                         /* report remaining messages, but do not do anything */
7692                         dd_dev_info(dd, "8051 info host message: %s\n",
7693                                     dc8051_info_host_msg_string(buf,
7694                                                                 sizeof(buf),
7695                                                                 host_msg));
7696                 }
7697
7698                 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK;
7699         }
7700         if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) {
7701                 /*
7702                  * Lost the 8051 heartbeat.  If this happens, we
7703                  * receive constant interrupts about it.  Disable
7704                  * the interrupt after the first.
7705                  */
7706                 dd_dev_err(dd, "Lost 8051 heartbeat\n");
7707                 write_csr(dd, DC_DC8051_ERR_EN,
7708                           read_csr(dd, DC_DC8051_ERR_EN) &
7709                           ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK);
7710
7711                 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK;
7712         }
7713         if (reg) {
7714                 /* report the error, but do not do anything */
7715                 dd_dev_err(dd, "8051 error: %s\n",
7716                            dc8051_err_string(buf, sizeof(buf), reg));
7717         }
7718
7719         if (queue_link_down) {
7720                 /*
7721                  * if the link is already going down or disabled, do not
7722                  * queue another
7723                  */
7724                 if ((ppd->host_link_state &
7725                     (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) ||
7726                     ppd->link_enabled == 0) {
7727                         dd_dev_info(dd, "%s: not queuing link down\n",
7728                                     __func__);
7729                 } else {
7730                         queue_work(ppd->hfi1_wq, &ppd->link_down_work);
7731                 }
7732         }
7733 }
7734
7735 static const char * const fm_config_txt[] = {
7736 [0] =
7737         "BadHeadDist: Distance violation between two head flits",
7738 [1] =
7739         "BadTailDist: Distance violation between two tail flits",
7740 [2] =
7741         "BadCtrlDist: Distance violation between two credit control flits",
7742 [3] =
7743         "BadCrdAck: Credits return for unsupported VL",
7744 [4] =
7745         "UnsupportedVLMarker: Received VL Marker",
7746 [5] =
7747         "BadPreempt: Exceeded the preemption nesting level",
7748 [6] =
7749         "BadControlFlit: Received unsupported control flit",
7750 /* no 7 */
7751 [8] =
7752         "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL",
7753 };
7754
7755 static const char * const port_rcv_txt[] = {
7756 [1] =
7757         "BadPktLen: Illegal PktLen",
7758 [2] =
7759         "PktLenTooLong: Packet longer than PktLen",
7760 [3] =
7761         "PktLenTooShort: Packet shorter than PktLen",
7762 [4] =
7763         "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7764 [5] =
7765         "BadDLID: Illegal DLID (0, doesn't match HFI)",
7766 [6] =
7767         "BadL2: Illegal L2 opcode",
7768 [7] =
7769         "BadSC: Unsupported SC",
7770 [9] =
7771         "BadRC: Illegal RC",
7772 [11] =
7773         "PreemptError: Preempting with same VL",
7774 [12] =
7775         "PreemptVL15: Preempting a VL15 packet",
7776 };
7777
7778 #define OPA_LDR_FMCONFIG_OFFSET 16
7779 #define OPA_LDR_PORTRCV_OFFSET 0
7780 static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7781 {
7782         u64 info, hdr0, hdr1;
7783         const char *extra;
7784         char buf[96];
7785         struct hfi1_pportdata *ppd = dd->pport;
7786         u8 lcl_reason = 0;
7787         int do_bounce = 0;
7788
7789         if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) {
7790                 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) {
7791                         info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
7792                         dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK;
7793                         /* set status bit */
7794                         dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK;
7795                 }
7796                 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK;
7797         }
7798
7799         if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) {
7800                 struct hfi1_pportdata *ppd = dd->pport;
7801                 /* this counter saturates at (2^32) - 1 */
7802                 if (ppd->link_downed < (u32)UINT_MAX)
7803                         ppd->link_downed++;
7804                 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK;
7805         }
7806
7807         if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) {
7808                 u8 reason_valid = 1;
7809
7810                 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
7811                 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) {
7812                         dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK;
7813                         /* set status bit */
7814                         dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK;
7815                 }
7816                 switch (info) {
7817                 case 0:
7818                 case 1:
7819                 case 2:
7820                 case 3:
7821                 case 4:
7822                 case 5:
7823                 case 6:
7824                         extra = fm_config_txt[info];
7825                         break;
7826                 case 8:
7827                         extra = fm_config_txt[info];
7828                         if (ppd->port_error_action &
7829                             OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
7830                                 do_bounce = 1;
7831                                 /*
7832                                  * lcl_reason cannot be derived from info
7833                                  * for this error
7834                                  */
7835                                 lcl_reason =
7836                                   OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
7837                         }
7838                         break;
7839                 default:
7840                         reason_valid = 0;
7841                         snprintf(buf, sizeof(buf), "reserved%lld", info);
7842                         extra = buf;
7843                         break;
7844                 }
7845
7846                 if (reason_valid && !do_bounce) {
7847                         do_bounce = ppd->port_error_action &
7848                                         (1 << (OPA_LDR_FMCONFIG_OFFSET + info));
7849                         lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST;
7850                 }
7851
7852                 /* just report this */
7853                 dd_dev_info_ratelimited(dd, "DCC Error: fmconfig error: %s\n",
7854                                         extra);
7855                 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK;
7856         }
7857
7858         if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) {
7859                 u8 reason_valid = 1;
7860
7861                 info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
7862                 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
7863                 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
7864                 if (!(dd->err_info_rcvport.status_and_code &
7865                       OPA_EI_STATUS_SMASK)) {
7866                         dd->err_info_rcvport.status_and_code =
7867                                 info & OPA_EI_CODE_SMASK;
7868                         /* set status bit */
7869                         dd->err_info_rcvport.status_and_code |=
7870                                 OPA_EI_STATUS_SMASK;
7871                         /*
7872                          * save first 2 flits in the packet that caused
7873                          * the error
7874                          */
7875                         dd->err_info_rcvport.packet_flit1 = hdr0;
7876                         dd->err_info_rcvport.packet_flit2 = hdr1;
7877                 }
7878                 switch (info) {
7879                 case 1:
7880                 case 2:
7881                 case 3:
7882                 case 4:
7883                 case 5:
7884                 case 6:
7885                 case 7:
7886                 case 9:
7887                 case 11:
7888                 case 12:
7889                         extra = port_rcv_txt[info];
7890                         break;
7891                 default:
7892                         reason_valid = 0;
7893                         snprintf(buf, sizeof(buf), "reserved%lld", info);
7894                         extra = buf;
7895                         break;
7896                 }
7897
7898                 if (reason_valid && !do_bounce) {
7899                         do_bounce = ppd->port_error_action &
7900                                         (1 << (OPA_LDR_PORTRCV_OFFSET + info));
7901                         lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0;
7902                 }
7903
7904                 /* just report this */
7905                 dd_dev_info_ratelimited(dd, "DCC Error: PortRcv error: %s\n"
7906                                         "               hdr0 0x%llx, hdr1 0x%llx\n",
7907                                         extra, hdr0, hdr1);
7908
7909                 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK;
7910         }
7911
7912         if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) {
7913                 /* informative only */
7914                 dd_dev_info_ratelimited(dd, "8051 access to LCB blocked\n");
7915                 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK;
7916         }
7917         if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) {
7918                 /* informative only */
7919                 dd_dev_info_ratelimited(dd, "host access to LCB blocked\n");
7920                 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK;
7921         }
7922
7923         if (unlikely(hfi1_dbg_fault_suppress_err(&dd->verbs_dev)))
7924                 reg &= ~DCC_ERR_FLG_LATE_EBP_ERR_SMASK;
7925
7926         /* report any remaining errors */
7927         if (reg)
7928                 dd_dev_info_ratelimited(dd, "DCC Error: %s\n",
7929                                         dcc_err_string(buf, sizeof(buf), reg));
7930
7931         if (lcl_reason == 0)
7932                 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN;
7933
7934         if (do_bounce) {
7935                 dd_dev_info_ratelimited(dd, "%s: PortErrorAction bounce\n",
7936                                         __func__);
7937                 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason);
7938                 queue_work(ppd->hfi1_wq, &ppd->link_bounce_work);
7939         }
7940 }
7941
7942 static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7943 {
7944         char buf[96];
7945
7946         dd_dev_info(dd, "LCB Error: %s\n",
7947                     lcb_err_string(buf, sizeof(buf), reg));
7948 }
7949
7950 /*
7951  * CCE block DC interrupt.  Source is < 8.
7952  */
7953 static void is_dc_int(struct hfi1_devdata *dd, unsigned int source)
7954 {
7955         const struct err_reg_info *eri = &dc_errs[source];
7956
7957         if (eri->handler) {
7958                 interrupt_clear_down(dd, 0, eri);
7959         } else if (source == 3 /* dc_lbm_int */) {
7960                 /*
7961                  * This indicates that a parity error has occurred on the
7962                  * address/control lines presented to the LBM.  The error
7963                  * is a single pulse, there is no associated error flag,
7964                  * and it is non-maskable.  This is because if a parity
7965                  * error occurs on the request the request is dropped.
7966                  * This should never occur, but it is nice to know if it
7967                  * ever does.
7968                  */
7969                 dd_dev_err(dd, "Parity error in DC LBM block\n");
7970         } else {
7971                 dd_dev_err(dd, "Invalid DC interrupt %u\n", source);
7972         }
7973 }
7974
7975 /*
7976  * TX block send credit interrupt.  Source is < 160.
7977  */
7978 static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source)
7979 {
7980         sc_group_release_update(dd, source);
7981 }
7982
7983 /*
7984  * TX block SDMA interrupt.  Source is < 48.
7985  *
7986  * SDMA interrupts are grouped by type:
7987  *
7988  *       0 -  N-1 = SDma
7989  *       N - 2N-1 = SDmaProgress
7990  *      2N - 3N-1 = SDmaIdle
7991  */
7992 static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source)
7993 {
7994         /* what interrupt */
7995         unsigned int what  = source / TXE_NUM_SDMA_ENGINES;
7996         /* which engine */
7997         unsigned int which = source % TXE_NUM_SDMA_ENGINES;
7998
7999 #ifdef CONFIG_SDMA_VERBOSITY
8000         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which,
8001                    slashstrip(__FILE__), __LINE__, __func__);
8002         sdma_dumpstate(&dd->per_sdma[which]);
8003 #endif
8004
8005         if (likely(what < 3 && which < dd->num_sdma)) {
8006                 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source);
8007         } else {
8008                 /* should not happen */
8009                 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source);
8010         }
8011 }
8012
8013 /*
8014  * RX block receive available interrupt.  Source is < 160.
8015  */
8016 static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source)
8017 {
8018         struct hfi1_ctxtdata *rcd;
8019         char *err_detail;
8020
8021         if (likely(source < dd->num_rcv_contexts)) {
8022                 rcd = dd->rcd[source];
8023                 if (rcd) {
8024                         /* Check for non-user contexts, including vnic */
8025                         if ((source < dd->first_dyn_alloc_ctxt) ||
8026                             (rcd->sc && (rcd->sc->type == SC_KERNEL)))
8027                                 rcd->do_interrupt(rcd, 0);
8028                         else
8029                                 handle_user_interrupt(rcd);
8030                         return; /* OK */
8031                 }
8032                 /* received an interrupt, but no rcd */
8033                 err_detail = "dataless";
8034         } else {
8035                 /* received an interrupt, but are not using that context */
8036                 err_detail = "out of range";
8037         }
8038         dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n",
8039                    err_detail, source);
8040 }
8041
8042 /*
8043  * RX block receive urgent interrupt.  Source is < 160.
8044  */
8045 static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source)
8046 {
8047         struct hfi1_ctxtdata *rcd;
8048         char *err_detail;
8049
8050         if (likely(source < dd->num_rcv_contexts)) {
8051                 rcd = dd->rcd[source];
8052                 if (rcd) {
8053                         /* only pay attention to user urgent interrupts */
8054                         if ((source >= dd->first_dyn_alloc_ctxt) &&
8055                             (!rcd->sc || (rcd->sc->type == SC_USER)))
8056                                 handle_user_interrupt(rcd);
8057                         return; /* OK */
8058                 }
8059                 /* received an interrupt, but no rcd */
8060                 err_detail = "dataless";
8061         } else {
8062                 /* received an interrupt, but are not using that context */
8063                 err_detail = "out of range";
8064         }
8065         dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n",
8066                    err_detail, source);
8067 }
8068
8069 /*
8070  * Reserved range interrupt.  Should not be called in normal operation.
8071  */
8072 static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source)
8073 {
8074         char name[64];
8075
8076         dd_dev_err(dd, "unexpected %s interrupt\n",
8077                    is_reserved_name(name, sizeof(name), source));
8078 }
8079
8080 static const struct is_table is_table[] = {
8081 /*
8082  * start                 end
8083  *                              name func               interrupt func
8084  */
8085 { IS_GENERAL_ERR_START,  IS_GENERAL_ERR_END,
8086                                 is_misc_err_name,       is_misc_err_int },
8087 { IS_SDMAENG_ERR_START,  IS_SDMAENG_ERR_END,
8088                                 is_sdma_eng_err_name,   is_sdma_eng_err_int },
8089 { IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END,
8090                                 is_sendctxt_err_name,   is_sendctxt_err_int },
8091 { IS_SDMA_START,             IS_SDMA_END,
8092                                 is_sdma_eng_name,       is_sdma_eng_int },
8093 { IS_VARIOUS_START,          IS_VARIOUS_END,
8094                                 is_various_name,        is_various_int },
8095 { IS_DC_START,       IS_DC_END,
8096                                 is_dc_name,             is_dc_int },
8097 { IS_RCVAVAIL_START,     IS_RCVAVAIL_END,
8098                                 is_rcv_avail_name,      is_rcv_avail_int },
8099 { IS_RCVURGENT_START,    IS_RCVURGENT_END,
8100                                 is_rcv_urgent_name,     is_rcv_urgent_int },
8101 { IS_SENDCREDIT_START,   IS_SENDCREDIT_END,
8102                                 is_send_credit_name,    is_send_credit_int},
8103 { IS_RESERVED_START,     IS_RESERVED_END,
8104                                 is_reserved_name,       is_reserved_int},
8105 };
8106
8107 /*
8108  * Interrupt source interrupt - called when the given source has an interrupt.
8109  * Source is a bit index into an array of 64-bit integers.
8110  */
8111 static void is_interrupt(struct hfi1_devdata *dd, unsigned int source)
8112 {
8113         const struct is_table *entry;
8114
8115         /* avoids a double compare by walking the table in-order */
8116         for (entry = &is_table[0]; entry->is_name; entry++) {
8117                 if (source < entry->end) {
8118                         trace_hfi1_interrupt(dd, entry, source);
8119                         entry->is_int(dd, source - entry->start);
8120                         return;
8121                 }
8122         }
8123         /* fell off the end */
8124         dd_dev_err(dd, "invalid interrupt source %u\n", source);
8125 }
8126
8127 /*
8128  * General interrupt handler.  This is able to correctly handle
8129  * all interrupts in case INTx is used.
8130  */
8131 static irqreturn_t general_interrupt(int irq, void *data)
8132 {
8133         struct hfi1_devdata *dd = data;
8134         u64 regs[CCE_NUM_INT_CSRS];
8135         u32 bit;
8136         int i;
8137
8138         this_cpu_inc(*dd->int_counter);
8139
8140         /* phase 1: scan and clear all handled interrupts */
8141         for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
8142                 if (dd->gi_mask[i] == 0) {
8143                         regs[i] = 0;    /* used later */
8144                         continue;
8145                 }
8146                 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
8147                                 dd->gi_mask[i];
8148                 /* only clear if anything is set */
8149                 if (regs[i])
8150                         write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
8151         }
8152
8153         /* phase 2: call the appropriate handler */
8154         for_each_set_bit(bit, (unsigned long *)&regs[0],
8155                          CCE_NUM_INT_CSRS * 64) {
8156                 is_interrupt(dd, bit);
8157         }
8158
8159         return IRQ_HANDLED;
8160 }
8161
8162 static irqreturn_t sdma_interrupt(int irq, void *data)
8163 {
8164         struct sdma_engine *sde = data;
8165         struct hfi1_devdata *dd = sde->dd;
8166         u64 status;
8167
8168 #ifdef CONFIG_SDMA_VERBOSITY
8169         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
8170                    slashstrip(__FILE__), __LINE__, __func__);
8171         sdma_dumpstate(sde);
8172 #endif
8173
8174         this_cpu_inc(*dd->int_counter);
8175
8176         /* This read_csr is really bad in the hot path */
8177         status = read_csr(dd,
8178                           CCE_INT_STATUS + (8 * (IS_SDMA_START / 64)))
8179                           & sde->imask;
8180         if (likely(status)) {
8181                 /* clear the interrupt(s) */
8182                 write_csr(dd,
8183                           CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)),
8184                           status);
8185
8186                 /* handle the interrupt(s) */
8187                 sdma_engine_interrupt(sde, status);
8188         } else {
8189                 dd_dev_err(dd, "SDMA engine %u interrupt, but no status bits set\n",
8190                            sde->this_idx);
8191         }
8192         return IRQ_HANDLED;
8193 }
8194
8195 /*
8196  * Clear the receive interrupt.  Use a read of the interrupt clear CSR
8197  * to insure that the write completed.  This does NOT guarantee that
8198  * queued DMA writes to memory from the chip are pushed.
8199  */
8200 static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd)
8201 {
8202         struct hfi1_devdata *dd = rcd->dd;
8203         u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg);
8204
8205         mmiowb();       /* make sure everything before is written */
8206         write_csr(dd, addr, rcd->imask);
8207         /* force the above write on the chip and get a value back */
8208         (void)read_csr(dd, addr);
8209 }
8210
8211 /* force the receive interrupt */
8212 void force_recv_intr(struct hfi1_ctxtdata *rcd)
8213 {
8214         write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8215 }
8216
8217 /*
8218  * Return non-zero if a packet is present.
8219  *
8220  * This routine is called when rechecking for packets after the RcvAvail
8221  * interrupt has been cleared down.  First, do a quick check of memory for
8222  * a packet present.  If not found, use an expensive CSR read of the context
8223  * tail to determine the actual tail.  The CSR read is necessary because there
8224  * is no method to push pending DMAs to memory other than an interrupt and we
8225  * are trying to determine if we need to force an interrupt.
8226  */
8227 static inline int check_packet_present(struct hfi1_ctxtdata *rcd)
8228 {
8229         u32 tail;
8230         int present;
8231
8232         if (!HFI1_CAP_IS_KSET(DMA_RTAIL))
8233                 present = (rcd->seq_cnt ==
8234                                 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd))));
8235         else /* is RDMA rtail */
8236                 present = (rcd->head != get_rcvhdrtail(rcd));
8237
8238         if (present)
8239                 return 1;
8240
8241         /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8242         tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8243         return rcd->head != tail;
8244 }
8245
8246 /*
8247  * Receive packet IRQ handler.  This routine expects to be on its own IRQ.
8248  * This routine will try to handle packets immediately (latency), but if
8249  * it finds too many, it will invoke the thread handler (bandwitdh).  The
8250  * chip receive interrupt is *not* cleared down until this or the thread (if
8251  * invoked) is finished.  The intent is to avoid extra interrupts while we
8252  * are processing packets anyway.
8253  */
8254 static irqreturn_t receive_context_interrupt(int irq, void *data)
8255 {
8256         struct hfi1_ctxtdata *rcd = data;
8257         struct hfi1_devdata *dd = rcd->dd;
8258         int disposition;
8259         int present;
8260
8261         trace_hfi1_receive_interrupt(dd, rcd->ctxt);
8262         this_cpu_inc(*dd->int_counter);
8263         aspm_ctx_disable(rcd);
8264
8265         /* receive interrupt remains blocked while processing packets */
8266         disposition = rcd->do_interrupt(rcd, 0);
8267
8268         /*
8269          * Too many packets were seen while processing packets in this
8270          * IRQ handler.  Invoke the handler thread.  The receive interrupt
8271          * remains blocked.
8272          */
8273         if (disposition == RCV_PKT_LIMIT)
8274                 return IRQ_WAKE_THREAD;
8275
8276         /*
8277          * The packet processor detected no more packets.  Clear the receive
8278          * interrupt and recheck for a packet packet that may have arrived
8279          * after the previous check and interrupt clear.  If a packet arrived,
8280          * force another interrupt.
8281          */
8282         clear_recv_intr(rcd);
8283         present = check_packet_present(rcd);
8284         if (present)
8285                 force_recv_intr(rcd);
8286
8287         return IRQ_HANDLED;
8288 }
8289
8290 /*
8291  * Receive packet thread handler.  This expects to be invoked with the
8292  * receive interrupt still blocked.
8293  */
8294 static irqreturn_t receive_context_thread(int irq, void *data)
8295 {
8296         struct hfi1_ctxtdata *rcd = data;
8297         int present;
8298
8299         /* receive interrupt is still blocked from the IRQ handler */
8300         (void)rcd->do_interrupt(rcd, 1);
8301
8302         /*
8303          * The packet processor will only return if it detected no more
8304          * packets.  Hold IRQs here so we can safely clear the interrupt and
8305          * recheck for a packet that may have arrived after the previous
8306          * check and the interrupt clear.  If a packet arrived, force another
8307          * interrupt.
8308          */
8309         local_irq_disable();
8310         clear_recv_intr(rcd);
8311         present = check_packet_present(rcd);
8312         if (present)
8313                 force_recv_intr(rcd);
8314         local_irq_enable();
8315
8316         return IRQ_HANDLED;
8317 }
8318
8319 /* ========================================================================= */
8320
8321 u32 read_physical_state(struct hfi1_devdata *dd)
8322 {
8323         u64 reg;
8324
8325         reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
8326         return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT)
8327                                 & DC_DC8051_STS_CUR_STATE_PORT_MASK;
8328 }
8329
8330 u32 read_logical_state(struct hfi1_devdata *dd)
8331 {
8332         u64 reg;
8333
8334         reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8335         return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT)
8336                                 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK;
8337 }
8338
8339 static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate)
8340 {
8341         u64 reg;
8342
8343         reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8344         /* clear current state, set new state */
8345         reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK;
8346         reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT;
8347         write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
8348 }
8349
8350 /*
8351  * Use the 8051 to read a LCB CSR.
8352  */
8353 static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data)
8354 {
8355         u32 regno;
8356         int ret;
8357
8358         if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8359                 if (acquire_lcb_access(dd, 0) == 0) {
8360                         *data = read_csr(dd, addr);
8361                         release_lcb_access(dd, 0);
8362                         return 0;
8363                 }
8364                 return -EBUSY;
8365         }
8366
8367         /* register is an index of LCB registers: (offset - base) / 8 */
8368         regno = (addr - DC_LCB_CFG_RUN) >> 3;
8369         ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data);
8370         if (ret != HCMD_SUCCESS)
8371                 return -EBUSY;
8372         return 0;
8373 }
8374
8375 /*
8376  * Provide a cache for some of the LCB registers in case the LCB is
8377  * unavailable.
8378  * (The LCB is unavailable in certain link states, for example.)
8379  */
8380 struct lcb_datum {
8381         u32 off;
8382         u64 val;
8383 };
8384
8385 static struct lcb_datum lcb_cache[] = {
8386         { DC_LCB_ERR_INFO_RX_REPLAY_CNT, 0},
8387         { DC_LCB_ERR_INFO_SEQ_CRC_CNT, 0 },
8388         { DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 0 },
8389 };
8390
8391 static void update_lcb_cache(struct hfi1_devdata *dd)
8392 {
8393         int i;
8394         int ret;
8395         u64 val;
8396
8397         for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) {
8398                 ret = read_lcb_csr(dd, lcb_cache[i].off, &val);
8399
8400                 /* Update if we get good data */
8401                 if (likely(ret != -EBUSY))
8402                         lcb_cache[i].val = val;
8403         }
8404 }
8405
8406 static int read_lcb_cache(u32 off, u64 *val)
8407 {
8408         int i;
8409
8410         for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) {
8411                 if (lcb_cache[i].off == off) {
8412                         *val = lcb_cache[i].val;
8413                         return 0;
8414                 }
8415         }
8416
8417         pr_warn("%s bad offset 0x%x\n", __func__, off);
8418         return -1;
8419 }
8420
8421 /*
8422  * Read an LCB CSR.  Access may not be in host control, so check.
8423  * Return 0 on success, -EBUSY on failure.
8424  */
8425 int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data)
8426 {
8427         struct hfi1_pportdata *ppd = dd->pport;
8428
8429         /* if up, go through the 8051 for the value */
8430         if (ppd->host_link_state & HLS_UP)
8431                 return read_lcb_via_8051(dd, addr, data);
8432         /* if going up or down, check the cache, otherwise, no access */
8433         if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) {
8434                 if (read_lcb_cache(addr, data))
8435                         return -EBUSY;
8436                 return 0;
8437         }
8438
8439         /* otherwise, host has access */
8440         *data = read_csr(dd, addr);
8441         return 0;
8442 }
8443
8444 /*
8445  * Use the 8051 to write a LCB CSR.
8446  */
8447 static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data)
8448 {
8449         u32 regno;
8450         int ret;
8451
8452         if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR ||
8453             (dd->dc8051_ver < dc8051_ver(0, 20, 0))) {
8454                 if (acquire_lcb_access(dd, 0) == 0) {
8455                         write_csr(dd, addr, data);
8456                         release_lcb_access(dd, 0);
8457                         return 0;
8458                 }
8459                 return -EBUSY;
8460         }
8461
8462         /* register is an index of LCB registers: (offset - base) / 8 */
8463         regno = (addr - DC_LCB_CFG_RUN) >> 3;
8464         ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data);
8465         if (ret != HCMD_SUCCESS)
8466                 return -EBUSY;
8467         return 0;
8468 }
8469
8470 /*
8471  * Write an LCB CSR.  Access may not be in host control, so check.
8472  * Return 0 on success, -EBUSY on failure.
8473  */
8474 int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data)
8475 {
8476         struct hfi1_pportdata *ppd = dd->pport;
8477
8478         /* if up, go through the 8051 for the value */
8479         if (ppd->host_link_state & HLS_UP)
8480                 return write_lcb_via_8051(dd, addr, data);
8481         /* if going up or down, no access */
8482         if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8483                 return -EBUSY;
8484         /* otherwise, host has access */
8485         write_csr(dd, addr, data);
8486         return 0;
8487 }
8488
8489 /*
8490  * Returns:
8491  *      < 0 = Linux error, not able to get access
8492  *      > 0 = 8051 command RETURN_CODE
8493  */
8494 static int do_8051_command(
8495         struct hfi1_devdata *dd,
8496         u32 type,
8497         u64 in_data,
8498         u64 *out_data)
8499 {
8500         u64 reg, completed;
8501         int return_code;
8502         unsigned long timeout;
8503
8504         hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data);
8505
8506         mutex_lock(&dd->dc8051_lock);
8507
8508         /* We can't send any commands to the 8051 if it's in reset */
8509         if (dd->dc_shutdown) {
8510                 return_code = -ENODEV;
8511                 goto fail;
8512         }
8513
8514         /*
8515          * If an 8051 host command timed out previously, then the 8051 is
8516          * stuck.
8517          *
8518          * On first timeout, attempt to reset and restart the entire DC
8519          * block (including 8051). (Is this too big of a hammer?)
8520          *
8521          * If the 8051 times out a second time, the reset did not bring it
8522          * back to healthy life. In that case, fail any subsequent commands.
8523          */
8524         if (dd->dc8051_timed_out) {
8525                 if (dd->dc8051_timed_out > 1) {
8526                         dd_dev_err(dd,
8527                                    "Previous 8051 host command timed out, skipping command %u\n",
8528                                    type);
8529                         return_code = -ENXIO;
8530                         goto fail;
8531                 }
8532                 _dc_shutdown(dd);
8533                 _dc_start(dd);
8534         }
8535
8536         /*
8537          * If there is no timeout, then the 8051 command interface is
8538          * waiting for a command.
8539          */
8540
8541         /*
8542          * When writing a LCB CSR, out_data contains the full value to
8543          * to be written, while in_data contains the relative LCB
8544          * address in 7:0.  Do the work here, rather than the caller,
8545          * of distrubting the write data to where it needs to go:
8546          *
8547          * Write data
8548          *   39:00 -> in_data[47:8]
8549          *   47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8550          *   63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8551          */
8552         if (type == HCMD_WRITE_LCB_CSR) {
8553                 in_data |= ((*out_data) & 0xffffffffffull) << 8;
8554                 /* must preserve COMPLETED - it is tied to hardware */
8555                 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0);
8556                 reg &= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK;
8557                 reg |= ((((*out_data) >> 40) & 0xff) <<
8558                                 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8559                       | ((((*out_data) >> 48) & 0xffff) <<
8560                                 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8561                 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
8562         }
8563
8564         /*
8565          * Do two writes: the first to stabilize the type and req_data, the
8566          * second to activate.
8567          */
8568         reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK)
8569                         << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8570                 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK)
8571                         << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT;
8572         write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8573         reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK;
8574         write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8575
8576         /* wait for completion, alternate: interrupt */
8577         timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT);
8578         while (1) {
8579                 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
8580                 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK;
8581                 if (completed)
8582                         break;
8583                 if (time_after(jiffies, timeout)) {
8584                         dd->dc8051_timed_out++;
8585                         dd_dev_err(dd, "8051 host command %u timeout\n", type);
8586                         if (out_data)
8587                                 *out_data = 0;
8588                         return_code = -ETIMEDOUT;
8589                         goto fail;
8590                 }
8591                 udelay(2);
8592         }
8593
8594         if (out_data) {
8595                 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT)
8596                                 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK;
8597                 if (type == HCMD_READ_LCB_CSR) {
8598                         /* top 16 bits are in a different register */
8599                         *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
8600                                 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK)
8601                                 << (48
8602                                     - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT);
8603                 }
8604         }
8605         return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT)
8606                                 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK;
8607         dd->dc8051_timed_out = 0;
8608         /*
8609          * Clear command for next user.
8610          */
8611         write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
8612
8613 fail:
8614         mutex_unlock(&dd->dc8051_lock);
8615         return return_code;
8616 }
8617
8618 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state)
8619 {
8620         return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL);
8621 }
8622
8623 int load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8624                      u8 lane_id, u32 config_data)
8625 {
8626         u64 data;
8627         int ret;
8628
8629         data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT
8630                 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT
8631                 | (u64)config_data << LOAD_DATA_DATA_SHIFT;
8632         ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL);
8633         if (ret != HCMD_SUCCESS) {
8634                 dd_dev_err(dd,
8635                            "load 8051 config: field id %d, lane %d, err %d\n",
8636                            (int)field_id, (int)lane_id, ret);
8637         }
8638         return ret;
8639 }
8640
8641 /*
8642  * Read the 8051 firmware "registers".  Use the RAM directly.  Always
8643  * set the result, even on error.
8644  * Return 0 on success, -errno on failure
8645  */
8646 int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id,
8647                      u32 *result)
8648 {
8649         u64 big_data;
8650         u32 addr;
8651         int ret;
8652
8653         /* address start depends on the lane_id */
8654         if (lane_id < 4)
8655                 addr = (4 * NUM_GENERAL_FIELDS)
8656                         + (lane_id * 4 * NUM_LANE_FIELDS);
8657         else
8658                 addr = 0;
8659         addr += field_id * 4;
8660
8661         /* read is in 8-byte chunks, hardware will truncate the address down */
8662         ret = read_8051_data(dd, addr, 8, &big_data);
8663
8664         if (ret == 0) {
8665                 /* extract the 4 bytes we want */
8666                 if (addr & 0x4)
8667                         *result = (u32)(big_data >> 32);
8668                 else
8669                         *result = (u32)big_data;
8670         } else {
8671                 *result = 0;
8672                 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n",
8673                            __func__, lane_id, field_id);
8674         }
8675
8676         return ret;
8677 }
8678
8679 static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management,
8680                               u8 continuous)
8681 {
8682         u32 frame;
8683
8684         frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT
8685                 | power_management << POWER_MANAGEMENT_SHIFT;
8686         return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY,
8687                                 GENERAL_CONFIG, frame);
8688 }
8689
8690 static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu,
8691                                  u16 vl15buf, u8 crc_sizes)
8692 {
8693         u32 frame;
8694
8695         frame = (u32)vau << VAU_SHIFT
8696                 | (u32)z << Z_SHIFT
8697                 | (u32)vcu << VCU_SHIFT
8698                 | (u32)vl15buf << VL15BUF_SHIFT
8699                 | (u32)crc_sizes << CRC_SIZES_SHIFT;
8700         return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC,
8701                                 GENERAL_CONFIG, frame);
8702 }
8703
8704 static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
8705                                      u8 *flag_bits, u16 *link_widths)
8706 {
8707         u32 frame;
8708
8709         read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8710                          &frame);
8711         *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK;
8712         *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK;
8713         *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8714 }
8715
8716 static int write_vc_local_link_width(struct hfi1_devdata *dd,
8717                                      u8 misc_bits,
8718                                      u8 flag_bits,
8719                                      u16 link_widths)
8720 {
8721         u32 frame;
8722
8723         frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT
8724                 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT
8725                 | (u32)link_widths << LINK_WIDTH_SHIFT;
8726         return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_WIDTH, GENERAL_CONFIG,
8727                      frame);
8728 }
8729
8730 static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id,
8731                                  u8 device_rev)
8732 {
8733         u32 frame;
8734
8735         frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT)
8736                 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT);
8737         return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame);
8738 }
8739
8740 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
8741                                   u8 *device_rev)
8742 {
8743         u32 frame;
8744
8745         read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame);
8746         *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK;
8747         *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT)
8748                         & REMOTE_DEVICE_REV_MASK;
8749 }
8750
8751 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor,
8752                       u8 *ver_patch)
8753 {
8754         u32 frame;
8755
8756         read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame);
8757         *ver_major = (frame >> STS_FM_VERSION_MAJOR_SHIFT) &
8758                 STS_FM_VERSION_MAJOR_MASK;
8759         *ver_minor = (frame >> STS_FM_VERSION_MINOR_SHIFT) &
8760                 STS_FM_VERSION_MINOR_MASK;
8761
8762         read_8051_config(dd, VERSION_PATCH, GENERAL_CONFIG, &frame);
8763         *ver_patch = (frame >> STS_FM_VERSION_PATCH_SHIFT) &
8764                 STS_FM_VERSION_PATCH_MASK;
8765 }
8766
8767 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
8768                                u8 *continuous)
8769 {
8770         u32 frame;
8771
8772         read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame);
8773         *power_management = (frame >> POWER_MANAGEMENT_SHIFT)
8774                                         & POWER_MANAGEMENT_MASK;
8775         *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT)
8776                                         & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK;
8777 }
8778
8779 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
8780                                   u8 *vcu, u16 *vl15buf, u8 *crc_sizes)
8781 {
8782         u32 frame;
8783
8784         read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame);
8785         *vau = (frame >> VAU_SHIFT) & VAU_MASK;
8786         *z = (frame >> Z_SHIFT) & Z_MASK;
8787         *vcu = (frame >> VCU_SHIFT) & VCU_MASK;
8788         *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK;
8789         *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK;
8790 }
8791
8792 static void read_vc_remote_link_width(struct hfi1_devdata *dd,
8793                                       u8 *remote_tx_rate,
8794                                       u16 *link_widths)
8795 {
8796         u32 frame;
8797
8798         read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG,
8799                          &frame);
8800         *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT)
8801                                 & REMOTE_TX_RATE_MASK;
8802         *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8803 }
8804
8805 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx)
8806 {
8807         u32 frame;
8808
8809         read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame);
8810         *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK;
8811 }
8812
8813 static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed)
8814 {
8815         u32 frame;
8816
8817         read_8051_config(dd, REMOTE_LNI_INFO, GENERAL_CONFIG, &frame);
8818         *mgmt_allowed = (frame >> MGMT_ALLOWED_SHIFT) & MGMT_ALLOWED_MASK;
8819 }
8820
8821 static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls)
8822 {
8823         read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls);
8824 }
8825
8826 static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs)
8827 {
8828         read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs);
8829 }
8830
8831 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality)
8832 {
8833         u32 frame;
8834         int ret;
8835
8836         *link_quality = 0;
8837         if (dd->pport->host_link_state & HLS_UP) {
8838                 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG,
8839                                        &frame);
8840                 if (ret == 0)
8841                         *link_quality = (frame >> LINK_QUALITY_SHIFT)
8842                                                 & LINK_QUALITY_MASK;
8843         }
8844 }
8845
8846 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc)
8847 {
8848         u32 frame;
8849
8850         read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame);
8851         *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK;
8852 }
8853
8854 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr)
8855 {
8856         u32 frame;
8857
8858         read_8051_config(dd, LINK_DOWN_REASON, GENERAL_CONFIG, &frame);
8859         *ldr = (frame & 0xff);
8860 }
8861
8862 static int read_tx_settings(struct hfi1_devdata *dd,
8863                             u8 *enable_lane_tx,
8864                             u8 *tx_polarity_inversion,
8865                             u8 *rx_polarity_inversion,
8866                             u8 *max_rate)
8867 {
8868         u32 frame;
8869         int ret;
8870
8871         ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame);
8872         *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT)
8873                                 & ENABLE_LANE_TX_MASK;
8874         *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT)
8875                                 & TX_POLARITY_INVERSION_MASK;
8876         *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT)
8877                                 & RX_POLARITY_INVERSION_MASK;
8878         *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK;
8879         return ret;
8880 }
8881
8882 static int write_tx_settings(struct hfi1_devdata *dd,
8883                              u8 enable_lane_tx,
8884                              u8 tx_polarity_inversion,
8885                              u8 rx_polarity_inversion,
8886                              u8 max_rate)
8887 {
8888         u32 frame;
8889
8890         /* no need to mask, all variable sizes match field widths */
8891         frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT
8892                 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT
8893                 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT
8894                 | max_rate << MAX_RATE_SHIFT;
8895         return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame);
8896 }
8897
8898 /*
8899  * Read an idle LCB message.
8900  *
8901  * Returns 0 on success, -EINVAL on error
8902  */
8903 static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out)
8904 {
8905         int ret;
8906
8907         ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out);
8908         if (ret != HCMD_SUCCESS) {
8909                 dd_dev_err(dd, "read idle message: type %d, err %d\n",
8910                            (u32)type, ret);
8911                 return -EINVAL;
8912         }
8913         dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out);
8914         /* return only the payload as we already know the type */
8915         *data_out >>= IDLE_PAYLOAD_SHIFT;
8916         return 0;
8917 }
8918
8919 /*
8920  * Read an idle SMA message.  To be done in response to a notification from
8921  * the 8051.
8922  *
8923  * Returns 0 on success, -EINVAL on error
8924  */
8925 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data)
8926 {
8927         return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT,
8928                                  data);
8929 }
8930
8931 /*
8932  * Send an idle LCB message.
8933  *
8934  * Returns 0 on success, -EINVAL on error
8935  */
8936 static int send_idle_message(struct hfi1_devdata *dd, u64 data)
8937 {
8938         int ret;
8939
8940         dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data);
8941         ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL);
8942         if (ret != HCMD_SUCCESS) {
8943                 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n",
8944                            data, ret);
8945                 return -EINVAL;
8946         }
8947         return 0;
8948 }
8949
8950 /*
8951  * Send an idle SMA message.
8952  *
8953  * Returns 0 on success, -EINVAL on error
8954  */
8955 int send_idle_sma(struct hfi1_devdata *dd, u64 message)
8956 {
8957         u64 data;
8958
8959         data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) |
8960                 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT);
8961         return send_idle_message(dd, data);
8962 }
8963
8964 /*
8965  * Initialize the LCB then do a quick link up.  This may or may not be
8966  * in loopback.
8967  *
8968  * return 0 on success, -errno on error
8969  */
8970 static int do_quick_linkup(struct hfi1_devdata *dd)
8971 {
8972         int ret;
8973
8974         lcb_shutdown(dd, 0);
8975
8976         if (loopback) {
8977                 /* LCB_CFG_LOOPBACK.VAL = 2 */
8978                 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
8979                 write_csr(dd, DC_LCB_CFG_LOOPBACK,
8980                           IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT);
8981                 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
8982         }
8983
8984         /* start the LCBs */
8985         /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
8986         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
8987
8988         /* simulator only loopback steps */
8989         if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8990                 /* LCB_CFG_RUN.EN = 1 */
8991                 write_csr(dd, DC_LCB_CFG_RUN,
8992                           1ull << DC_LCB_CFG_RUN_EN_SHIFT);
8993
8994                 ret = wait_link_transfer_active(dd, 10);
8995                 if (ret)
8996                         return ret;
8997
8998                 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
8999                           1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT);
9000         }
9001
9002         if (!loopback) {
9003                 /*
9004                  * When doing quick linkup and not in loopback, both
9005                  * sides must be done with LCB set-up before either
9006                  * starts the quick linkup.  Put a delay here so that
9007                  * both sides can be started and have a chance to be
9008                  * done with LCB set up before resuming.
9009                  */
9010                 dd_dev_err(dd,
9011                            "Pausing for peer to be finished with LCB set up\n");
9012                 msleep(5000);
9013                 dd_dev_err(dd, "Continuing with quick linkup\n");
9014         }
9015
9016         write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
9017         set_8051_lcb_access(dd);
9018
9019         /*
9020          * State "quick" LinkUp request sets the physical link state to
9021          * LinkUp without a verify capability sequence.
9022          * This state is in simulator v37 and later.
9023          */
9024         ret = set_physical_link_state(dd, PLS_QUICK_LINKUP);
9025         if (ret != HCMD_SUCCESS) {
9026                 dd_dev_err(dd,
9027                            "%s: set physical link state to quick LinkUp failed with return %d\n",
9028                            __func__, ret);
9029
9030                 set_host_lcb_access(dd);
9031                 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
9032
9033                 if (ret >= 0)
9034                         ret = -EINVAL;
9035                 return ret;
9036         }
9037
9038         return 0; /* success */
9039 }
9040
9041 /*
9042  * Set the SerDes to internal loopback mode.
9043  * Returns 0 on success, -errno on error.
9044  */
9045 static int set_serdes_loopback_mode(struct hfi1_devdata *dd)
9046 {
9047         int ret;
9048
9049         ret = set_physical_link_state(dd, PLS_INTERNAL_SERDES_LOOPBACK);
9050         if (ret == HCMD_SUCCESS)
9051                 return 0;
9052         dd_dev_err(dd,
9053                    "Set physical link state to SerDes Loopback failed with return %d\n",
9054                    ret);
9055         if (ret >= 0)
9056                 ret = -EINVAL;
9057         return ret;
9058 }
9059
9060 /*
9061  * Do all special steps to set up loopback.
9062  */
9063 static int init_loopback(struct hfi1_devdata *dd)
9064 {
9065         dd_dev_info(dd, "Entering loopback mode\n");
9066
9067         /* all loopbacks should disable self GUID check */
9068         write_csr(dd, DC_DC8051_CFG_MODE,
9069                   (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
9070
9071         /*
9072          * The simulator has only one loopback option - LCB.  Switch
9073          * to that option, which includes quick link up.
9074          *
9075          * Accept all valid loopback values.
9076          */
9077         if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) &&
9078             (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB ||
9079              loopback == LOOPBACK_CABLE)) {
9080                 loopback = LOOPBACK_LCB;
9081                 quick_linkup = 1;
9082                 return 0;
9083         }
9084
9085         /* handle serdes loopback */
9086         if (loopback == LOOPBACK_SERDES) {
9087                 /* internal serdes loopack needs quick linkup on RTL */
9088                 if (dd->icode == ICODE_RTL_SILICON)
9089                         quick_linkup = 1;
9090                 return set_serdes_loopback_mode(dd);
9091         }
9092
9093         /* LCB loopback - handled at poll time */
9094         if (loopback == LOOPBACK_LCB) {
9095                 quick_linkup = 1; /* LCB is always quick linkup */
9096
9097                 /* not supported in emulation due to emulation RTL changes */
9098                 if (dd->icode == ICODE_FPGA_EMULATION) {
9099                         dd_dev_err(dd,
9100                                    "LCB loopback not supported in emulation\n");
9101                         return -EINVAL;
9102                 }
9103                 return 0;
9104         }
9105
9106         /* external cable loopback requires no extra steps */
9107         if (loopback == LOOPBACK_CABLE)
9108                 return 0;
9109
9110         dd_dev_err(dd, "Invalid loopback mode %d\n", loopback);
9111         return -EINVAL;
9112 }
9113
9114 /*
9115  * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
9116  * used in the Verify Capability link width attribute.
9117  */
9118 static u16 opa_to_vc_link_widths(u16 opa_widths)
9119 {
9120         int i;
9121         u16 result = 0;
9122
9123         static const struct link_bits {
9124                 u16 from;
9125                 u16 to;
9126         } opa_link_xlate[] = {
9127                 { OPA_LINK_WIDTH_1X, 1 << (1 - 1)  },
9128                 { OPA_LINK_WIDTH_2X, 1 << (2 - 1)  },
9129                 { OPA_LINK_WIDTH_3X, 1 << (3 - 1)  },
9130                 { OPA_LINK_WIDTH_4X, 1 << (4 - 1)  },
9131         };
9132
9133         for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) {
9134                 if (opa_widths & opa_link_xlate[i].from)
9135                         result |= opa_link_xlate[i].to;
9136         }
9137         return result;
9138 }
9139
9140 /*
9141  * Set link attributes before moving to polling.
9142  */
9143 static int set_local_link_attributes(struct hfi1_pportdata *ppd)
9144 {
9145         struct hfi1_devdata *dd = ppd->dd;
9146         u8 enable_lane_tx;
9147         u8 tx_polarity_inversion;
9148         u8 rx_polarity_inversion;
9149         int ret;
9150
9151         /* reset our fabric serdes to clear any lingering problems */
9152         fabric_serdes_reset(dd);
9153
9154         /* set the local tx rate - need to read-modify-write */
9155         ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
9156                                &rx_polarity_inversion, &ppd->local_tx_rate);
9157         if (ret)
9158                 goto set_local_link_attributes_fail;
9159
9160         if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) {
9161                 /* set the tx rate to the fastest enabled */
9162                 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9163                         ppd->local_tx_rate = 1;
9164                 else
9165                         ppd->local_tx_rate = 0;
9166         } else {
9167                 /* set the tx rate to all enabled */
9168                 ppd->local_tx_rate = 0;
9169                 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9170                         ppd->local_tx_rate |= 2;
9171                 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G)
9172                         ppd->local_tx_rate |= 1;
9173         }
9174
9175         enable_lane_tx = 0xF; /* enable all four lanes */
9176         ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion,
9177                                 rx_polarity_inversion, ppd->local_tx_rate);
9178         if (ret != HCMD_SUCCESS)
9179                 goto set_local_link_attributes_fail;
9180
9181         /*
9182          * DC supports continuous updates.
9183          */
9184         ret = write_vc_local_phy(dd,
9185                                  0 /* no power management */,
9186                                  1 /* continuous updates */);
9187         if (ret != HCMD_SUCCESS)
9188                 goto set_local_link_attributes_fail;
9189
9190         /* z=1 in the next call: AU of 0 is not supported by the hardware */
9191         ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init,
9192                                     ppd->port_crc_mode_enabled);
9193         if (ret != HCMD_SUCCESS)
9194                 goto set_local_link_attributes_fail;
9195
9196         ret = write_vc_local_link_width(dd, 0, 0,
9197                                         opa_to_vc_link_widths(
9198                                                 ppd->link_width_enabled));
9199         if (ret != HCMD_SUCCESS)
9200                 goto set_local_link_attributes_fail;
9201
9202         /* let peer know who we are */
9203         ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev);
9204         if (ret == HCMD_SUCCESS)
9205                 return 0;
9206
9207 set_local_link_attributes_fail:
9208         dd_dev_err(dd,
9209                    "Failed to set local link attributes, return 0x%x\n",
9210                    ret);
9211         return ret;
9212 }
9213
9214 /*
9215  * Call this to start the link.
9216  * Do not do anything if the link is disabled.
9217  * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
9218  */
9219 int start_link(struct hfi1_pportdata *ppd)
9220 {
9221         /*
9222          * Tune the SerDes to a ballpark setting for optimal signal and bit
9223          * error rate.  Needs to be done before starting the link.
9224          */
9225         tune_serdes(ppd);
9226
9227         if (!ppd->link_enabled) {
9228                 dd_dev_info(ppd->dd,
9229                             "%s: stopping link start because link is disabled\n",
9230                             __func__);
9231                 return 0;
9232         }
9233         if (!ppd->driver_link_ready) {
9234                 dd_dev_info(ppd->dd,
9235                             "%s: stopping link start because driver is not ready\n",
9236                             __func__);
9237                 return 0;
9238         }
9239
9240         /*
9241          * FULL_MGMT_P_KEY is cleared from the pkey table, so that the
9242          * pkey table can be configured properly if the HFI unit is connected
9243          * to switch port with MgmtAllowed=NO
9244          */
9245         clear_full_mgmt_pkey(ppd);
9246
9247         return set_link_state(ppd, HLS_DN_POLL);
9248 }
9249
9250 static void wait_for_qsfp_init(struct hfi1_pportdata *ppd)
9251 {
9252         struct hfi1_devdata *dd = ppd->dd;
9253         u64 mask;
9254         unsigned long timeout;
9255
9256         /*
9257          * Some QSFP cables have a quirk that asserts the IntN line as a side
9258          * effect of power up on plug-in. We ignore this false positive
9259          * interrupt until the module has finished powering up by waiting for
9260          * a minimum timeout of the module inrush initialization time of
9261          * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the
9262          * module have stabilized.
9263          */
9264         msleep(500);
9265
9266         /*
9267          * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1)
9268          */
9269         timeout = jiffies + msecs_to_jiffies(2000);
9270         while (1) {
9271                 mask = read_csr(dd, dd->hfi1_id ?
9272                                 ASIC_QSFP2_IN : ASIC_QSFP1_IN);
9273                 if (!(mask & QSFP_HFI0_INT_N))
9274                         break;
9275                 if (time_after(jiffies, timeout)) {
9276                         dd_dev_info(dd, "%s: No IntN detected, reset complete\n",
9277                                     __func__);
9278                         break;
9279                 }
9280                 udelay(2);
9281         }
9282 }
9283
9284 static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable)
9285 {
9286         struct hfi1_devdata *dd = ppd->dd;
9287         u64 mask;
9288
9289         mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
9290         if (enable) {
9291                 /*
9292                  * Clear the status register to avoid an immediate interrupt
9293                  * when we re-enable the IntN pin
9294                  */
9295                 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9296                           QSFP_HFI0_INT_N);
9297                 mask |= (u64)QSFP_HFI0_INT_N;
9298         } else {
9299                 mask &= ~(u64)QSFP_HFI0_INT_N;
9300         }
9301         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9302 }
9303
9304 void reset_qsfp(struct hfi1_pportdata *ppd)
9305 {
9306         struct hfi1_devdata *dd = ppd->dd;
9307         u64 mask, qsfp_mask;
9308
9309         /* Disable INT_N from triggering QSFP interrupts */
9310         set_qsfp_int_n(ppd, 0);
9311
9312         /* Reset the QSFP */
9313         mask = (u64)QSFP_HFI0_RESET_N;
9314
9315         qsfp_mask = read_csr(dd,
9316                              dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT);
9317         qsfp_mask &= ~mask;
9318         write_csr(dd,
9319                   dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
9320
9321         udelay(10);
9322
9323         qsfp_mask |= mask;
9324         write_csr(dd,
9325                   dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
9326
9327         wait_for_qsfp_init(ppd);
9328
9329         /*
9330          * Allow INT_N to trigger the QSFP interrupt to watch
9331          * for alarms and warnings
9332          */
9333         set_qsfp_int_n(ppd, 1);
9334 }
9335
9336 static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd,
9337                                         u8 *qsfp_interrupt_status)
9338 {
9339         struct hfi1_devdata *dd = ppd->dd;
9340
9341         if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) ||
9342             (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING))
9343                 dd_dev_info(dd, "%s: QSFP cable temperature too high\n",
9344                             __func__);
9345
9346         if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) ||
9347             (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING))
9348                 dd_dev_info(dd, "%s: QSFP cable temperature too low\n",
9349                             __func__);
9350
9351         /*
9352          * The remaining alarms/warnings don't matter if the link is down.
9353          */
9354         if (ppd->host_link_state & HLS_DOWN)
9355                 return 0;
9356
9357         if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) ||
9358             (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING))
9359                 dd_dev_info(dd, "%s: QSFP supply voltage too high\n",
9360                             __func__);
9361
9362         if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) ||
9363             (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING))
9364                 dd_dev_info(dd, "%s: QSFP supply voltage too low\n",
9365                             __func__);
9366
9367         /* Byte 2 is vendor specific */
9368
9369         if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) ||
9370             (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING))
9371                 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too high\n",
9372                             __func__);
9373
9374         if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) ||
9375             (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING))
9376                 dd_dev_info(dd, "%s: Cable RX channel 1/2 power too low\n",
9377                             __func__);
9378
9379         if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) ||
9380             (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING))
9381                 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too high\n",
9382                             __func__);
9383
9384         if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) ||
9385             (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING))
9386                 dd_dev_info(dd, "%s: Cable RX channel 3/4 power too low\n",
9387                             __func__);
9388
9389         if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) ||
9390             (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING))
9391                 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too high\n",
9392                             __func__);
9393
9394         if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) ||
9395             (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING))
9396                 dd_dev_info(dd, "%s: Cable TX channel 1/2 bias too low\n",
9397                             __func__);
9398
9399         if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) ||
9400             (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING))
9401                 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too high\n",
9402                             __func__);
9403
9404         if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) ||
9405             (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING))
9406                 dd_dev_info(dd, "%s: Cable TX channel 3/4 bias too low\n",
9407                             __func__);
9408
9409         if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) ||
9410             (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING))
9411                 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too high\n",
9412                             __func__);
9413
9414         if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) ||
9415             (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING))
9416                 dd_dev_info(dd, "%s: Cable TX channel 1/2 power too low\n",
9417                             __func__);
9418
9419         if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) ||
9420             (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING))
9421                 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too high\n",
9422                             __func__);
9423
9424         if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) ||
9425             (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING))
9426                 dd_dev_info(dd, "%s: Cable TX channel 3/4 power too low\n",
9427                             __func__);
9428
9429         /* Bytes 9-10 and 11-12 are reserved */
9430         /* Bytes 13-15 are vendor specific */
9431
9432         return 0;
9433 }
9434
9435 /* This routine will only be scheduled if the QSFP module present is asserted */
9436 void qsfp_event(struct work_struct *work)
9437 {
9438         struct qsfp_data *qd;
9439         struct hfi1_pportdata *ppd;
9440         struct hfi1_devdata *dd;
9441
9442         qd = container_of(work, struct qsfp_data, qsfp_work);
9443         ppd = qd->ppd;
9444         dd = ppd->dd;
9445
9446         /* Sanity check */
9447         if (!qsfp_mod_present(ppd))
9448                 return;
9449
9450         /*
9451          * Turn DC back on after cable has been re-inserted. Up until
9452          * now, the DC has been in reset to save power.
9453          */
9454         dc_start(dd);
9455
9456         if (qd->cache_refresh_required) {
9457                 set_qsfp_int_n(ppd, 0);
9458
9459                 wait_for_qsfp_init(ppd);
9460
9461                 /*
9462                  * Allow INT_N to trigger the QSFP interrupt to watch
9463                  * for alarms and warnings
9464                  */
9465                 set_qsfp_int_n(ppd, 1);
9466
9467                 start_link(ppd);
9468         }
9469
9470         if (qd->check_interrupt_flags) {
9471                 u8 qsfp_interrupt_status[16] = {0,};
9472
9473                 if (one_qsfp_read(ppd, dd->hfi1_id, 6,
9474                                   &qsfp_interrupt_status[0], 16) != 16) {
9475                         dd_dev_info(dd,
9476                                     "%s: Failed to read status of QSFP module\n",
9477                                     __func__);
9478                 } else {
9479                         unsigned long flags;
9480
9481                         handle_qsfp_error_conditions(
9482                                         ppd, qsfp_interrupt_status);
9483                         spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
9484                         ppd->qsfp_info.check_interrupt_flags = 0;
9485                         spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
9486                                                flags);
9487                 }
9488         }
9489 }
9490
9491 static void init_qsfp_int(struct hfi1_devdata *dd)
9492 {
9493         struct hfi1_pportdata *ppd = dd->pport;
9494         u64 qsfp_mask, cce_int_mask;
9495         const int qsfp1_int_smask = QSFP1_INT % 64;
9496         const int qsfp2_int_smask = QSFP2_INT % 64;
9497
9498         /*
9499          * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0
9500          * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR,
9501          * therefore just one of QSFP1_INT/QSFP2_INT can be used to find
9502          * the index of the appropriate CSR in the CCEIntMask CSR array
9503          */
9504         cce_int_mask = read_csr(dd, CCE_INT_MASK +
9505                                 (8 * (QSFP1_INT / 64)));
9506         if (dd->hfi1_id) {
9507                 cce_int_mask &= ~((u64)1 << qsfp1_int_smask);
9508                 write_csr(dd, CCE_INT_MASK + (8 * (QSFP1_INT / 64)),
9509                           cce_int_mask);
9510         } else {
9511                 cce_int_mask &= ~((u64)1 << qsfp2_int_smask);
9512                 write_csr(dd, CCE_INT_MASK + (8 * (QSFP2_INT / 64)),
9513                           cce_int_mask);
9514         }
9515
9516         qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
9517         /* Clear current status to avoid spurious interrupts */
9518         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9519                   qsfp_mask);
9520         write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
9521                   qsfp_mask);
9522
9523         set_qsfp_int_n(ppd, 0);
9524
9525         /* Handle active low nature of INT_N and MODPRST_N pins */
9526         if (qsfp_mod_present(ppd))
9527                 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N;
9528         write_csr(dd,
9529                   dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT,
9530                   qsfp_mask);
9531 }
9532
9533 /*
9534  * Do a one-time initialize of the LCB block.
9535  */
9536 static void init_lcb(struct hfi1_devdata *dd)
9537 {
9538         /* simulator does not correctly handle LCB cclk loopback, skip */
9539         if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
9540                 return;
9541
9542         /* the DC has been reset earlier in the driver load */
9543
9544         /* set LCB for cclk loopback on the port */
9545         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
9546         write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
9547         write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
9548         write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
9549         write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
9550         write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
9551         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
9552 }
9553
9554 /*
9555  * Perform a test read on the QSFP.  Return 0 on success, -ERRNO
9556  * on error.
9557  */
9558 static int test_qsfp_read(struct hfi1_pportdata *ppd)
9559 {
9560         int ret;
9561         u8 status;
9562
9563         /*
9564          * Report success if not a QSFP or, if it is a QSFP, but the cable is
9565          * not present
9566          */
9567         if (ppd->port_type != PORT_TYPE_QSFP || !qsfp_mod_present(ppd))
9568                 return 0;
9569
9570         /* read byte 2, the status byte */
9571         ret = one_qsfp_read(ppd, ppd->dd->hfi1_id, 2, &status, 1);
9572         if (ret < 0)
9573                 return ret;
9574         if (ret != 1)
9575                 return -EIO;
9576
9577         return 0; /* success */
9578 }
9579
9580 /*
9581  * Values for QSFP retry.
9582  *
9583  * Give up after 10s (20 x 500ms).  The overall timeout was empirically
9584  * arrived at from experience on a large cluster.
9585  */
9586 #define MAX_QSFP_RETRIES 20
9587 #define QSFP_RETRY_WAIT 500 /* msec */
9588
9589 /*
9590  * Try a QSFP read.  If it fails, schedule a retry for later.
9591  * Called on first link activation after driver load.
9592  */
9593 static void try_start_link(struct hfi1_pportdata *ppd)
9594 {
9595         if (test_qsfp_read(ppd)) {
9596                 /* read failed */
9597                 if (ppd->qsfp_retry_count >= MAX_QSFP_RETRIES) {
9598                         dd_dev_err(ppd->dd, "QSFP not responding, giving up\n");
9599                         return;
9600                 }
9601                 dd_dev_info(ppd->dd,
9602                             "QSFP not responding, waiting and retrying %d\n",
9603                             (int)ppd->qsfp_retry_count);
9604                 ppd->qsfp_retry_count++;
9605                 queue_delayed_work(ppd->hfi1_wq, &ppd->start_link_work,
9606                                    msecs_to_jiffies(QSFP_RETRY_WAIT));
9607                 return;
9608         }
9609         ppd->qsfp_retry_count = 0;
9610
9611         start_link(ppd);
9612 }
9613
9614 /*
9615  * Workqueue function to start the link after a delay.
9616  */
9617 void handle_start_link(struct work_struct *work)
9618 {
9619         struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
9620                                                   start_link_work.work);
9621         try_start_link(ppd);
9622 }
9623
9624 int bringup_serdes(struct hfi1_pportdata *ppd)
9625 {
9626         struct hfi1_devdata *dd = ppd->dd;
9627         u64 guid;
9628         int ret;
9629
9630         if (HFI1_CAP_IS_KSET(EXTENDED_PSN))
9631                 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK);
9632
9633         guid = ppd->guids[HFI1_PORT_GUID_INDEX];
9634         if (!guid) {
9635                 if (dd->base_guid)
9636                         guid = dd->base_guid + ppd->port - 1;
9637                 ppd->guids[HFI1_PORT_GUID_INDEX] = guid;
9638         }
9639
9640         /* Set linkinit_reason on power up per OPA spec */
9641         ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP;
9642
9643         /* one-time init of the LCB */
9644         init_lcb(dd);
9645
9646         if (loopback) {
9647                 ret = init_loopback(dd);
9648                 if (ret < 0)
9649                         return ret;
9650         }
9651
9652         get_port_type(ppd);
9653         if (ppd->port_type == PORT_TYPE_QSFP) {
9654                 set_qsfp_int_n(ppd, 0);
9655                 wait_for_qsfp_init(ppd);
9656                 set_qsfp_int_n(ppd, 1);
9657         }
9658
9659         try_start_link(ppd);
9660         return 0;
9661 }
9662
9663 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd)
9664 {
9665         struct hfi1_devdata *dd = ppd->dd;
9666
9667         /*
9668          * Shut down the link and keep it down.   First turn off that the
9669          * driver wants to allow the link to be up (driver_link_ready).
9670          * Then make sure the link is not automatically restarted
9671          * (link_enabled).  Cancel any pending restart.  And finally
9672          * go offline.
9673          */
9674         ppd->driver_link_ready = 0;
9675         ppd->link_enabled = 0;
9676
9677         ppd->qsfp_retry_count = MAX_QSFP_RETRIES; /* prevent more retries */
9678         flush_delayed_work(&ppd->start_link_work);
9679         cancel_delayed_work_sync(&ppd->start_link_work);
9680
9681         ppd->offline_disabled_reason =
9682                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_SMA_DISABLED);
9683         set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SMA_DISABLED, 0,
9684                              OPA_LINKDOWN_REASON_SMA_DISABLED);
9685         set_link_state(ppd, HLS_DN_OFFLINE);
9686
9687         /* disable the port */
9688         clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
9689 }
9690
9691 static inline int init_cpu_counters(struct hfi1_devdata *dd)
9692 {
9693         struct hfi1_pportdata *ppd;
9694         int i;
9695
9696         ppd = (struct hfi1_pportdata *)(dd + 1);
9697         for (i = 0; i < dd->num_pports; i++, ppd++) {
9698                 ppd->ibport_data.rvp.rc_acks = NULL;
9699                 ppd->ibport_data.rvp.rc_qacks = NULL;
9700                 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
9701                 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
9702                 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
9703                 if (!ppd->ibport_data.rvp.rc_acks ||
9704                     !ppd->ibport_data.rvp.rc_delayed_comp ||
9705                     !ppd->ibport_data.rvp.rc_qacks)
9706                         return -ENOMEM;
9707         }
9708
9709         return 0;
9710 }
9711
9712 static const char * const pt_names[] = {
9713         "expected",
9714         "eager",
9715         "invalid"
9716 };
9717
9718 static const char *pt_name(u32 type)
9719 {
9720         return type >= ARRAY_SIZE(pt_names) ? "unknown" : pt_names[type];
9721 }
9722
9723 /*
9724  * index is the index into the receive array
9725  */
9726 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
9727                   u32 type, unsigned long pa, u16 order)
9728 {
9729         u64 reg;
9730         void __iomem *base = (dd->rcvarray_wc ? dd->rcvarray_wc :
9731                               (dd->kregbase + RCV_ARRAY));
9732
9733         if (!(dd->flags & HFI1_PRESENT))
9734                 goto done;
9735
9736         if (type == PT_INVALID) {
9737                 pa = 0;
9738         } else if (type > PT_INVALID) {
9739                 dd_dev_err(dd,
9740                            "unexpected receive array type %u for index %u, not handled\n",
9741                            type, index);
9742                 goto done;
9743         }
9744
9745         hfi1_cdbg(TID, "type %s, index 0x%x, pa 0x%lx, bsize 0x%lx",
9746                   pt_name(type), index, pa, (unsigned long)order);
9747
9748 #define RT_ADDR_SHIFT 12        /* 4KB kernel address boundary */
9749         reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9750                 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT
9751                 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK)
9752                                         << RCV_ARRAY_RT_ADDR_SHIFT;
9753         writeq(reg, base + (index * 8));
9754
9755         if (type == PT_EAGER)
9756                 /*
9757                  * Eager entries are written one-by-one so we have to push them
9758                  * after we write the entry.
9759                  */
9760                 flush_wc();
9761 done:
9762         return;
9763 }
9764
9765 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd)
9766 {
9767         struct hfi1_devdata *dd = rcd->dd;
9768         u32 i;
9769
9770         /* this could be optimized */
9771         for (i = rcd->eager_base; i < rcd->eager_base +
9772                      rcd->egrbufs.alloced; i++)
9773                 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9774
9775         for (i = rcd->expected_base;
9776                         i < rcd->expected_base + rcd->expected_count; i++)
9777                 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
9778 }
9779
9780 struct ib_header *hfi1_get_msgheader(
9781         struct hfi1_devdata *dd, __le32 *rhf_addr)
9782 {
9783         u32 offset = rhf_hdrq_offset(rhf_to_cpu(rhf_addr));
9784
9785         return (struct ib_header *)
9786                 (rhf_addr - dd->rhf_offset + offset);
9787 }
9788
9789 static const char * const ib_cfg_name_strings[] = {
9790         "HFI1_IB_CFG_LIDLMC",
9791         "HFI1_IB_CFG_LWID_DG_ENB",
9792         "HFI1_IB_CFG_LWID_ENB",
9793         "HFI1_IB_CFG_LWID",
9794         "HFI1_IB_CFG_SPD_ENB",
9795         "HFI1_IB_CFG_SPD",
9796         "HFI1_IB_CFG_RXPOL_ENB",
9797         "HFI1_IB_CFG_LREV_ENB",
9798         "HFI1_IB_CFG_LINKLATENCY",
9799         "HFI1_IB_CFG_HRTBT",
9800         "HFI1_IB_CFG_OP_VLS",
9801         "HFI1_IB_CFG_VL_HIGH_CAP",
9802         "HFI1_IB_CFG_VL_LOW_CAP",
9803         "HFI1_IB_CFG_OVERRUN_THRESH",
9804         "HFI1_IB_CFG_PHYERR_THRESH",
9805         "HFI1_IB_CFG_LINKDEFAULT",
9806         "HFI1_IB_CFG_PKEYS",
9807         "HFI1_IB_CFG_MTU",
9808         "HFI1_IB_CFG_LSTATE",
9809         "HFI1_IB_CFG_VL_HIGH_LIMIT",
9810         "HFI1_IB_CFG_PMA_TICKS",
9811         "HFI1_IB_CFG_PORT"
9812 };
9813
9814 static const char *ib_cfg_name(int which)
9815 {
9816         if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings))
9817                 return "invalid";
9818         return ib_cfg_name_strings[which];
9819 }
9820
9821 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which)
9822 {
9823         struct hfi1_devdata *dd = ppd->dd;
9824         int val = 0;
9825
9826         switch (which) {
9827         case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */
9828                 val = ppd->link_width_enabled;
9829                 break;
9830         case HFI1_IB_CFG_LWID: /* currently active Link-width */
9831                 val = ppd->link_width_active;
9832                 break;
9833         case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
9834                 val = ppd->link_speed_enabled;
9835                 break;
9836         case HFI1_IB_CFG_SPD: /* current Link speed */
9837                 val = ppd->link_speed_active;
9838                 break;
9839
9840         case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */
9841         case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */
9842         case HFI1_IB_CFG_LINKLATENCY:
9843                 goto unimplemented;
9844
9845         case HFI1_IB_CFG_OP_VLS:
9846                 val = ppd->vls_operational;
9847                 break;
9848         case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */
9849                 val = VL_ARB_HIGH_PRIO_TABLE_SIZE;
9850                 break;
9851         case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */
9852                 val = VL_ARB_LOW_PRIO_TABLE_SIZE;
9853                 break;
9854         case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
9855                 val = ppd->overrun_threshold;
9856                 break;
9857         case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
9858                 val = ppd->phy_error_threshold;
9859                 break;
9860         case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
9861                 val = dd->link_default;
9862                 break;
9863
9864         case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */
9865         case HFI1_IB_CFG_PMA_TICKS:
9866         default:
9867 unimplemented:
9868                 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
9869                         dd_dev_info(
9870                                 dd,
9871                                 "%s: which %s: not implemented\n",
9872                                 __func__,
9873                                 ib_cfg_name(which));
9874                 break;
9875         }
9876
9877         return val;
9878 }
9879
9880 /*
9881  * The largest MAD packet size.
9882  */
9883 #define MAX_MAD_PACKET 2048
9884
9885 /*
9886  * Return the maximum header bytes that can go on the _wire_
9887  * for this device. This count includes the ICRC which is
9888  * not part of the packet held in memory but it is appended
9889  * by the HW.
9890  * This is dependent on the device's receive header entry size.
9891  * HFI allows this to be set per-receive context, but the
9892  * driver presently enforces a global value.
9893  */
9894 u32 lrh_max_header_bytes(struct hfi1_devdata *dd)
9895 {
9896         /*
9897          * The maximum non-payload (MTU) bytes in LRH.PktLen are
9898          * the Receive Header Entry Size minus the PBC (or RHF) size
9899          * plus one DW for the ICRC appended by HW.
9900          *
9901          * dd->rcd[0].rcvhdrqentsize is in DW.
9902          * We use rcd[0] as all context will have the same value. Also,
9903          * the first kernel context would have been allocated by now so
9904          * we are guaranteed a valid value.
9905          */
9906         return (dd->rcd[0]->rcvhdrqentsize - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
9907 }
9908
9909 /*
9910  * Set Send Length
9911  * @ppd - per port data
9912  *
9913  * Set the MTU by limiting how many DWs may be sent.  The SendLenCheck*
9914  * registers compare against LRH.PktLen, so use the max bytes included
9915  * in the LRH.
9916  *
9917  * This routine changes all VL values except VL15, which it maintains at
9918  * the same value.
9919  */
9920 static void set_send_length(struct hfi1_pportdata *ppd)
9921 {
9922         struct hfi1_devdata *dd = ppd->dd;
9923         u32 max_hb = lrh_max_header_bytes(dd), dcmtu;
9924         u32 maxvlmtu = dd->vld[15].mtu;
9925         u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2)
9926                               & SEND_LEN_CHECK1_LEN_VL15_MASK) <<
9927                 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
9928         int i, j;
9929         u32 thres;
9930
9931         for (i = 0; i < ppd->vls_supported; i++) {
9932                 if (dd->vld[i].mtu > maxvlmtu)
9933                         maxvlmtu = dd->vld[i].mtu;
9934                 if (i <= 3)
9935                         len1 |= (((dd->vld[i].mtu + max_hb) >> 2)
9936                                  & SEND_LEN_CHECK0_LEN_VL0_MASK) <<
9937                                 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT);
9938                 else
9939                         len2 |= (((dd->vld[i].mtu + max_hb) >> 2)
9940                                  & SEND_LEN_CHECK1_LEN_VL4_MASK) <<
9941                                 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT);
9942         }
9943         write_csr(dd, SEND_LEN_CHECK0, len1);
9944         write_csr(dd, SEND_LEN_CHECK1, len2);
9945         /* adjust kernel credit return thresholds based on new MTUs */
9946         /* all kernel receive contexts have the same hdrqentsize */
9947         for (i = 0; i < ppd->vls_supported; i++) {
9948                 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50),
9949                             sc_mtu_to_threshold(dd->vld[i].sc,
9950                                                 dd->vld[i].mtu,
9951                                                 dd->rcd[0]->rcvhdrqentsize));
9952                 for (j = 0; j < INIT_SC_PER_VL; j++)
9953                         sc_set_cr_threshold(
9954                                         pio_select_send_context_vl(dd, j, i),
9955                                             thres);
9956         }
9957         thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50),
9958                     sc_mtu_to_threshold(dd->vld[15].sc,
9959                                         dd->vld[15].mtu,
9960                                         dd->rcd[0]->rcvhdrqentsize));
9961         sc_set_cr_threshold(dd->vld[15].sc, thres);
9962
9963         /* Adjust maximum MTU for the port in DC */
9964         dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 :
9965                 (ilog2(maxvlmtu >> 8) + 1);
9966         len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
9967         len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK;
9968         len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) <<
9969                 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
9970         write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
9971 }
9972
9973 static void set_lidlmc(struct hfi1_pportdata *ppd)
9974 {
9975         int i;
9976         u64 sreg = 0;
9977         struct hfi1_devdata *dd = ppd->dd;
9978         u32 mask = ~((1U << ppd->lmc) - 1);
9979         u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
9980
9981         c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
9982                 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK);
9983         c1 |= ((ppd->lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK)
9984                         << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) |
9985               ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK)
9986                         << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT);
9987         write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
9988
9989         /*
9990          * Iterate over all the send contexts and set their SLID check
9991          */
9992         sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) <<
9993                         SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
9994                (((ppd->lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) <<
9995                         SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
9996
9997         for (i = 0; i < dd->chip_send_contexts; i++) {
9998                 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x",
9999                           i, (u32)sreg);
10000                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg);
10001         }
10002
10003         /* Now we have to do the same thing for the sdma engines */
10004         sdma_update_lmc(dd, mask, ppd->lid);
10005 }
10006
10007 static int wait_phy_linkstate(struct hfi1_devdata *dd, u32 state, u32 msecs)
10008 {
10009         unsigned long timeout;
10010         u32 curr_state;
10011
10012         timeout = jiffies + msecs_to_jiffies(msecs);
10013         while (1) {
10014                 curr_state = read_physical_state(dd);
10015                 if (curr_state == state)
10016                         break;
10017                 if (time_after(jiffies, timeout)) {
10018                         dd_dev_err(dd,
10019                                    "timeout waiting for phy link state 0x%x, current state is 0x%x\n",
10020                                    state, curr_state);
10021                         return -ETIMEDOUT;
10022                 }
10023                 usleep_range(1950, 2050); /* sleep 2ms-ish */
10024         }
10025
10026         return 0;
10027 }
10028
10029 static const char *state_completed_string(u32 completed)
10030 {
10031         static const char * const state_completed[] = {
10032                 "EstablishComm",
10033                 "OptimizeEQ",
10034                 "VerifyCap"
10035         };
10036
10037         if (completed < ARRAY_SIZE(state_completed))
10038                 return state_completed[completed];
10039
10040         return "unknown";
10041 }
10042
10043 static const char all_lanes_dead_timeout_expired[] =
10044         "All lanes were inactive – was the interconnect media removed?";
10045 static const char tx_out_of_policy[] =
10046         "Passing lanes on local port do not meet the local link width policy";
10047 static const char no_state_complete[] =
10048         "State timeout occurred before link partner completed the state";
10049 static const char * const state_complete_reasons[] = {
10050         [0x00] = "Reason unknown",
10051         [0x01] = "Link was halted by driver, refer to LinkDownReason",
10052         [0x02] = "Link partner reported failure",
10053         [0x10] = "Unable to achieve frame sync on any lane",
10054         [0x11] =
10055           "Unable to find a common bit rate with the link partner",
10056         [0x12] =
10057           "Unable to achieve frame sync on sufficient lanes to meet the local link width policy",
10058         [0x13] =
10059           "Unable to identify preset equalization on sufficient lanes to meet the local link width policy",
10060         [0x14] = no_state_complete,
10061         [0x15] =
10062           "State timeout occurred before link partner identified equalization presets",
10063         [0x16] =
10064           "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy",
10065         [0x17] = tx_out_of_policy,
10066         [0x20] = all_lanes_dead_timeout_expired,
10067         [0x21] =
10068           "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy",
10069         [0x22] = no_state_complete,
10070         [0x23] =
10071           "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy",
10072         [0x24] = tx_out_of_policy,
10073         [0x30] = all_lanes_dead_timeout_expired,
10074         [0x31] =
10075           "State timeout occurred waiting for host to process received frames",
10076         [0x32] = no_state_complete,
10077         [0x33] =
10078           "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
10079         [0x34] = tx_out_of_policy,
10080 };
10081
10082 static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd,
10083                                                      u32 code)
10084 {
10085         const char *str = NULL;
10086
10087         if (code < ARRAY_SIZE(state_complete_reasons))
10088                 str = state_complete_reasons[code];
10089
10090         if (str)
10091                 return str;
10092         return "Reserved";
10093 }
10094
10095 /* describe the given last state complete frame */
10096 static void decode_state_complete(struct hfi1_pportdata *ppd, u32 frame,
10097                                   const char *prefix)
10098 {
10099         struct hfi1_devdata *dd = ppd->dd;
10100         u32 success;
10101         u32 state;
10102         u32 reason;
10103         u32 lanes;
10104
10105         /*
10106          * Decode frame:
10107          *  [ 0: 0] - success
10108          *  [ 3: 1] - state
10109          *  [ 7: 4] - next state timeout
10110          *  [15: 8] - reason code
10111          *  [31:16] - lanes
10112          */
10113         success = frame & 0x1;
10114         state = (frame >> 1) & 0x7;
10115         reason = (frame >> 8) & 0xff;
10116         lanes = (frame >> 16) & 0xffff;
10117
10118         dd_dev_err(dd, "Last %s LNI state complete frame 0x%08x:\n",
10119                    prefix, frame);
10120         dd_dev_err(dd, "    last reported state state: %s (0x%x)\n",
10121                    state_completed_string(state), state);
10122         dd_dev_err(dd, "    state successfully completed: %s\n",
10123                    success ? "yes" : "no");
10124         dd_dev_err(dd, "    fail reason 0x%x: %s\n",
10125                    reason, state_complete_reason_code_string(ppd, reason));
10126         dd_dev_err(dd, "    passing lane mask: 0x%x", lanes);
10127 }
10128
10129 /*
10130  * Read the last state complete frames and explain them.  This routine
10131  * expects to be called if the link went down during link negotiation
10132  * and initialization (LNI).  That is, anywhere between polling and link up.
10133  */
10134 static void check_lni_states(struct hfi1_pportdata *ppd)
10135 {
10136         u32 last_local_state;
10137         u32 last_remote_state;
10138
10139         read_last_local_state(ppd->dd, &last_local_state);
10140         read_last_remote_state(ppd->dd, &last_remote_state);
10141
10142         /*
10143          * Don't report anything if there is nothing to report.  A value of
10144          * 0 means the link was taken down while polling and there was no
10145          * training in-process.
10146          */
10147         if (last_local_state == 0 && last_remote_state == 0)
10148                 return;
10149
10150         decode_state_complete(ppd, last_local_state, "transmitted");
10151         decode_state_complete(ppd, last_remote_state, "received");
10152 }
10153
10154 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */
10155 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms)
10156 {
10157         u64 reg;
10158         unsigned long timeout;
10159
10160         /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
10161         timeout = jiffies + msecs_to_jiffies(wait_ms);
10162         while (1) {
10163                 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);
10164                 if (reg)
10165                         break;
10166                 if (time_after(jiffies, timeout)) {
10167                         dd_dev_err(dd,
10168                                    "timeout waiting for LINK_TRANSFER_ACTIVE\n");
10169                         return -ETIMEDOUT;
10170                 }
10171                 udelay(2);
10172         }
10173         return 0;
10174 }
10175
10176 /* called when the logical link state is not down as it should be */
10177 static void force_logical_link_state_down(struct hfi1_pportdata *ppd)
10178 {
10179         struct hfi1_devdata *dd = ppd->dd;
10180
10181         /*
10182          * Bring link up in LCB loopback
10183          */
10184         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10185         write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
10186                   DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
10187
10188         write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
10189         write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0);
10190         write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
10191         write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2);
10192
10193         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
10194         (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET);
10195         udelay(3);
10196         write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1);
10197         write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
10198
10199         wait_link_transfer_active(dd, 100);
10200
10201         /*
10202          * Bring the link down again.
10203          */
10204         write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10205         write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0);
10206         write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0);
10207
10208         /* call again to adjust ppd->statusp, if needed */
10209         get_logical_state(ppd);
10210 }
10211
10212 /*
10213  * Helper for set_link_state().  Do not call except from that routine.
10214  * Expects ppd->hls_mutex to be held.
10215  *
10216  * @rem_reason value to be sent to the neighbor
10217  *
10218  * LinkDownReasons only set if transition succeeds.
10219  */
10220 static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason)
10221 {
10222         struct hfi1_devdata *dd = ppd->dd;
10223         u32 pstate, previous_state;
10224         int ret;
10225         int do_transition;
10226         int do_wait;
10227
10228         update_lcb_cache(dd);
10229
10230         previous_state = ppd->host_link_state;
10231         ppd->host_link_state = HLS_GOING_OFFLINE;
10232         pstate = read_physical_state(dd);
10233         if (pstate == PLS_OFFLINE) {
10234                 do_transition = 0;      /* in right state */
10235                 do_wait = 0;            /* ...no need to wait */
10236         } else if ((pstate & 0xf0) == PLS_OFFLINE) {
10237                 do_transition = 0;      /* in an offline transient state */
10238                 do_wait = 1;            /* ...wait for it to settle */
10239         } else {
10240                 do_transition = 1;      /* need to move to offline */
10241                 do_wait = 1;            /* ...will need to wait */
10242         }
10243
10244         if (do_transition) {
10245                 ret = set_physical_link_state(dd,
10246                                               (rem_reason << 8) | PLS_OFFLINE);
10247
10248                 if (ret != HCMD_SUCCESS) {
10249                         dd_dev_err(dd,
10250                                    "Failed to transition to Offline link state, return %d\n",
10251                                    ret);
10252                         return -EINVAL;
10253                 }
10254                 if (ppd->offline_disabled_reason ==
10255                                 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))
10256                         ppd->offline_disabled_reason =
10257                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
10258         }
10259
10260         if (do_wait) {
10261                 /* it can take a while for the link to go down */
10262                 ret = wait_phy_linkstate(dd, PLS_OFFLINE, 10000);
10263                 if (ret < 0)
10264                         return ret;
10265         }
10266
10267         /*
10268          * Now in charge of LCB - must be after the physical state is
10269          * offline.quiet and before host_link_state is changed.
10270          */
10271         set_host_lcb_access(dd);
10272         write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
10273
10274         /* make sure the logical state is also down */
10275         ret = wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000);
10276         if (ret)
10277                 force_logical_link_state_down(ppd);
10278
10279         ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
10280
10281         if (ppd->port_type == PORT_TYPE_QSFP &&
10282             ppd->qsfp_info.limiting_active &&
10283             qsfp_mod_present(ppd)) {
10284                 int ret;
10285
10286                 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT);
10287                 if (ret == 0) {
10288                         set_qsfp_tx(ppd, 0);
10289                         release_chip_resource(dd, qsfp_resource(dd));
10290                 } else {
10291                         /* not fatal, but should warn */
10292                         dd_dev_err(dd,
10293                                    "Unable to acquire lock to turn off QSFP TX\n");
10294                 }
10295         }
10296
10297         /*
10298          * The LNI has a mandatory wait time after the physical state
10299          * moves to Offline.Quiet.  The wait time may be different
10300          * depending on how the link went down.  The 8051 firmware
10301          * will observe the needed wait time and only move to ready
10302          * when that is completed.  The largest of the quiet timeouts
10303          * is 6s, so wait that long and then at least 0.5s more for
10304          * other transitions, and another 0.5s for a buffer.
10305          */
10306         ret = wait_fm_ready(dd, 7000);
10307         if (ret) {
10308                 dd_dev_err(dd,
10309                            "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
10310                 /* state is really offline, so make it so */
10311                 ppd->host_link_state = HLS_DN_OFFLINE;
10312                 return ret;
10313         }
10314
10315         /*
10316          * The state is now offline and the 8051 is ready to accept host
10317          * requests.
10318          *      - change our state
10319          *      - notify others if we were previously in a linkup state
10320          */
10321         ppd->host_link_state = HLS_DN_OFFLINE;
10322         if (previous_state & HLS_UP) {
10323                 /* went down while link was up */
10324                 handle_linkup_change(dd, 0);
10325         } else if (previous_state
10326                         & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
10327                 /* went down while attempting link up */
10328                 check_lni_states(ppd);
10329         }
10330
10331         /* the active link width (downgrade) is 0 on link down */
10332         ppd->link_width_active = 0;
10333         ppd->link_width_downgrade_tx_active = 0;
10334         ppd->link_width_downgrade_rx_active = 0;
10335         ppd->current_egress_rate = 0;
10336         return 0;
10337 }
10338
10339 /* return the link state name */
10340 static const char *link_state_name(u32 state)
10341 {
10342         const char *name;
10343         int n = ilog2(state);
10344         static const char * const names[] = {
10345                 [__HLS_UP_INIT_BP]       = "INIT",
10346                 [__HLS_UP_ARMED_BP]      = "ARMED",
10347                 [__HLS_UP_ACTIVE_BP]     = "ACTIVE",
10348                 [__HLS_DN_DOWNDEF_BP]    = "DOWNDEF",
10349                 [__HLS_DN_POLL_BP]       = "POLL",
10350                 [__HLS_DN_DISABLE_BP]    = "DISABLE",
10351                 [__HLS_DN_OFFLINE_BP]    = "OFFLINE",
10352                 [__HLS_VERIFY_CAP_BP]    = "VERIFY_CAP",
10353                 [__HLS_GOING_UP_BP]      = "GOING_UP",
10354                 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE",
10355                 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN"
10356         };
10357
10358         name = n < ARRAY_SIZE(names) ? names[n] : NULL;
10359         return name ? name : "unknown";
10360 }
10361
10362 /* return the link state reason name */
10363 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state)
10364 {
10365         if (state == HLS_UP_INIT) {
10366                 switch (ppd->linkinit_reason) {
10367                 case OPA_LINKINIT_REASON_LINKUP:
10368                         return "(LINKUP)";
10369                 case OPA_LINKINIT_REASON_FLAPPING:
10370                         return "(FLAPPING)";
10371                 case OPA_LINKINIT_OUTSIDE_POLICY:
10372                         return "(OUTSIDE_POLICY)";
10373                 case OPA_LINKINIT_QUARANTINED:
10374                         return "(QUARANTINED)";
10375                 case OPA_LINKINIT_INSUFIC_CAPABILITY:
10376                         return "(INSUFIC_CAPABILITY)";
10377                 default:
10378                         break;
10379                 }
10380         }
10381         return "";
10382 }
10383
10384 /*
10385  * driver_physical_state - convert the driver's notion of a port's
10386  * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
10387  * Return -1 (converted to a u32) to indicate error.
10388  */
10389 u32 driver_physical_state(struct hfi1_pportdata *ppd)
10390 {
10391         switch (ppd->host_link_state) {
10392         case HLS_UP_INIT:
10393         case HLS_UP_ARMED:
10394         case HLS_UP_ACTIVE:
10395                 return IB_PORTPHYSSTATE_LINKUP;
10396         case HLS_DN_POLL:
10397                 return IB_PORTPHYSSTATE_POLLING;
10398         case HLS_DN_DISABLE:
10399                 return IB_PORTPHYSSTATE_DISABLED;
10400         case HLS_DN_OFFLINE:
10401                 return OPA_PORTPHYSSTATE_OFFLINE;
10402         case HLS_VERIFY_CAP:
10403                 return IB_PORTPHYSSTATE_POLLING;
10404         case HLS_GOING_UP:
10405                 return IB_PORTPHYSSTATE_POLLING;
10406         case HLS_GOING_OFFLINE:
10407                 return OPA_PORTPHYSSTATE_OFFLINE;
10408         case HLS_LINK_COOLDOWN:
10409                 return OPA_PORTPHYSSTATE_OFFLINE;
10410         case HLS_DN_DOWNDEF:
10411         default:
10412                 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10413                            ppd->host_link_state);
10414                 return  -1;
10415         }
10416 }
10417
10418 /*
10419  * driver_logical_state - convert the driver's notion of a port's
10420  * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
10421  * (converted to a u32) to indicate error.
10422  */
10423 u32 driver_logical_state(struct hfi1_pportdata *ppd)
10424 {
10425         if (ppd->host_link_state && (ppd->host_link_state & HLS_DOWN))
10426                 return IB_PORT_DOWN;
10427
10428         switch (ppd->host_link_state & HLS_UP) {
10429         case HLS_UP_INIT:
10430                 return IB_PORT_INIT;
10431         case HLS_UP_ARMED:
10432                 return IB_PORT_ARMED;
10433         case HLS_UP_ACTIVE:
10434                 return IB_PORT_ACTIVE;
10435         default:
10436                 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10437                            ppd->host_link_state);
10438         return -1;
10439         }
10440 }
10441
10442 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
10443                           u8 neigh_reason, u8 rem_reason)
10444 {
10445         if (ppd->local_link_down_reason.latest == 0 &&
10446             ppd->neigh_link_down_reason.latest == 0) {
10447                 ppd->local_link_down_reason.latest = lcl_reason;
10448                 ppd->neigh_link_down_reason.latest = neigh_reason;
10449                 ppd->remote_link_down_reason = rem_reason;
10450         }
10451 }
10452
10453 /*
10454  * Change the physical and/or logical link state.
10455  *
10456  * Do not call this routine while inside an interrupt.  It contains
10457  * calls to routines that can take multiple seconds to finish.
10458  *
10459  * Returns 0 on success, -errno on failure.
10460  */
10461 int set_link_state(struct hfi1_pportdata *ppd, u32 state)
10462 {
10463         struct hfi1_devdata *dd = ppd->dd;
10464         struct ib_event event = {.device = NULL};
10465         int ret1, ret = 0;
10466         int orig_new_state, poll_bounce;
10467
10468         mutex_lock(&ppd->hls_lock);
10469
10470         orig_new_state = state;
10471         if (state == HLS_DN_DOWNDEF)
10472                 state = dd->link_default;
10473
10474         /* interpret poll -> poll as a link bounce */
10475         poll_bounce = ppd->host_link_state == HLS_DN_POLL &&
10476                       state == HLS_DN_POLL;
10477
10478         dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__,
10479                     link_state_name(ppd->host_link_state),
10480                     link_state_name(orig_new_state),
10481                     poll_bounce ? "(bounce) " : "",
10482                     link_state_reason_name(ppd, state));
10483
10484         /*
10485          * If we're going to a (HLS_*) link state that implies the logical
10486          * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10487          * reset is_sm_config_started to 0.
10488          */
10489         if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE)))
10490                 ppd->is_sm_config_started = 0;
10491
10492         /*
10493          * Do nothing if the states match.  Let a poll to poll link bounce
10494          * go through.
10495          */
10496         if (ppd->host_link_state == state && !poll_bounce)
10497                 goto done;
10498
10499         switch (state) {
10500         case HLS_UP_INIT:
10501                 if (ppd->host_link_state == HLS_DN_POLL &&
10502                     (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) {
10503                         /*
10504                          * Quick link up jumps from polling to here.
10505                          *
10506                          * Whether in normal or loopback mode, the
10507                          * simulator jumps from polling to link up.
10508                          * Accept that here.
10509                          */
10510                         /* OK */
10511                 } else if (ppd->host_link_state != HLS_GOING_UP) {
10512                         goto unexpected;
10513                 }
10514
10515                 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000);
10516                 if (ret) {
10517                         dd_dev_err(dd,
10518                                    "%s: logical state did not change to INIT\n",
10519                                    __func__);
10520                 } else {
10521                         /* clear old transient LINKINIT_REASON code */
10522                         if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR)
10523                                 ppd->linkinit_reason =
10524                                         OPA_LINKINIT_REASON_LINKUP;
10525
10526                         /* enable the port */
10527                         add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
10528
10529                         handle_linkup_change(dd, 1);
10530                         ppd->host_link_state = HLS_UP_INIT;
10531                 }
10532                 break;
10533         case HLS_UP_ARMED:
10534                 if (ppd->host_link_state != HLS_UP_INIT)
10535                         goto unexpected;
10536
10537                 ppd->host_link_state = HLS_UP_ARMED;
10538                 set_logical_state(dd, LSTATE_ARMED);
10539                 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000);
10540                 if (ret) {
10541                         /* logical state didn't change, stay at init */
10542                         ppd->host_link_state = HLS_UP_INIT;
10543                         dd_dev_err(dd,
10544                                    "%s: logical state did not change to ARMED\n",
10545                                    __func__);
10546                 }
10547                 /*
10548                  * The simulator does not currently implement SMA messages,
10549                  * so neighbor_normal is not set.  Set it here when we first
10550                  * move to Armed.
10551                  */
10552                 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
10553                         ppd->neighbor_normal = 1;
10554                 break;
10555         case HLS_UP_ACTIVE:
10556                 if (ppd->host_link_state != HLS_UP_ARMED)
10557                         goto unexpected;
10558
10559                 ppd->host_link_state = HLS_UP_ACTIVE;
10560                 set_logical_state(dd, LSTATE_ACTIVE);
10561                 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000);
10562                 if (ret) {
10563                         /* logical state didn't change, stay at armed */
10564                         ppd->host_link_state = HLS_UP_ARMED;
10565                         dd_dev_err(dd,
10566                                    "%s: logical state did not change to ACTIVE\n",
10567                                    __func__);
10568                 } else {
10569                         /* tell all engines to go running */
10570                         sdma_all_running(dd);
10571
10572                         /* Signal the IB layer that the port has went active */
10573                         event.device = &dd->verbs_dev.rdi.ibdev;
10574                         event.element.port_num = ppd->port;
10575                         event.event = IB_EVENT_PORT_ACTIVE;
10576                 }
10577                 break;
10578         case HLS_DN_POLL:
10579                 if ((ppd->host_link_state == HLS_DN_DISABLE ||
10580                      ppd->host_link_state == HLS_DN_OFFLINE) &&
10581                     dd->dc_shutdown)
10582                         dc_start(dd);
10583                 /* Hand LED control to the DC */
10584                 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
10585
10586                 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10587                         u8 tmp = ppd->link_enabled;
10588
10589                         ret = goto_offline(ppd, ppd->remote_link_down_reason);
10590                         if (ret) {
10591                                 ppd->link_enabled = tmp;
10592                                 break;
10593                         }
10594                         ppd->remote_link_down_reason = 0;
10595
10596                         if (ppd->driver_link_ready)
10597                                 ppd->link_enabled = 1;
10598                 }
10599
10600                 set_all_slowpath(ppd->dd);
10601                 ret = set_local_link_attributes(ppd);
10602                 if (ret)
10603                         break;
10604
10605                 ppd->port_error_action = 0;
10606                 ppd->host_link_state = HLS_DN_POLL;
10607
10608                 if (quick_linkup) {
10609                         /* quick linkup does not go into polling */
10610                         ret = do_quick_linkup(dd);
10611                 } else {
10612                         ret1 = set_physical_link_state(dd, PLS_POLLING);
10613                         if (ret1 != HCMD_SUCCESS) {
10614                                 dd_dev_err(dd,
10615                                            "Failed to transition to Polling link state, return 0x%x\n",
10616                                            ret1);
10617                                 ret = -EINVAL;
10618                         }
10619                 }
10620                 ppd->offline_disabled_reason =
10621                         HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE);
10622                 /*
10623                  * If an error occurred above, go back to offline.  The
10624                  * caller may reschedule another attempt.
10625                  */
10626                 if (ret)
10627                         goto_offline(ppd, 0);
10628                 break;
10629         case HLS_DN_DISABLE:
10630                 /* link is disabled */
10631                 ppd->link_enabled = 0;
10632
10633                 /* allow any state to transition to disabled */
10634
10635                 /* must transition to offline first */
10636                 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10637                         ret = goto_offline(ppd, ppd->remote_link_down_reason);
10638                         if (ret)
10639                                 break;
10640                         ppd->remote_link_down_reason = 0;
10641                 }
10642
10643                 if (!dd->dc_shutdown) {
10644                         ret1 = set_physical_link_state(dd, PLS_DISABLED);
10645                         if (ret1 != HCMD_SUCCESS) {
10646                                 dd_dev_err(dd,
10647                                            "Failed to transition to Disabled link state, return 0x%x\n",
10648                                            ret1);
10649                                 ret = -EINVAL;
10650                                 break;
10651                         }
10652                         dc_shutdown(dd);
10653                 }
10654                 ppd->host_link_state = HLS_DN_DISABLE;
10655                 break;
10656         case HLS_DN_OFFLINE:
10657                 if (ppd->host_link_state == HLS_DN_DISABLE)
10658                         dc_start(dd);
10659
10660                 /* allow any state to transition to offline */
10661                 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10662                 if (!ret)
10663                         ppd->remote_link_down_reason = 0;
10664                 break;
10665         case HLS_VERIFY_CAP:
10666                 if (ppd->host_link_state != HLS_DN_POLL)
10667                         goto unexpected;
10668                 ppd->host_link_state = HLS_VERIFY_CAP;
10669                 break;
10670         case HLS_GOING_UP:
10671                 if (ppd->host_link_state != HLS_VERIFY_CAP)
10672                         goto unexpected;
10673
10674                 ret1 = set_physical_link_state(dd, PLS_LINKUP);
10675                 if (ret1 != HCMD_SUCCESS) {
10676                         dd_dev_err(dd,
10677                                    "Failed to transition to link up state, return 0x%x\n",
10678                                    ret1);
10679                         ret = -EINVAL;
10680                         break;
10681                 }
10682                 ppd->host_link_state = HLS_GOING_UP;
10683                 break;
10684
10685         case HLS_GOING_OFFLINE:         /* transient within goto_offline() */
10686         case HLS_LINK_COOLDOWN:         /* transient within goto_offline() */
10687         default:
10688                 dd_dev_info(dd, "%s: state 0x%x: not supported\n",
10689                             __func__, state);
10690                 ret = -EINVAL;
10691                 break;
10692         }
10693
10694         goto done;
10695
10696 unexpected:
10697         dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n",
10698                    __func__, link_state_name(ppd->host_link_state),
10699                    link_state_name(state));
10700         ret = -EINVAL;
10701
10702 done:
10703         mutex_unlock(&ppd->hls_lock);
10704
10705         if (event.device)
10706                 ib_dispatch_event(&event);
10707
10708         return ret;
10709 }
10710
10711 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val)
10712 {
10713         u64 reg;
10714         int ret = 0;
10715
10716         switch (which) {
10717         case HFI1_IB_CFG_LIDLMC:
10718                 set_lidlmc(ppd);
10719                 break;
10720         case HFI1_IB_CFG_VL_HIGH_LIMIT:
10721                 /*
10722                  * The VL Arbitrator high limit is sent in units of 4k
10723                  * bytes, while HFI stores it in units of 64 bytes.
10724                  */
10725                 val *= 4096 / 64;
10726                 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK)
10727                         << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT;
10728                 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
10729                 break;
10730         case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
10731                 /* HFI only supports POLL as the default link down state */
10732                 if (val != HLS_DN_POLL)
10733                         ret = -EINVAL;
10734                 break;
10735         case HFI1_IB_CFG_OP_VLS:
10736                 if (ppd->vls_operational != val) {
10737                         ppd->vls_operational = val;
10738                         if (!ppd->port)
10739                                 ret = -EINVAL;
10740                 }
10741                 break;
10742         /*
10743          * For link width, link width downgrade, and speed enable, always AND
10744          * the setting with what is actually supported.  This has two benefits.
10745          * First, enabled can't have unsupported values, no matter what the
10746          * SM or FM might want.  Second, the ALL_SUPPORTED wildcards that mean
10747          * "fill in with your supported value" have all the bits in the
10748          * field set, so simply ANDing with supported has the desired result.
10749          */
10750         case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */
10751                 ppd->link_width_enabled = val & ppd->link_width_supported;
10752                 break;
10753         case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */
10754                 ppd->link_width_downgrade_enabled =
10755                                 val & ppd->link_width_downgrade_supported;
10756                 break;
10757         case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
10758                 ppd->link_speed_enabled = val & ppd->link_speed_supported;
10759                 break;
10760         case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
10761                 /*
10762                  * HFI does not follow IB specs, save this value
10763                  * so we can report it, if asked.
10764                  */
10765                 ppd->overrun_threshold = val;
10766                 break;
10767         case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
10768                 /*
10769                  * HFI does not follow IB specs, save this value
10770                  * so we can report it, if asked.
10771                  */
10772                 ppd->phy_error_threshold = val;
10773                 break;
10774
10775         case HFI1_IB_CFG_MTU:
10776                 set_send_length(ppd);
10777                 break;
10778
10779         case HFI1_IB_CFG_PKEYS:
10780                 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
10781                         set_partition_keys(ppd);
10782                 break;
10783
10784         default:
10785                 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
10786                         dd_dev_info(ppd->dd,
10787                                     "%s: which %s, val 0x%x: not implemented\n",
10788                                     __func__, ib_cfg_name(which), val);
10789                 break;
10790         }
10791         return ret;
10792 }
10793
10794 /* begin functions related to vl arbitration table caching */
10795 static void init_vl_arb_caches(struct hfi1_pportdata *ppd)
10796 {
10797         int i;
10798
10799         BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10800                         VL_ARB_LOW_PRIO_TABLE_SIZE);
10801         BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
10802                         VL_ARB_HIGH_PRIO_TABLE_SIZE);
10803
10804         /*
10805          * Note that we always return values directly from the
10806          * 'vl_arb_cache' (and do no CSR reads) in response to a
10807          * 'Get(VLArbTable)'. This is obviously correct after a
10808          * 'Set(VLArbTable)', since the cache will then be up to
10809          * date. But it's also correct prior to any 'Set(VLArbTable)'
10810          * since then both the cache, and the relevant h/w registers
10811          * will be zeroed.
10812          */
10813
10814         for (i = 0; i < MAX_PRIO_TABLE; i++)
10815                 spin_lock_init(&ppd->vl_arb_cache[i].lock);
10816 }
10817
10818 /*
10819  * vl_arb_lock_cache
10820  *
10821  * All other vl_arb_* functions should be called only after locking
10822  * the cache.
10823  */
10824 static inline struct vl_arb_cache *
10825 vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx)
10826 {
10827         if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE)
10828                 return NULL;
10829         spin_lock(&ppd->vl_arb_cache[idx].lock);
10830         return &ppd->vl_arb_cache[idx];
10831 }
10832
10833 static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx)
10834 {
10835         spin_unlock(&ppd->vl_arb_cache[idx].lock);
10836 }
10837
10838 static void vl_arb_get_cache(struct vl_arb_cache *cache,
10839                              struct ib_vl_weight_elem *vl)
10840 {
10841         memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl));
10842 }
10843
10844 static void vl_arb_set_cache(struct vl_arb_cache *cache,
10845                              struct ib_vl_weight_elem *vl)
10846 {
10847         memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10848 }
10849
10850 static int vl_arb_match_cache(struct vl_arb_cache *cache,
10851                               struct ib_vl_weight_elem *vl)
10852 {
10853         return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
10854 }
10855
10856 /* end functions related to vl arbitration table caching */
10857
10858 static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target,
10859                           u32 size, struct ib_vl_weight_elem *vl)
10860 {
10861         struct hfi1_devdata *dd = ppd->dd;
10862         u64 reg;
10863         unsigned int i, is_up = 0;
10864         int drain, ret = 0;
10865
10866         mutex_lock(&ppd->hls_lock);
10867
10868         if (ppd->host_link_state & HLS_UP)
10869                 is_up = 1;
10870
10871         drain = !is_ax(dd) && is_up;
10872
10873         if (drain)
10874                 /*
10875                  * Before adjusting VL arbitration weights, empty per-VL
10876                  * FIFOs, otherwise a packet whose VL weight is being
10877                  * set to 0 could get stuck in a FIFO with no chance to
10878                  * egress.
10879                  */
10880                 ret = stop_drain_data_vls(dd);
10881
10882         if (ret) {
10883                 dd_dev_err(
10884                         dd,
10885                         "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n",
10886                         __func__);
10887                 goto err;
10888         }
10889
10890         for (i = 0; i < size; i++, vl++) {
10891                 /*
10892                  * NOTE: The low priority shift and mask are used here, but
10893                  * they are the same for both the low and high registers.
10894                  */
10895                 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK)
10896                                 << SEND_LOW_PRIORITY_LIST_VL_SHIFT)
10897                       | (((u64)vl->weight
10898                                 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK)
10899                                 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT);
10900                 write_csr(dd, target + (i * 8), reg);
10901         }
10902         pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE);
10903
10904         if (drain)
10905                 open_fill_data_vls(dd); /* reopen all VLs */
10906
10907 err:
10908         mutex_unlock(&ppd->hls_lock);
10909
10910         return ret;
10911 }
10912
10913 /*
10914  * Read one credit merge VL register.
10915  */
10916 static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr,
10917                            struct vl_limit *vll)
10918 {
10919         u64 reg = read_csr(dd, csr);
10920
10921         vll->dedicated = cpu_to_be16(
10922                 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT)
10923                 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK);
10924         vll->shared = cpu_to_be16(
10925                 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT)
10926                 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK);
10927 }
10928
10929 /*
10930  * Read the current credit merge limits.
10931  */
10932 static int get_buffer_control(struct hfi1_devdata *dd,
10933                               struct buffer_control *bc, u16 *overall_limit)
10934 {
10935         u64 reg;
10936         int i;
10937
10938         /* not all entries are filled in */
10939         memset(bc, 0, sizeof(*bc));
10940
10941         /* OPA and HFI have a 1-1 mapping */
10942         for (i = 0; i < TXE_NUM_DATA_VL; i++)
10943                 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]);
10944
10945         /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
10946         read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]);
10947
10948         reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
10949         bc->overall_shared_limit = cpu_to_be16(
10950                 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT)
10951                 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK);
10952         if (overall_limit)
10953                 *overall_limit = (reg
10954                         >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT)
10955                         & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK;
10956         return sizeof(struct buffer_control);
10957 }
10958
10959 static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10960 {
10961         u64 reg;
10962         int i;
10963
10964         /* each register contains 16 SC->VLnt mappings, 4 bits each */
10965         reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
10966         for (i = 0; i < sizeof(u64); i++) {
10967                 u8 byte = *(((u8 *)&reg) + i);
10968
10969                 dp->vlnt[2 * i] = byte & 0xf;
10970                 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4;
10971         }
10972
10973         reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
10974         for (i = 0; i < sizeof(u64); i++) {
10975                 u8 byte = *(((u8 *)&reg) + i);
10976
10977                 dp->vlnt[16 + (2 * i)] = byte & 0xf;
10978                 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4;
10979         }
10980         return sizeof(struct sc2vlnt);
10981 }
10982
10983 static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems,
10984                               struct ib_vl_weight_elem *vl)
10985 {
10986         unsigned int i;
10987
10988         for (i = 0; i < nelems; i++, vl++) {
10989                 vl->vl = 0xf;
10990                 vl->weight = 0;
10991         }
10992 }
10993
10994 static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
10995 {
10996         write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
10997                   DC_SC_VL_VAL(15_0,
10998                                0, dp->vlnt[0] & 0xf,
10999                                1, dp->vlnt[1] & 0xf,
11000                                2, dp->vlnt[2] & 0xf,
11001                                3, dp->vlnt[3] & 0xf,
11002                                4, dp->vlnt[4] & 0xf,
11003                                5, dp->vlnt[5] & 0xf,
11004                                6, dp->vlnt[6] & 0xf,
11005                                7, dp->vlnt[7] & 0xf,
11006                                8, dp->vlnt[8] & 0xf,
11007                                9, dp->vlnt[9] & 0xf,
11008                                10, dp->vlnt[10] & 0xf,
11009                                11, dp->vlnt[11] & 0xf,
11010                                12, dp->vlnt[12] & 0xf,
11011                                13, dp->vlnt[13] & 0xf,
11012                                14, dp->vlnt[14] & 0xf,
11013                                15, dp->vlnt[15] & 0xf));
11014         write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
11015                   DC_SC_VL_VAL(31_16,
11016                                16, dp->vlnt[16] & 0xf,
11017                                17, dp->vlnt[17] & 0xf,
11018                                18, dp->vlnt[18] & 0xf,
11019                                19, dp->vlnt[19] & 0xf,
11020                                20, dp->vlnt[20] & 0xf,
11021                                21, dp->vlnt[21] & 0xf,
11022                                22, dp->vlnt[22] & 0xf,
11023                                23, dp->vlnt[23] & 0xf,
11024                                24, dp->vlnt[24] & 0xf,
11025                                25, dp->vlnt[25] & 0xf,
11026                                26, dp->vlnt[26] & 0xf,
11027                                27, dp->vlnt[27] & 0xf,
11028                                28, dp->vlnt[28] & 0xf,
11029                                29, dp->vlnt[29] & 0xf,
11030                                30, dp->vlnt[30] & 0xf,
11031                                31, dp->vlnt[31] & 0xf));
11032 }
11033
11034 static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what,
11035                         u16 limit)
11036 {
11037         if (limit != 0)
11038                 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n",
11039                             what, (int)limit, idx);
11040 }
11041
11042 /* change only the shared limit portion of SendCmGLobalCredit */
11043 static void set_global_shared(struct hfi1_devdata *dd, u16 limit)
11044 {
11045         u64 reg;
11046
11047         reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11048         reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK;
11049         reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT;
11050         write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11051 }
11052
11053 /* change only the total credit limit portion of SendCmGLobalCredit */
11054 static void set_global_limit(struct hfi1_devdata *dd, u16 limit)
11055 {
11056         u64 reg;
11057
11058         reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11059         reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK;
11060         reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
11061         write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11062 }
11063
11064 /* set the given per-VL shared limit */
11065 static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit)
11066 {
11067         u64 reg;
11068         u32 addr;
11069
11070         if (vl < TXE_NUM_DATA_VL)
11071                 addr = SEND_CM_CREDIT_VL + (8 * vl);
11072         else
11073                 addr = SEND_CM_CREDIT_VL15;
11074
11075         reg = read_csr(dd, addr);
11076         reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK;
11077         reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT;
11078         write_csr(dd, addr, reg);
11079 }
11080
11081 /* set the given per-VL dedicated limit */
11082 static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit)
11083 {
11084         u64 reg;
11085         u32 addr;
11086
11087         if (vl < TXE_NUM_DATA_VL)
11088                 addr = SEND_CM_CREDIT_VL + (8 * vl);
11089         else
11090                 addr = SEND_CM_CREDIT_VL15;
11091
11092         reg = read_csr(dd, addr);
11093         reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK;
11094         reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT;
11095         write_csr(dd, addr, reg);
11096 }
11097
11098 /* spin until the given per-VL status mask bits clear */
11099 static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask,
11100                                      const char *which)
11101 {
11102         unsigned long timeout;
11103         u64 reg;
11104
11105         timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT);
11106         while (1) {
11107                 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
11108
11109                 if (reg == 0)
11110                         return; /* success */
11111                 if (time_after(jiffies, timeout))
11112                         break;          /* timed out */
11113                 udelay(1);
11114         }
11115
11116         dd_dev_err(dd,
11117                    "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
11118                    which, VL_STATUS_CLEAR_TIMEOUT, mask, reg);
11119         /*
11120          * If this occurs, it is likely there was a credit loss on the link.
11121          * The only recovery from that is a link bounce.
11122          */
11123         dd_dev_err(dd,
11124                    "Continuing anyway.  A credit loss may occur.  Suggest a link bounce\n");
11125 }
11126
11127 /*
11128  * The number of credits on the VLs may be changed while everything
11129  * is "live", but the following algorithm must be followed due to
11130  * how the hardware is actually implemented.  In particular,
11131  * Return_Credit_Status[] is the only correct status check.
11132  *
11133  * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
11134  *     set Global_Shared_Credit_Limit = 0
11135  *     use_all_vl = 1
11136  * mask0 = all VLs that are changing either dedicated or shared limits
11137  * set Shared_Limit[mask0] = 0
11138  * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
11139  * if (changing any dedicated limit)
11140  *     mask1 = all VLs that are lowering dedicated limits
11141  *     lower Dedicated_Limit[mask1]
11142  *     spin until Return_Credit_Status[mask1] == 0
11143  *     raise Dedicated_Limits
11144  * raise Shared_Limits
11145  * raise Global_Shared_Credit_Limit
11146  *
11147  * lower = if the new limit is lower, set the limit to the new value
11148  * raise = if the new limit is higher than the current value (may be changed
11149  *      earlier in the algorithm), set the new limit to the new value
11150  */
11151 int set_buffer_control(struct hfi1_pportdata *ppd,
11152                        struct buffer_control *new_bc)
11153 {
11154         struct hfi1_devdata *dd = ppd->dd;
11155         u64 changing_mask, ld_mask, stat_mask;
11156         int change_count;
11157         int i, use_all_mask;
11158         int this_shared_changing;
11159         int vl_count = 0, ret;
11160         /*
11161          * A0: add the variable any_shared_limit_changing below and in the
11162          * algorithm above.  If removing A0 support, it can be removed.
11163          */
11164         int any_shared_limit_changing;
11165         struct buffer_control cur_bc;
11166         u8 changing[OPA_MAX_VLS];
11167         u8 lowering_dedicated[OPA_MAX_VLS];
11168         u16 cur_total;
11169         u32 new_total = 0;
11170         const u64 all_mask =
11171         SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
11172          | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
11173          | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
11174          | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
11175          | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
11176          | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
11177          | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
11178          | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
11179          | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK;
11180
11181 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
11182 #define NUM_USABLE_VLS 16       /* look at VL15 and less */
11183
11184         /* find the new total credits, do sanity check on unused VLs */
11185         for (i = 0; i < OPA_MAX_VLS; i++) {
11186                 if (valid_vl(i)) {
11187                         new_total += be16_to_cpu(new_bc->vl[i].dedicated);
11188                         continue;
11189                 }
11190                 nonzero_msg(dd, i, "dedicated",
11191                             be16_to_cpu(new_bc->vl[i].dedicated));
11192                 nonzero_msg(dd, i, "shared",
11193                             be16_to_cpu(new_bc->vl[i].shared));
11194                 new_bc->vl[i].dedicated = 0;
11195                 new_bc->vl[i].shared = 0;
11196         }
11197         new_total += be16_to_cpu(new_bc->overall_shared_limit);
11198
11199         /* fetch the current values */
11200         get_buffer_control(dd, &cur_bc, &cur_total);
11201
11202         /*
11203          * Create the masks we will use.
11204          */
11205         memset(changing, 0, sizeof(changing));
11206         memset(lowering_dedicated, 0, sizeof(lowering_dedicated));
11207         /*
11208          * NOTE: Assumes that the individual VL bits are adjacent and in
11209          * increasing order
11210          */
11211         stat_mask =
11212                 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
11213         changing_mask = 0;
11214         ld_mask = 0;
11215         change_count = 0;
11216         any_shared_limit_changing = 0;
11217         for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) {
11218                 if (!valid_vl(i))
11219                         continue;
11220                 this_shared_changing = new_bc->vl[i].shared
11221                                                 != cur_bc.vl[i].shared;
11222                 if (this_shared_changing)
11223                         any_shared_limit_changing = 1;
11224                 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated ||
11225                     this_shared_changing) {
11226                         changing[i] = 1;
11227                         changing_mask |= stat_mask;
11228                         change_count++;
11229                 }
11230                 if (be16_to_cpu(new_bc->vl[i].dedicated) <
11231                                         be16_to_cpu(cur_bc.vl[i].dedicated)) {
11232                         lowering_dedicated[i] = 1;
11233                         ld_mask |= stat_mask;
11234                 }
11235         }
11236
11237         /* bracket the credit change with a total adjustment */
11238         if (new_total > cur_total)
11239                 set_global_limit(dd, new_total);
11240
11241         /*
11242          * Start the credit change algorithm.
11243          */
11244         use_all_mask = 0;
11245         if ((be16_to_cpu(new_bc->overall_shared_limit) <
11246              be16_to_cpu(cur_bc.overall_shared_limit)) ||
11247             (is_ax(dd) && any_shared_limit_changing)) {
11248                 set_global_shared(dd, 0);
11249                 cur_bc.overall_shared_limit = 0;
11250                 use_all_mask = 1;
11251         }
11252
11253         for (i = 0; i < NUM_USABLE_VLS; i++) {
11254                 if (!valid_vl(i))
11255                         continue;
11256
11257                 if (changing[i]) {
11258                         set_vl_shared(dd, i, 0);
11259                         cur_bc.vl[i].shared = 0;
11260                 }
11261         }
11262
11263         wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask,
11264                                  "shared");
11265
11266         if (change_count > 0) {
11267                 for (i = 0; i < NUM_USABLE_VLS; i++) {
11268                         if (!valid_vl(i))
11269                                 continue;
11270
11271                         if (lowering_dedicated[i]) {
11272                                 set_vl_dedicated(dd, i,
11273                                                  be16_to_cpu(new_bc->
11274                                                              vl[i].dedicated));
11275                                 cur_bc.vl[i].dedicated =
11276                                                 new_bc->vl[i].dedicated;
11277                         }
11278                 }
11279
11280                 wait_for_vl_status_clear(dd, ld_mask, "dedicated");
11281
11282                 /* now raise all dedicated that are going up */
11283                 for (i = 0; i < NUM_USABLE_VLS; i++) {
11284                         if (!valid_vl(i))
11285                                 continue;
11286
11287                         if (be16_to_cpu(new_bc->vl[i].dedicated) >
11288                                         be16_to_cpu(cur_bc.vl[i].dedicated))
11289                                 set_vl_dedicated(dd, i,
11290                                                  be16_to_cpu(new_bc->
11291                                                              vl[i].dedicated));
11292                 }
11293         }
11294
11295         /* next raise all shared that are going up */
11296         for (i = 0; i < NUM_USABLE_VLS; i++) {
11297                 if (!valid_vl(i))
11298                         continue;
11299
11300                 if (be16_to_cpu(new_bc->vl[i].shared) >
11301                                 be16_to_cpu(cur_bc.vl[i].shared))
11302                         set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared));
11303         }
11304
11305         /* finally raise the global shared */
11306         if (be16_to_cpu(new_bc->overall_shared_limit) >
11307             be16_to_cpu(cur_bc.overall_shared_limit))
11308                 set_global_shared(dd,
11309                                   be16_to_cpu(new_bc->overall_shared_limit));
11310
11311         /* bracket the credit change with a total adjustment */
11312         if (new_total < cur_total)
11313                 set_global_limit(dd, new_total);
11314
11315         /*
11316          * Determine the actual number of operational VLS using the number of
11317          * dedicated and shared credits for each VL.
11318          */
11319         if (change_count > 0) {
11320                 for (i = 0; i < TXE_NUM_DATA_VL; i++)
11321                         if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 ||
11322                             be16_to_cpu(new_bc->vl[i].shared) > 0)
11323                                 vl_count++;
11324                 ppd->actual_vls_operational = vl_count;
11325                 ret = sdma_map_init(dd, ppd->port - 1, vl_count ?
11326                                     ppd->actual_vls_operational :
11327                                     ppd->vls_operational,
11328                                     NULL);
11329                 if (ret == 0)
11330                         ret = pio_map_init(dd, ppd->port - 1, vl_count ?
11331                                            ppd->actual_vls_operational :
11332                                            ppd->vls_operational, NULL);
11333                 if (ret)
11334                         return ret;
11335         }
11336         return 0;
11337 }
11338
11339 /*
11340  * Read the given fabric manager table. Return the size of the
11341  * table (in bytes) on success, and a negative error code on
11342  * failure.
11343  */
11344 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t)
11345
11346 {
11347         int size;
11348         struct vl_arb_cache *vlc;
11349
11350         switch (which) {
11351         case FM_TBL_VL_HIGH_ARB:
11352                 size = 256;
11353                 /*
11354                  * OPA specifies 128 elements (of 2 bytes each), though
11355                  * HFI supports only 16 elements in h/w.
11356                  */
11357                 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11358                 vl_arb_get_cache(vlc, t);
11359                 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11360                 break;
11361         case FM_TBL_VL_LOW_ARB:
11362                 size = 256;
11363                 /*
11364                  * OPA specifies 128 elements (of 2 bytes each), though
11365                  * HFI supports only 16 elements in h/w.
11366                  */
11367                 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11368                 vl_arb_get_cache(vlc, t);
11369                 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11370                 break;
11371         case FM_TBL_BUFFER_CONTROL:
11372                 size = get_buffer_control(ppd->dd, t, NULL);
11373                 break;
11374         case FM_TBL_SC2VLNT:
11375                 size = get_sc2vlnt(ppd->dd, t);
11376                 break;
11377         case FM_TBL_VL_PREEMPT_ELEMS:
11378                 size = 256;
11379                 /* OPA specifies 128 elements, of 2 bytes each */
11380                 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t);
11381                 break;
11382         case FM_TBL_VL_PREEMPT_MATRIX:
11383                 size = 256;
11384                 /*
11385                  * OPA specifies that this is the same size as the VL
11386                  * arbitration tables (i.e., 256 bytes).
11387                  */
11388                 break;
11389         default:
11390                 return -EINVAL;
11391         }
11392         return size;
11393 }
11394
11395 /*
11396  * Write the given fabric manager table.
11397  */
11398 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t)
11399 {
11400         int ret = 0;
11401         struct vl_arb_cache *vlc;
11402
11403         switch (which) {
11404         case FM_TBL_VL_HIGH_ARB:
11405                 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11406                 if (vl_arb_match_cache(vlc, t)) {
11407                         vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11408                         break;
11409                 }
11410                 vl_arb_set_cache(vlc, t);
11411                 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11412                 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST,
11413                                      VL_ARB_HIGH_PRIO_TABLE_SIZE, t);
11414                 break;
11415         case FM_TBL_VL_LOW_ARB:
11416                 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11417                 if (vl_arb_match_cache(vlc, t)) {
11418                         vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11419                         break;
11420                 }
11421                 vl_arb_set_cache(vlc, t);
11422                 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11423                 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST,
11424                                      VL_ARB_LOW_PRIO_TABLE_SIZE, t);
11425                 break;
11426         case FM_TBL_BUFFER_CONTROL:
11427                 ret = set_buffer_control(ppd, t);
11428                 break;
11429         case FM_TBL_SC2VLNT:
11430                 set_sc2vlnt(ppd->dd, t);
11431                 break;
11432         default:
11433                 ret = -EINVAL;
11434         }
11435         return ret;
11436 }
11437
11438 /*
11439  * Disable all data VLs.
11440  *
11441  * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11442  */
11443 static int disable_data_vls(struct hfi1_devdata *dd)
11444 {
11445         if (is_ax(dd))
11446                 return 1;
11447
11448         pio_send_control(dd, PSC_DATA_VL_DISABLE);
11449
11450         return 0;
11451 }
11452
11453 /*
11454  * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11455  * Just re-enables all data VLs (the "fill" part happens
11456  * automatically - the name was chosen for symmetry with
11457  * stop_drain_data_vls()).
11458  *
11459  * Return 0 if successful, non-zero if the VLs cannot be enabled.
11460  */
11461 int open_fill_data_vls(struct hfi1_devdata *dd)
11462 {
11463         if (is_ax(dd))
11464                 return 1;
11465
11466         pio_send_control(dd, PSC_DATA_VL_ENABLE);
11467
11468         return 0;
11469 }
11470
11471 /*
11472  * drain_data_vls() - assumes that disable_data_vls() has been called,
11473  * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11474  * engines to drop to 0.
11475  */
11476 static void drain_data_vls(struct hfi1_devdata *dd)
11477 {
11478         sc_wait(dd);
11479         sdma_wait(dd);
11480         pause_for_credit_return(dd);
11481 }
11482
11483 /*
11484  * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11485  *
11486  * Use open_fill_data_vls() to resume using data VLs.  This pair is
11487  * meant to be used like this:
11488  *
11489  * stop_drain_data_vls(dd);
11490  * // do things with per-VL resources
11491  * open_fill_data_vls(dd);
11492  */
11493 int stop_drain_data_vls(struct hfi1_devdata *dd)
11494 {
11495         int ret;
11496
11497         ret = disable_data_vls(dd);
11498         if (ret == 0)
11499                 drain_data_vls(dd);
11500
11501         return ret;
11502 }
11503
11504 /*
11505  * Convert a nanosecond time to a cclock count.  No matter how slow
11506  * the cclock, a non-zero ns will always have a non-zero result.
11507  */
11508 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns)
11509 {
11510         u32 cclocks;
11511
11512         if (dd->icode == ICODE_FPGA_EMULATION)
11513                 cclocks = (ns * 1000) / FPGA_CCLOCK_PS;
11514         else  /* simulation pretends to be ASIC */
11515                 cclocks = (ns * 1000) / ASIC_CCLOCK_PS;
11516         if (ns && !cclocks)     /* if ns nonzero, must be at least 1 */
11517                 cclocks = 1;
11518         return cclocks;
11519 }
11520
11521 /*
11522  * Convert a cclock count to nanoseconds. Not matter how slow
11523  * the cclock, a non-zero cclocks will always have a non-zero result.
11524  */
11525 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks)
11526 {
11527         u32 ns;
11528
11529         if (dd->icode == ICODE_FPGA_EMULATION)
11530                 ns = (cclocks * FPGA_CCLOCK_PS) / 1000;
11531         else  /* simulation pretends to be ASIC */
11532                 ns = (cclocks * ASIC_CCLOCK_PS) / 1000;
11533         if (cclocks && !ns)
11534                 ns = 1;
11535         return ns;
11536 }
11537
11538 /*
11539  * Dynamically adjust the receive interrupt timeout for a context based on
11540  * incoming packet rate.
11541  *
11542  * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11543  */
11544 static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
11545 {
11546         struct hfi1_devdata *dd = rcd->dd;
11547         u32 timeout = rcd->rcvavail_timeout;
11548
11549         /*
11550          * This algorithm doubles or halves the timeout depending on whether
11551          * the number of packets received in this interrupt were less than or
11552          * greater equal the interrupt count.
11553          *
11554          * The calculations below do not allow a steady state to be achieved.
11555          * Only at the endpoints it is possible to have an unchanging
11556          * timeout.
11557          */
11558         if (npkts < rcv_intr_count) {
11559                 /*
11560                  * Not enough packets arrived before the timeout, adjust
11561                  * timeout downward.
11562                  */
11563                 if (timeout < 2) /* already at minimum? */
11564                         return;
11565                 timeout >>= 1;
11566         } else {
11567                 /*
11568                  * More than enough packets arrived before the timeout, adjust
11569                  * timeout upward.
11570                  */
11571                 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */
11572                         return;
11573                 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr);
11574         }
11575
11576         rcd->rcvavail_timeout = timeout;
11577         /*
11578          * timeout cannot be larger than rcv_intr_timeout_csr which has already
11579          * been verified to be in range
11580          */
11581         write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
11582                         (u64)timeout <<
11583                         RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11584 }
11585
11586 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
11587                     u32 intr_adjust, u32 npkts)
11588 {
11589         struct hfi1_devdata *dd = rcd->dd;
11590         u64 reg;
11591         u32 ctxt = rcd->ctxt;
11592
11593         /*
11594          * Need to write timeout register before updating RcvHdrHead to ensure
11595          * that a new value is used when the HW decides to restart counting.
11596          */
11597         if (intr_adjust)
11598                 adjust_rcv_timeout(rcd, npkts);
11599         if (updegr) {
11600                 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK)
11601                         << RCV_EGR_INDEX_HEAD_HEAD_SHIFT;
11602                 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg);
11603         }
11604         mmiowb();
11605         reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) |
11606                 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK)
11607                         << RCV_HDR_HEAD_HEAD_SHIFT);
11608         write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11609         mmiowb();
11610 }
11611
11612 u32 hdrqempty(struct hfi1_ctxtdata *rcd)
11613 {
11614         u32 head, tail;
11615
11616         head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11617                 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT;
11618
11619         if (rcd->rcvhdrtail_kvaddr)
11620                 tail = get_rcvhdrtail(rcd);
11621         else
11622                 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
11623
11624         return head == tail;
11625 }
11626
11627 /*
11628  * Context Control and Receive Array encoding for buffer size:
11629  *      0x0 invalid
11630  *      0x1   4 KB
11631  *      0x2   8 KB
11632  *      0x3  16 KB
11633  *      0x4  32 KB
11634  *      0x5  64 KB
11635  *      0x6 128 KB
11636  *      0x7 256 KB
11637  *      0x8 512 KB (Receive Array only)
11638  *      0x9   1 MB (Receive Array only)
11639  *      0xa   2 MB (Receive Array only)
11640  *
11641  *      0xB-0xF - reserved (Receive Array only)
11642  *
11643  *
11644  * This routine assumes that the value has already been sanity checked.
11645  */
11646 static u32 encoded_size(u32 size)
11647 {
11648         switch (size) {
11649         case   4 * 1024: return 0x1;
11650         case   8 * 1024: return 0x2;
11651         case  16 * 1024: return 0x3;
11652         case  32 * 1024: return 0x4;
11653         case  64 * 1024: return 0x5;
11654         case 128 * 1024: return 0x6;
11655         case 256 * 1024: return 0x7;
11656         case 512 * 1024: return 0x8;
11657         case   1 * 1024 * 1024: return 0x9;
11658         case   2 * 1024 * 1024: return 0xa;
11659         }
11660         return 0x1;     /* if invalid, go with the minimum size */
11661 }
11662
11663 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, int ctxt)
11664 {
11665         struct hfi1_ctxtdata *rcd;
11666         u64 rcvctrl, reg;
11667         int did_enable = 0;
11668
11669         rcd = dd->rcd[ctxt];
11670         if (!rcd)
11671                 return;
11672
11673         hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
11674
11675         rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
11676         /* if the context already enabled, don't do the extra steps */
11677         if ((op & HFI1_RCVCTRL_CTXT_ENB) &&
11678             !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) {
11679                 /* reset the tail and hdr addresses, and sequence count */
11680                 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
11681                                 rcd->rcvhdrq_dma);
11682                 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL))
11683                         write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11684                                         rcd->rcvhdrqtailaddr_dma);
11685                 rcd->seq_cnt = 1;
11686
11687                 /* reset the cached receive header queue head value */
11688                 rcd->head = 0;
11689
11690                 /*
11691                  * Zero the receive header queue so we don't get false
11692                  * positives when checking the sequence number.  The
11693                  * sequence numbers could land exactly on the same spot.
11694                  * E.g. a rcd restart before the receive header wrapped.
11695                  */
11696                 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
11697
11698                 /* starting timeout */
11699                 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr;
11700
11701                 /* enable the context */
11702                 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK;
11703
11704                 /* clean the egr buffer size first */
11705                 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11706                 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size)
11707                                 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK)
11708                                         << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT;
11709
11710                 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
11711                 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0);
11712                 did_enable = 1;
11713
11714                 /* zero RcvEgrIndexHead */
11715                 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0);
11716
11717                 /* set eager count and base index */
11718                 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT)
11719                         & RCV_EGR_CTRL_EGR_CNT_MASK)
11720                        << RCV_EGR_CTRL_EGR_CNT_SHIFT) |
11721                         (((rcd->eager_base >> RCV_SHIFT)
11722                           & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK)
11723                          << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT);
11724                 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg);
11725
11726                 /*
11727                  * Set TID (expected) count and base index.
11728                  * rcd->expected_count is set to individual RcvArray entries,
11729                  * not pairs, and the CSR takes a pair-count in groups of
11730                  * four, so divide by 8.
11731                  */
11732                 reg = (((rcd->expected_count >> RCV_SHIFT)
11733                                         & RCV_TID_CTRL_TID_PAIR_CNT_MASK)
11734                                 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) |
11735                       (((rcd->expected_base >> RCV_SHIFT)
11736                                         & RCV_TID_CTRL_TID_BASE_INDEX_MASK)
11737                                 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT);
11738                 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg);
11739                 if (ctxt == HFI1_CTRL_CTXT)
11740                         write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
11741         }
11742         if (op & HFI1_RCVCTRL_CTXT_DIS) {
11743                 write_csr(dd, RCV_VL15, 0);
11744                 /*
11745                  * When receive context is being disabled turn on tail
11746                  * update with a dummy tail address and then disable
11747                  * receive context.
11748                  */
11749                 if (dd->rcvhdrtail_dummy_dma) {
11750                         write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11751                                         dd->rcvhdrtail_dummy_dma);
11752                         /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
11753                         rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11754                 }
11755
11756                 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK;
11757         }
11758         if (op & HFI1_RCVCTRL_INTRAVAIL_ENB)
11759                 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11760         if (op & HFI1_RCVCTRL_INTRAVAIL_DIS)
11761                 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11762         if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_dma)
11763                 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11764         if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
11765                 /* See comment on RcvCtxtCtrl.TailUpd above */
11766                 if (!(op & HFI1_RCVCTRL_CTXT_DIS))
11767                         rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11768         }
11769         if (op & HFI1_RCVCTRL_TIDFLOW_ENB)
11770                 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11771         if (op & HFI1_RCVCTRL_TIDFLOW_DIS)
11772                 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
11773         if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) {
11774                 /*
11775                  * In one-packet-per-eager mode, the size comes from
11776                  * the RcvArray entry.
11777                  */
11778                 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
11779                 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11780         }
11781         if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS)
11782                 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
11783         if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB)
11784                 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11785         if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS)
11786                 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
11787         if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB)
11788                 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11789         if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS)
11790                 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
11791         rcd->rcvctrl = rcvctrl;
11792         hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl);
11793         write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcd->rcvctrl);
11794
11795         /* work around sticky RcvCtxtStatus.BlockedRHQFull */
11796         if (did_enable &&
11797             (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) {
11798                 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11799                 if (reg != 0) {
11800                         dd_dev_info(dd, "ctxt %d status %lld (blocked)\n",
11801                                     ctxt, reg);
11802                         read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11803                         write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10);
11804                         write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00);
11805                         read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
11806                         reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
11807                         dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n",
11808                                     ctxt, reg, reg == 0 ? "not" : "still");
11809                 }
11810         }
11811
11812         if (did_enable) {
11813                 /*
11814                  * The interrupt timeout and count must be set after
11815                  * the context is enabled to take effect.
11816                  */
11817                 /* set interrupt timeout */
11818                 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT,
11819                                 (u64)rcd->rcvavail_timeout <<
11820                                 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11821
11822                 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
11823                 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT;
11824                 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11825         }
11826
11827         if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS))
11828                 /*
11829                  * If the context has been disabled and the Tail Update has
11830                  * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11831                  * so it doesn't contain an address that is invalid.
11832                  */
11833                 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11834                                 dd->rcvhdrtail_dummy_dma);
11835 }
11836
11837 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp)
11838 {
11839         int ret;
11840         u64 val = 0;
11841
11842         if (namep) {
11843                 ret = dd->cntrnameslen;
11844                 *namep = dd->cntrnames;
11845         } else {
11846                 const struct cntr_entry *entry;
11847                 int i, j;
11848
11849                 ret = (dd->ndevcntrs) * sizeof(u64);
11850
11851                 /* Get the start of the block of counters */
11852                 *cntrp = dd->cntrs;
11853
11854                 /*
11855                  * Now go and fill in each counter in the block.
11856                  */
11857                 for (i = 0; i < DEV_CNTR_LAST; i++) {
11858                         entry = &dev_cntrs[i];
11859                         hfi1_cdbg(CNTR, "reading %s", entry->name);
11860                         if (entry->flags & CNTR_DISABLED) {
11861                                 /* Nothing */
11862                                 hfi1_cdbg(CNTR, "\tDisabled\n");
11863                         } else {
11864                                 if (entry->flags & CNTR_VL) {
11865                                         hfi1_cdbg(CNTR, "\tPer VL\n");
11866                                         for (j = 0; j < C_VL_COUNT; j++) {
11867                                                 val = entry->rw_cntr(entry,
11868                                                                   dd, j,
11869                                                                   CNTR_MODE_R,
11870                                                                   0);
11871                                                 hfi1_cdbg(
11872                                                    CNTR,
11873                                                    "\t\tRead 0x%llx for %d\n",
11874                                                    val, j);
11875                                                 dd->cntrs[entry->offset + j] =
11876                                                                             val;
11877                                         }
11878                                 } else if (entry->flags & CNTR_SDMA) {
11879                                         hfi1_cdbg(CNTR,
11880                                                   "\t Per SDMA Engine\n");
11881                                         for (j = 0; j < dd->chip_sdma_engines;
11882                                              j++) {
11883                                                 val =
11884                                                 entry->rw_cntr(entry, dd, j,
11885                                                                CNTR_MODE_R, 0);
11886                                                 hfi1_cdbg(CNTR,
11887                                                           "\t\tRead 0x%llx for %d\n",
11888                                                           val, j);
11889                                                 dd->cntrs[entry->offset + j] =
11890                                                                         val;
11891                                         }
11892                                 } else {
11893                                         val = entry->rw_cntr(entry, dd,
11894                                                         CNTR_INVALID_VL,
11895                                                         CNTR_MODE_R, 0);
11896                                         dd->cntrs[entry->offset] = val;
11897                                         hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11898                                 }
11899                         }
11900                 }
11901         }
11902         return ret;
11903 }
11904
11905 /*
11906  * Used by sysfs to create files for hfi stats to read
11907  */
11908 u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp)
11909 {
11910         int ret;
11911         u64 val = 0;
11912
11913         if (namep) {
11914                 ret = ppd->dd->portcntrnameslen;
11915                 *namep = ppd->dd->portcntrnames;
11916         } else {
11917                 const struct cntr_entry *entry;
11918                 int i, j;
11919
11920                 ret = ppd->dd->nportcntrs * sizeof(u64);
11921                 *cntrp = ppd->cntrs;
11922
11923                 for (i = 0; i < PORT_CNTR_LAST; i++) {
11924                         entry = &port_cntrs[i];
11925                         hfi1_cdbg(CNTR, "reading %s", entry->name);
11926                         if (entry->flags & CNTR_DISABLED) {
11927                                 /* Nothing */
11928                                 hfi1_cdbg(CNTR, "\tDisabled\n");
11929                                 continue;
11930                         }
11931
11932                         if (entry->flags & CNTR_VL) {
11933                                 hfi1_cdbg(CNTR, "\tPer VL");
11934                                 for (j = 0; j < C_VL_COUNT; j++) {
11935                                         val = entry->rw_cntr(entry, ppd, j,
11936                                                                CNTR_MODE_R,
11937                                                                0);
11938                                         hfi1_cdbg(
11939                                            CNTR,
11940                                            "\t\tRead 0x%llx for %d",
11941                                            val, j);
11942                                         ppd->cntrs[entry->offset + j] = val;
11943                                 }
11944                         } else {
11945                                 val = entry->rw_cntr(entry, ppd,
11946                                                        CNTR_INVALID_VL,
11947                                                        CNTR_MODE_R,
11948                                                        0);
11949                                 ppd->cntrs[entry->offset] = val;
11950                                 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
11951                         }
11952                 }
11953         }
11954         return ret;
11955 }
11956
11957 static void free_cntrs(struct hfi1_devdata *dd)
11958 {
11959         struct hfi1_pportdata *ppd;
11960         int i;
11961
11962         if (dd->synth_stats_timer.data)
11963                 del_timer_sync(&dd->synth_stats_timer);
11964         dd->synth_stats_timer.data = 0;
11965         ppd = (struct hfi1_pportdata *)(dd + 1);
11966         for (i = 0; i < dd->num_pports; i++, ppd++) {
11967                 kfree(ppd->cntrs);
11968                 kfree(ppd->scntrs);
11969                 free_percpu(ppd->ibport_data.rvp.rc_acks);
11970                 free_percpu(ppd->ibport_data.rvp.rc_qacks);
11971                 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
11972                 ppd->cntrs = NULL;
11973                 ppd->scntrs = NULL;
11974                 ppd->ibport_data.rvp.rc_acks = NULL;
11975                 ppd->ibport_data.rvp.rc_qacks = NULL;
11976                 ppd->ibport_data.rvp.rc_delayed_comp = NULL;
11977         }
11978         kfree(dd->portcntrnames);
11979         dd->portcntrnames = NULL;
11980         kfree(dd->cntrs);
11981         dd->cntrs = NULL;
11982         kfree(dd->scntrs);
11983         dd->scntrs = NULL;
11984         kfree(dd->cntrnames);
11985         dd->cntrnames = NULL;
11986         if (dd->update_cntr_wq) {
11987                 destroy_workqueue(dd->update_cntr_wq);
11988                 dd->update_cntr_wq = NULL;
11989         }
11990 }
11991
11992 static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry,
11993                               u64 *psval, void *context, int vl)
11994 {
11995         u64 val;
11996         u64 sval = *psval;
11997
11998         if (entry->flags & CNTR_DISABLED) {
11999                 dd_dev_err(dd, "Counter %s not enabled", entry->name);
12000                 return 0;
12001         }
12002
12003         hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
12004
12005         val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0);
12006
12007         /* If its a synthetic counter there is more work we need to do */
12008         if (entry->flags & CNTR_SYNTH) {
12009                 if (sval == CNTR_MAX) {
12010                         /* No need to read already saturated */
12011                         return CNTR_MAX;
12012                 }
12013
12014                 if (entry->flags & CNTR_32BIT) {
12015                         /* 32bit counters can wrap multiple times */
12016                         u64 upper = sval >> 32;
12017                         u64 lower = (sval << 32) >> 32;
12018
12019                         if (lower > val) { /* hw wrapped */
12020                                 if (upper == CNTR_32BIT_MAX)
12021                                         val = CNTR_MAX;
12022                                 else
12023                                         upper++;
12024                         }
12025
12026                         if (val != CNTR_MAX)
12027                                 val = (upper << 32) | val;
12028
12029                 } else {
12030                         /* If we rolled we are saturated */
12031                         if ((val < sval) || (val > CNTR_MAX))
12032                                 val = CNTR_MAX;
12033                 }
12034         }
12035
12036         *psval = val;
12037
12038         hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
12039
12040         return val;
12041 }
12042
12043 static u64 write_dev_port_cntr(struct hfi1_devdata *dd,
12044                                struct cntr_entry *entry,
12045                                u64 *psval, void *context, int vl, u64 data)
12046 {
12047         u64 val;
12048
12049         if (entry->flags & CNTR_DISABLED) {
12050                 dd_dev_err(dd, "Counter %s not enabled", entry->name);
12051                 return 0;
12052         }
12053
12054         hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
12055
12056         if (entry->flags & CNTR_SYNTH) {
12057                 *psval = data;
12058                 if (entry->flags & CNTR_32BIT) {
12059                         val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
12060                                              (data << 32) >> 32);
12061                         val = data; /* return the full 64bit value */
12062                 } else {
12063                         val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
12064                                              data);
12065                 }
12066         } else {
12067                 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data);
12068         }
12069
12070         *psval = val;
12071
12072         hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
12073
12074         return val;
12075 }
12076
12077 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl)
12078 {
12079         struct cntr_entry *entry;
12080         u64 *sval;
12081
12082         entry = &dev_cntrs[index];
12083         sval = dd->scntrs + entry->offset;
12084
12085         if (vl != CNTR_INVALID_VL)
12086                 sval += vl;
12087
12088         return read_dev_port_cntr(dd, entry, sval, dd, vl);
12089 }
12090
12091 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data)
12092 {
12093         struct cntr_entry *entry;
12094         u64 *sval;
12095
12096         entry = &dev_cntrs[index];
12097         sval = dd->scntrs + entry->offset;
12098
12099         if (vl != CNTR_INVALID_VL)
12100                 sval += vl;
12101
12102         return write_dev_port_cntr(dd, entry, sval, dd, vl, data);
12103 }
12104
12105 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl)
12106 {
12107         struct cntr_entry *entry;
12108         u64 *sval;
12109
12110         entry = &port_cntrs[index];
12111         sval = ppd->scntrs + entry->offset;
12112
12113         if (vl != CNTR_INVALID_VL)
12114                 sval += vl;
12115
12116         if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
12117             (index <= C_RCV_HDR_OVF_LAST)) {
12118                 /* We do not want to bother for disabled contexts */
12119                 return 0;
12120         }
12121
12122         return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl);
12123 }
12124
12125 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data)
12126 {
12127         struct cntr_entry *entry;
12128         u64 *sval;
12129
12130         entry = &port_cntrs[index];
12131         sval = ppd->scntrs + entry->offset;
12132
12133         if (vl != CNTR_INVALID_VL)
12134                 sval += vl;
12135
12136         if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
12137             (index <= C_RCV_HDR_OVF_LAST)) {
12138                 /* We do not want to bother for disabled contexts */
12139                 return 0;
12140         }
12141
12142         return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data);
12143 }
12144
12145 static void do_update_synth_timer(struct work_struct *work)
12146 {
12147         u64 cur_tx;
12148         u64 cur_rx;
12149         u64 total_flits;
12150         u8 update = 0;
12151         int i, j, vl;
12152         struct hfi1_pportdata *ppd;
12153         struct cntr_entry *entry;
12154         struct hfi1_devdata *dd = container_of(work, struct hfi1_devdata,
12155                                                update_cntr_work);
12156
12157         /*
12158          * Rather than keep beating on the CSRs pick a minimal set that we can
12159          * check to watch for potential roll over. We can do this by looking at
12160          * the number of flits sent/recv. If the total flits exceeds 32bits then
12161          * we have to iterate all the counters and update.
12162          */
12163         entry = &dev_cntrs[C_DC_RCV_FLITS];
12164         cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
12165
12166         entry = &dev_cntrs[C_DC_XMIT_FLITS];
12167         cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
12168
12169         hfi1_cdbg(
12170             CNTR,
12171             "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n",
12172             dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx);
12173
12174         if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) {
12175                 /*
12176                  * May not be strictly necessary to update but it won't hurt and
12177                  * simplifies the logic here.
12178                  */
12179                 update = 1;
12180                 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",
12181                           dd->unit);
12182         } else {
12183                 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx);
12184                 hfi1_cdbg(CNTR,
12185                           "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit,
12186                           total_flits, (u64)CNTR_32BIT_MAX);
12187                 if (total_flits >= CNTR_32BIT_MAX) {
12188                         hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",
12189                                   dd->unit);
12190                         update = 1;
12191                 }
12192         }
12193
12194         if (update) {
12195                 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);
12196                 for (i = 0; i < DEV_CNTR_LAST; i++) {
12197                         entry = &dev_cntrs[i];
12198                         if (entry->flags & CNTR_VL) {
12199                                 for (vl = 0; vl < C_VL_COUNT; vl++)
12200                                         read_dev_cntr(dd, i, vl);
12201                         } else {
12202                                 read_dev_cntr(dd, i, CNTR_INVALID_VL);
12203                         }
12204                 }
12205                 ppd = (struct hfi1_pportdata *)(dd + 1);
12206                 for (i = 0; i < dd->num_pports; i++, ppd++) {
12207                         for (j = 0; j < PORT_CNTR_LAST; j++) {
12208                                 entry = &port_cntrs[j];
12209                                 if (entry->flags & CNTR_VL) {
12210                                         for (vl = 0; vl < C_VL_COUNT; vl++)
12211                                                 read_port_cntr(ppd, j, vl);
12212                                 } else {
12213                                         read_port_cntr(ppd, j, CNTR_INVALID_VL);
12214                                 }
12215                         }
12216                 }
12217
12218                 /*
12219                  * We want the value in the register. The goal is to keep track
12220                  * of the number of "ticks" not the counter value. In other
12221                  * words if the register rolls we want to notice it and go ahead
12222                  * and force an update.
12223                  */
12224                 entry = &dev_cntrs[C_DC_XMIT_FLITS];
12225                 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12226                                                 CNTR_MODE_R, 0);
12227
12228                 entry = &dev_cntrs[C_DC_RCV_FLITS];
12229                 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12230                                                 CNTR_MODE_R, 0);
12231
12232                 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",
12233                           dd->unit, dd->last_tx, dd->last_rx);
12234
12235         } else {
12236                 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);
12237         }
12238 }
12239
12240 static void update_synth_timer(unsigned long opaque)
12241 {
12242         struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque;
12243
12244         queue_work(dd->update_cntr_wq, &dd->update_cntr_work);
12245         mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12246 }
12247
12248 #define C_MAX_NAME 16 /* 15 chars + one for /0 */
12249 static int init_cntrs(struct hfi1_devdata *dd)
12250 {
12251         int i, rcv_ctxts, j;
12252         size_t sz;
12253         char *p;
12254         char name[C_MAX_NAME];
12255         struct hfi1_pportdata *ppd;
12256         const char *bit_type_32 = ",32";
12257         const int bit_type_32_sz = strlen(bit_type_32);
12258
12259         /* set up the stats timer; the add_timer is done at the end */
12260         setup_timer(&dd->synth_stats_timer, update_synth_timer,
12261                     (unsigned long)dd);
12262
12263         /***********************/
12264         /* per device counters */
12265         /***********************/
12266
12267         /* size names and determine how many we have*/
12268         dd->ndevcntrs = 0;
12269         sz = 0;
12270
12271         for (i = 0; i < DEV_CNTR_LAST; i++) {
12272                 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12273                         hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name);
12274                         continue;
12275                 }
12276
12277                 if (dev_cntrs[i].flags & CNTR_VL) {
12278                         dev_cntrs[i].offset = dd->ndevcntrs;
12279                         for (j = 0; j < C_VL_COUNT; j++) {
12280                                 snprintf(name, C_MAX_NAME, "%s%d",
12281                                          dev_cntrs[i].name, vl_from_idx(j));
12282                                 sz += strlen(name);
12283                                 /* Add ",32" for 32-bit counters */
12284                                 if (dev_cntrs[i].flags & CNTR_32BIT)
12285                                         sz += bit_type_32_sz;
12286                                 sz++;
12287                                 dd->ndevcntrs++;
12288                         }
12289                 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
12290                         dev_cntrs[i].offset = dd->ndevcntrs;
12291                         for (j = 0; j < dd->chip_sdma_engines; j++) {
12292                                 snprintf(name, C_MAX_NAME, "%s%d",
12293                                          dev_cntrs[i].name, j);
12294                                 sz += strlen(name);
12295                                 /* Add ",32" for 32-bit counters */
12296                                 if (dev_cntrs[i].flags & CNTR_32BIT)
12297                                         sz += bit_type_32_sz;
12298                                 sz++;
12299                                 dd->ndevcntrs++;
12300                         }
12301                 } else {
12302                         /* +1 for newline. */
12303                         sz += strlen(dev_cntrs[i].name) + 1;
12304                         /* Add ",32" for 32-bit counters */
12305                         if (dev_cntrs[i].flags & CNTR_32BIT)
12306                                 sz += bit_type_32_sz;
12307                         dev_cntrs[i].offset = dd->ndevcntrs;
12308                         dd->ndevcntrs++;
12309                 }
12310         }
12311
12312         /* allocate space for the counter values */
12313         dd->cntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
12314         if (!dd->cntrs)
12315                 goto bail;
12316
12317         dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
12318         if (!dd->scntrs)
12319                 goto bail;
12320
12321         /* allocate space for the counter names */
12322         dd->cntrnameslen = sz;
12323         dd->cntrnames = kmalloc(sz, GFP_KERNEL);
12324         if (!dd->cntrnames)
12325                 goto bail;
12326
12327         /* fill in the names */
12328         for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) {
12329                 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12330                         /* Nothing */
12331                 } else if (dev_cntrs[i].flags & CNTR_VL) {
12332                         for (j = 0; j < C_VL_COUNT; j++) {
12333                                 snprintf(name, C_MAX_NAME, "%s%d",
12334                                          dev_cntrs[i].name,
12335                                          vl_from_idx(j));
12336                                 memcpy(p, name, strlen(name));
12337                                 p += strlen(name);
12338
12339                                 /* Counter is 32 bits */
12340                                 if (dev_cntrs[i].flags & CNTR_32BIT) {
12341                                         memcpy(p, bit_type_32, bit_type_32_sz);
12342                                         p += bit_type_32_sz;
12343                                 }
12344
12345                                 *p++ = '\n';
12346                         }
12347                 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
12348                         for (j = 0; j < dd->chip_sdma_engines; j++) {
12349                                 snprintf(name, C_MAX_NAME, "%s%d",
12350                                          dev_cntrs[i].name, j);
12351                                 memcpy(p, name, strlen(name));
12352                                 p += strlen(name);
12353
12354                                 /* Counter is 32 bits */
12355                                 if (dev_cntrs[i].flags & CNTR_32BIT) {
12356                                         memcpy(p, bit_type_32, bit_type_32_sz);
12357                                         p += bit_type_32_sz;
12358                                 }
12359
12360                                 *p++ = '\n';
12361                         }
12362                 } else {
12363                         memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name));
12364                         p += strlen(dev_cntrs[i].name);
12365
12366                         /* Counter is 32 bits */
12367                         if (dev_cntrs[i].flags & CNTR_32BIT) {
12368                                 memcpy(p, bit_type_32, bit_type_32_sz);
12369                                 p += bit_type_32_sz;
12370                         }
12371
12372                         *p++ = '\n';
12373                 }
12374         }
12375
12376         /*********************/
12377         /* per port counters */
12378         /*********************/
12379
12380         /*
12381          * Go through the counters for the overflows and disable the ones we
12382          * don't need. This varies based on platform so we need to do it
12383          * dynamically here.
12384          */
12385         rcv_ctxts = dd->num_rcv_contexts;
12386         for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts;
12387              i <= C_RCV_HDR_OVF_LAST; i++) {
12388                 port_cntrs[i].flags |= CNTR_DISABLED;
12389         }
12390
12391         /* size port counter names and determine how many we have*/
12392         sz = 0;
12393         dd->nportcntrs = 0;
12394         for (i = 0; i < PORT_CNTR_LAST; i++) {
12395                 if (port_cntrs[i].flags & CNTR_DISABLED) {
12396                         hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name);
12397                         continue;
12398                 }
12399
12400                 if (port_cntrs[i].flags & CNTR_VL) {
12401                         port_cntrs[i].offset = dd->nportcntrs;
12402                         for (j = 0; j < C_VL_COUNT; j++) {
12403                                 snprintf(name, C_MAX_NAME, "%s%d",
12404                                          port_cntrs[i].name, vl_from_idx(j));
12405                                 sz += strlen(name);
12406                                 /* Add ",32" for 32-bit counters */
12407                                 if (port_cntrs[i].flags & CNTR_32BIT)
12408                                         sz += bit_type_32_sz;
12409                                 sz++;
12410                                 dd->nportcntrs++;
12411                         }
12412                 } else {
12413                         /* +1 for newline */
12414                         sz += strlen(port_cntrs[i].name) + 1;
12415                         /* Add ",32" for 32-bit counters */
12416                         if (port_cntrs[i].flags & CNTR_32BIT)
12417                                 sz += bit_type_32_sz;
12418                         port_cntrs[i].offset = dd->nportcntrs;
12419                         dd->nportcntrs++;
12420                 }
12421         }
12422
12423         /* allocate space for the counter names */
12424         dd->portcntrnameslen = sz;
12425         dd->portcntrnames = kmalloc(sz, GFP_KERNEL);
12426         if (!dd->portcntrnames)
12427                 goto bail;
12428
12429         /* fill in port cntr names */
12430         for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) {
12431                 if (port_cntrs[i].flags & CNTR_DISABLED)
12432                         continue;
12433
12434                 if (port_cntrs[i].flags & CNTR_VL) {
12435                         for (j = 0; j < C_VL_COUNT; j++) {
12436                                 snprintf(name, C_MAX_NAME, "%s%d",
12437                                          port_cntrs[i].name, vl_from_idx(j));
12438                                 memcpy(p, name, strlen(name));
12439                                 p += strlen(name);
12440
12441                                 /* Counter is 32 bits */
12442                                 if (port_cntrs[i].flags & CNTR_32BIT) {
12443                                         memcpy(p, bit_type_32, bit_type_32_sz);
12444                                         p += bit_type_32_sz;
12445                                 }
12446
12447                                 *p++ = '\n';
12448                         }
12449                 } else {
12450                         memcpy(p, port_cntrs[i].name,
12451                                strlen(port_cntrs[i].name));
12452                         p += strlen(port_cntrs[i].name);
12453
12454                         /* Counter is 32 bits */
12455                         if (port_cntrs[i].flags & CNTR_32BIT) {
12456                                 memcpy(p, bit_type_32, bit_type_32_sz);
12457                                 p += bit_type_32_sz;
12458                         }
12459
12460                         *p++ = '\n';
12461                 }
12462         }
12463
12464         /* allocate per port storage for counter values */
12465         ppd = (struct hfi1_pportdata *)(dd + 1);
12466         for (i = 0; i < dd->num_pports; i++, ppd++) {
12467                 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12468                 if (!ppd->cntrs)
12469                         goto bail;
12470
12471                 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12472                 if (!ppd->scntrs)
12473                         goto bail;
12474         }
12475
12476         /* CPU counters need to be allocated and zeroed */
12477         if (init_cpu_counters(dd))
12478                 goto bail;
12479
12480         dd->update_cntr_wq = alloc_ordered_workqueue("hfi1_update_cntr_%d",
12481                                                      WQ_MEM_RECLAIM, dd->unit);
12482         if (!dd->update_cntr_wq)
12483                 goto bail;
12484
12485         INIT_WORK(&dd->update_cntr_work, do_update_synth_timer);
12486
12487         mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12488         return 0;
12489 bail:
12490         free_cntrs(dd);
12491         return -ENOMEM;
12492 }
12493
12494 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate)
12495 {
12496         switch (chip_lstate) {
12497         default:
12498                 dd_dev_err(dd,
12499                            "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n",
12500                            chip_lstate);
12501                 /* fall through */
12502         case LSTATE_DOWN:
12503                 return IB_PORT_DOWN;
12504         case LSTATE_INIT:
12505                 return IB_PORT_INIT;
12506         case LSTATE_ARMED:
12507                 return IB_PORT_ARMED;
12508         case LSTATE_ACTIVE:
12509                 return IB_PORT_ACTIVE;
12510         }
12511 }
12512
12513 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate)
12514 {
12515         /* look at the HFI meta-states only */
12516         switch (chip_pstate & 0xf0) {
12517         default:
12518                 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n",
12519                            chip_pstate);
12520                 /* fall through */
12521         case PLS_DISABLED:
12522                 return IB_PORTPHYSSTATE_DISABLED;
12523         case PLS_OFFLINE:
12524                 return OPA_PORTPHYSSTATE_OFFLINE;
12525         case PLS_POLLING:
12526                 return IB_PORTPHYSSTATE_POLLING;
12527         case PLS_CONFIGPHY:
12528                 return IB_PORTPHYSSTATE_TRAINING;
12529         case PLS_LINKUP:
12530                 return IB_PORTPHYSSTATE_LINKUP;
12531         case PLS_PHYTEST:
12532                 return IB_PORTPHYSSTATE_PHY_TEST;
12533         }
12534 }
12535
12536 /* return the OPA port logical state name */
12537 const char *opa_lstate_name(u32 lstate)
12538 {
12539         static const char * const port_logical_names[] = {
12540                 "PORT_NOP",
12541                 "PORT_DOWN",
12542                 "PORT_INIT",
12543                 "PORT_ARMED",
12544                 "PORT_ACTIVE",
12545                 "PORT_ACTIVE_DEFER",
12546         };
12547         if (lstate < ARRAY_SIZE(port_logical_names))
12548                 return port_logical_names[lstate];
12549         return "unknown";
12550 }
12551
12552 /* return the OPA port physical state name */
12553 const char *opa_pstate_name(u32 pstate)
12554 {
12555         static const char * const port_physical_names[] = {
12556                 "PHYS_NOP",
12557                 "reserved1",
12558                 "PHYS_POLL",
12559                 "PHYS_DISABLED",
12560                 "PHYS_TRAINING",
12561                 "PHYS_LINKUP",
12562                 "PHYS_LINK_ERR_RECOVER",
12563                 "PHYS_PHY_TEST",
12564                 "reserved8",
12565                 "PHYS_OFFLINE",
12566                 "PHYS_GANGED",
12567                 "PHYS_TEST",
12568         };
12569         if (pstate < ARRAY_SIZE(port_physical_names))
12570                 return port_physical_names[pstate];
12571         return "unknown";
12572 }
12573
12574 /*
12575  * Read the hardware link state and set the driver's cached value of it.
12576  * Return the (new) current value.
12577  */
12578 u32 get_logical_state(struct hfi1_pportdata *ppd)
12579 {
12580         u32 new_state;
12581
12582         new_state = chip_to_opa_lstate(ppd->dd, read_logical_state(ppd->dd));
12583         if (new_state != ppd->lstate) {
12584                 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n",
12585                             opa_lstate_name(new_state), new_state);
12586                 ppd->lstate = new_state;
12587         }
12588         /*
12589          * Set port status flags in the page mapped into userspace
12590          * memory. Do it here to ensure a reliable state - this is
12591          * the only function called by all state handling code.
12592          * Always set the flags due to the fact that the cache value
12593          * might have been changed explicitly outside of this
12594          * function.
12595          */
12596         if (ppd->statusp) {
12597                 switch (ppd->lstate) {
12598                 case IB_PORT_DOWN:
12599                 case IB_PORT_INIT:
12600                         *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
12601                                            HFI1_STATUS_IB_READY);
12602                         break;
12603                 case IB_PORT_ARMED:
12604                         *ppd->statusp |= HFI1_STATUS_IB_CONF;
12605                         break;
12606                 case IB_PORT_ACTIVE:
12607                         *ppd->statusp |= HFI1_STATUS_IB_READY;
12608                         break;
12609                 }
12610         }
12611         return ppd->lstate;
12612 }
12613
12614 /**
12615  * wait_logical_linkstate - wait for an IB link state change to occur
12616  * @ppd: port device
12617  * @state: the state to wait for
12618  * @msecs: the number of milliseconds to wait
12619  *
12620  * Wait up to msecs milliseconds for IB link state change to occur.
12621  * For now, take the easy polling route.
12622  * Returns 0 if state reached, otherwise -ETIMEDOUT.
12623  */
12624 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
12625                                   int msecs)
12626 {
12627         unsigned long timeout;
12628
12629         timeout = jiffies + msecs_to_jiffies(msecs);
12630         while (1) {
12631                 if (get_logical_state(ppd) == state)
12632                         return 0;
12633                 if (time_after(jiffies, timeout))
12634                         break;
12635                 msleep(20);
12636         }
12637         dd_dev_err(ppd->dd, "timeout waiting for link state 0x%x\n", state);
12638
12639         return -ETIMEDOUT;
12640 }
12641
12642 u8 hfi1_ibphys_portstate(struct hfi1_pportdata *ppd)
12643 {
12644         u32 pstate;
12645         u32 ib_pstate;
12646
12647         pstate = read_physical_state(ppd->dd);
12648         ib_pstate = chip_to_opa_pstate(ppd->dd, pstate);
12649         if (ppd->last_pstate != ib_pstate) {
12650                 dd_dev_info(ppd->dd,
12651                             "%s: physical state changed to %s (0x%x), phy 0x%x\n",
12652                             __func__, opa_pstate_name(ib_pstate), ib_pstate,
12653                             pstate);
12654                 ppd->last_pstate = ib_pstate;
12655         }
12656         return ib_pstate;
12657 }
12658
12659 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
12660 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12661
12662 #define SET_STATIC_RATE_CONTROL_SMASK(r) \
12663 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12664
12665 void hfi1_init_ctxt(struct send_context *sc)
12666 {
12667         if (sc) {
12668                 struct hfi1_devdata *dd = sc->dd;
12669                 u64 reg;
12670                 u8 set = (sc->type == SC_USER ?
12671                           HFI1_CAP_IS_USET(STATIC_RATE_CTRL) :
12672                           HFI1_CAP_IS_KSET(STATIC_RATE_CTRL));
12673                 reg = read_kctxt_csr(dd, sc->hw_context,
12674                                      SEND_CTXT_CHECK_ENABLE);
12675                 if (set)
12676                         CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
12677                 else
12678                         SET_STATIC_RATE_CONTROL_SMASK(reg);
12679                 write_kctxt_csr(dd, sc->hw_context,
12680                                 SEND_CTXT_CHECK_ENABLE, reg);
12681         }
12682 }
12683
12684 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp)
12685 {
12686         int ret = 0;
12687         u64 reg;
12688
12689         if (dd->icode != ICODE_RTL_SILICON) {
12690                 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
12691                         dd_dev_info(dd, "%s: tempsense not supported by HW\n",
12692                                     __func__);
12693                 return -EINVAL;
12694         }
12695         reg = read_csr(dd, ASIC_STS_THERM);
12696         temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) &
12697                       ASIC_STS_THERM_CURR_TEMP_MASK);
12698         temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) &
12699                         ASIC_STS_THERM_LO_TEMP_MASK);
12700         temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) &
12701                         ASIC_STS_THERM_HI_TEMP_MASK);
12702         temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) &
12703                           ASIC_STS_THERM_CRIT_TEMP_MASK);
12704         /* triggers is a 3-bit value - 1 bit per trigger. */
12705         temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7);
12706
12707         return ret;
12708 }
12709
12710 /* ========================================================================= */
12711
12712 /*
12713  * Enable/disable chip from delivering interrupts.
12714  */
12715 void set_intr_state(struct hfi1_devdata *dd, u32 enable)
12716 {
12717         int i;
12718
12719         /*
12720          * In HFI, the mask needs to be 1 to allow interrupts.
12721          */
12722         if (enable) {
12723                 /* enable all interrupts */
12724                 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12725                         write_csr(dd, CCE_INT_MASK + (8 * i), ~(u64)0);
12726
12727                 init_qsfp_int(dd);
12728         } else {
12729                 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12730                         write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
12731         }
12732 }
12733
12734 /*
12735  * Clear all interrupt sources on the chip.
12736  */
12737 static void clear_all_interrupts(struct hfi1_devdata *dd)
12738 {
12739         int i;
12740
12741         for (i = 0; i < CCE_NUM_INT_CSRS; i++)
12742                 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
12743
12744         write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
12745         write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
12746         write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
12747         write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
12748         write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
12749         write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
12750         write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
12751         for (i = 0; i < dd->chip_send_contexts; i++)
12752                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0);
12753         for (i = 0; i < dd->chip_sdma_engines; i++)
12754                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0);
12755
12756         write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
12757         write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
12758         write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
12759 }
12760
12761 /* Move to pcie.c? */
12762 static void disable_intx(struct pci_dev *pdev)
12763 {
12764         pci_intx(pdev, 0);
12765 }
12766
12767 static void clean_up_interrupts(struct hfi1_devdata *dd)
12768 {
12769         int i;
12770
12771         /* remove irqs - must happen before disabling/turning off */
12772         if (dd->num_msix_entries) {
12773                 /* MSI-X */
12774                 struct hfi1_msix_entry *me = dd->msix_entries;
12775
12776                 for (i = 0; i < dd->num_msix_entries; i++, me++) {
12777                         if (!me->arg) /* => no irq, no affinity */
12778                                 continue;
12779                         hfi1_put_irq_affinity(dd, &dd->msix_entries[i]);
12780                         free_irq(me->msix.vector, me->arg);
12781                 }
12782         } else {
12783                 /* INTx */
12784                 if (dd->requested_intx_irq) {
12785                         free_irq(dd->pcidev->irq, dd);
12786                         dd->requested_intx_irq = 0;
12787                 }
12788         }
12789
12790         /* turn off interrupts */
12791         if (dd->num_msix_entries) {
12792                 /* MSI-X */
12793                 pci_disable_msix(dd->pcidev);
12794         } else {
12795                 /* INTx */
12796                 disable_intx(dd->pcidev);
12797         }
12798
12799         /* clean structures */
12800         kfree(dd->msix_entries);
12801         dd->msix_entries = NULL;
12802         dd->num_msix_entries = 0;
12803 }
12804
12805 /*
12806  * Remap the interrupt source from the general handler to the given MSI-X
12807  * interrupt.
12808  */
12809 static void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr)
12810 {
12811         u64 reg;
12812         int m, n;
12813
12814         /* clear from the handled mask of the general interrupt */
12815         m = isrc / 64;
12816         n = isrc % 64;
12817         dd->gi_mask[m] &= ~((u64)1 << n);
12818
12819         /* direct the chip source to the given MSI-X interrupt */
12820         m = isrc / 8;
12821         n = isrc % 8;
12822         reg = read_csr(dd, CCE_INT_MAP + (8 * m));
12823         reg &= ~((u64)0xff << (8 * n));
12824         reg |= ((u64)msix_intr & 0xff) << (8 * n);
12825         write_csr(dd, CCE_INT_MAP + (8 * m), reg);
12826 }
12827
12828 static void remap_sdma_interrupts(struct hfi1_devdata *dd,
12829                                   int engine, int msix_intr)
12830 {
12831         /*
12832          * SDMA engine interrupt sources grouped by type, rather than
12833          * engine.  Per-engine interrupts are as follows:
12834          *      SDMA
12835          *      SDMAProgress
12836          *      SDMAIdle
12837          */
12838         remap_intr(dd, IS_SDMA_START + 0 * TXE_NUM_SDMA_ENGINES + engine,
12839                    msix_intr);
12840         remap_intr(dd, IS_SDMA_START + 1 * TXE_NUM_SDMA_ENGINES + engine,
12841                    msix_intr);
12842         remap_intr(dd, IS_SDMA_START + 2 * TXE_NUM_SDMA_ENGINES + engine,
12843                    msix_intr);
12844 }
12845
12846 static int request_intx_irq(struct hfi1_devdata *dd)
12847 {
12848         int ret;
12849
12850         snprintf(dd->intx_name, sizeof(dd->intx_name), DRIVER_NAME "_%d",
12851                  dd->unit);
12852         ret = request_irq(dd->pcidev->irq, general_interrupt,
12853                           IRQF_SHARED, dd->intx_name, dd);
12854         if (ret)
12855                 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n",
12856                            ret);
12857         else
12858                 dd->requested_intx_irq = 1;
12859         return ret;
12860 }
12861
12862 static int request_msix_irqs(struct hfi1_devdata *dd)
12863 {
12864         int first_general, last_general;
12865         int first_sdma, last_sdma;
12866         int first_rx, last_rx;
12867         int i, ret = 0;
12868
12869         /* calculate the ranges we are going to use */
12870         first_general = 0;
12871         last_general = first_general + 1;
12872         first_sdma = last_general;
12873         last_sdma = first_sdma + dd->num_sdma;
12874         first_rx = last_sdma;
12875         last_rx = first_rx + dd->n_krcv_queues + HFI1_NUM_VNIC_CTXT;
12876
12877         /* VNIC MSIx interrupts get mapped when VNIC contexts are created */
12878         dd->first_dyn_msix_idx = first_rx + dd->n_krcv_queues;
12879
12880         /*
12881          * Sanity check - the code expects all SDMA chip source
12882          * interrupts to be in the same CSR, starting at bit 0.  Verify
12883          * that this is true by checking the bit location of the start.
12884          */
12885         BUILD_BUG_ON(IS_SDMA_START % 64);
12886
12887         for (i = 0; i < dd->num_msix_entries; i++) {
12888                 struct hfi1_msix_entry *me = &dd->msix_entries[i];
12889                 const char *err_info;
12890                 irq_handler_t handler;
12891                 irq_handler_t thread = NULL;
12892                 void *arg = NULL;
12893                 int idx;
12894                 struct hfi1_ctxtdata *rcd = NULL;
12895                 struct sdma_engine *sde = NULL;
12896
12897                 /* obtain the arguments to request_irq */
12898                 if (first_general <= i && i < last_general) {
12899                         idx = i - first_general;
12900                         handler = general_interrupt;
12901                         arg = dd;
12902                         snprintf(me->name, sizeof(me->name),
12903                                  DRIVER_NAME "_%d", dd->unit);
12904                         err_info = "general";
12905                         me->type = IRQ_GENERAL;
12906                 } else if (first_sdma <= i && i < last_sdma) {
12907                         idx = i - first_sdma;
12908                         sde = &dd->per_sdma[idx];
12909                         handler = sdma_interrupt;
12910                         arg = sde;
12911                         snprintf(me->name, sizeof(me->name),
12912                                  DRIVER_NAME "_%d sdma%d", dd->unit, idx);
12913                         err_info = "sdma";
12914                         remap_sdma_interrupts(dd, idx, i);
12915                         me->type = IRQ_SDMA;
12916                 } else if (first_rx <= i && i < last_rx) {
12917                         idx = i - first_rx;
12918                         rcd = dd->rcd[idx];
12919                         if (rcd) {
12920                                 /*
12921                                  * Set the interrupt register and mask for this
12922                                  * context's interrupt.
12923                                  */
12924                                 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
12925                                 rcd->imask = ((u64)1) <<
12926                                           ((IS_RCVAVAIL_START + idx) % 64);
12927                                 handler = receive_context_interrupt;
12928                                 thread = receive_context_thread;
12929                                 arg = rcd;
12930                                 snprintf(me->name, sizeof(me->name),
12931                                          DRIVER_NAME "_%d kctxt%d",
12932                                          dd->unit, idx);
12933                                 err_info = "receive context";
12934                                 remap_intr(dd, IS_RCVAVAIL_START + idx, i);
12935                                 me->type = IRQ_RCVCTXT;
12936                                 rcd->msix_intr = i;
12937                         }
12938                 } else {
12939                         /* not in our expected range - complain, then
12940                          * ignore it
12941                          */
12942                         dd_dev_err(dd,
12943                                    "Unexpected extra MSI-X interrupt %d\n", i);
12944                         continue;
12945                 }
12946                 /* no argument, no interrupt */
12947                 if (!arg)
12948                         continue;
12949                 /* make sure the name is terminated */
12950                 me->name[sizeof(me->name) - 1] = 0;
12951
12952                 ret = request_threaded_irq(me->msix.vector, handler, thread, 0,
12953                                            me->name, arg);
12954                 if (ret) {
12955                         dd_dev_err(dd,
12956                                    "unable to allocate %s interrupt, vector %d, index %d, err %d\n",
12957                                    err_info, me->msix.vector, idx, ret);
12958                         return ret;
12959                 }
12960                 /*
12961                  * assign arg after request_irq call, so it will be
12962                  * cleaned up
12963                  */
12964                 me->arg = arg;
12965
12966                 ret = hfi1_get_irq_affinity(dd, me);
12967                 if (ret)
12968                         dd_dev_err(dd,
12969                                    "unable to pin IRQ %d\n", ret);
12970         }
12971
12972         return ret;
12973 }
12974
12975 void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd)
12976 {
12977         int i;
12978
12979         if (!dd->num_msix_entries) {
12980                 synchronize_irq(dd->pcidev->irq);
12981                 return;
12982         }
12983
12984         for (i = 0; i < dd->vnic.num_ctxt; i++) {
12985                 struct hfi1_ctxtdata *rcd = dd->vnic.ctxt[i];
12986                 struct hfi1_msix_entry *me = &dd->msix_entries[rcd->msix_intr];
12987
12988                 synchronize_irq(me->msix.vector);
12989         }
12990 }
12991
12992 void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd)
12993 {
12994         struct hfi1_devdata *dd = rcd->dd;
12995         struct hfi1_msix_entry *me = &dd->msix_entries[rcd->msix_intr];
12996
12997         if (!me->arg) /* => no irq, no affinity */
12998                 return;
12999
13000         hfi1_put_irq_affinity(dd, me);
13001         free_irq(me->msix.vector, me->arg);
13002
13003         me->arg = NULL;
13004 }
13005
13006 void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd)
13007 {
13008         struct hfi1_devdata *dd = rcd->dd;
13009         struct hfi1_msix_entry *me;
13010         int idx = rcd->ctxt;
13011         void *arg = rcd;
13012         int ret;
13013
13014         rcd->msix_intr = dd->vnic.msix_idx++;
13015         me = &dd->msix_entries[rcd->msix_intr];
13016
13017         /*
13018          * Set the interrupt register and mask for this
13019          * context's interrupt.
13020          */
13021         rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
13022         rcd->imask = ((u64)1) <<
13023                   ((IS_RCVAVAIL_START + idx) % 64);
13024
13025         snprintf(me->name, sizeof(me->name),
13026                  DRIVER_NAME "_%d kctxt%d", dd->unit, idx);
13027         me->name[sizeof(me->name) - 1] = 0;
13028         me->type = IRQ_RCVCTXT;
13029
13030         remap_intr(dd, IS_RCVAVAIL_START + idx, rcd->msix_intr);
13031
13032         ret = request_threaded_irq(me->msix.vector, receive_context_interrupt,
13033                                    receive_context_thread, 0, me->name, arg);
13034         if (ret) {
13035                 dd_dev_err(dd, "vnic irq request (vector %d, idx %d) fail %d\n",
13036                            me->msix.vector, idx, ret);
13037                 return;
13038         }
13039         /*
13040          * assign arg after request_irq call, so it will be
13041          * cleaned up
13042          */
13043         me->arg = arg;
13044
13045         ret = hfi1_get_irq_affinity(dd, me);
13046         if (ret) {
13047                 dd_dev_err(dd,
13048                            "unable to pin IRQ %d\n", ret);
13049                 free_irq(me->msix.vector, me->arg);
13050         }
13051 }
13052
13053 /*
13054  * Set the general handler to accept all interrupts, remap all
13055  * chip interrupts back to MSI-X 0.
13056  */
13057 static void reset_interrupts(struct hfi1_devdata *dd)
13058 {
13059         int i;
13060
13061         /* all interrupts handled by the general handler */
13062         for (i = 0; i < CCE_NUM_INT_CSRS; i++)
13063                 dd->gi_mask[i] = ~(u64)0;
13064
13065         /* all chip interrupts map to MSI-X 0 */
13066         for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13067                 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
13068 }
13069
13070 static int set_up_interrupts(struct hfi1_devdata *dd)
13071 {
13072         struct hfi1_msix_entry *entries;
13073         u32 total, request;
13074         int i, ret;
13075         int single_interrupt = 0; /* we expect to have all the interrupts */
13076
13077         /*
13078          * Interrupt count:
13079          *      1 general, "slow path" interrupt (includes the SDMA engines
13080          *              slow source, SDMACleanupDone)
13081          *      N interrupts - one per used SDMA engine
13082          *      M interrupt - one per kernel receive context
13083          */
13084         total = 1 + dd->num_sdma + dd->n_krcv_queues + HFI1_NUM_VNIC_CTXT;
13085
13086         entries = kcalloc(total, sizeof(*entries), GFP_KERNEL);
13087         if (!entries) {
13088                 ret = -ENOMEM;
13089                 goto fail;
13090         }
13091         /* 1-1 MSI-X entry assignment */
13092         for (i = 0; i < total; i++)
13093                 entries[i].msix.entry = i;
13094
13095         /* ask for MSI-X interrupts */
13096         request = total;
13097         request_msix(dd, &request, entries);
13098
13099         if (request == 0) {
13100                 /* using INTx */
13101                 /* dd->num_msix_entries already zero */
13102                 kfree(entries);
13103                 single_interrupt = 1;
13104                 dd_dev_err(dd, "MSI-X failed, using INTx interrupts\n");
13105         } else {
13106                 /* using MSI-X */
13107                 dd->num_msix_entries = request;
13108                 dd->msix_entries = entries;
13109
13110                 if (request != total) {
13111                         /* using MSI-X, with reduced interrupts */
13112                         dd_dev_err(
13113                                 dd,
13114                                 "cannot handle reduced interrupt case, want %u, got %u\n",
13115                                 total, request);
13116                         ret = -EINVAL;
13117                         goto fail;
13118                 }
13119                 dd_dev_info(dd, "%u MSI-X interrupts allocated\n", total);
13120         }
13121
13122         /* mask all interrupts */
13123         set_intr_state(dd, 0);
13124         /* clear all pending interrupts */
13125         clear_all_interrupts(dd);
13126
13127         /* reset general handler mask, chip MSI-X mappings */
13128         reset_interrupts(dd);
13129
13130         if (single_interrupt)
13131                 ret = request_intx_irq(dd);
13132         else
13133                 ret = request_msix_irqs(dd);
13134         if (ret)
13135                 goto fail;
13136
13137         return 0;
13138
13139 fail:
13140         clean_up_interrupts(dd);
13141         return ret;
13142 }
13143
13144 /*
13145  * Set up context values in dd.  Sets:
13146  *
13147  *      num_rcv_contexts - number of contexts being used
13148  *      n_krcv_queues - number of kernel contexts
13149  *      first_dyn_alloc_ctxt - first dynamically allocated context
13150  *                             in array of contexts
13151  *      freectxts  - number of free user contexts
13152  *      num_send_contexts - number of PIO send contexts being used
13153  */
13154 static int set_up_context_variables(struct hfi1_devdata *dd)
13155 {
13156         unsigned long num_kernel_contexts;
13157         int total_contexts;
13158         int ret;
13159         unsigned ngroups;
13160         int qos_rmt_count;
13161         int user_rmt_reduced;
13162
13163         /*
13164          * Kernel receive contexts:
13165          * - Context 0 - control context (VL15/multicast/error)
13166          * - Context 1 - first kernel context
13167          * - Context 2 - second kernel context
13168          * ...
13169          */
13170         if (n_krcvqs)
13171                 /*
13172                  * n_krcvqs is the sum of module parameter kernel receive
13173                  * contexts, krcvqs[].  It does not include the control
13174                  * context, so add that.
13175                  */
13176                 num_kernel_contexts = n_krcvqs + 1;
13177         else
13178                 num_kernel_contexts = DEFAULT_KRCVQS + 1;
13179         /*
13180          * Every kernel receive context needs an ACK send context.
13181          * one send context is allocated for each VL{0-7} and VL15
13182          */
13183         if (num_kernel_contexts > (dd->chip_send_contexts - num_vls - 1)) {
13184                 dd_dev_err(dd,
13185                            "Reducing # kernel rcv contexts to: %d, from %lu\n",
13186                            (int)(dd->chip_send_contexts - num_vls - 1),
13187                            num_kernel_contexts);
13188                 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1;
13189         }
13190         /*
13191          * User contexts:
13192          *      - default to 1 user context per real (non-HT) CPU core if
13193          *        num_user_contexts is negative
13194          */
13195         if (num_user_contexts < 0)
13196                 num_user_contexts =
13197                         cpumask_weight(&node_affinity.real_cpu_mask);
13198
13199         total_contexts = num_kernel_contexts + num_user_contexts;
13200
13201         /*
13202          * Adjust the counts given a global max.
13203          */
13204         if (total_contexts > dd->chip_rcv_contexts) {
13205                 dd_dev_err(dd,
13206                            "Reducing # user receive contexts to: %d, from %d\n",
13207                            (int)(dd->chip_rcv_contexts - num_kernel_contexts),
13208                            (int)num_user_contexts);
13209                 num_user_contexts = dd->chip_rcv_contexts - num_kernel_contexts;
13210                 /* recalculate */
13211                 total_contexts = num_kernel_contexts + num_user_contexts;
13212         }
13213
13214         /* each user context requires an entry in the RMT */
13215         qos_rmt_count = qos_rmt_entries(dd, NULL, NULL);
13216         if (qos_rmt_count + num_user_contexts > NUM_MAP_ENTRIES) {
13217                 user_rmt_reduced = NUM_MAP_ENTRIES - qos_rmt_count;
13218                 dd_dev_err(dd,
13219                            "RMT size is reducing the number of user receive contexts from %d to %d\n",
13220                            (int)num_user_contexts,
13221                            user_rmt_reduced);
13222                 /* recalculate */
13223                 num_user_contexts = user_rmt_reduced;
13224                 total_contexts = num_kernel_contexts + num_user_contexts;
13225         }
13226
13227         /* Accommodate VNIC contexts */
13228         if ((total_contexts + HFI1_NUM_VNIC_CTXT) <= dd->chip_rcv_contexts)
13229                 total_contexts += HFI1_NUM_VNIC_CTXT;
13230
13231         /* the first N are kernel contexts, the rest are user/vnic contexts */
13232         dd->num_rcv_contexts = total_contexts;
13233         dd->n_krcv_queues = num_kernel_contexts;
13234         dd->first_dyn_alloc_ctxt = num_kernel_contexts;
13235         dd->num_user_contexts = num_user_contexts;
13236         dd->freectxts = num_user_contexts;
13237         dd_dev_info(dd,
13238                     "rcv contexts: chip %d, used %d (kernel %d, user %d)\n",
13239                     (int)dd->chip_rcv_contexts,
13240                     (int)dd->num_rcv_contexts,
13241                     (int)dd->n_krcv_queues,
13242                     (int)dd->num_rcv_contexts - dd->n_krcv_queues);
13243
13244         /*
13245          * Receive array allocation:
13246          *   All RcvArray entries are divided into groups of 8. This
13247          *   is required by the hardware and will speed up writes to
13248          *   consecutive entries by using write-combining of the entire
13249          *   cacheline.
13250          *
13251          *   The number of groups are evenly divided among all contexts.
13252          *   any left over groups will be given to the first N user
13253          *   contexts.
13254          */
13255         dd->rcv_entries.group_size = RCV_INCREMENT;
13256         ngroups = dd->chip_rcv_array_count / dd->rcv_entries.group_size;
13257         dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts;
13258         dd->rcv_entries.nctxt_extra = ngroups -
13259                 (dd->num_rcv_contexts * dd->rcv_entries.ngroups);
13260         dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n",
13261                     dd->rcv_entries.ngroups,
13262                     dd->rcv_entries.nctxt_extra);
13263         if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size >
13264             MAX_EAGER_ENTRIES * 2) {
13265                 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) /
13266                         dd->rcv_entries.group_size;
13267                 dd_dev_info(dd,
13268                             "RcvArray group count too high, change to %u\n",
13269                             dd->rcv_entries.ngroups);
13270                 dd->rcv_entries.nctxt_extra = 0;
13271         }
13272         /*
13273          * PIO send contexts
13274          */
13275         ret = init_sc_pools_and_sizes(dd);
13276         if (ret >= 0) { /* success */
13277                 dd->num_send_contexts = ret;
13278                 dd_dev_info(
13279                         dd,
13280                         "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n",
13281                         dd->chip_send_contexts,
13282                         dd->num_send_contexts,
13283                         dd->sc_sizes[SC_KERNEL].count,
13284                         dd->sc_sizes[SC_ACK].count,
13285                         dd->sc_sizes[SC_USER].count,
13286                         dd->sc_sizes[SC_VL15].count);
13287                 ret = 0;        /* success */
13288         }
13289
13290         return ret;
13291 }
13292
13293 /*
13294  * Set the device/port partition key table. The MAD code
13295  * will ensure that, at least, the partial management
13296  * partition key is present in the table.
13297  */
13298 static void set_partition_keys(struct hfi1_pportdata *ppd)
13299 {
13300         struct hfi1_devdata *dd = ppd->dd;
13301         u64 reg = 0;
13302         int i;
13303
13304         dd_dev_info(dd, "Setting partition keys\n");
13305         for (i = 0; i < hfi1_get_npkeys(dd); i++) {
13306                 reg |= (ppd->pkeys[i] &
13307                         RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
13308                         ((i % 4) *
13309                          RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
13310                 /* Each register holds 4 PKey values. */
13311                 if ((i % 4) == 3) {
13312                         write_csr(dd, RCV_PARTITION_KEY +
13313                                   ((i - 3) * 2), reg);
13314                         reg = 0;
13315                 }
13316         }
13317
13318         /* Always enable HW pkeys check when pkeys table is set */
13319         add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK);
13320 }
13321
13322 /*
13323  * These CSRs and memories are uninitialized on reset and must be
13324  * written before reading to set the ECC/parity bits.
13325  *
13326  * NOTE: All user context CSRs that are not mmaped write-only
13327  * (e.g. the TID flows) must be initialized even if the driver never
13328  * reads them.
13329  */
13330 static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd)
13331 {
13332         int i, j;
13333
13334         /* CceIntMap */
13335         for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13336                 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
13337
13338         /* SendCtxtCreditReturnAddr */
13339         for (i = 0; i < dd->chip_send_contexts; i++)
13340                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13341
13342         /* PIO Send buffers */
13343         /* SDMA Send buffers */
13344         /*
13345          * These are not normally read, and (presently) have no method
13346          * to be read, so are not pre-initialized
13347          */
13348
13349         /* RcvHdrAddr */
13350         /* RcvHdrTailAddr */
13351         /* RcvTidFlowTable */
13352         for (i = 0; i < dd->chip_rcv_contexts; i++) {
13353                 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13354                 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13355                 for (j = 0; j < RXE_NUM_TID_FLOWS; j++)
13356                         write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0);
13357         }
13358
13359         /* RcvArray */
13360         for (i = 0; i < dd->chip_rcv_array_count; i++)
13361                 write_csr(dd, RCV_ARRAY + (8 * i),
13362                           RCV_ARRAY_RT_WRITE_ENABLE_SMASK);
13363
13364         /* RcvQPMapTable */
13365         for (i = 0; i < 32; i++)
13366                 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13367 }
13368
13369 /*
13370  * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13371  */
13372 static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits,
13373                              u64 ctrl_bits)
13374 {
13375         unsigned long timeout;
13376         u64 reg;
13377
13378         /* is the condition present? */
13379         reg = read_csr(dd, CCE_STATUS);
13380         if ((reg & status_bits) == 0)
13381                 return;
13382
13383         /* clear the condition */
13384         write_csr(dd, CCE_CTRL, ctrl_bits);
13385
13386         /* wait for the condition to clear */
13387         timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT);
13388         while (1) {
13389                 reg = read_csr(dd, CCE_STATUS);
13390                 if ((reg & status_bits) == 0)
13391                         return;
13392                 if (time_after(jiffies, timeout)) {
13393                         dd_dev_err(dd,
13394                                    "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
13395                                    status_bits, reg & status_bits);
13396                         return;
13397                 }
13398                 udelay(1);
13399         }
13400 }
13401
13402 /* set CCE CSRs to chip reset defaults */
13403 static void reset_cce_csrs(struct hfi1_devdata *dd)
13404 {
13405         int i;
13406
13407         /* CCE_REVISION read-only */
13408         /* CCE_REVISION2 read-only */
13409         /* CCE_CTRL - bits clear automatically */
13410         /* CCE_STATUS read-only, use CceCtrl to clear */
13411         clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK);
13412         clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK);
13413         clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK);
13414         for (i = 0; i < CCE_NUM_SCRATCH; i++)
13415                 write_csr(dd, CCE_SCRATCH + (8 * i), 0);
13416         /* CCE_ERR_STATUS read-only */
13417         write_csr(dd, CCE_ERR_MASK, 0);
13418         write_csr(dd, CCE_ERR_CLEAR, ~0ull);
13419         /* CCE_ERR_FORCE leave alone */
13420         for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++)
13421                 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
13422         write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
13423         /* CCE_PCIE_CTRL leave alone */
13424         for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) {
13425                 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
13426                 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
13427                           CCE_MSIX_TABLE_UPPER_RESETCSR);
13428         }
13429         for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) {
13430                 /* CCE_MSIX_PBA read-only */
13431                 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
13432                 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
13433         }
13434         for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13435                 write_csr(dd, CCE_INT_MAP, 0);
13436         for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
13437                 /* CCE_INT_STATUS read-only */
13438                 write_csr(dd, CCE_INT_MASK + (8 * i), 0);
13439                 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
13440                 /* CCE_INT_FORCE leave alone */
13441                 /* CCE_INT_BLOCKED read-only */
13442         }
13443         for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++)
13444                 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
13445 }
13446
13447 /* set MISC CSRs to chip reset defaults */
13448 static void reset_misc_csrs(struct hfi1_devdata *dd)
13449 {
13450         int i;
13451
13452         for (i = 0; i < 32; i++) {
13453                 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
13454                 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
13455                 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
13456         }
13457         /*
13458          * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13459          * only be written 128-byte chunks
13460          */
13461         /* init RSA engine to clear lingering errors */
13462         write_csr(dd, MISC_CFG_RSA_CMD, 1);
13463         write_csr(dd, MISC_CFG_RSA_MU, 0);
13464         write_csr(dd, MISC_CFG_FW_CTRL, 0);
13465         /* MISC_STS_8051_DIGEST read-only */
13466         /* MISC_STS_SBM_DIGEST read-only */
13467         /* MISC_STS_PCIE_DIGEST read-only */
13468         /* MISC_STS_FAB_DIGEST read-only */
13469         /* MISC_ERR_STATUS read-only */
13470         write_csr(dd, MISC_ERR_MASK, 0);
13471         write_csr(dd, MISC_ERR_CLEAR, ~0ull);
13472         /* MISC_ERR_FORCE leave alone */
13473 }
13474
13475 /* set TXE CSRs to chip reset defaults */
13476 static void reset_txe_csrs(struct hfi1_devdata *dd)
13477 {
13478         int i;
13479
13480         /*
13481          * TXE Kernel CSRs
13482          */
13483         write_csr(dd, SEND_CTRL, 0);
13484         __cm_reset(dd, 0);      /* reset CM internal state */
13485         /* SEND_CONTEXTS read-only */
13486         /* SEND_DMA_ENGINES read-only */
13487         /* SEND_PIO_MEM_SIZE read-only */
13488         /* SEND_DMA_MEM_SIZE read-only */
13489         write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
13490         pio_reset_all(dd);      /* SEND_PIO_INIT_CTXT */
13491         /* SEND_PIO_ERR_STATUS read-only */
13492         write_csr(dd, SEND_PIO_ERR_MASK, 0);
13493         write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
13494         /* SEND_PIO_ERR_FORCE leave alone */
13495         /* SEND_DMA_ERR_STATUS read-only */
13496         write_csr(dd, SEND_DMA_ERR_MASK, 0);
13497         write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
13498         /* SEND_DMA_ERR_FORCE leave alone */
13499         /* SEND_EGRESS_ERR_STATUS read-only */
13500         write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
13501         write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
13502         /* SEND_EGRESS_ERR_FORCE leave alone */
13503         write_csr(dd, SEND_BTH_QP, 0);
13504         write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
13505         write_csr(dd, SEND_SC2VLT0, 0);
13506         write_csr(dd, SEND_SC2VLT1, 0);
13507         write_csr(dd, SEND_SC2VLT2, 0);
13508         write_csr(dd, SEND_SC2VLT3, 0);
13509         write_csr(dd, SEND_LEN_CHECK0, 0);
13510         write_csr(dd, SEND_LEN_CHECK1, 0);
13511         /* SEND_ERR_STATUS read-only */
13512         write_csr(dd, SEND_ERR_MASK, 0);
13513         write_csr(dd, SEND_ERR_CLEAR, ~0ull);
13514         /* SEND_ERR_FORCE read-only */
13515         for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++)
13516                 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
13517         for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++)
13518                 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
13519         for (i = 0; i < dd->chip_send_contexts / NUM_CONTEXTS_PER_SET; i++)
13520                 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
13521         for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++)
13522                 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
13523         for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++)
13524                 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
13525         write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
13526         write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
13527         /* SEND_CM_CREDIT_USED_STATUS read-only */
13528         write_csr(dd, SEND_CM_TIMER_CTRL, 0);
13529         write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
13530         write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
13531         write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
13532         write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
13533         for (i = 0; i < TXE_NUM_DATA_VL; i++)
13534                 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
13535         write_csr(dd, SEND_CM_CREDIT_VL15, 0);
13536         /* SEND_CM_CREDIT_USED_VL read-only */
13537         /* SEND_CM_CREDIT_USED_VL15 read-only */
13538         /* SEND_EGRESS_CTXT_STATUS read-only */
13539         /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13540         write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
13541         /* SEND_EGRESS_ERR_INFO read-only */
13542         /* SEND_EGRESS_ERR_SOURCE read-only */
13543
13544         /*
13545          * TXE Per-Context CSRs
13546          */
13547         for (i = 0; i < dd->chip_send_contexts; i++) {
13548                 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13549                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0);
13550                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13551                 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0);
13552                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0);
13553                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull);
13554                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0);
13555                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0);
13556                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0);
13557                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13558                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0);
13559                 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0);
13560         }
13561
13562         /*
13563          * TXE Per-SDMA CSRs
13564          */
13565         for (i = 0; i < dd->chip_sdma_engines; i++) {
13566                 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13567                 /* SEND_DMA_STATUS read-only */
13568                 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0);
13569                 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0);
13570                 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0);
13571                 /* SEND_DMA_HEAD read-only */
13572                 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0);
13573                 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0);
13574                 /* SEND_DMA_IDLE_CNT read-only */
13575                 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0);
13576                 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0);
13577                 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13578                 /* SEND_DMA_ENG_ERR_STATUS read-only */
13579                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0);
13580                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull);
13581                 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13582                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0);
13583                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0);
13584                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0);
13585                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0);
13586                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0);
13587                 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0);
13588                 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0);
13589         }
13590 }
13591
13592 /*
13593  * Expect on entry:
13594  * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13595  */
13596 static void init_rbufs(struct hfi1_devdata *dd)
13597 {
13598         u64 reg;
13599         int count;
13600
13601         /*
13602          * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13603          * clear.
13604          */
13605         count = 0;
13606         while (1) {
13607                 reg = read_csr(dd, RCV_STATUS);
13608                 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK
13609                             | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0)
13610                         break;
13611                 /*
13612                  * Give up after 1ms - maximum wait time.
13613                  *
13614                  * RBuf size is 136KiB.  Slowest possible is PCIe Gen1 x1 at
13615                  * 250MB/s bandwidth.  Lower rate to 66% for overhead to get:
13616                  *      136 KB / (66% * 250MB/s) = 844us
13617                  */
13618                 if (count++ > 500) {
13619                         dd_dev_err(dd,
13620                                    "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n",
13621                                    __func__, reg);
13622                         break;
13623                 }
13624                 udelay(2); /* do not busy-wait the CSR */
13625         }
13626
13627         /* start the init - expect RcvCtrl to be 0 */
13628         write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
13629
13630         /*
13631          * Read to force the write of Rcvtrl.RxRbufInit.  There is a brief
13632          * period after the write before RcvStatus.RxRbufInitDone is valid.
13633          * The delay in the first run through the loop below is sufficient and
13634          * required before the first read of RcvStatus.RxRbufInintDone.
13635          */
13636         read_csr(dd, RCV_CTRL);
13637
13638         /* wait for the init to finish */
13639         count = 0;
13640         while (1) {
13641                 /* delay is required first time through - see above */
13642                 udelay(2); /* do not busy-wait the CSR */
13643                 reg = read_csr(dd, RCV_STATUS);
13644                 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK))
13645                         break;
13646
13647                 /* give up after 100us - slowest possible at 33MHz is 73us */
13648                 if (count++ > 50) {
13649                         dd_dev_err(dd,
13650                                    "%s: RcvStatus.RxRbufInit not set, continuing\n",
13651                                    __func__);
13652                         break;
13653                 }
13654         }
13655 }
13656
13657 /* set RXE CSRs to chip reset defaults */
13658 static void reset_rxe_csrs(struct hfi1_devdata *dd)
13659 {
13660         int i, j;
13661
13662         /*
13663          * RXE Kernel CSRs
13664          */
13665         write_csr(dd, RCV_CTRL, 0);
13666         init_rbufs(dd);
13667         /* RCV_STATUS read-only */
13668         /* RCV_CONTEXTS read-only */
13669         /* RCV_ARRAY_CNT read-only */
13670         /* RCV_BUF_SIZE read-only */
13671         write_csr(dd, RCV_BTH_QP, 0);
13672         write_csr(dd, RCV_MULTICAST, 0);
13673         write_csr(dd, RCV_BYPASS, 0);
13674         write_csr(dd, RCV_VL15, 0);
13675         /* this is a clear-down */
13676         write_csr(dd, RCV_ERR_INFO,
13677                   RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
13678         /* RCV_ERR_STATUS read-only */
13679         write_csr(dd, RCV_ERR_MASK, 0);
13680         write_csr(dd, RCV_ERR_CLEAR, ~0ull);
13681         /* RCV_ERR_FORCE leave alone */
13682         for (i = 0; i < 32; i++)
13683                 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13684         for (i = 0; i < 4; i++)
13685                 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
13686         for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++)
13687                 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
13688         for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++)
13689                 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
13690         for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++)
13691                 clear_rsm_rule(dd, i);
13692         for (i = 0; i < 32; i++)
13693                 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
13694
13695         /*
13696          * RXE Kernel and User Per-Context CSRs
13697          */
13698         for (i = 0; i < dd->chip_rcv_contexts; i++) {
13699                 /* kernel */
13700                 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0);
13701                 /* RCV_CTXT_STATUS read-only */
13702                 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0);
13703                 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0);
13704                 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0);
13705                 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13706                 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0);
13707                 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0);
13708                 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0);
13709                 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13710                 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0);
13711                 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0);
13712
13713                 /* user */
13714                 /* RCV_HDR_TAIL read-only */
13715                 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0);
13716                 /* RCV_EGR_INDEX_TAIL read-only */
13717                 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0);
13718                 /* RCV_EGR_OFFSET_TAIL read-only */
13719                 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) {
13720                         write_uctxt_csr(dd, i,
13721                                         RCV_TID_FLOW_TABLE + (8 * j), 0);
13722                 }
13723         }
13724 }
13725
13726 /*
13727  * Set sc2vl tables.
13728  *
13729  * They power on to zeros, so to avoid send context errors
13730  * they need to be set:
13731  *
13732  * SC 0-7 -> VL 0-7 (respectively)
13733  * SC 15  -> VL 15
13734  * otherwise
13735  *        -> VL 0
13736  */
13737 static void init_sc2vl_tables(struct hfi1_devdata *dd)
13738 {
13739         int i;
13740         /* init per architecture spec, constrained by hardware capability */
13741
13742         /* HFI maps sent packets */
13743         write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
13744                 0,
13745                 0, 0, 1, 1,
13746                 2, 2, 3, 3,
13747                 4, 4, 5, 5,
13748                 6, 6, 7, 7));
13749         write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
13750                 1,
13751                 8, 0, 9, 0,
13752                 10, 0, 11, 0,
13753                 12, 0, 13, 0,
13754                 14, 0, 15, 15));
13755         write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
13756                 2,
13757                 16, 0, 17, 0,
13758                 18, 0, 19, 0,
13759                 20, 0, 21, 0,
13760                 22, 0, 23, 0));
13761         write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
13762                 3,
13763                 24, 0, 25, 0,
13764                 26, 0, 27, 0,
13765                 28, 0, 29, 0,
13766                 30, 0, 31, 0));
13767
13768         /* DC maps received packets */
13769         write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
13770                 15_0,
13771                 0, 0, 1, 1,  2, 2,  3, 3,  4, 4,  5, 5,  6, 6,  7,  7,
13772                 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15));
13773         write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
13774                 31_16,
13775                 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0,
13776                 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0));
13777
13778         /* initialize the cached sc2vl values consistently with h/w */
13779         for (i = 0; i < 32; i++) {
13780                 if (i < 8 || i == 15)
13781                         *((u8 *)(dd->sc2vl) + i) = (u8)i;
13782                 else
13783                         *((u8 *)(dd->sc2vl) + i) = 0;
13784         }
13785 }
13786
13787 /*
13788  * Read chip sizes and then reset parts to sane, disabled, values.  We cannot
13789  * depend on the chip going through a power-on reset - a driver may be loaded
13790  * and unloaded many times.
13791  *
13792  * Do not write any CSR values to the chip in this routine - there may be
13793  * a reset following the (possible) FLR in this routine.
13794  *
13795  */
13796 static void init_chip(struct hfi1_devdata *dd)
13797 {
13798         int i;
13799
13800         /*
13801          * Put the HFI CSRs in a known state.
13802          * Combine this with a DC reset.
13803          *
13804          * Stop the device from doing anything while we do a
13805          * reset.  We know there are no other active users of
13806          * the device since we are now in charge.  Turn off
13807          * off all outbound and inbound traffic and make sure
13808          * the device does not generate any interrupts.
13809          */
13810
13811         /* disable send contexts and SDMA engines */
13812         write_csr(dd, SEND_CTRL, 0);
13813         for (i = 0; i < dd->chip_send_contexts; i++)
13814                 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13815         for (i = 0; i < dd->chip_sdma_engines; i++)
13816                 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13817         /* disable port (turn off RXE inbound traffic) and contexts */
13818         write_csr(dd, RCV_CTRL, 0);
13819         for (i = 0; i < dd->chip_rcv_contexts; i++)
13820                 write_csr(dd, RCV_CTXT_CTRL, 0);
13821         /* mask all interrupt sources */
13822         for (i = 0; i < CCE_NUM_INT_CSRS; i++)
13823                 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
13824
13825         /*
13826          * DC Reset: do a full DC reset before the register clear.
13827          * A recommended length of time to hold is one CSR read,
13828          * so reread the CceDcCtrl.  Then, hold the DC in reset
13829          * across the clear.
13830          */
13831         write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
13832         (void)read_csr(dd, CCE_DC_CTRL);
13833
13834         if (use_flr) {
13835                 /*
13836                  * A FLR will reset the SPC core and part of the PCIe.
13837                  * The parts that need to be restored have already been
13838                  * saved.
13839                  */
13840                 dd_dev_info(dd, "Resetting CSRs with FLR\n");
13841
13842                 /* do the FLR, the DC reset will remain */
13843                 pcie_flr(dd->pcidev);
13844
13845                 /* restore command and BARs */
13846                 restore_pci_variables(dd);
13847
13848                 if (is_ax(dd)) {
13849                         dd_dev_info(dd, "Resetting CSRs with FLR\n");
13850                         pcie_flr(dd->pcidev);
13851                         restore_pci_variables(dd);
13852                 }
13853         } else {
13854                 dd_dev_info(dd, "Resetting CSRs with writes\n");
13855                 reset_cce_csrs(dd);
13856                 reset_txe_csrs(dd);
13857                 reset_rxe_csrs(dd);
13858                 reset_misc_csrs(dd);
13859         }
13860         /* clear the DC reset */
13861         write_csr(dd, CCE_DC_CTRL, 0);
13862
13863         /* Set the LED off */
13864         setextled(dd, 0);
13865
13866         /*
13867          * Clear the QSFP reset.
13868          * An FLR enforces a 0 on all out pins. The driver does not touch
13869          * ASIC_QSFPn_OUT otherwise.  This leaves RESET_N low and
13870          * anything plugged constantly in reset, if it pays attention
13871          * to RESET_N.
13872          * Prime examples of this are optical cables. Set all pins high.
13873          * I2CCLK and I2CDAT will change per direction, and INT_N and
13874          * MODPRS_N are input only and their value is ignored.
13875          */
13876         write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
13877         write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
13878         init_chip_resources(dd);
13879 }
13880
13881 static void init_early_variables(struct hfi1_devdata *dd)
13882 {
13883         int i;
13884
13885         /* assign link credit variables */
13886         dd->vau = CM_VAU;
13887         dd->link_credits = CM_GLOBAL_CREDITS;
13888         if (is_ax(dd))
13889                 dd->link_credits--;
13890         dd->vcu = cu_to_vcu(hfi1_cu);
13891         /* enough room for 8 MAD packets plus header - 17K */
13892         dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau);
13893         if (dd->vl15_init > dd->link_credits)
13894                 dd->vl15_init = dd->link_credits;
13895
13896         write_uninitialized_csrs_and_memories(dd);
13897
13898         if (HFI1_CAP_IS_KSET(PKEY_CHECK))
13899                 for (i = 0; i < dd->num_pports; i++) {
13900                         struct hfi1_pportdata *ppd = &dd->pport[i];
13901
13902                         set_partition_keys(ppd);
13903                 }
13904         init_sc2vl_tables(dd);
13905 }
13906
13907 static void init_kdeth_qp(struct hfi1_devdata *dd)
13908 {
13909         /* user changed the KDETH_QP */
13910         if (kdeth_qp != 0 && kdeth_qp >= 0xff) {
13911                 /* out of range or illegal value */
13912                 dd_dev_err(dd, "Invalid KDETH queue pair prefix, ignoring");
13913                 kdeth_qp = 0;
13914         }
13915         if (kdeth_qp == 0)      /* not set, or failed range check */
13916                 kdeth_qp = DEFAULT_KDETH_QP;
13917
13918         write_csr(dd, SEND_BTH_QP,
13919                   (kdeth_qp & SEND_BTH_QP_KDETH_QP_MASK) <<
13920                   SEND_BTH_QP_KDETH_QP_SHIFT);
13921
13922         write_csr(dd, RCV_BTH_QP,
13923                   (kdeth_qp & RCV_BTH_QP_KDETH_QP_MASK) <<
13924                   RCV_BTH_QP_KDETH_QP_SHIFT);
13925 }
13926
13927 /**
13928  * init_qpmap_table
13929  * @dd - device data
13930  * @first_ctxt - first context
13931  * @last_ctxt - first context
13932  *
13933  * This return sets the qpn mapping table that
13934  * is indexed by qpn[8:1].
13935  *
13936  * The routine will round robin the 256 settings
13937  * from first_ctxt to last_ctxt.
13938  *
13939  * The first/last looks ahead to having specialized
13940  * receive contexts for mgmt and bypass.  Normal
13941  * verbs traffic will assumed to be on a range
13942  * of receive contexts.
13943  */
13944 static void init_qpmap_table(struct hfi1_devdata *dd,
13945                              u32 first_ctxt,
13946                              u32 last_ctxt)
13947 {
13948         u64 reg = 0;
13949         u64 regno = RCV_QP_MAP_TABLE;
13950         int i;
13951         u64 ctxt = first_ctxt;
13952
13953         for (i = 0; i < 256; i++) {
13954                 reg |= ctxt << (8 * (i % 8));
13955                 ctxt++;
13956                 if (ctxt > last_ctxt)
13957                         ctxt = first_ctxt;
13958                 if (i % 8 == 7) {
13959                         write_csr(dd, regno, reg);
13960                         reg = 0;
13961                         regno += 8;
13962                 }
13963         }
13964
13965         add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK
13966                         | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK);
13967 }
13968
13969 struct rsm_map_table {
13970         u64 map[NUM_MAP_REGS];
13971         unsigned int used;
13972 };
13973
13974 struct rsm_rule_data {
13975         u8 offset;
13976         u8 pkt_type;
13977         u32 field1_off;
13978         u32 field2_off;
13979         u32 index1_off;
13980         u32 index1_width;
13981         u32 index2_off;
13982         u32 index2_width;
13983         u32 mask1;
13984         u32 value1;
13985         u32 mask2;
13986         u32 value2;
13987 };
13988
13989 /*
13990  * Return an initialized RMT map table for users to fill in.  OK if it
13991  * returns NULL, indicating no table.
13992  */
13993 static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd)
13994 {
13995         struct rsm_map_table *rmt;
13996         u8 rxcontext = is_ax(dd) ? 0 : 0xff;  /* 0 is default if a0 ver. */
13997
13998         rmt = kmalloc(sizeof(*rmt), GFP_KERNEL);
13999         if (rmt) {
14000                 memset(rmt->map, rxcontext, sizeof(rmt->map));
14001                 rmt->used = 0;
14002         }
14003
14004         return rmt;
14005 }
14006
14007 /*
14008  * Write the final RMT map table to the chip and free the table.  OK if
14009  * table is NULL.
14010  */
14011 static void complete_rsm_map_table(struct hfi1_devdata *dd,
14012                                    struct rsm_map_table *rmt)
14013 {
14014         int i;
14015
14016         if (rmt) {
14017                 /* write table to chip */
14018                 for (i = 0; i < NUM_MAP_REGS; i++)
14019                         write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
14020
14021                 /* enable RSM */
14022                 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
14023         }
14024 }
14025
14026 /*
14027  * Add a receive side mapping rule.
14028  */
14029 static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index,
14030                          struct rsm_rule_data *rrd)
14031 {
14032         write_csr(dd, RCV_RSM_CFG + (8 * rule_index),
14033                   (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT |
14034                   1ull << rule_index | /* enable bit */
14035                   (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT);
14036         write_csr(dd, RCV_RSM_SELECT + (8 * rule_index),
14037                   (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT |
14038                   (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT |
14039                   (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT |
14040                   (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT |
14041                   (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT |
14042                   (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT);
14043         write_csr(dd, RCV_RSM_MATCH + (8 * rule_index),
14044                   (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT |
14045                   (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT |
14046                   (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT |
14047                   (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT);
14048 }
14049
14050 /*
14051  * Clear a receive side mapping rule.
14052  */
14053 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index)
14054 {
14055         write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0);
14056         write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0);
14057         write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0);
14058 }
14059
14060 /* return the number of RSM map table entries that will be used for QOS */
14061 static int qos_rmt_entries(struct hfi1_devdata *dd, unsigned int *mp,
14062                            unsigned int *np)
14063 {
14064         int i;
14065         unsigned int m, n;
14066         u8 max_by_vl = 0;
14067
14068         /* is QOS active at all? */
14069         if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS ||
14070             num_vls == 1 ||
14071             krcvqsset <= 1)
14072                 goto no_qos;
14073
14074         /* determine bits for qpn */
14075         for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++)
14076                 if (krcvqs[i] > max_by_vl)
14077                         max_by_vl = krcvqs[i];
14078         if (max_by_vl > 32)
14079                 goto no_qos;
14080         m = ilog2(__roundup_pow_of_two(max_by_vl));
14081
14082         /* determine bits for vl */
14083         n = ilog2(__roundup_pow_of_two(num_vls));
14084
14085         /* reject if too much is used */
14086         if ((m + n) > 7)
14087                 goto no_qos;
14088
14089         if (mp)
14090                 *mp = m;
14091         if (np)
14092                 *np = n;
14093
14094         return 1 << (m + n);
14095
14096 no_qos:
14097         if (mp)
14098                 *mp = 0;
14099         if (np)
14100                 *np = 0;
14101         return 0;
14102 }
14103
14104 /**
14105  * init_qos - init RX qos
14106  * @dd - device data
14107  * @rmt - RSM map table
14108  *
14109  * This routine initializes Rule 0 and the RSM map table to implement
14110  * quality of service (qos).
14111  *
14112  * If all of the limit tests succeed, qos is applied based on the array
14113  * interpretation of krcvqs where entry 0 is VL0.
14114  *
14115  * The number of vl bits (n) and the number of qpn bits (m) are computed to
14116  * feed both the RSM map table and the single rule.
14117  */
14118 static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt)
14119 {
14120         struct rsm_rule_data rrd;
14121         unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
14122         unsigned int rmt_entries;
14123         u64 reg;
14124
14125         if (!rmt)
14126                 goto bail;
14127         rmt_entries = qos_rmt_entries(dd, &m, &n);
14128         if (rmt_entries == 0)
14129                 goto bail;
14130         qpns_per_vl = 1 << m;
14131
14132         /* enough room in the map table? */
14133         rmt_entries = 1 << (m + n);
14134         if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES)
14135                 goto bail;
14136
14137         /* add qos entries to the the RSM map table */
14138         for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) {
14139                 unsigned tctxt;
14140
14141                 for (qpn = 0, tctxt = ctxt;
14142                      krcvqs[i] && qpn < qpns_per_vl; qpn++) {
14143                         unsigned idx, regoff, regidx;
14144
14145                         /* generate the index the hardware will produce */
14146                         idx = rmt->used + ((qpn << n) ^ i);
14147                         regoff = (idx % 8) * 8;
14148                         regidx = idx / 8;
14149                         /* replace default with context number */
14150                         reg = rmt->map[regidx];
14151                         reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
14152                                 << regoff);
14153                         reg |= (u64)(tctxt++) << regoff;
14154                         rmt->map[regidx] = reg;
14155                         if (tctxt == ctxt + krcvqs[i])
14156                                 tctxt = ctxt;
14157                 }
14158                 ctxt += krcvqs[i];
14159         }
14160
14161         rrd.offset = rmt->used;
14162         rrd.pkt_type = 2;
14163         rrd.field1_off = LRH_BTH_MATCH_OFFSET;
14164         rrd.field2_off = LRH_SC_MATCH_OFFSET;
14165         rrd.index1_off = LRH_SC_SELECT_OFFSET;
14166         rrd.index1_width = n;
14167         rrd.index2_off = QPN_SELECT_OFFSET;
14168         rrd.index2_width = m + n;
14169         rrd.mask1 = LRH_BTH_MASK;
14170         rrd.value1 = LRH_BTH_VALUE;
14171         rrd.mask2 = LRH_SC_MASK;
14172         rrd.value2 = LRH_SC_VALUE;
14173
14174         /* add rule 0 */
14175         add_rsm_rule(dd, RSM_INS_VERBS, &rrd);
14176
14177         /* mark RSM map entries as used */
14178         rmt->used += rmt_entries;
14179         /* map everything else to the mcast/err/vl15 context */
14180         init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT);
14181         dd->qos_shift = n + 1;
14182         return;
14183 bail:
14184         dd->qos_shift = 1;
14185         init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1);
14186 }
14187
14188 static void init_user_fecn_handling(struct hfi1_devdata *dd,
14189                                     struct rsm_map_table *rmt)
14190 {
14191         struct rsm_rule_data rrd;
14192         u64 reg;
14193         int i, idx, regoff, regidx;
14194         u8 offset;
14195
14196         /* there needs to be enough room in the map table */
14197         if (rmt->used + dd->num_user_contexts >= NUM_MAP_ENTRIES) {
14198                 dd_dev_err(dd, "User FECN handling disabled - too many user contexts allocated\n");
14199                 return;
14200         }
14201
14202         /*
14203          * RSM will extract the destination context as an index into the
14204          * map table.  The destination contexts are a sequential block
14205          * in the range first_dyn_alloc_ctxt...num_rcv_contexts-1 (inclusive).
14206          * Map entries are accessed as offset + extracted value.  Adjust
14207          * the added offset so this sequence can be placed anywhere in
14208          * the table - as long as the entries themselves do not wrap.
14209          * There are only enough bits in offset for the table size, so
14210          * start with that to allow for a "negative" offset.
14211          */
14212         offset = (u8)(NUM_MAP_ENTRIES + (int)rmt->used -
14213                                                 (int)dd->first_dyn_alloc_ctxt);
14214
14215         for (i = dd->first_dyn_alloc_ctxt, idx = rmt->used;
14216                                 i < dd->num_rcv_contexts; i++, idx++) {
14217                 /* replace with identity mapping */
14218                 regoff = (idx % 8) * 8;
14219                 regidx = idx / 8;
14220                 reg = rmt->map[regidx];
14221                 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff);
14222                 reg |= (u64)i << regoff;
14223                 rmt->map[regidx] = reg;
14224         }
14225
14226         /*
14227          * For RSM intercept of Expected FECN packets:
14228          * o packet type 0 - expected
14229          * o match on F (bit 95), using select/match 1, and
14230          * o match on SH (bit 133), using select/match 2.
14231          *
14232          * Use index 1 to extract the 8-bit receive context from DestQP
14233          * (start at bit 64).  Use that as the RSM map table index.
14234          */
14235         rrd.offset = offset;
14236         rrd.pkt_type = 0;
14237         rrd.field1_off = 95;
14238         rrd.field2_off = 133;
14239         rrd.index1_off = 64;
14240         rrd.index1_width = 8;
14241         rrd.index2_off = 0;
14242         rrd.index2_width = 0;
14243         rrd.mask1 = 1;
14244         rrd.value1 = 1;
14245         rrd.mask2 = 1;
14246         rrd.value2 = 1;
14247
14248         /* add rule 1 */
14249         add_rsm_rule(dd, RSM_INS_FECN, &rrd);
14250
14251         rmt->used += dd->num_user_contexts;
14252 }
14253
14254 /* Initialize RSM for VNIC */
14255 void hfi1_init_vnic_rsm(struct hfi1_devdata *dd)
14256 {
14257         u8 i, j;
14258         u8 ctx_id = 0;
14259         u64 reg;
14260         u32 regoff;
14261         struct rsm_rule_data rrd;
14262
14263         if (hfi1_vnic_is_rsm_full(dd, NUM_VNIC_MAP_ENTRIES)) {
14264                 dd_dev_err(dd, "Vnic RSM disabled, rmt entries used = %d\n",
14265                            dd->vnic.rmt_start);
14266                 return;
14267         }
14268
14269         dev_dbg(&(dd)->pcidev->dev, "Vnic rsm start = %d, end %d\n",
14270                 dd->vnic.rmt_start,
14271                 dd->vnic.rmt_start + NUM_VNIC_MAP_ENTRIES);
14272
14273         /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */
14274         regoff = RCV_RSM_MAP_TABLE + (dd->vnic.rmt_start / 8) * 8;
14275         reg = read_csr(dd, regoff);
14276         for (i = 0; i < NUM_VNIC_MAP_ENTRIES; i++) {
14277                 /* Update map register with vnic context */
14278                 j = (dd->vnic.rmt_start + i) % 8;
14279                 reg &= ~(0xffllu << (j * 8));
14280                 reg |= (u64)dd->vnic.ctxt[ctx_id++]->ctxt << (j * 8);
14281                 /* Wrap up vnic ctx index */
14282                 ctx_id %= dd->vnic.num_ctxt;
14283                 /* Write back map register */
14284                 if (j == 7 || ((i + 1) == NUM_VNIC_MAP_ENTRIES)) {
14285                         dev_dbg(&(dd)->pcidev->dev,
14286                                 "Vnic rsm map reg[%d] =0x%llx\n",
14287                                 regoff - RCV_RSM_MAP_TABLE, reg);
14288
14289                         write_csr(dd, regoff, reg);
14290                         regoff += 8;
14291                         if (i < (NUM_VNIC_MAP_ENTRIES - 1))
14292                                 reg = read_csr(dd, regoff);
14293                 }
14294         }
14295
14296         /* Add rule for vnic */
14297         rrd.offset = dd->vnic.rmt_start;
14298         rrd.pkt_type = 4;
14299         /* Match 16B packets */
14300         rrd.field1_off = L2_TYPE_MATCH_OFFSET;
14301         rrd.mask1 = L2_TYPE_MASK;
14302         rrd.value1 = L2_16B_VALUE;
14303         /* Match ETH L4 packets */
14304         rrd.field2_off = L4_TYPE_MATCH_OFFSET;
14305         rrd.mask2 = L4_16B_TYPE_MASK;
14306         rrd.value2 = L4_16B_ETH_VALUE;
14307         /* Calc context from veswid and entropy */
14308         rrd.index1_off = L4_16B_HDR_VESWID_OFFSET;
14309         rrd.index1_width = ilog2(NUM_VNIC_MAP_ENTRIES);
14310         rrd.index2_off = L2_16B_ENTROPY_OFFSET;
14311         rrd.index2_width = ilog2(NUM_VNIC_MAP_ENTRIES);
14312         add_rsm_rule(dd, RSM_INS_VNIC, &rrd);
14313
14314         /* Enable RSM if not already enabled */
14315         add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
14316 }
14317
14318 void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd)
14319 {
14320         clear_rsm_rule(dd, RSM_INS_VNIC);
14321
14322         /* Disable RSM if used only by vnic */
14323         if (dd->vnic.rmt_start == 0)
14324                 clear_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
14325 }
14326
14327 static void init_rxe(struct hfi1_devdata *dd)
14328 {
14329         struct rsm_map_table *rmt;
14330
14331         /* enable all receive errors */
14332         write_csr(dd, RCV_ERR_MASK, ~0ull);
14333
14334         rmt = alloc_rsm_map_table(dd);
14335         /* set up QOS, including the QPN map table */
14336         init_qos(dd, rmt);
14337         init_user_fecn_handling(dd, rmt);
14338         complete_rsm_map_table(dd, rmt);
14339         /* record number of used rsm map entries for vnic */
14340         dd->vnic.rmt_start = rmt->used;
14341         kfree(rmt);
14342
14343         /*
14344          * make sure RcvCtrl.RcvWcb <= PCIe Device Control
14345          * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
14346          * space, PciCfgCap2.MaxPayloadSize in HFI).  There is only one
14347          * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
14348          * Max_PayLoad_Size set to its minimum of 128.
14349          *
14350          * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
14351          * (64 bytes).  Max_Payload_Size is possibly modified upward in
14352          * tune_pcie_caps() which is called after this routine.
14353          */
14354 }
14355
14356 static void init_other(struct hfi1_devdata *dd)
14357 {
14358         /* enable all CCE errors */
14359         write_csr(dd, CCE_ERR_MASK, ~0ull);
14360         /* enable *some* Misc errors */
14361         write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
14362         /* enable all DC errors, except LCB */
14363         write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
14364         write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
14365 }
14366
14367 /*
14368  * Fill out the given AU table using the given CU.  A CU is defined in terms
14369  * AUs.  The table is a an encoding: given the index, how many AUs does that
14370  * represent?
14371  *
14372  * NOTE: Assumes that the register layout is the same for the
14373  * local and remote tables.
14374  */
14375 static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu,
14376                                u32 csr0to3, u32 csr4to7)
14377 {
14378         write_csr(dd, csr0to3,
14379                   0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT |
14380                   1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT |
14381                   2ull * cu <<
14382                   SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
14383                   4ull * cu <<
14384                   SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
14385         write_csr(dd, csr4to7,
14386                   8ull * cu <<
14387                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
14388                   16ull * cu <<
14389                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
14390                   32ull * cu <<
14391                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
14392                   64ull * cu <<
14393                   SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
14394 }
14395
14396 static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14397 {
14398         assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3,
14399                            SEND_CM_LOCAL_AU_TABLE4_TO7);
14400 }
14401
14402 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14403 {
14404         assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3,
14405                            SEND_CM_REMOTE_AU_TABLE4_TO7);
14406 }
14407
14408 static void init_txe(struct hfi1_devdata *dd)
14409 {
14410         int i;
14411
14412         /* enable all PIO, SDMA, general, and Egress errors */
14413         write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
14414         write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
14415         write_csr(dd, SEND_ERR_MASK, ~0ull);
14416         write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
14417
14418         /* enable all per-context and per-SDMA engine errors */
14419         for (i = 0; i < dd->chip_send_contexts; i++)
14420                 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull);
14421         for (i = 0; i < dd->chip_sdma_engines; i++)
14422                 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull);
14423
14424         /* set the local CU to AU mapping */
14425         assign_local_cm_au_table(dd, dd->vcu);
14426
14427         /*
14428          * Set reasonable default for Credit Return Timer
14429          * Don't set on Simulator - causes it to choke.
14430          */
14431         if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
14432                 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
14433 }
14434
14435 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt, u16 jkey)
14436 {
14437         struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
14438         unsigned sctxt;
14439         int ret = 0;
14440         u64 reg;
14441
14442         if (!rcd || !rcd->sc) {
14443                 ret = -EINVAL;
14444                 goto done;
14445         }
14446         sctxt = rcd->sc->hw_context;
14447         reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */
14448                 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) <<
14449                  SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
14450         /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
14451         if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY))
14452                 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK;
14453         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, reg);
14454         /*
14455          * Enable send-side J_KEY integrity check, unless this is A0 h/w
14456          */
14457         if (!is_ax(dd)) {
14458                 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14459                 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14460                 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14461         }
14462
14463         /* Enable J_KEY check on receive context. */
14464         reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK |
14465                 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) <<
14466                  RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
14467         write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, reg);
14468 done:
14469         return ret;
14470 }
14471
14472 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt)
14473 {
14474         struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
14475         unsigned sctxt;
14476         int ret = 0;
14477         u64 reg;
14478
14479         if (!rcd || !rcd->sc) {
14480                 ret = -EINVAL;
14481                 goto done;
14482         }
14483         sctxt = rcd->sc->hw_context;
14484         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_JOB_KEY, 0);
14485         /*
14486          * Disable send-side J_KEY integrity check, unless this is A0 h/w.
14487          * This check would not have been enabled for A0 h/w, see
14488          * set_ctxt_jkey().
14489          */
14490         if (!is_ax(dd)) {
14491                 reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14492                 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14493                 write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14494         }
14495         /* Turn off the J_KEY on the receive side */
14496         write_kctxt_csr(dd, ctxt, RCV_KEY_CTRL, 0);
14497 done:
14498         return ret;
14499 }
14500
14501 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt, u16 pkey)
14502 {
14503         struct hfi1_ctxtdata *rcd;
14504         unsigned sctxt;
14505         int ret = 0;
14506         u64 reg;
14507
14508         if (ctxt < dd->num_rcv_contexts) {
14509                 rcd = dd->rcd[ctxt];
14510         } else {
14511                 ret = -EINVAL;
14512                 goto done;
14513         }
14514         if (!rcd || !rcd->sc) {
14515                 ret = -EINVAL;
14516                 goto done;
14517         }
14518         sctxt = rcd->sc->hw_context;
14519         reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) <<
14520                 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
14521         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg);
14522         reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
14523         reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
14524         reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK;
14525         write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
14526 done:
14527         return ret;
14528 }
14529
14530 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt)
14531 {
14532         u8 hw_ctxt;
14533         u64 reg;
14534
14535         if (!ctxt || !ctxt->sc)
14536                 return -EINVAL;
14537
14538         if (ctxt->ctxt >= dd->num_rcv_contexts)
14539                 return -EINVAL;
14540
14541         hw_ctxt = ctxt->sc->hw_context;
14542         reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE);
14543         reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
14544         write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg);
14545         write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0);
14546
14547         return 0;
14548 }
14549
14550 /*
14551  * Start doing the clean up the the chip. Our clean up happens in multiple
14552  * stages and this is just the first.
14553  */
14554 void hfi1_start_cleanup(struct hfi1_devdata *dd)
14555 {
14556         aspm_exit(dd);
14557         free_cntrs(dd);
14558         free_rcverr(dd);
14559         clean_up_interrupts(dd);
14560         finish_chip_resources(dd);
14561 }
14562
14563 #define HFI_BASE_GUID(dev) \
14564         ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
14565
14566 /*
14567  * Information can be shared between the two HFIs on the same ASIC
14568  * in the same OS.  This function finds the peer device and sets
14569  * up a shared structure.
14570  */
14571 static int init_asic_data(struct hfi1_devdata *dd)
14572 {
14573         unsigned long flags;
14574         struct hfi1_devdata *tmp, *peer = NULL;
14575         struct hfi1_asic_data *asic_data;
14576         int ret = 0;
14577
14578         /* pre-allocate the asic structure in case we are the first device */
14579         asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL);
14580         if (!asic_data)
14581                 return -ENOMEM;
14582
14583         spin_lock_irqsave(&hfi1_devs_lock, flags);
14584         /* Find our peer device */
14585         list_for_each_entry(tmp, &hfi1_dev_list, list) {
14586                 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(tmp)) &&
14587                     dd->unit != tmp->unit) {
14588                         peer = tmp;
14589                         break;
14590                 }
14591         }
14592
14593         if (peer) {
14594                 /* use already allocated structure */
14595                 dd->asic_data = peer->asic_data;
14596                 kfree(asic_data);
14597         } else {
14598                 dd->asic_data = asic_data;
14599                 mutex_init(&dd->asic_data->asic_resource_mutex);
14600         }
14601         dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */
14602         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
14603
14604         /* first one through - set up i2c devices */
14605         if (!peer)
14606                 ret = set_up_i2c(dd, dd->asic_data);
14607
14608         return ret;
14609 }
14610
14611 /*
14612  * Set dd->boardname.  Use a generic name if a name is not returned from
14613  * EFI variable space.
14614  *
14615  * Return 0 on success, -ENOMEM if space could not be allocated.
14616  */
14617 static int obtain_boardname(struct hfi1_devdata *dd)
14618 {
14619         /* generic board description */
14620         const char generic[] =
14621                 "Intel Omni-Path Host Fabric Interface Adapter 100 Series";
14622         unsigned long size;
14623         int ret;
14624
14625         ret = read_hfi1_efi_var(dd, "description", &size,
14626                                 (void **)&dd->boardname);
14627         if (ret) {
14628                 dd_dev_info(dd, "Board description not found\n");
14629                 /* use generic description */
14630                 dd->boardname = kstrdup(generic, GFP_KERNEL);
14631                 if (!dd->boardname)
14632                         return -ENOMEM;
14633         }
14634         return 0;
14635 }
14636
14637 /*
14638  * Check the interrupt registers to make sure that they are mapped correctly.
14639  * It is intended to help user identify any mismapping by VMM when the driver
14640  * is running in a VM. This function should only be called before interrupt
14641  * is set up properly.
14642  *
14643  * Return 0 on success, -EINVAL on failure.
14644  */
14645 static int check_int_registers(struct hfi1_devdata *dd)
14646 {
14647         u64 reg;
14648         u64 all_bits = ~(u64)0;
14649         u64 mask;
14650
14651         /* Clear CceIntMask[0] to avoid raising any interrupts */
14652         mask = read_csr(dd, CCE_INT_MASK);
14653         write_csr(dd, CCE_INT_MASK, 0ull);
14654         reg = read_csr(dd, CCE_INT_MASK);
14655         if (reg)
14656                 goto err_exit;
14657
14658         /* Clear all interrupt status bits */
14659         write_csr(dd, CCE_INT_CLEAR, all_bits);
14660         reg = read_csr(dd, CCE_INT_STATUS);
14661         if (reg)
14662                 goto err_exit;
14663
14664         /* Set all interrupt status bits */
14665         write_csr(dd, CCE_INT_FORCE, all_bits);
14666         reg = read_csr(dd, CCE_INT_STATUS);
14667         if (reg != all_bits)
14668                 goto err_exit;
14669
14670         /* Restore the interrupt mask */
14671         write_csr(dd, CCE_INT_CLEAR, all_bits);
14672         write_csr(dd, CCE_INT_MASK, mask);
14673
14674         return 0;
14675 err_exit:
14676         write_csr(dd, CCE_INT_MASK, mask);
14677         dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n");
14678         return -EINVAL;
14679 }
14680
14681 /**
14682  * Allocate and initialize the device structure for the hfi.
14683  * @dev: the pci_dev for hfi1_ib device
14684  * @ent: pci_device_id struct for this dev
14685  *
14686  * Also allocates, initializes, and returns the devdata struct for this
14687  * device instance
14688  *
14689  * This is global, and is called directly at init to set up the
14690  * chip-specific function pointers for later use.
14691  */
14692 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
14693                                   const struct pci_device_id *ent)
14694 {
14695         struct hfi1_devdata *dd;
14696         struct hfi1_pportdata *ppd;
14697         u64 reg;
14698         int i, ret;
14699         static const char * const inames[] = { /* implementation names */
14700                 "RTL silicon",
14701                 "RTL VCS simulation",
14702                 "RTL FPGA emulation",
14703                 "Functional simulator"
14704         };
14705         struct pci_dev *parent = pdev->bus->self;
14706
14707         dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS *
14708                                 sizeof(struct hfi1_pportdata));
14709         if (IS_ERR(dd))
14710                 goto bail;
14711         ppd = dd->pport;
14712         for (i = 0; i < dd->num_pports; i++, ppd++) {
14713                 int vl;
14714                 /* init common fields */
14715                 hfi1_init_pportdata(pdev, ppd, dd, 0, 1);
14716                 /* DC supports 4 link widths */
14717                 ppd->link_width_supported =
14718                         OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X |
14719                         OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X;
14720                 ppd->link_width_downgrade_supported =
14721                         ppd->link_width_supported;
14722                 /* start out enabling only 4X */
14723                 ppd->link_width_enabled = OPA_LINK_WIDTH_4X;
14724                 ppd->link_width_downgrade_enabled =
14725                                         ppd->link_width_downgrade_supported;
14726                 /* link width active is 0 when link is down */
14727                 /* link width downgrade active is 0 when link is down */
14728
14729                 if (num_vls < HFI1_MIN_VLS_SUPPORTED ||
14730                     num_vls > HFI1_MAX_VLS_SUPPORTED) {
14731                         hfi1_early_err(&pdev->dev,
14732                                        "Invalid num_vls %u, using %u VLs\n",
14733                                     num_vls, HFI1_MAX_VLS_SUPPORTED);
14734                         num_vls = HFI1_MAX_VLS_SUPPORTED;
14735                 }
14736                 ppd->vls_supported = num_vls;
14737                 ppd->vls_operational = ppd->vls_supported;
14738                 ppd->actual_vls_operational = ppd->vls_supported;
14739                 /* Set the default MTU. */
14740                 for (vl = 0; vl < num_vls; vl++)
14741                         dd->vld[vl].mtu = hfi1_max_mtu;
14742                 dd->vld[15].mtu = MAX_MAD_PACKET;
14743                 /*
14744                  * Set the initial values to reasonable default, will be set
14745                  * for real when link is up.
14746                  */
14747                 ppd->lstate = IB_PORT_DOWN;
14748                 ppd->overrun_threshold = 0x4;
14749                 ppd->phy_error_threshold = 0xf;
14750                 ppd->port_crc_mode_enabled = link_crc_mask;
14751                 /* initialize supported LTP CRC mode */
14752                 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
14753                 /* initialize enabled LTP CRC mode */
14754                 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4;
14755                 /* start in offline */
14756                 ppd->host_link_state = HLS_DN_OFFLINE;
14757                 init_vl_arb_caches(ppd);
14758                 ppd->last_pstate = 0xff; /* invalid value */
14759         }
14760
14761         dd->link_default = HLS_DN_POLL;
14762
14763         /*
14764          * Do remaining PCIe setup and save PCIe values in dd.
14765          * Any error printing is already done by the init code.
14766          * On return, we have the chip mapped.
14767          */
14768         ret = hfi1_pcie_ddinit(dd, pdev);
14769         if (ret < 0)
14770                 goto bail_free;
14771
14772         /* verify that reads actually work, save revision for reset check */
14773         dd->revision = read_csr(dd, CCE_REVISION);
14774         if (dd->revision == ~(u64)0) {
14775                 dd_dev_err(dd, "cannot read chip CSRs\n");
14776                 ret = -EINVAL;
14777                 goto bail_cleanup;
14778         }
14779         dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT)
14780                         & CCE_REVISION_CHIP_REV_MAJOR_MASK;
14781         dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT)
14782                         & CCE_REVISION_CHIP_REV_MINOR_MASK;
14783
14784         /*
14785          * Check interrupt registers mapping if the driver has no access to
14786          * the upstream component. In this case, it is likely that the driver
14787          * is running in a VM.
14788          */
14789         if (!parent) {
14790                 ret = check_int_registers(dd);
14791                 if (ret)
14792                         goto bail_cleanup;
14793         }
14794
14795         /*
14796          * obtain the hardware ID - NOT related to unit, which is a
14797          * software enumeration
14798          */
14799         reg = read_csr(dd, CCE_REVISION2);
14800         dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT)
14801                                         & CCE_REVISION2_HFI_ID_MASK;
14802         /* the variable size will remove unwanted bits */
14803         dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT;
14804         dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT;
14805         dd_dev_info(dd, "Implementation: %s, revision 0x%x\n",
14806                     dd->icode < ARRAY_SIZE(inames) ?
14807                     inames[dd->icode] : "unknown", (int)dd->irev);
14808
14809         /* speeds the hardware can support */
14810         dd->pport->link_speed_supported = OPA_LINK_SPEED_25G;
14811         /* speeds allowed to run at */
14812         dd->pport->link_speed_enabled = dd->pport->link_speed_supported;
14813         /* give a reasonable active value, will be set on link up */
14814         dd->pport->link_speed_active = OPA_LINK_SPEED_25G;
14815
14816         dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS);
14817         dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS);
14818         dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES);
14819         dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE);
14820         dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE);
14821         /* fix up link widths for emulation _p */
14822         ppd = dd->pport;
14823         if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) {
14824                 ppd->link_width_supported =
14825                         ppd->link_width_enabled =
14826                         ppd->link_width_downgrade_supported =
14827                         ppd->link_width_downgrade_enabled =
14828                                 OPA_LINK_WIDTH_1X;
14829         }
14830         /* insure num_vls isn't larger than number of sdma engines */
14831         if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) {
14832                 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n",
14833                            num_vls, dd->chip_sdma_engines);
14834                 num_vls = dd->chip_sdma_engines;
14835                 ppd->vls_supported = dd->chip_sdma_engines;
14836                 ppd->vls_operational = ppd->vls_supported;
14837         }
14838
14839         /*
14840          * Convert the ns parameter to the 64 * cclocks used in the CSR.
14841          * Limit the max if larger than the field holds.  If timeout is
14842          * non-zero, then the calculated field will be at least 1.
14843          *
14844          * Must be after icode is set up - the cclock rate depends
14845          * on knowing the hardware being used.
14846          */
14847         dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64;
14848         if (dd->rcv_intr_timeout_csr >
14849                         RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
14850                 dd->rcv_intr_timeout_csr =
14851                         RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
14852         else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout)
14853                 dd->rcv_intr_timeout_csr = 1;
14854
14855         /* needs to be done before we look for the peer device */
14856         read_guid(dd);
14857
14858         /* set up shared ASIC data with peer device */
14859         ret = init_asic_data(dd);
14860         if (ret)
14861                 goto bail_cleanup;
14862
14863         /* obtain chip sizes, reset chip CSRs */
14864         init_chip(dd);
14865
14866         /* read in the PCIe link speed information */
14867         ret = pcie_speeds(dd);
14868         if (ret)
14869                 goto bail_cleanup;
14870
14871         /* call before get_platform_config(), after init_chip_resources() */
14872         ret = eprom_init(dd);
14873         if (ret)
14874                 goto bail_free_rcverr;
14875
14876         /* Needs to be called before hfi1_firmware_init */
14877         get_platform_config(dd);
14878
14879         /* read in firmware */
14880         ret = hfi1_firmware_init(dd);
14881         if (ret)
14882                 goto bail_cleanup;
14883
14884         /*
14885          * In general, the PCIe Gen3 transition must occur after the
14886          * chip has been idled (so it won't initiate any PCIe transactions
14887          * e.g. an interrupt) and before the driver changes any registers
14888          * (the transition will reset the registers).
14889          *
14890          * In particular, place this call after:
14891          * - init_chip()     - the chip will not initiate any PCIe transactions
14892          * - pcie_speeds()   - reads the current link speed
14893          * - hfi1_firmware_init() - the needed firmware is ready to be
14894          *                          downloaded
14895          */
14896         ret = do_pcie_gen3_transition(dd);
14897         if (ret)
14898                 goto bail_cleanup;
14899
14900         /* start setting dd values and adjusting CSRs */
14901         init_early_variables(dd);
14902
14903         parse_platform_config(dd);
14904
14905         ret = obtain_boardname(dd);
14906         if (ret)
14907                 goto bail_cleanup;
14908
14909         snprintf(dd->boardversion, BOARD_VERS_MAX,
14910                  "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n",
14911                  HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN,
14912                  (u32)dd->majrev,
14913                  (u32)dd->minrev,
14914                  (dd->revision >> CCE_REVISION_SW_SHIFT)
14915                     & CCE_REVISION_SW_MASK);
14916
14917         ret = set_up_context_variables(dd);
14918         if (ret)
14919                 goto bail_cleanup;
14920
14921         /* set initial RXE CSRs */
14922         init_rxe(dd);
14923         /* set initial TXE CSRs */
14924         init_txe(dd);
14925         /* set initial non-RXE, non-TXE CSRs */
14926         init_other(dd);
14927         /* set up KDETH QP prefix in both RX and TX CSRs */
14928         init_kdeth_qp(dd);
14929
14930         ret = hfi1_dev_affinity_init(dd);
14931         if (ret)
14932                 goto bail_cleanup;
14933
14934         /* send contexts must be set up before receive contexts */
14935         ret = init_send_contexts(dd);
14936         if (ret)
14937                 goto bail_cleanup;
14938
14939         ret = hfi1_create_ctxts(dd);
14940         if (ret)
14941                 goto bail_cleanup;
14942
14943         dd->rcvhdrsize = DEFAULT_RCVHDRSIZE;
14944         /*
14945          * rcd[0] is guaranteed to be valid by this point. Also, all
14946          * context are using the same value, as per the module parameter.
14947          */
14948         dd->rhf_offset = dd->rcd[0]->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
14949
14950         ret = init_pervl_scs(dd);
14951         if (ret)
14952                 goto bail_cleanup;
14953
14954         /* sdma init */
14955         for (i = 0; i < dd->num_pports; ++i) {
14956                 ret = sdma_init(dd, i);
14957                 if (ret)
14958                         goto bail_cleanup;
14959         }
14960
14961         /* use contexts created by hfi1_create_ctxts */
14962         ret = set_up_interrupts(dd);
14963         if (ret)
14964                 goto bail_cleanup;
14965
14966         /* set up LCB access - must be after set_up_interrupts() */
14967         init_lcb_access(dd);
14968
14969         /*
14970          * Serial number is created from the base guid:
14971          * [27:24] = base guid [38:35]
14972          * [23: 0] = base guid [23: 0]
14973          */
14974         snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n",
14975                  (dd->base_guid & 0xFFFFFF) |
14976                      ((dd->base_guid >> 11) & 0xF000000));
14977
14978         dd->oui1 = dd->base_guid >> 56 & 0xFF;
14979         dd->oui2 = dd->base_guid >> 48 & 0xFF;
14980         dd->oui3 = dd->base_guid >> 40 & 0xFF;
14981
14982         ret = load_firmware(dd); /* asymmetric with dispose_firmware() */
14983         if (ret)
14984                 goto bail_clear_intr;
14985
14986         thermal_init(dd);
14987
14988         ret = init_cntrs(dd);
14989         if (ret)
14990                 goto bail_clear_intr;
14991
14992         ret = init_rcverr(dd);
14993         if (ret)
14994                 goto bail_free_cntrs;
14995
14996         init_completion(&dd->user_comp);
14997
14998         /* The user refcount starts with one to inidicate an active device */
14999         atomic_set(&dd->user_refcount, 1);
15000
15001         goto bail;
15002
15003 bail_free_rcverr:
15004         free_rcverr(dd);
15005 bail_free_cntrs:
15006         free_cntrs(dd);
15007 bail_clear_intr:
15008         clean_up_interrupts(dd);
15009 bail_cleanup:
15010         hfi1_pcie_ddcleanup(dd);
15011 bail_free:
15012         hfi1_free_devdata(dd);
15013         dd = ERR_PTR(ret);
15014 bail:
15015         return dd;
15016 }
15017
15018 static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate,
15019                         u32 dw_len)
15020 {
15021         u32 delta_cycles;
15022         u32 current_egress_rate = ppd->current_egress_rate;
15023         /* rates here are in units of 10^6 bits/sec */
15024
15025         if (desired_egress_rate == -1)
15026                 return 0; /* shouldn't happen */
15027
15028         if (desired_egress_rate >= current_egress_rate)
15029                 return 0; /* we can't help go faster, only slower */
15030
15031         delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) -
15032                         egress_cycles(dw_len * 4, current_egress_rate);
15033
15034         return (u16)delta_cycles;
15035 }
15036
15037 /**
15038  * create_pbc - build a pbc for transmission
15039  * @flags: special case flags or-ed in built pbc
15040  * @srate: static rate
15041  * @vl: vl
15042  * @dwlen: dword length (header words + data words + pbc words)
15043  *
15044  * Create a PBC with the given flags, rate, VL, and length.
15045  *
15046  * NOTE: The PBC created will not insert any HCRC - all callers but one are
15047  * for verbs, which does not use this PSM feature.  The lone other caller
15048  * is for the diagnostic interface which calls this if the user does not
15049  * supply their own PBC.
15050  */
15051 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
15052                u32 dw_len)
15053 {
15054         u64 pbc, delay = 0;
15055
15056         if (unlikely(srate_mbs))
15057                 delay = delay_cycles(ppd, srate_mbs, dw_len);
15058
15059         pbc = flags
15060                 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
15061                 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT)
15062                 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT
15063                 | (dw_len & PBC_LENGTH_DWS_MASK)
15064                         << PBC_LENGTH_DWS_SHIFT;
15065
15066         return pbc;
15067 }
15068
15069 #define SBUS_THERMAL    0x4f
15070 #define SBUS_THERM_MONITOR_MODE 0x1
15071
15072 #define THERM_FAILURE(dev, ret, reason) \
15073         dd_dev_err((dd),                                                \
15074                    "Thermal sensor initialization failed: %s (%d)\n",   \
15075                    (reason), (ret))
15076
15077 /*
15078  * Initialize the thermal sensor.
15079  *
15080  * After initialization, enable polling of thermal sensor through
15081  * SBus interface. In order for this to work, the SBus Master
15082  * firmware has to be loaded due to the fact that the HW polling
15083  * logic uses SBus interrupts, which are not supported with
15084  * default firmware. Otherwise, no data will be returned through
15085  * the ASIC_STS_THERM CSR.
15086  */
15087 static int thermal_init(struct hfi1_devdata *dd)
15088 {
15089         int ret = 0;
15090
15091         if (dd->icode != ICODE_RTL_SILICON ||
15092             check_chip_resource(dd, CR_THERM_INIT, NULL))
15093                 return ret;
15094
15095         ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
15096         if (ret) {
15097                 THERM_FAILURE(dd, ret, "Acquire SBus");
15098                 return ret;
15099         }
15100
15101         dd_dev_info(dd, "Initializing thermal sensor\n");
15102         /* Disable polling of thermal readings */
15103         write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
15104         msleep(100);
15105         /* Thermal Sensor Initialization */
15106         /*    Step 1: Reset the Thermal SBus Receiver */
15107         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
15108                                 RESET_SBUS_RECEIVER, 0);
15109         if (ret) {
15110                 THERM_FAILURE(dd, ret, "Bus Reset");
15111                 goto done;
15112         }
15113         /*    Step 2: Set Reset bit in Thermal block */
15114         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
15115                                 WRITE_SBUS_RECEIVER, 0x1);
15116         if (ret) {
15117                 THERM_FAILURE(dd, ret, "Therm Block Reset");
15118                 goto done;
15119         }
15120         /*    Step 3: Write clock divider value (100MHz -> 2MHz) */
15121         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1,
15122                                 WRITE_SBUS_RECEIVER, 0x32);
15123         if (ret) {
15124                 THERM_FAILURE(dd, ret, "Write Clock Div");
15125                 goto done;
15126         }
15127         /*    Step 4: Select temperature mode */
15128         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3,
15129                                 WRITE_SBUS_RECEIVER,
15130                                 SBUS_THERM_MONITOR_MODE);
15131         if (ret) {
15132                 THERM_FAILURE(dd, ret, "Write Mode Sel");
15133                 goto done;
15134         }
15135         /*    Step 5: De-assert block reset and start conversion */
15136         ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
15137                                 WRITE_SBUS_RECEIVER, 0x2);
15138         if (ret) {
15139                 THERM_FAILURE(dd, ret, "Write Reset Deassert");
15140                 goto done;
15141         }
15142         /*    Step 5.1: Wait for first conversion (21.5ms per spec) */
15143         msleep(22);
15144
15145         /* Enable polling of thermal readings */
15146         write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
15147
15148         /* Set initialized flag */
15149         ret = acquire_chip_resource(dd, CR_THERM_INIT, 0);
15150         if (ret)
15151                 THERM_FAILURE(dd, ret, "Unable to set thermal init flag");
15152
15153 done:
15154         release_chip_resource(dd, CR_SBUS);
15155         return ret;
15156 }
15157
15158 static void handle_temp_err(struct hfi1_devdata *dd)
15159 {
15160         struct hfi1_pportdata *ppd = &dd->pport[0];
15161         /*
15162          * Thermal Critical Interrupt
15163          * Put the device into forced freeze mode, take link down to
15164          * offline, and put DC into reset.
15165          */
15166         dd_dev_emerg(dd,
15167                      "Critical temperature reached! Forcing device into freeze mode!\n");
15168         dd->flags |= HFI1_FORCED_FREEZE;
15169         start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT);
15170         /*
15171          * Shut DC down as much and as quickly as possible.
15172          *
15173          * Step 1: Take the link down to OFFLINE. This will cause the
15174          *         8051 to put the Serdes in reset. However, we don't want to
15175          *         go through the entire link state machine since we want to
15176          *         shutdown ASAP. Furthermore, this is not a graceful shutdown
15177          *         but rather an attempt to save the chip.
15178          *         Code below is almost the same as quiet_serdes() but avoids
15179          *         all the extra work and the sleeps.
15180          */
15181         ppd->driver_link_ready = 0;
15182         ppd->link_enabled = 0;
15183         set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) |
15184                                 PLS_OFFLINE);
15185         /*
15186          * Step 2: Shutdown LCB and 8051
15187          *         After shutdown, do not restore DC_CFG_RESET value.
15188          */
15189         dc_shutdown(dd);
15190 }