drivers/mmc/host/sdhci-esdhc-imx.c

   1 /*
   2  * Freescale eSDHC i.MX controller driver for the platform bus.
   3  *
   4  * derived from the OF-version.
   5  *
   6  * Copyright (c) 2010 Pengutronix e.K.
   7  *   Author: Wolfram Sang <w.sang@pengutronix.de>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/gpio.h>
  19 #include <linux/slab.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/sdhci-pltfm.h>
  22 #include <linux/mmc/mmc.h>
  23 #include <linux/mmc/card.h>
  24 #include <linux/mmc/sdio.h>
  25 #include <linux/mmc/sd.h>
  26 #include <linux/scatterlist.h>
  27 #include <mach/hardware.h>
  28 #include <mach/esdhc.h>
  29 #include "sdhci.h"
  30 #include "sdhci-pltfm.h"
  31 #include "sdhci-esdhc.h"
  32
  33 /* VENDOR SPEC register */
  34 #define SDHCI_VENDOR_SPEC               0xC0
  35 #define  SDHCI_VENDOR_SPEC_SDIO_QUIRK   0x00000002
  36
  37 #define SDHCI_MIX_CTRL_AC23EN           (1 << 7)
  38 #define SDHCI_MIX_CTRL_EXE_TUNE         (1 << 22)
  39 #define SDHCI_MIX_CTRL_SMPCLK_SEL       (1 << 23)
  40 #define SDHCI_MIX_CTRL_AUTO_TUNE        (1 << 24)
  41 #define SDHCI_MIX_CTRL_FBCLK_SEL        (1 << 25)
  42
  43 #define SDHCI_SYS_CTRL                  0x2C
  44 #define SDHCI_SYS_CTRL_RSTA_LSH 24
  45
  46 #define SDHCI_DLL_CTRL                  0x60
  47 #define SDHCI_DLL_OVERRIDE_OFFSET       0x9
  48 #define SDHCI_DLL_OVERRIDE_EN_OFFSET    0x8
  49
  50 #define SDHCI_TUNE_CTRL_STATUS          0x68
  51 #define SDHCI_TUNE_CTRL_STEP            0x1
  52 #define SDHCI_TUNE_CTRL_MIN             0x0
  53 #define SDHCI_TUNE_CTRL_MAX             ((1 << 7) - 1)
  54
  55 #define  SDHCI_VENDOR_SPEC_VSELECT      (1 << 1)
  56 #define  SDHCI_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  57
  58 #define  SDHCI_PRESENT_STATE_CLSL       (1 << 23)
  59 #define  SDHCI_PRESENT_STATE_DLSL_L4    (0xF << 24)
  60 #define  SDHCI_PRESENT_STATE_DLSL_H4    (0xF << 28)
  61
  62 #define ESDHC_FLAG_GPIO_FOR_CD_WP       (1 << 0)
  63
  64 #define SDHCI_CTRL_D3CD                 0x08
  65
  66 #define SDHCI_PROT_CTRL_DMASEL_MASK             (3 << 8)
  67 #define SDHCI_PROT_CTRL_DTW             (3 << 1)
  68 #define SDHCI_PROT_CTRL_8BIT            (2 << 1)
  69 #define SDHCI_PROT_CTRL_4BIT            (1 << 1)
  70 #define SDHCI_PROT_CTRL_1BIT            (0 << 1)
  71 #define SDHCI_PROT_CTRL_LCTL            (1 << 0)
  72
  73 /* SDHCI_FSL_SVN_300 only for mx6q and mx6dl */
  74 #define SDHCI_FSL_SVN_300                       0x3
  75
  76 #define SDHCI_TUNE_CTRL         0xCC
  77 #define SDHCI_TUNE_CTRL_STD_TUNING_EN           (1 << 24)
  78
  79 #define SDHCI_HOST_CAP_UHS_MODE_MASK            0x7
  80
  81 #define SDHCI_TUNING_BLOCK_PATTERN_LEN          64
  82 /*
  83  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
  84  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
  85  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
  86  * Define this macro DMA error INT for fsl eSDHC
  87  */
  88 #define SDHCI_INT_VENDOR_SPEC_DMA_ERR   0x10000000
  89
  90 /*
  91  * The CMDTYPE of the CMD register (offset 0xE) should be set to
  92  * "11" when the STOP CMD12 is issued on imx53 to abort one
  93  * open ended multi-blk IO. Otherwise the TC INT wouldn't
  94  * be generated.
  95  * In exact block transfer, the controller doesn't complete the
  96  * operations automatically as required at the end of the
  97  * transfer and remains on hold if the abort command is not sent.
  98  * As a result, the TC flag is not asserted and SW  received timeout
  99  * exeception. Bit1 of Vendor Spec registor is used to fix it.
 100  */
 101 #define ESDHC_FLAG_MULTIBLK_NO_INT      (1 << 1)
 102
 103 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val);
 104 static void esdhc_post_tuning(struct sdhci_host *host);
 105
 106 struct pltfm_imx_data {
 107         int flags;
 108         u32 scratchpad;
 109         /* uhs mode for sdhc host control2 */
 110         unsigned char uhs_mode;
 111 };
 112
 113 static void request_done(struct mmc_request *mrq)
 114 {
 115         complete(&mrq->completion);
 116 }
 117
 118 static int esdhc_send_tuning_cmd(struct sdhci_host *host)
 119 {
 120         struct mmc_command cmd = {0};
 121         struct mmc_request mrq = {0};
 122         struct mmc_data data = {0};
 123         struct scatterlist sg;
 124         char tuning_pattern[SDHCI_TUNING_BLOCK_PATTERN_LEN];
 125
 126         cmd.opcode = MMC_SEND_TUNING_BLOCK;
 127         cmd.arg = 0;
 128         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
 129
 130         data.blksz = SDHCI_TUNING_BLOCK_PATTERN_LEN;
 131         data.blocks = 1;
 132         data.flags = MMC_DATA_READ;
 133         data.sg = &sg;
 134         data.sg_len = 1;
 135
 136         sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern));
 137
 138         mrq.cmd = &cmd;
 139         mrq.cmd->mrq = &mrq;
 140         mrq.data = &data;
 141         mrq.data->mrq = &mrq;
 142         mrq.cmd->data = mrq.data;
 143
 144         mrq.done = request_done;
 145
 146         init_completion(&(mrq.completion));
 147         sdhci_request(host->mmc, &mrq);
 148         wait_for_completion(&(mrq.completion));
 149
 150         if (cmd.error)
 151                 return cmd.error;
 152         if (data.error)
 153                 return data.error;
 154
 155         return 0;
 156 }
 157
 158 static int esdhc_execute_tuning(struct sdhci_host *host)
 159 {
 160         int min, max, avg;
 161
 162         min = host->tuning_min;
 163         while (min < host->tuning_max) {
 164                 esdhc_prepare_tuning(host, min);
 165                 if (!esdhc_send_tuning_cmd(host))
 166                         break;
 167                 min += host->tuning_step;
 168         }
 169
 170         max = min + host->tuning_step;
 171         while (max < host->tuning_max) {
 172                 esdhc_prepare_tuning(host, max);
 173                 if (esdhc_send_tuning_cmd(host)) {
 174                         max -= host->tuning_step;
 175                         break;
 176                 }
 177                 max += host->tuning_step;
 178         }
 179
 180         avg = (min + max) / 2;
 181         esdhc_prepare_tuning(host, avg);
 182         esdhc_send_tuning_cmd(host);
 183         esdhc_post_tuning(host);
 184         return 0;
 185 }
 186
 187 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 188 {
 189         void __iomem *base = host->ioaddr + (reg & ~0x3);
 190         u32 shift = (reg & 0x3) * 8;
 191
 192         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 193 }
 194
 195 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 196 {
 197         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 198         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 199         struct esdhc_platform_data *boarddata
 200                                 = host->mmc->parent->platform_data;
 201
 202         /* fake CARD_PRESENT flag on mx25/35 */
 203         u32 val = readl(host->ioaddr + reg);
 204
 205         /*
 206          * mx6q: SDHCI_PRESENT_STATE bit 16, CINST is not functional on SD3.
 207          * So move the section up, and check GPIO for card presence again in
 208          * the following block.
 209          */
 210         if (reg == SDHCI_PRESENT_STATE && cpu_is_mx6()) {
 211                 u32 fsl_prss = readl(host->ioaddr + SDHCI_PRESENT_STATE);
 212                 /* save the least 20 bits */
 213                 val |= fsl_prss & 0x000FFFFF;
 214                 /* move dat[0-3] line signal bits */
 215                 val |= (fsl_prss & 0x0F000000) >> 4;
 216                 /* move cmd line signal bits */
 217                 val |= (fsl_prss & 0x00800000) << 1;
 218         }
 219
 220         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 221                 if (boarddata && boarddata->always_present)
 222                         val |= SDHCI_CARD_PRESENT;
 223                 else if (imx_data->flags & ESDHC_FLAG_GPIO_FOR_CD_WP) {
 224                         if (boarddata && gpio_is_valid(boarddata->cd_gpio)
 225                                         && gpio_get_value(boarddata->cd_gpio))
 226                                 /* no card, if a valid gpio says so */
 227                                 val &= ~SDHCI_CARD_PRESENT;
 228                         else
 229                                 /* in all other cases assume card is present */
 230                                 val |= SDHCI_CARD_PRESENT;
 231                 }
 232         }
 233
 234         if (reg == SDHCI_INT_STATUS && cpu_is_mx6()
 235                 && mx6q_revision() == IMX_CHIP_REVISION_1_0) {
 236                 /*
 237                  * on mx6q TO1.0, there is low possibility that
 238                  * DATA END interrupt comes ealier than DMA
 239                  * END interrupt which is conflict with standard
 240                  * host controller spec. In this case, read the
 241                  * status register again will workaround this issue.
 242                  */
 243                 if ((val & SDHCI_INT_DATA_END) && \
 244                         !(val & SDHCI_INT_DMA_END))
 245                         val = readl(host->ioaddr + reg);
 246         } else if (reg == SDHCI_CAPABILITIES_1
 247                         && (cpu_is_mx6q() || cpu_is_mx6dl())) {
 248                 /*
 249                  * on mx6q, no cap_1 available, fake one.
 250                  */
 251                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 | \
 252                           SDHCI_SUPPORT_SDR50;
 253         } else if (reg == SDHCI_CAPABILITIES_1 && cpu_is_mx6sl()) {
 254                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 255         } else if (reg == SDHCI_MAX_CURRENT && cpu_is_mx6()) {
 256                 /*
 257                  * on mx6q, no max current available, fake one.
 258                  */
 259                 val = 0;
 260                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
 261                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
 262                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
 263         }
 264
 265         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 266                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 267                  * ADMA2 capability of esdhc, but this bit is messed up on
 268                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 269                  * don't actually support ADMA2). So set the BROKEN_ADMA
 270                  * uirk on MX25/35 platforms.
 271                  */
 272
 273                 if (val & SDHCI_CAN_DO_ADMA1) {
 274                         val &= ~SDHCI_CAN_DO_ADMA1;
 275                         val |= SDHCI_CAN_DO_ADMA2;
 276                 }
 277         }
 278
 279         if (unlikely(reg == SDHCI_INT_STATUS)) {
 280                 if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) {
 281                         val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR;
 282                         val |= SDHCI_INT_ADMA_ERROR;
 283                 }
 284         }
 285
 286         return val;
 287 }
 288
 289 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 290 {
 291         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 292         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 293         u32 data;
 294
 295         if (unlikely((reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE))) {
 296                 if (imx_data->flags & ESDHC_FLAG_GPIO_FOR_CD_WP)
 297                         /*
 298                          * these interrupts won't work with a custom
 299                          * card_detect gpio (only applied to mx25/35)
 300                          */
 301                         val &= ~(SDHCI_INT_CARD_REMOVE | \
 302                                 SDHCI_INT_CARD_INSERT);
 303
 304                 if (!(val & SDHCI_INT_CARD_INT) && cpu_is_mx6()
 305                         && mx6q_revision() == IMX_CHIP_REVISION_1_0)
 306                         /*
 307                          * write 1 to clear card interrupt status bit
 308                          * (only applied to mx6q TO1.0)
 309                          * uSDHC used for mx6q has such problem which is
 310                          * not consistant with standard host controller
 311                          * definition.
 312                          * eSDHC used for mx25/35/50/51/53 does not have
 313                          * such problem.
 314                          */
 315                         writel(SDHCI_INT_CARD_INT, \
 316                                 host->ioaddr + SDHCI_INT_STATUS);
 317
 318                 if (val & SDHCI_INT_CARD_INT && !cpu_is_mx6()) {
 319                         /*
 320                          * clear D3CD bit and set D3CD bit to avoid
 321                          * losing card interrupt
 322                          * (applied to all processors except mx6q)
 323                          * eSDHC controller used for mx25/35/50/51/53
 324                          * has such issue, so that we need to do following
 325                          * operation to avoid losing card interrupt.
 326                          * uSDCH controller used for mx6q and after won't
 327                          * have such problem.
 328                          */
 329                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 330                         data &= ~SDHCI_CTRL_D3CD;
 331                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 332                         data |= SDHCI_CTRL_D3CD;
 333                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 334                 }
 335         }
 336
 337         if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 338                                 && (reg == SDHCI_INT_STATUS)
 339                                 && (val & SDHCI_INT_DATA_END))) {
 340                         u32 v;
 341                         v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
 342                         v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK;
 343                         writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
 344         }
 345
 346         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
 347                 if (val & SDHCI_INT_ADMA_ERROR) {
 348                         val &= ~SDHCI_INT_ADMA_ERROR;
 349                         val |= SDHCI_INT_VENDOR_SPEC_DMA_ERR;
 350                 }
 351         }
 352
 353         writel(val, host->ioaddr + reg);
 354 }
 355
 356 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 357 {
 358         u16 ret;
 359         u32 val;
 360         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 361         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 362
 363         switch (reg) {
 364         case SDHCI_HOST_VERSION:
 365                 reg ^= 2;
 366                 val = readl(host->ioaddr + reg);
 367                 if ((cpu_is_mx6q() || cpu_is_mx6dl()) &&
 368                         ((val & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT)
 369                         == SDHCI_FSL_SVN_300) {
 370                         val &= ~SDHCI_SPEC_VER_MASK;
 371                         val |= SDHCI_SPEC_300;
 372                 }
 373                 ret = 0xFFFF & val;
 374                 return ret;
 375         case SDHCI_HOST_CONTROL2:
 376                 ret = 0;
 377                 /* collect bit info from several regs */
 378                 val = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
 379                 ret |= (val & SDHCI_VENDOR_SPEC_VSELECT)
 380                         ? SDHCI_CTRL_VDD_180 : 0;
 381
 382                 if (cpu_is_mx6sl()) {
 383                         val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 384                         ret |= (val & SDHCI_MIX_CTRL_EXE_TUNE)
 385                                 ? SDHCI_CTRL_EXEC_TUNING : 0;
 386                         ret |= (val & SDHCI_MIX_CTRL_SMPCLK_SEL)
 387                                 ? SDHCI_CTRL_TUNED_CLK : 0;
 388                 } else {
 389                         val = readl(host->ioaddr + SDHCI_MIX_CTRL);
 390                         ret |= (val & SDHCI_MIX_CTRL_EXE_TUNE)
 391                                 ? SDHCI_CTRL_EXEC_TUNING : 0;
 392                         ret |= (val & SDHCI_MIX_CTRL_SMPCLK_SEL)
 393                                 ? SDHCI_CTRL_TUNED_CLK : 0;
 394                 }
 395                 ret |= SDHCI_CTRL_UHS_MASK & imx_data->uhs_mode;
 396                 /* no preset enable available  */
 397                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 398
 399                 return ret;
 400         }
 401
 402         return readw(host->ioaddr + reg);
 403 }
 404
 405 static void esdhc_post_tuning(struct sdhci_host *host)
 406 {
 407         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 408         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 409         u32 reg;
 410
 411         imx_data->scratchpad &= ~SDHCI_MIX_CTRL_EXE_TUNE;
 412         reg = readl(host->ioaddr + SDHCI_MIX_CTRL);
 413         reg &= ~SDHCI_MIX_CTRL_EXE_TUNE;
 414         writel(reg, host->ioaddr + SDHCI_MIX_CTRL);
 415 }
 416
 417 static void esdhc_reset(struct sdhci_host *host)
 418 {
 419         unsigned long timeout;
 420         u32 reg;
 421
 422         reg = readl(host->ioaddr + SDHCI_SYS_CTRL);
 423         reg |= 1 << SDHCI_SYS_CTRL_RSTA_LSH;
 424         writel(reg, host->ioaddr + SDHCI_SYS_CTRL);
 425
 426         /* Wait max 100ms */
 427         timeout = 100;
 428
 429         /* hw clears the bit when it's done */
 430         while (readl(host->ioaddr + SDHCI_SYS_CTRL)
 431                         & (1 << SDHCI_SYS_CTRL_RSTA_LSH)) {
 432                 if (timeout == 0) {
 433                         printk(KERN_ERR "%s: Reset never completed.\n",
 434                                         mmc_hostname(host->mmc));
 435                         return;
 436                 }
 437                 timeout--;
 438                 mdelay(1);
 439         }
 440 }
 441
 442 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 443 {
 444         u32 reg;
 445
 446         esdhc_reset(host);
 447         mdelay(1);
 448
 449         reg = readl(host->ioaddr + SDHCI_MIX_CTRL);
 450         reg |= SDHCI_MIX_CTRL_EXE_TUNE | \
 451                 SDHCI_MIX_CTRL_SMPCLK_SEL | \
 452                 SDHCI_MIX_CTRL_FBCLK_SEL;
 453         writel(reg, host->ioaddr + SDHCI_MIX_CTRL);
 454         writel((val << 8), host->ioaddr + SDHCI_TUNE_CTRL_STATUS);
 455 }
 456
 457
 458 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 459 {
 460         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 461         struct esdhc_platform_data *boarddata =
 462                                 host->mmc->parent->platform_data;
 463         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 464         u32 orig_reg;
 465
 466         switch (reg) {
 467         case SDHCI_CLOCK_CONTROL:
 468                 orig_reg = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
 469                 if (val & SDHCI_CLOCK_CARD_EN) {
 470                         writel(orig_reg | SDHCI_VENDOR_SPEC_FRC_SDCLK_ON, \
 471                                 host->ioaddr + SDHCI_VENDOR_SPEC);
 472                 } else {
 473                         writel(orig_reg & ~SDHCI_VENDOR_SPEC_FRC_SDCLK_ON, \
 474                                 host->ioaddr + SDHCI_VENDOR_SPEC);
 475                 }
 476
 477                 return;
 478         case SDHCI_HOST_CONTROL2:
 479                 orig_reg = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
 480                 if (val & SDHCI_CTRL_VDD_180) {
 481                         orig_reg |= SDHCI_VENDOR_SPEC_VSELECT;
 482                         writel(orig_reg, host->ioaddr + SDHCI_VENDOR_SPEC);
 483                 } else {
 484                         orig_reg &= ~SDHCI_VENDOR_SPEC_VSELECT;
 485                         writel(orig_reg, host->ioaddr + SDHCI_VENDOR_SPEC);
 486                 }
 487
 488                 /*
 489                  * FSL sdhc controls bus and signal voltage via one bit
 490                  * VSELECT in VENDOR_SPEC, which has been set in
 491                  * SDHCI_POWER_CONTROL. So we skip the SDHCI_CTRL_VDD_180
 492                  * here.
 493                  *
 494                  * ignore exec_tuning flag written to SDHCI_HOST_CONTROL2,
 495                  * tuning will be handled differently for FSL SDHC ip.
 496                  */
 497                 if (cpu_is_mx6sl()) {
 498                         orig_reg = readl(host->ioaddr + SDHCI_TUNE_CTRL);
 499                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 500                                 orig_reg |= SDHCI_TUNE_CTRL_STD_TUNING_EN;
 501                                 writel(orig_reg,
 502                                         host->ioaddr + SDHCI_TUNE_CTRL);
 503
 504                                 orig_reg =
 505                                         readl(host->ioaddr + SDHCI_ACMD12_ERR);
 506                                 orig_reg |= SDHCI_MIX_CTRL_EXE_TUNE;
 507                                 writel(orig_reg,
 508                                         host->ioaddr + SDHCI_ACMD12_ERR);
 509                         }
 510                 } else {
 511                         orig_reg = readl(host->ioaddr + SDHCI_MIX_CTRL);
 512                         orig_reg &= ~SDHCI_MIX_CTRL_SMPCLK_SEL;
 513                         orig_reg |= (val & SDHCI_CTRL_TUNED_CLK)
 514                                 ? SDHCI_MIX_CTRL_SMPCLK_SEL : 0;
 515                 }
 516
 517                 if (val & SDHCI_CTRL_UHS_DDR50) {
 518                         orig_reg |= SDHCI_MIX_CTRL_DDREN;
 519                         imx_data->scratchpad |= SDHCI_MIX_CTRL_DDREN;
 520                 } else {
 521                         orig_reg &= ~SDHCI_MIX_CTRL_DDREN;
 522                         imx_data->scratchpad &= ~SDHCI_MIX_CTRL_DDREN;
 523                 }
 524                 writel(orig_reg, host->ioaddr + SDHCI_MIX_CTRL);
 525
 526                 /* set clock frequency again */
 527                 esdhc_set_clock(host, host->clock);
 528                 imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK;
 529
 530                 /* delay line setting */
 531                 if (!boarddata->delay_line)
 532                         return;
 533
 534                 if (val & SDHCI_CTRL_UHS_DDR50)
 535                         writel((boarddata->delay_line \
 536                                         << SDHCI_DLL_OVERRIDE_OFFSET) \
 537                                         | (1 << SDHCI_DLL_OVERRIDE_EN_OFFSET),
 538                                         host->ioaddr + SDHCI_DLL_CTRL);
 539                 else
 540                         writel(0, host->ioaddr + SDHCI_DLL_CTRL);
 541
 542                 return;
 543         case SDHCI_TRANSFER_MODE:
 544                 /*
 545                  * Postpone this write, we must do it together with a
 546                  * command write that is down below.
 547                  */
 548                 if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 549                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 550                                 && (host->cmd->data->blocks > 1)
 551                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 552                         u32 v;
 553                         v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
 554                         v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK;
 555                         writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
 556                 }
 557                 imx_data->scratchpad = val;
 558
 559                 if (val & SDHCI_TRNS_AUTO_CMD23)
 560                         imx_data->scratchpad |= SDHCI_MIX_CTRL_AC23EN;
 561
 562                 return;
 563         case SDHCI_COMMAND:
 564                 if ((host->cmd->opcode == MMC_STOP_TRANSMISSION ||
 565                      host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 566                     (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 567                         val |= SDHCI_CMD_ABORTCMD;
 568
 569                 writel(0x08800880, host->ioaddr + SDHCI_CAPABILITIES_1);
 570                 if (cpu_is_mx6()) {
 571                         imx_data->scratchpad |= \
 572                         (readl(host->ioaddr + SDHCI_MIX_CTRL) & \
 573                                 (SDHCI_MIX_CTRL_EXE_TUNE | \
 574                                 SDHCI_MIX_CTRL_SMPCLK_SEL | \
 575                                 SDHCI_MIX_CTRL_AUTO_TUNE | \
 576                                 SDHCI_MIX_CTRL_FBCLK_SEL | \
 577                                 SDHCI_MIX_CTRL_DDREN));
 578
 579                         writel(imx_data->scratchpad,
 580                                 host->ioaddr + SDHCI_MIX_CTRL);
 581
 582                         writel(val << 16,
 583                                 host->ioaddr + SDHCI_TRANSFER_MODE);
 584                 } else {
 585                         writel(val << 16 | imx_data->scratchpad,
 586                                 host->ioaddr + SDHCI_TRANSFER_MODE);
 587                 }
 588                 return;
 589         case SDHCI_BLOCK_SIZE:
 590                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 591                 break;
 592         }
 593         esdhc_clrset_le(host, 0xffff, val, reg);
 594 }
 595
 596 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
 597 {
 598         u8 ret;
 599         u32 reg_val;
 600
 601         ret = 0;
 602         switch (reg) {
 603         case SDHCI_POWER_CONTROL:
 604                 reg_val = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
 605                 ret |= reg_val & SDHCI_VENDOR_SPEC_VSELECT
 606                                 ? SDHCI_POWER_180 : SDHCI_POWER_300;
 607                 /* could not power off */
 608                 ret |= SDHCI_POWER_ON;
 609                 return ret;
 610         case SDHCI_HOST_CONTROL:
 611                 reg_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 612                 if (reg_val & SDHCI_PROT_CTRL_LCTL)
 613                         ret |= SDHCI_CTRL_LED;
 614                 else
 615                         ret &= ~SDHCI_CTRL_LED;
 616
 617                 ret |= (reg_val & SDHCI_PROT_CTRL_DMASEL_MASK) >> 5;
 618                 if (SDHCI_PROT_CTRL_8BIT == (reg_val & SDHCI_PROT_CTRL_DTW)) {
 619                         ret &= ~SDHCI_CTRL_4BITBUS;
 620                         ret |= SDHCI_CTRL_8BITBUS;
 621                 } else if (SDHCI_PROT_CTRL_4BIT
 622                                 == (reg_val & SDHCI_PROT_CTRL_DTW)) {
 623                         ret &= ~SDHCI_CTRL_8BITBUS;
 624                         ret |= SDHCI_CTRL_4BITBUS;
 625                 } else if (SDHCI_PROT_CTRL_1BIT
 626                                 == (reg_val & SDHCI_PROT_CTRL_DTW))
 627                         ret &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
 628                 return ret;
 629         case SDHCI_SOFTWARE_RESET:
 630                 reg_val = readl(host->ioaddr + SDHCI_CLOCK_CONTROL);
 631                 ret = reg_val >> 24;
 632                 return ret;
 633         case SDHCI_RESPONSE + 3:
 634                 reg_val = readl(host->ioaddr + SDHCI_RESPONSE);
 635                 ret = reg_val >> 24;
 636                 return ret;
 637         case SDHCI_RESPONSE + 7:
 638                 reg_val = readl(host->ioaddr + SDHCI_RESPONSE + 4);
 639                 ret = reg_val >> 24;
 640                 return ret;
 641         case SDHCI_RESPONSE + 11:
 642                 reg_val = readl(host->ioaddr + SDHCI_RESPONSE + 8);
 643                 ret = reg_val >> 24;
 644                 return ret;
 645         default:
 646                 ret = 0;
 647                 break;
 648         }
 649         return ret;
 650 }
 651
 652 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 653 {
 654         u32 new_val;
 655
 656         switch (reg) {
 657         case SDHCI_POWER_CONTROL:
 658                 /*
 659                  * FSL put some DMA bits here
 660                  * If your board has a regulator, code should be here
 661                  */
 662                 if (val == (SDHCI_POWER_ON | SDHCI_POWER_180)) {
 663                         u32 reg;
 664
 665                         /* stop sd clock */
 666                         reg = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
 667                         writel(reg & ~SDHCI_VENDOR_SPEC_FRC_SDCLK_ON, \
 668                                 host->ioaddr + SDHCI_VENDOR_SPEC);
 669
 670                         /* switch to 1.8V */
 671                         reg = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
 672                         reg |= SDHCI_VENDOR_SPEC_VSELECT;
 673                         writel(reg, host->ioaddr + SDHCI_VENDOR_SPEC);
 674
 675                 } else {
 676                         u32 reg;
 677
 678                         reg = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
 679                         reg &= ~SDHCI_VENDOR_SPEC_VSELECT;
 680                         writel(reg, host->ioaddr + SDHCI_VENDOR_SPEC);
 681                 }
 682                 return;
 683         case SDHCI_HOST_CONTROL:
 684                 /* FSL messed up here, so we can just keep those three */
 685                 new_val = val & (SDHCI_CTRL_LED);
 686                 if (val & SDHCI_CTRL_8BITBUS) {
 687                         new_val |= SDHCI_PROT_CTRL_8BIT;
 688                         new_val &= ~SDHCI_PROT_CTRL_4BIT;
 689                 } else if (val & SDHCI_CTRL_4BITBUS) {
 690                         new_val &= ~SDHCI_PROT_CTRL_8BIT;
 691                         new_val |= SDHCI_PROT_CTRL_4BIT;
 692                 }
 693                 /* ensure the endianess */
 694                 new_val |= ESDHC_HOST_CONTROL_LE;
 695                 /* DMA mode bits are shifted */
 696                 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 697
 698                 esdhc_clrset_le(host, 0xffff, new_val, reg);
 699                 return;
 700         }
 701         esdhc_clrset_le(host, 0xff, val, reg);
 702 }
 703
 704 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 705 {
 706         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 707
 708         return clk_get_rate(pltfm_host->clk);
 709 }
 710
 711 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 712 {
 713         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 714
 715         return clk_get_rate(pltfm_host->clk) / 256 / 16;
 716 }
 717
 718 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 719 {
 720         struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data;
 721
 722         if (boarddata && gpio_is_valid(boarddata->wp_gpio))
 723                 return gpio_get_value(boarddata->wp_gpio);
 724         else
 725                 return -ENOSYS;
 726 }
 727
 728 static int plt_8bit_width(struct sdhci_host *host, int width)
 729 {
 730         u32 reg = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 731
 732         reg &= ~SDHCI_PROT_CTRL_DTW;
 733
 734         if (width == MMC_BUS_WIDTH_8)
 735                 reg |= SDHCI_PROT_CTRL_8BIT;
 736         else if (width == MMC_BUS_WIDTH_4)
 737                 reg |= SDHCI_PROT_CTRL_4BIT;
 738
 739         writel(reg, host->ioaddr + SDHCI_HOST_CONTROL);
 740         return 0;
 741 }
 742
 743 static void plt_clk_ctrl(struct sdhci_host *host, bool enable)
 744 {
 745         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 746
 747         if (enable) {
 748                 clk_enable(pltfm_host->clk);
 749                 host->clk_status = true;
 750         } else {
 751                 clk_disable(pltfm_host->clk);
 752                 host->clk_status = false;
 753         }
 754 }
 755
 756 static struct sdhci_ops sdhci_esdhc_ops = {
 757         .read_l = esdhc_readl_le,
 758         .read_w = esdhc_readw_le,
 759         .read_b = esdhc_readb_le,
 760         .write_l = esdhc_writel_le,
 761         .write_w = esdhc_writew_le,
 762         .write_b = esdhc_writeb_le,
 763         .set_clock = esdhc_set_clock,
 764         .get_max_clock = esdhc_pltfm_get_max_clock,
 765         .get_min_clock = esdhc_pltfm_get_min_clock,
 766         .platform_8bit_width = plt_8bit_width,
 767         .platform_clk_ctrl = plt_clk_ctrl,
 768 };
 769
 770 static irqreturn_t cd_irq(int irq, void *data)
 771 {
 772         struct sdhci_host *sdhost = (struct sdhci_host *)data;
 773         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhost);
 774         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 775
 776         writel(0, sdhost->ioaddr + SDHCI_MIX_CTRL);
 777         writel(0, sdhost->ioaddr + SDHCI_TUNE_CTRL_STATUS);
 778
 779         if (cpu_is_mx6()) {
 780                 imx_data->scratchpad &= ~SDHCI_MIX_CTRL_DDREN;
 781                 imx_data->scratchpad &= ~SDHCI_MIX_CTRL_FBCLK_SEL;
 782                 imx_data->scratchpad &= ~SDHCI_MIX_CTRL_SMPCLK_SEL;
 783         }
 784
 785         esdhc_reset(sdhost);
 786         mdelay(1);
 787
 788         tasklet_schedule(&sdhost->card_tasklet);
 789         return IRQ_HANDLED;
 790 };
 791
 792 static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pdata)
 793 {
 794         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 795         struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data;
 796         struct clk *clk;
 797         int err;
 798         struct pltfm_imx_data *imx_data;
 799         u32 reg;
 800
 801         clk = clk_get(mmc_dev(host->mmc), NULL);
 802         if (IS_ERR(clk)) {
 803                 dev_err(mmc_dev(host->mmc), "clk err\n");
 804                 return PTR_ERR(clk);
 805         }
 806         clk_enable(clk);
 807         pltfm_host->clk = clk;
 808
 809         imx_data = kzalloc(sizeof(struct pltfm_imx_data), GFP_KERNEL);
 810         if (!imx_data) {
 811                 clk_disable(pltfm_host->clk);
 812                 clk_put(pltfm_host->clk);
 813                 return -ENOMEM;
 814         }
 815         pltfm_host->priv = imx_data;
 816
 817         host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 818
 819         if (cpu_is_mx25() || cpu_is_mx35())
 820                 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
 821                 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
 822                         | SDHCI_QUIRK_BROKEN_ADMA;
 823
 824         /*
 825          * on mx6dl TO 1.1, ADMA can work when ahb bus frequency is low,
 826          * like 24Mhz.
 827          */
 828         if (mx6dl_revision() >= IMX_CHIP_REVISION_1_1)
 829                 host->quirks &= ~SDHCI_QUIRK_BROKEN_ADMA;
 830
 831         if (cpu_is_mx6())
 832                 host->quirks2 |= SDHCI_QUIRK_BROKEN_AUTO_CMD23,
 833
 834         /* write_protect can't be routed to controller, use gpio */
 835         sdhci_esdhc_ops.get_ro = esdhc_pltfm_get_ro;
 836
 837         if (!(cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51() || cpu_is_mx6()))
 838                 imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
 839
 840         host->ocr_avail_sd = MMC_VDD_29_30 | MMC_VDD_30_31 | \
 841                         MMC_VDD_32_33 | MMC_VDD_33_34;
 842         host->ocr_avail_mmc = MMC_VDD_29_30 | MMC_VDD_30_31 | \
 843                         MMC_VDD_32_33 | MMC_VDD_33_34;
 844         host->ocr_avail_sdio = MMC_VDD_29_30 | MMC_VDD_30_31 | \
 845                         MMC_VDD_32_33 | MMC_VDD_33_34;
 846
 847         if (cpu_is_mx6q() || cpu_is_mx6dl())
 848                 sdhci_esdhc_ops.platform_execute_tuning = esdhc_execute_tuning;
 849
 850         if (boarddata->support_18v) {
 851                 host->ocr_avail_sd |= MMC_VDD_165_195;
 852                 host->ocr_avail_mmc |= MMC_VDD_165_195;
 853                 host->ocr_avail_sdio |= MMC_VDD_165_195;
 854         }
 855
 856         if (boarddata->support_8bit)
 857                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 858         if (boarddata->keep_power_at_suspend)
 859                 host->mmc->pm_caps |= (MMC_PM_KEEP_POWER | \
 860                                         MMC_PM_WAKE_SDIO_IRQ);
 861         if (boarddata->cd_type == ESDHC_CD_PERMANENT)
 862                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
 863         else if (boarddata->cd_type == ESDHC_CD_CONTROLLER
 864                 || boarddata->cd_type == ESDHC_CD_NONE
 865                 || boarddata->cd_type == ESDHC_CD_GPIO)
 866                 host->mmc->caps &= ~MMC_CAP_NONREMOVABLE;
 867         if (cpu_is_mx6()) {
 868                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
 869                 host->tuning_min = SDHCI_TUNE_CTRL_MIN;
 870                 host->tuning_max = SDHCI_TUNE_CTRL_MAX;
 871                 host->tuning_step = SDHCI_TUNE_CTRL_STEP;
 872                 host->clk_mgr_en = true;
 873         }
 874
 875         reg = readl(host->ioaddr + SDHCI_MIX_CTRL);
 876         reg &= ~SDHCI_MIX_CTRL_DDREN;
 877         writel(reg, host->ioaddr + SDHCI_MIX_CTRL);
 878
 879         if (boarddata) {
 880                 /* Device is always present, e.x, populated emmc device */
 881                 if (boarddata->always_present) {
 882                         /* remove BROKEN_CD to disable card polling */
 883                         host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 884                         /* if it is always present, invalidate cd_gpio */
 885                         boarddata->cd_gpio = -EINVAL;
 886                         if (host->clk_mgr_en)
 887                                 clk_disable(pltfm_host->clk);
 888                         return 0;
 889                 }
 890
 891                 if (gpio_is_valid(boarddata->wp_gpio)) {
 892                         err = gpio_request_one(boarddata->wp_gpio, GPIOF_IN, "ESDHC_WP");
 893                         if (err) {
 894                                 dev_err(mmc_dev(host->mmc),
 895                                         "failed to request write-protect pin: %d!\n",
 896                                         err);
 897                         }
 898                 } else {
 899                         dev_warn(mmc_dev(host->mmc),
 900                                 "no write-protect pin available!\n");
 901                 }
 902
 903                 if (gpio_is_valid(boarddata->cd_gpio)) {
 904                         err = gpio_request_one(boarddata->cd_gpio, GPIOF_IN, "ESDHC_CD");
 905                         if (err) {
 906                                 dev_err(mmc_dev(host->mmc),
 907                                         "failed to request card-detect pin: %d!\n",
 908                                         err);
 909                                 goto no_card_detect_pin;
 910                         }
 911                 } else {
 912                         dev_warn(mmc_dev(host->mmc),
 913                                 "no card-detect pin available!\n");
 914                         goto no_card_detect_pin;
 915                 }
 916
 917                 err = request_irq(gpio_to_irq(boarddata->cd_gpio), cd_irq,
 918                                  IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
 919                                  mmc_hostname(host->mmc), host);
 920                 if (err) {
 921                         dev_warn(mmc_dev(host->mmc), "request irq error\n");
 922                         goto no_card_detect_irq;
 923                 }
 924
 925                 imx_data->flags |= ESDHC_FLAG_GPIO_FOR_CD_WP;
 926                 /* Now we have a working card_detect again */
 927                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 928         }
 929
 930 #ifdef CONFIG_PM_RUNTIME
 931         host->mmc->caps |= MMC_CAP_POWER_OFF_CARD;
 932 #endif
 933
 934         if (host->clk_mgr_en)
 935                 clk_disable(pltfm_host->clk);
 936         return 0;
 937
 938  no_card_detect_irq:
 939         gpio_free(boarddata->cd_gpio);
 940  no_card_detect_pin:
 941         kfree(imx_data);
 942         if (host->clk_mgr_en)
 943                 clk_disable(pltfm_host->clk);
 944         return 0;
 945 }
 946
 947 static void esdhc_pltfm_exit(struct sdhci_host *host)
 948 {
 949         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 950         struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data;
 951         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 952
 953         if (boarddata && gpio_is_valid(boarddata->wp_gpio))
 954                 gpio_free(boarddata->wp_gpio);
 955
 956         if (boarddata && gpio_is_valid(boarddata->cd_gpio)) {
 957                 gpio_free(boarddata->cd_gpio);
 958
 959                 if (!(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION))
 960                         free_irq(gpio_to_irq(boarddata->cd_gpio), host);
 961         }
 962
 963         if (!host->clk_mgr_en)
 964                 clk_disable(pltfm_host->clk);
 965         clk_put(pltfm_host->clk);
 966         kfree(imx_data);
 967 }
 968
 969 struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
 970         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 971                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
 972                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION
 973                         | SDHCI_QUIRK_BROKEN_ADMA
 974                         | SDHCI_QUIRK_NO_HISPD_BIT,
 975         /* ADMA has issues. Might be fixable */
 976         .ops = &sdhci_esdhc_ops,
 977         .init = esdhc_pltfm_init,
 978         .exit = esdhc_pltfm_exit,
 979 };