drivers/mtd/nand/fsl_ifc_nand.c

   1 /*
   2  * Freescale Integrated Flash Controller NAND driver
   3  *
   4  * Copyright 2011-2012 Freescale Semiconductor, Inc
   5  *
   6  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/types.h>
  25 #include <linux/init.h>
  26 #include <linux/kernel.h>
  27 #include <linux/of_address.h>
  28 #include <linux/slab.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/nand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/mtd/nand_ecc.h>
  33 #include <asm/fsl_ifc.h>
  34
  35 #define FSL_IFC_V1_1_0  0x01010000
  36 #define ERR_BYTE                0xFF /* Value returned for read
  37                                         bytes when read failed  */
  38 #define IFC_TIMEOUT_MSECS       500  /* Maximum number of mSecs to wait
  39                                         for IFC NAND Machine    */
  40
  41 struct fsl_ifc_ctrl;
  42
  43 /* mtd information per set */
  44 struct fsl_ifc_mtd {
  45         struct mtd_info mtd;
  46         struct nand_chip chip;
  47         struct fsl_ifc_ctrl *ctrl;
  48
  49         struct device *dev;
  50         int bank;               /* Chip select bank number              */
  51         unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  52         u8 __iomem *vbase;      /* Chip select base virtual address     */
  53 };
  54
  55 /* overview of the fsl ifc controller */
  56 struct fsl_ifc_nand_ctrl {
  57         struct nand_hw_control controller;
  58         struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
  59
  60         u8 __iomem *addr;       /* Address of assigned IFC buffer       */
  61         unsigned int page;      /* Last page written to / read from     */
  62         unsigned int read_bytes;/* Number of bytes read during command  */
  63         unsigned int column;    /* Saved column from SEQIN              */
  64         unsigned int index;     /* Pointer to next byte to 'read'       */
  65         unsigned int oob;       /* Non zero if operating on OOB data    */
  66         unsigned int eccread;   /* Non zero for a full-page ECC read    */
  67         unsigned int counter;   /* counter for the initializations      */
  68         unsigned int max_bitflips;  /* Saved during READ0 cmd           */
  69 };
  70
  71 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
  72
  73 /* 512-byte page with 4-bit ECC, 8-bit */
  74 static struct nand_ecclayout oob_512_8bit_ecc4 = {
  75         .eccbytes = 8,
  76         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  77         .oobfree = { {0, 5}, {6, 2} },
  78 };
  79
  80 /* 512-byte page with 4-bit ECC, 16-bit */
  81 static struct nand_ecclayout oob_512_16bit_ecc4 = {
  82         .eccbytes = 8,
  83         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  84         .oobfree = { {2, 6}, },
  85 };
  86
  87 /* 2048-byte page size with 4-bit ECC */
  88 static struct nand_ecclayout oob_2048_ecc4 = {
  89         .eccbytes = 32,
  90         .eccpos = {
  91                 8, 9, 10, 11, 12, 13, 14, 15,
  92                 16, 17, 18, 19, 20, 21, 22, 23,
  93                 24, 25, 26, 27, 28, 29, 30, 31,
  94                 32, 33, 34, 35, 36, 37, 38, 39,
  95         },
  96         .oobfree = { {2, 6}, {40, 24} },
  97 };
  98
  99 /* 4096-byte page size with 4-bit ECC */
 100 static struct nand_ecclayout oob_4096_ecc4 = {
 101         .eccbytes = 64,
 102         .eccpos = {
 103                 8, 9, 10, 11, 12, 13, 14, 15,
 104                 16, 17, 18, 19, 20, 21, 22, 23,
 105                 24, 25, 26, 27, 28, 29, 30, 31,
 106                 32, 33, 34, 35, 36, 37, 38, 39,
 107                 40, 41, 42, 43, 44, 45, 46, 47,
 108                 48, 49, 50, 51, 52, 53, 54, 55,
 109                 56, 57, 58, 59, 60, 61, 62, 63,
 110                 64, 65, 66, 67, 68, 69, 70, 71,
 111         },
 112         .oobfree = { {2, 6}, {72, 56} },
 113 };
 114
 115 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
 116 static struct nand_ecclayout oob_4096_ecc8 = {
 117         .eccbytes = 128,
 118         .eccpos = {
 119                 8, 9, 10, 11, 12, 13, 14, 15,
 120                 16, 17, 18, 19, 20, 21, 22, 23,
 121                 24, 25, 26, 27, 28, 29, 30, 31,
 122                 32, 33, 34, 35, 36, 37, 38, 39,
 123                 40, 41, 42, 43, 44, 45, 46, 47,
 124                 48, 49, 50, 51, 52, 53, 54, 55,
 125                 56, 57, 58, 59, 60, 61, 62, 63,
 126                 64, 65, 66, 67, 68, 69, 70, 71,
 127                 72, 73, 74, 75, 76, 77, 78, 79,
 128                 80, 81, 82, 83, 84, 85, 86, 87,
 129                 88, 89, 90, 91, 92, 93, 94, 95,
 130                 96, 97, 98, 99, 100, 101, 102, 103,
 131                 104, 105, 106, 107, 108, 109, 110, 111,
 132                 112, 113, 114, 115, 116, 117, 118, 119,
 133                 120, 121, 122, 123, 124, 125, 126, 127,
 134                 128, 129, 130, 131, 132, 133, 134, 135,
 135         },
 136         .oobfree = { {2, 6}, {136, 82} },
 137 };
 138
 139 /* 8192-byte page size with 4-bit ECC */
 140 static struct nand_ecclayout oob_8192_ecc4 = {
 141         .eccbytes = 128,
 142         .eccpos = {
 143                 8, 9, 10, 11, 12, 13, 14, 15,
 144                 16, 17, 18, 19, 20, 21, 22, 23,
 145                 24, 25, 26, 27, 28, 29, 30, 31,
 146                 32, 33, 34, 35, 36, 37, 38, 39,
 147                 40, 41, 42, 43, 44, 45, 46, 47,
 148                 48, 49, 50, 51, 52, 53, 54, 55,
 149                 56, 57, 58, 59, 60, 61, 62, 63,
 150                 64, 65, 66, 67, 68, 69, 70, 71,
 151                 72, 73, 74, 75, 76, 77, 78, 79,
 152                 80, 81, 82, 83, 84, 85, 86, 87,
 153                 88, 89, 90, 91, 92, 93, 94, 95,
 154                 96, 97, 98, 99, 100, 101, 102, 103,
 155                 104, 105, 106, 107, 108, 109, 110, 111,
 156                 112, 113, 114, 115, 116, 117, 118, 119,
 157                 120, 121, 122, 123, 124, 125, 126, 127,
 158                 128, 129, 130, 131, 132, 133, 134, 135,
 159         },
 160         .oobfree = { {2, 6}, {136, 208} },
 161 };
 162
 163 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
 164 static struct nand_ecclayout oob_8192_ecc8 = {
 165         .eccbytes = 256,
 166         .eccpos = {
 167                 8, 9, 10, 11, 12, 13, 14, 15,
 168                 16, 17, 18, 19, 20, 21, 22, 23,
 169                 24, 25, 26, 27, 28, 29, 30, 31,
 170                 32, 33, 34, 35, 36, 37, 38, 39,
 171                 40, 41, 42, 43, 44, 45, 46, 47,
 172                 48, 49, 50, 51, 52, 53, 54, 55,
 173                 56, 57, 58, 59, 60, 61, 62, 63,
 174                 64, 65, 66, 67, 68, 69, 70, 71,
 175                 72, 73, 74, 75, 76, 77, 78, 79,
 176                 80, 81, 82, 83, 84, 85, 86, 87,
 177                 88, 89, 90, 91, 92, 93, 94, 95,
 178                 96, 97, 98, 99, 100, 101, 102, 103,
 179                 104, 105, 106, 107, 108, 109, 110, 111,
 180                 112, 113, 114, 115, 116, 117, 118, 119,
 181                 120, 121, 122, 123, 124, 125, 126, 127,
 182                 128, 129, 130, 131, 132, 133, 134, 135,
 183                 136, 137, 138, 139, 140, 141, 142, 143,
 184                 144, 145, 146, 147, 148, 149, 150, 151,
 185                 152, 153, 154, 155, 156, 157, 158, 159,
 186                 160, 161, 162, 163, 164, 165, 166, 167,
 187                 168, 169, 170, 171, 172, 173, 174, 175,
 188                 176, 177, 178, 179, 180, 181, 182, 183,
 189                 184, 185, 186, 187, 188, 189, 190, 191,
 190                 192, 193, 194, 195, 196, 197, 198, 199,
 191                 200, 201, 202, 203, 204, 205, 206, 207,
 192                 208, 209, 210, 211, 212, 213, 214, 215,
 193                 216, 217, 218, 219, 220, 221, 222, 223,
 194                 224, 225, 226, 227, 228, 229, 230, 231,
 195                 232, 233, 234, 235, 236, 237, 238, 239,
 196                 240, 241, 242, 243, 244, 245, 246, 247,
 197                 248, 249, 250, 251, 252, 253, 254, 255,
 198                 256, 257, 258, 259, 260, 261, 262, 263,
 199         },
 200         .oobfree = { {2, 6}, {264, 80} },
 201 };
 202
 203 /*
 204  * Generic flash bbt descriptors
 205  */
 206 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 207 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 208
 209 static struct nand_bbt_descr bbt_main_descr = {
 210         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 211                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 212         .offs = 2, /* 0 on 8-bit small page */
 213         .len = 4,
 214         .veroffs = 6,
 215         .maxblocks = 4,
 216         .pattern = bbt_pattern,
 217 };
 218
 219 static struct nand_bbt_descr bbt_mirror_descr = {
 220         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 221                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 222         .offs = 2, /* 0 on 8-bit small page */
 223         .len = 4,
 224         .veroffs = 6,
 225         .maxblocks = 4,
 226         .pattern = mirror_pattern,
 227 };
 228
 229 /*
 230  * Set up the IFC hardware block and page address fields, and the ifc nand
 231  * structure addr field to point to the correct IFC buffer in memory
 232  */
 233 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 234 {
 235         struct nand_chip *chip = mtd->priv;
 236         struct fsl_ifc_mtd *priv = chip->priv;
 237         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 238         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 239         int buf_num;
 240
 241         ifc_nand_ctrl->page = page_addr;
 242         /* Program ROW0/COL0 */
 243         iowrite32be(page_addr, &ifc->ifc_nand.row0);
 244         iowrite32be((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
 245
 246         buf_num = page_addr & priv->bufnum_mask;
 247
 248         ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
 249         ifc_nand_ctrl->index = column;
 250
 251         /* for OOB data point to the second half of the buffer */
 252         if (oob)
 253                 ifc_nand_ctrl->index += mtd->writesize;
 254 }
 255
 256 static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
 257 {
 258         struct nand_chip *chip = mtd->priv;
 259         struct fsl_ifc_mtd *priv = chip->priv;
 260         u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
 261         u32 __iomem *mainarea = (u32 __iomem *)addr;
 262         u8 __iomem *oob = addr + mtd->writesize;
 263         int i;
 264
 265         for (i = 0; i < mtd->writesize / 4; i++) {
 266                 if (__raw_readl(&mainarea[i]) != 0xffffffff)
 267                         return 0;
 268         }
 269
 270         for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
 271                 int pos = chip->ecc.layout->eccpos[i];
 272
 273                 if (__raw_readb(&oob[pos]) != 0xff)
 274                         return 0;
 275         }
 276
 277         return 1;
 278 }
 279
 280 /* returns nonzero if entire page is blank */
 281 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 282                           u32 *eccstat, unsigned int bufnum)
 283 {
 284         u32 reg = eccstat[bufnum / 4];
 285         int errors;
 286
 287         errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
 288
 289         return errors;
 290 }
 291
 292 /*
 293  * execute IFC NAND command and wait for it to complete
 294  */
 295 static void fsl_ifc_run_command(struct mtd_info *mtd)
 296 {
 297         struct nand_chip *chip = mtd->priv;
 298         struct fsl_ifc_mtd *priv = chip->priv;
 299         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 300         struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
 301         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 302         u32 eccstat[4];
 303         int i;
 304
 305         /* set the chip select for NAND Transaction */
 306         iowrite32be(priv->bank << IFC_NAND_CSEL_SHIFT,
 307                     &ifc->ifc_nand.nand_csel);
 308
 309         dev_vdbg(priv->dev,
 310                         "%s: fir0=%08x fcr0=%08x\n",
 311                         __func__,
 312                         ioread32be(&ifc->ifc_nand.nand_fir0),
 313                         ioread32be(&ifc->ifc_nand.nand_fcr0));
 314
 315         ctrl->nand_stat = 0;
 316
 317         /* start read/write seq */
 318         iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
 319
 320         /* wait for command complete flag or timeout */
 321         wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
 322                            IFC_TIMEOUT_MSECS * HZ/1000);
 323
 324         /* ctrl->nand_stat will be updated from IRQ context */
 325         if (!ctrl->nand_stat)
 326                 dev_err(priv->dev, "Controller is not responding\n");
 327         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
 328                 dev_err(priv->dev, "NAND Flash Timeout Error\n");
 329         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
 330                 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
 331
 332         nctrl->max_bitflips = 0;
 333
 334         if (nctrl->eccread) {
 335                 int errors;
 336                 int bufnum = nctrl->page & priv->bufnum_mask;
 337                 int sector = bufnum * chip->ecc.steps;
 338                 int sector_end = sector + chip->ecc.steps - 1;
 339
 340                 for (i = sector / 4; i <= sector_end / 4; i++)
 341                         eccstat[i] = ioread32be(&ifc->ifc_nand.nand_eccstat[i]);
 342
 343                 for (i = sector; i <= sector_end; i++) {
 344                         errors = check_read_ecc(mtd, ctrl, eccstat, i);
 345
 346                         if (errors == 15) {
 347                                 /*
 348                                  * Uncorrectable error.
 349                                  * OK only if the whole page is blank.
 350                                  *
 351                                  * We disable ECCER reporting due to...
 352                                  * erratum IFC-A002770 -- so report it now if we
 353                                  * see an uncorrectable error in ECCSTAT.
 354                                  */
 355                                 if (!is_blank(mtd, bufnum))
 356                                         ctrl->nand_stat |=
 357                                                 IFC_NAND_EVTER_STAT_ECCER;
 358                                 break;
 359                         }
 360
 361                         mtd->ecc_stats.corrected += errors;
 362                         nctrl->max_bitflips = max_t(unsigned int,
 363                                                     nctrl->max_bitflips,
 364                                                     errors);
 365                 }
 366
 367                 nctrl->eccread = 0;
 368         }
 369 }
 370
 371 static void fsl_ifc_do_read(struct nand_chip *chip,
 372                             int oob,
 373                             struct mtd_info *mtd)
 374 {
 375         struct fsl_ifc_mtd *priv = chip->priv;
 376         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 377         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 378
 379         /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 380         if (mtd->writesize > 512) {
 381                 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 382                             (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 383                             (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 384                             (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 385                             (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
 386                             &ifc->ifc_nand.nand_fir0);
 387                 iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
 388
 389                 iowrite32be((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 390                             (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
 391                             &ifc->ifc_nand.nand_fcr0);
 392         } else {
 393                 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 394                             (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 395                             (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 396                             (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
 397                             &ifc->ifc_nand.nand_fir0);
 398                 iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
 399
 400                 if (oob)
 401                         iowrite32be(NAND_CMD_READOOB <<
 402                                     IFC_NAND_FCR0_CMD0_SHIFT,
 403                                     &ifc->ifc_nand.nand_fcr0);
 404                 else
 405                         iowrite32be(NAND_CMD_READ0 <<
 406                                     IFC_NAND_FCR0_CMD0_SHIFT,
 407                                     &ifc->ifc_nand.nand_fcr0);
 408         }
 409 }
 410
 411 /* cmdfunc send commands to the IFC NAND Machine */
 412 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 413                              int column, int page_addr) {
 414         struct nand_chip *chip = mtd->priv;
 415         struct fsl_ifc_mtd *priv = chip->priv;
 416         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 417         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 418
 419         /* clear the read buffer */
 420         ifc_nand_ctrl->read_bytes = 0;
 421         if (command != NAND_CMD_PAGEPROG)
 422                 ifc_nand_ctrl->index = 0;
 423
 424         switch (command) {
 425         /* READ0 read the entire buffer to use hardware ECC. */
 426         case NAND_CMD_READ0:
 427                 iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
 428                 set_addr(mtd, 0, page_addr, 0);
 429
 430                 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 431                 ifc_nand_ctrl->index += column;
 432
 433                 if (chip->ecc.mode == NAND_ECC_HW)
 434                         ifc_nand_ctrl->eccread = 1;
 435
 436                 fsl_ifc_do_read(chip, 0, mtd);
 437                 fsl_ifc_run_command(mtd);
 438                 return;
 439
 440         /* READOOB reads only the OOB because no ECC is performed. */
 441         case NAND_CMD_READOOB:
 442                 iowrite32be(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
 443                 set_addr(mtd, column, page_addr, 1);
 444
 445                 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 446
 447                 fsl_ifc_do_read(chip, 1, mtd);
 448                 fsl_ifc_run_command(mtd);
 449
 450                 return;
 451
 452         case NAND_CMD_READID:
 453         case NAND_CMD_PARAM: {
 454                 int timing = IFC_FIR_OP_RB;
 455                 if (command == NAND_CMD_PARAM)
 456                         timing = IFC_FIR_OP_RBCD;
 457
 458                 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 459                             (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 460                             (timing << IFC_NAND_FIR0_OP2_SHIFT),
 461                             &ifc->ifc_nand.nand_fir0);
 462                 iowrite32be(command << IFC_NAND_FCR0_CMD0_SHIFT,
 463                             &ifc->ifc_nand.nand_fcr0);
 464                 iowrite32be(column, &ifc->ifc_nand.row3);
 465
 466                 /*
 467                  * although currently it's 8 bytes for READID, we always read
 468                  * the maximum 256 bytes(for PARAM)
 469                  */
 470                 iowrite32be(256, &ifc->ifc_nand.nand_fbcr);
 471                 ifc_nand_ctrl->read_bytes = 256;
 472
 473                 set_addr(mtd, 0, 0, 0);
 474                 fsl_ifc_run_command(mtd);
 475                 return;
 476         }
 477
 478         /* ERASE1 stores the block and page address */
 479         case NAND_CMD_ERASE1:
 480                 set_addr(mtd, 0, page_addr, 0);
 481                 return;
 482
 483         /* ERASE2 uses the block and page address from ERASE1 */
 484         case NAND_CMD_ERASE2:
 485                 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 486                             (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 487                             (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
 488                             &ifc->ifc_nand.nand_fir0);
 489
 490                 iowrite32be((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
 491                             (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
 492                             &ifc->ifc_nand.nand_fcr0);
 493
 494                 iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
 495                 ifc_nand_ctrl->read_bytes = 0;
 496                 fsl_ifc_run_command(mtd);
 497                 return;
 498
 499         /* SEQIN sets up the addr buffer and all registers except the length */
 500         case NAND_CMD_SEQIN: {
 501                 u32 nand_fcr0;
 502                 ifc_nand_ctrl->column = column;
 503                 ifc_nand_ctrl->oob = 0;
 504
 505                 if (mtd->writesize > 512) {
 506                         nand_fcr0 =
 507                                 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
 508                                 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
 509                                 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
 510
 511                         iowrite32be(
 512                                  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 513                                  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 514                                  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 515                                  (IFC_FIR_OP_WBCD  << IFC_NAND_FIR0_OP3_SHIFT) |
 516                                  (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
 517                                  &ifc->ifc_nand.nand_fir0);
 518                         iowrite32be(
 519                                  (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
 520                                  (IFC_FIR_OP_RDSTAT <<
 521                                         IFC_NAND_FIR1_OP6_SHIFT) |
 522                                  (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
 523                                  &ifc->ifc_nand.nand_fir1);
 524                 } else {
 525                         nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 526                                         IFC_NAND_FCR0_CMD1_SHIFT) |
 527                                     (NAND_CMD_SEQIN <<
 528                                         IFC_NAND_FCR0_CMD2_SHIFT) |
 529                                     (NAND_CMD_STATUS <<
 530                                         IFC_NAND_FCR0_CMD3_SHIFT));
 531
 532                         iowrite32be(
 533                                 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 534                                 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
 535                                 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 536                                 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
 537                                 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
 538                                 &ifc->ifc_nand.nand_fir0);
 539                         iowrite32be(
 540                                  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
 541                                  (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
 542                                  (IFC_FIR_OP_RDSTAT <<
 543                                         IFC_NAND_FIR1_OP7_SHIFT) |
 544                                  (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
 545                                   &ifc->ifc_nand.nand_fir1);
 546
 547                         if (column >= mtd->writesize)
 548                                 nand_fcr0 |=
 549                                 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
 550                         else
 551                                 nand_fcr0 |=
 552                                 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
 553                 }
 554
 555                 if (column >= mtd->writesize) {
 556                         /* OOB area --> READOOB */
 557                         column -= mtd->writesize;
 558                         ifc_nand_ctrl->oob = 1;
 559                 }
 560                 iowrite32be(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
 561                 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
 562                 return;
 563         }
 564
 565         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 566         case NAND_CMD_PAGEPROG: {
 567                 if (ifc_nand_ctrl->oob) {
 568                         iowrite32be(ifc_nand_ctrl->index -
 569                                     ifc_nand_ctrl->column,
 570                                     &ifc->ifc_nand.nand_fbcr);
 571                 } else {
 572                         iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
 573                 }
 574
 575                 fsl_ifc_run_command(mtd);
 576                 return;
 577         }
 578
 579         case NAND_CMD_STATUS:
 580                 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 581                             (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
 582                             &ifc->ifc_nand.nand_fir0);
 583                 iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
 584                             &ifc->ifc_nand.nand_fcr0);
 585                 iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
 586                 set_addr(mtd, 0, 0, 0);
 587                 ifc_nand_ctrl->read_bytes = 1;
 588
 589                 fsl_ifc_run_command(mtd);
 590
 591                 /*
 592                  * The chip always seems to report that it is
 593                  * write-protected, even when it is not.
 594                  */
 595                 setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);
 596                 return;
 597
 598         case NAND_CMD_RESET:
 599                 iowrite32be(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
 600                             &ifc->ifc_nand.nand_fir0);
 601                 iowrite32be(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
 602                             &ifc->ifc_nand.nand_fcr0);
 603                 fsl_ifc_run_command(mtd);
 604                 return;
 605
 606         default:
 607                 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
 608                                         __func__, command);
 609         }
 610 }
 611
 612 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 613 {
 614         /* The hardware does not seem to support multiple
 615          * chips per bank.
 616          */
 617 }
 618
 619 /*
 620  * Write buf to the IFC NAND Controller Data Buffer
 621  */
 622 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 623 {
 624         struct nand_chip *chip = mtd->priv;
 625         struct fsl_ifc_mtd *priv = chip->priv;
 626         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 627
 628         if (len <= 0) {
 629                 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
 630                 return;
 631         }
 632
 633         if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
 634                 dev_err(priv->dev,
 635                         "%s: beyond end of buffer (%d requested, %u available)\n",
 636                         __func__, len, bufsize - ifc_nand_ctrl->index);
 637                 len = bufsize - ifc_nand_ctrl->index;
 638         }
 639
 640         memcpy_toio(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index], buf, len);
 641         ifc_nand_ctrl->index += len;
 642 }
 643
 644 /*
 645  * Read a byte from either the IFC hardware buffer
 646  * read function for 8-bit buswidth
 647  */
 648 static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
 649 {
 650         struct nand_chip *chip = mtd->priv;
 651         struct fsl_ifc_mtd *priv = chip->priv;
 652
 653         /*
 654          * If there are still bytes in the IFC buffer, then use the
 655          * next byte.
 656          */
 657         if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes)
 658                 return in_8(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index++]);
 659
 660         dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
 661         return ERR_BYTE;
 662 }
 663
 664 /*
 665  * Read two bytes from the IFC hardware buffer
 666  * read function for 16-bit buswith
 667  */
 668 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 669 {
 670         struct nand_chip *chip = mtd->priv;
 671         struct fsl_ifc_mtd *priv = chip->priv;
 672         uint16_t data;
 673
 674         /*
 675          * If there are still bytes in the IFC buffer, then use the
 676          * next byte.
 677          */
 678         if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
 679                 data = in_be16((uint16_t __iomem *)&ifc_nand_ctrl->
 680                                addr[ifc_nand_ctrl->index]);
 681                 ifc_nand_ctrl->index += 2;
 682                 return (uint8_t) data;
 683         }
 684
 685         dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
 686         return ERR_BYTE;
 687 }
 688
 689 /*
 690  * Read from the IFC Controller Data Buffer
 691  */
 692 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 693 {
 694         struct nand_chip *chip = mtd->priv;
 695         struct fsl_ifc_mtd *priv = chip->priv;
 696         int avail;
 697
 698         if (len < 0) {
 699                 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
 700                 return;
 701         }
 702
 703         avail = min((unsigned int)len,
 704                         ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
 705         memcpy_fromio(buf, &ifc_nand_ctrl->addr[ifc_nand_ctrl->index], avail);
 706         ifc_nand_ctrl->index += avail;
 707
 708         if (len > avail)
 709                 dev_err(priv->dev,
 710                         "%s: beyond end of buffer (%d requested, %d available)\n",
 711                         __func__, len, avail);
 712 }
 713
 714 /*
 715  * This function is called after Program and Erase Operations to
 716  * check for success or failure.
 717  */
 718 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 719 {
 720         struct fsl_ifc_mtd *priv = chip->priv;
 721         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 722         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 723         u32 nand_fsr;
 724
 725         /* Use READ_STATUS command, but wait for the device to be ready */
 726         iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 727                     (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
 728                     &ifc->ifc_nand.nand_fir0);
 729         iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
 730                     &ifc->ifc_nand.nand_fcr0);
 731         iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
 732         set_addr(mtd, 0, 0, 0);
 733         ifc_nand_ctrl->read_bytes = 1;
 734
 735         fsl_ifc_run_command(mtd);
 736
 737         nand_fsr = ioread32be(&ifc->ifc_nand.nand_fsr);
 738
 739         /*
 740          * The chip always seems to report that it is
 741          * write-protected, even when it is not.
 742          */
 743         return nand_fsr | NAND_STATUS_WP;
 744 }
 745
 746 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 747                              uint8_t *buf, int oob_required, int page)
 748 {
 749         struct fsl_ifc_mtd *priv = chip->priv;
 750         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 751         struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
 752
 753         fsl_ifc_read_buf(mtd, buf, mtd->writesize);
 754         if (oob_required)
 755                 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 756
 757         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
 758                 dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
 759
 760         if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
 761                 mtd->ecc_stats.failed++;
 762
 763         return nctrl->max_bitflips;
 764 }
 765
 766 /* ECC will be calculated automatically, and errors will be detected in
 767  * waitfunc.
 768  */
 769 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 770                                const uint8_t *buf, int oob_required)
 771 {
 772         fsl_ifc_write_buf(mtd, buf, mtd->writesize);
 773         fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 774
 775         return 0;
 776 }
 777
 778 static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
 779 {
 780         struct nand_chip *chip = mtd->priv;
 781         struct fsl_ifc_mtd *priv = chip->priv;
 782
 783         dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
 784                                                         chip->numchips);
 785         dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
 786                                                         chip->chipsize);
 787         dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
 788                                                         chip->pagemask);
 789         dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
 790                                                         chip->chip_delay);
 791         dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
 792                                                         chip->badblockpos);
 793         dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
 794                                                         chip->chip_shift);
 795         dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
 796                                                         chip->page_shift);
 797         dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
 798                                                         chip->phys_erase_shift);
 799         dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
 800                                                         chip->ecc.mode);
 801         dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
 802                                                         chip->ecc.steps);
 803         dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
 804                                                         chip->ecc.bytes);
 805         dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
 806                                                         chip->ecc.total);
 807         dev_dbg(priv->dev, "%s: nand->ecc.layout = %p\n", __func__,
 808                                                         chip->ecc.layout);
 809         dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
 810         dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
 811         dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
 812                                                         mtd->erasesize);
 813         dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
 814                                                         mtd->writesize);
 815         dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
 816                                                         mtd->oobsize);
 817
 818         return 0;
 819 }
 820
 821 static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
 822 {
 823         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 824         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 825         uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
 826         uint32_t cs = priv->bank;
 827
 828         /* Save CSOR and CSOR_ext */
 829         csor = ioread32be(&ifc->csor_cs[cs].csor);
 830         csor_ext = ioread32be(&ifc->csor_cs[cs].csor_ext);
 831
 832         /* chage PageSize 8K and SpareSize 1K*/
 833         csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
 834         iowrite32be(csor_8k, &ifc->csor_cs[cs].csor);
 835         iowrite32be(0x0000400, &ifc->csor_cs[cs].csor_ext);
 836
 837         /* READID */
 838         iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 839                     (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 840                     (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
 841                     &ifc->ifc_nand.nand_fir0);
 842         iowrite32be(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
 843                     &ifc->ifc_nand.nand_fcr0);
 844         iowrite32be(0x0, &ifc->ifc_nand.row3);
 845
 846         iowrite32be(0x0, &ifc->ifc_nand.nand_fbcr);
 847
 848         /* Program ROW0/COL0 */
 849         iowrite32be(0x0, &ifc->ifc_nand.row0);
 850         iowrite32be(0x0, &ifc->ifc_nand.col0);
 851
 852         /* set the chip select for NAND Transaction */
 853         iowrite32be(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
 854
 855         /* start read seq */
 856         iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
 857
 858         /* wait for command complete flag or timeout */
 859         wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
 860                            IFC_TIMEOUT_MSECS * HZ/1000);
 861
 862         if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
 863                 printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
 864
 865         /* Restore CSOR and CSOR_ext */
 866         iowrite32be(csor, &ifc->csor_cs[cs].csor);
 867         iowrite32be(csor_ext, &ifc->csor_cs[cs].csor_ext);
 868 }
 869
 870 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 871 {
 872         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 873         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 874         struct nand_chip *chip = &priv->chip;
 875         struct nand_ecclayout *layout;
 876         u32 csor, ver;
 877
 878         /* Fill in fsl_ifc_mtd structure */
 879         priv->mtd.priv = chip;
 880         priv->mtd.owner = THIS_MODULE;
 881
 882         /* fill in nand_chip structure */
 883         /* set up function call table */
 884         if ((ioread32be(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
 885                 chip->read_byte = fsl_ifc_read_byte16;
 886         else
 887                 chip->read_byte = fsl_ifc_read_byte;
 888
 889         chip->write_buf = fsl_ifc_write_buf;
 890         chip->read_buf = fsl_ifc_read_buf;
 891         chip->select_chip = fsl_ifc_select_chip;
 892         chip->cmdfunc = fsl_ifc_cmdfunc;
 893         chip->waitfunc = fsl_ifc_wait;
 894
 895         chip->bbt_td = &bbt_main_descr;
 896         chip->bbt_md = &bbt_mirror_descr;
 897
 898         iowrite32be(0x0, &ifc->ifc_nand.ncfgr);
 899
 900         /* set up nand options */
 901         chip->bbt_options = NAND_BBT_USE_FLASH;
 902         chip->options = NAND_NO_SUBPAGE_WRITE;
 903
 904         if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
 905                 chip->read_byte = fsl_ifc_read_byte16;
 906                 chip->options |= NAND_BUSWIDTH_16;
 907         } else {
 908                 chip->read_byte = fsl_ifc_read_byte;
 909         }
 910
 911         chip->controller = &ifc_nand_ctrl->controller;
 912         chip->priv = priv;
 913
 914         chip->ecc.read_page = fsl_ifc_read_page;
 915         chip->ecc.write_page = fsl_ifc_write_page;
 916
 917         csor = ioread32be(&ifc->csor_cs[priv->bank].csor);
 918
 919         /* Hardware generates ECC per 512 Bytes */
 920         chip->ecc.size = 512;
 921         chip->ecc.bytes = 8;
 922         chip->ecc.strength = 4;
 923
 924         switch (csor & CSOR_NAND_PGS_MASK) {
 925         case CSOR_NAND_PGS_512:
 926                 if (chip->options & NAND_BUSWIDTH_16) {
 927                         layout = &oob_512_16bit_ecc4;
 928                 } else {
 929                         layout = &oob_512_8bit_ecc4;
 930
 931                         /* Avoid conflict with bad block marker */
 932                         bbt_main_descr.offs = 0;
 933                         bbt_mirror_descr.offs = 0;
 934                 }
 935
 936                 priv->bufnum_mask = 15;
 937                 break;
 938
 939         case CSOR_NAND_PGS_2K:
 940                 layout = &oob_2048_ecc4;
 941                 priv->bufnum_mask = 3;
 942                 break;
 943
 944         case CSOR_NAND_PGS_4K:
 945                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
 946                     CSOR_NAND_ECC_MODE_4) {
 947                         layout = &oob_4096_ecc4;
 948                 } else {
 949                         layout = &oob_4096_ecc8;
 950                         chip->ecc.bytes = 16;
 951                         chip->ecc.strength = 8;
 952                 }
 953
 954                 priv->bufnum_mask = 1;
 955                 break;
 956
 957         case CSOR_NAND_PGS_8K:
 958                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
 959                     CSOR_NAND_ECC_MODE_4) {
 960                         layout = &oob_8192_ecc4;
 961                 } else {
 962                         layout = &oob_8192_ecc8;
 963                         chip->ecc.bytes = 16;
 964                         chip->ecc.strength = 8;
 965                 }
 966
 967                 priv->bufnum_mask = 0;
 968         break;
 969
 970         default:
 971                 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
 972                 return -ENODEV;
 973         }
 974
 975         /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
 976         if (csor & CSOR_NAND_ECC_DEC_EN) {
 977                 chip->ecc.mode = NAND_ECC_HW;
 978                 chip->ecc.layout = layout;
 979         } else {
 980                 chip->ecc.mode = NAND_ECC_SOFT;
 981         }
 982
 983         ver = ioread32be(&ifc->ifc_rev);
 984         if (ver == FSL_IFC_V1_1_0)
 985                 fsl_ifc_sram_init(priv);
 986
 987         return 0;
 988 }
 989
 990 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
 991 {
 992         nand_release(&priv->mtd);
 993
 994         kfree(priv->mtd.name);
 995
 996         if (priv->vbase)
 997                 iounmap(priv->vbase);
 998
 999         ifc_nand_ctrl->chips[priv->bank] = NULL;
1000
1001         return 0;
1002 }
1003
1004 static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
1005                       phys_addr_t addr)
1006 {
1007         u32 cspr = ioread32be(&ifc->cspr_cs[bank].cspr);
1008
1009         if (!(cspr & CSPR_V))
1010                 return 0;
1011         if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
1012                 return 0;
1013
1014         return (cspr & CSPR_BA) == convert_ifc_address(addr);
1015 }
1016
1017 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
1018
1019 static int fsl_ifc_nand_probe(struct platform_device *dev)
1020 {
1021         struct fsl_ifc_regs __iomem *ifc;
1022         struct fsl_ifc_mtd *priv;
1023         struct resource res;
1024         static const char *part_probe_types[]
1025                 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
1026         int ret;
1027         int bank;
1028         struct device_node *node = dev->dev.of_node;
1029         struct mtd_part_parser_data ppdata;
1030
1031         ppdata.of_node = dev->dev.of_node;
1032         if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
1033                 return -ENODEV;
1034         ifc = fsl_ifc_ctrl_dev->regs;
1035
1036         /* get, allocate and map the memory resource */
1037         ret = of_address_to_resource(node, 0, &res);
1038         if (ret) {
1039                 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
1040                 return ret;
1041         }
1042
1043         /* find which chip select it is connected to */
1044         for (bank = 0; bank < FSL_IFC_BANK_COUNT; bank++) {
1045                 if (match_bank(ifc, bank, res.start))
1046                         break;
1047         }
1048
1049         if (bank >= FSL_IFC_BANK_COUNT) {
1050                 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
1051                         __func__);
1052                 return -ENODEV;
1053         }
1054
1055         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1056         if (!priv)
1057                 return -ENOMEM;
1058
1059         mutex_lock(&fsl_ifc_nand_mutex);
1060         if (!fsl_ifc_ctrl_dev->nand) {
1061                 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
1062                 if (!ifc_nand_ctrl) {
1063                         dev_err(&dev->dev, "failed to allocate memory\n");
1064                         mutex_unlock(&fsl_ifc_nand_mutex);
1065                         return -ENOMEM;
1066                 }
1067
1068                 ifc_nand_ctrl->read_bytes = 0;
1069                 ifc_nand_ctrl->index = 0;
1070                 ifc_nand_ctrl->addr = NULL;
1071                 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
1072
1073                 spin_lock_init(&ifc_nand_ctrl->controller.lock);
1074                 init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
1075         } else {
1076                 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1077         }
1078         mutex_unlock(&fsl_ifc_nand_mutex);
1079
1080         ifc_nand_ctrl->chips[bank] = priv;
1081         priv->bank = bank;
1082         priv->ctrl = fsl_ifc_ctrl_dev;
1083         priv->dev = &dev->dev;
1084
1085         priv->vbase = ioremap(res.start, resource_size(&res));
1086         if (!priv->vbase) {
1087                 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1088                 ret = -ENOMEM;
1089                 goto err;
1090         }
1091
1092         dev_set_drvdata(priv->dev, priv);
1093
1094         iowrite32be(IFC_NAND_EVTER_EN_OPC_EN |
1095                     IFC_NAND_EVTER_EN_FTOER_EN |
1096                     IFC_NAND_EVTER_EN_WPER_EN,
1097                     &ifc->ifc_nand.nand_evter_en);
1098
1099         /* enable NAND Machine Interrupts */
1100         iowrite32be(IFC_NAND_EVTER_INTR_OPCIR_EN |
1101                     IFC_NAND_EVTER_INTR_FTOERIR_EN |
1102                     IFC_NAND_EVTER_INTR_WPERIR_EN,
1103                     &ifc->ifc_nand.nand_evter_intr_en);
1104         priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
1105         if (!priv->mtd.name) {
1106                 ret = -ENOMEM;
1107                 goto err;
1108         }
1109
1110         ret = fsl_ifc_chip_init(priv);
1111         if (ret)
1112                 goto err;
1113
1114         ret = nand_scan_ident(&priv->mtd, 1, NULL);
1115         if (ret)
1116                 goto err;
1117
1118         ret = fsl_ifc_chip_init_tail(&priv->mtd);
1119         if (ret)
1120                 goto err;
1121
1122         ret = nand_scan_tail(&priv->mtd);
1123         if (ret)
1124                 goto err;
1125
1126         /* First look for RedBoot table or partitions on the command
1127          * line, these take precedence over device tree information */
1128         mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
1129                                                 NULL, 0);
1130
1131         dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1132                  (unsigned long long)res.start, priv->bank);
1133         return 0;
1134
1135 err:
1136         fsl_ifc_chip_remove(priv);
1137         return ret;
1138 }
1139
1140 static int fsl_ifc_nand_remove(struct platform_device *dev)
1141 {
1142         struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1143
1144         fsl_ifc_chip_remove(priv);
1145
1146         mutex_lock(&fsl_ifc_nand_mutex);
1147         ifc_nand_ctrl->counter--;
1148         if (!ifc_nand_ctrl->counter) {
1149                 fsl_ifc_ctrl_dev->nand = NULL;
1150                 kfree(ifc_nand_ctrl);
1151         }
1152         mutex_unlock(&fsl_ifc_nand_mutex);
1153
1154         return 0;
1155 }
1156
1157 static const struct of_device_id fsl_ifc_nand_match[] = {
1158         {
1159                 .compatible = "fsl,ifc-nand",
1160         },
1161         {}
1162 };
1163
1164 static struct platform_driver fsl_ifc_nand_driver = {
1165         .driver = {
1166                 .name   = "fsl,ifc-nand",
1167                 .owner = THIS_MODULE,
1168                 .of_match_table = fsl_ifc_nand_match,
1169         },
1170         .probe       = fsl_ifc_nand_probe,
1171         .remove      = fsl_ifc_nand_remove,
1172 };
1173
1174 module_platform_driver(fsl_ifc_nand_driver);
1175
1176 MODULE_LICENSE("GPL");
1177 MODULE_AUTHOR("Freescale");
1178 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");