drivers/net/ethernet/amd/pcnet32.c

   1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
   2 /*
   3  *      Copyright 1996-1999 Thomas Bogendoerfer
   4  *
   5  *      Derived from the lance driver written 1993,1994,1995 by Donald Becker.
   6  *
   7  *      Copyright 1993 United States Government as represented by the
   8  *      Director, National Security Agency.
   9  *
  10  *      This software may be used and distributed according to the terms
  11  *      of the GNU General Public License, incorporated herein by reference.
  12  *
  13  *      This driver is for PCnet32 and PCnetPCI based ethercards
  14  */
  15 /**************************************************************************
  16  *  23 Oct, 2000.
  17  *  Fixed a few bugs, related to running the controller in 32bit mode.
  18  *
  19  *  Carsten Langgaard, carstenl@mips.com
  20  *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  21  *
  22  *************************************************************************/
  23
  24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  25
  26 #define DRV_NAME        "pcnet32"
  27 #define DRV_VERSION     "1.35"
  28 #define DRV_RELDATE     "21.Apr.2008"
  29 #define PFX             DRV_NAME ": "
  30
  31 static const char *const version =
  32     DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
  33
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/sched.h>
  37 #include <linux/string.h>
  38 #include <linux/errno.h>
  39 #include <linux/ioport.h>
  40 #include <linux/slab.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/pci.h>
  43 #include <linux/delay.h>
  44 #include <linux/init.h>
  45 #include <linux/ethtool.h>
  46 #include <linux/mii.h>
  47 #include <linux/crc32.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/etherdevice.h>
  50 #include <linux/if_ether.h>
  51 #include <linux/skbuff.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/bitops.h>
  55 #include <linux/io.h>
  56 #include <linux/uaccess.h>
  57
  58 #include <asm/dma.h>
  59 #include <asm/irq.h>
  60
  61 /*
  62  * PCI device identifiers for "new style" Linux PCI Device Drivers
  63  */
  64 static DEFINE_PCI_DEVICE_TABLE(pcnet32_pci_tbl) = {
  65         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
  66         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
  67
  68         /*
  69          * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
  70          * the incorrect vendor id.
  71          */
  72         { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
  73           .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
  74
  75         { }     /* terminate list */
  76 };
  77
  78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
  79
  80 static int cards_found;
  81
  82 /*
  83  * VLB I/O addresses
  84  */
  85 static unsigned int pcnet32_portlist[] =
  86     { 0x300, 0x320, 0x340, 0x360, 0 };
  87
  88 static int pcnet32_debug;
  89 static int tx_start = 1;        /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
  90 static int pcnet32vlb;          /* check for VLB cards ? */
  91
  92 static struct net_device *pcnet32_dev;
  93
  94 static int max_interrupt_work = 2;
  95 static int rx_copybreak = 200;
  96
  97 #define PCNET32_PORT_AUI      0x00
  98 #define PCNET32_PORT_10BT     0x01
  99 #define PCNET32_PORT_GPSI     0x02
 100 #define PCNET32_PORT_MII      0x03
 101
 102 #define PCNET32_PORT_PORTSEL  0x03
 103 #define PCNET32_PORT_ASEL     0x04
 104 #define PCNET32_PORT_100      0x40
 105 #define PCNET32_PORT_FD       0x80
 106
 107 #define PCNET32_DMA_MASK 0xffffffff
 108
 109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
 110 #define PCNET32_BLINK_TIMEOUT   (jiffies + (HZ/4))
 111
 112 /*
 113  * table to translate option values from tulip
 114  * to internal options
 115  */
 116 static const unsigned char options_mapping[] = {
 117         PCNET32_PORT_ASEL,                      /*  0 Auto-select      */
 118         PCNET32_PORT_AUI,                       /*  1 BNC/AUI          */
 119         PCNET32_PORT_AUI,                       /*  2 AUI/BNC          */
 120         PCNET32_PORT_ASEL,                      /*  3 not supported    */
 121         PCNET32_PORT_10BT | PCNET32_PORT_FD,    /*  4 10baseT-FD       */
 122         PCNET32_PORT_ASEL,                      /*  5 not supported    */
 123         PCNET32_PORT_ASEL,                      /*  6 not supported    */
 124         PCNET32_PORT_ASEL,                      /*  7 not supported    */
 125         PCNET32_PORT_ASEL,                      /*  8 not supported    */
 126         PCNET32_PORT_MII,                       /*  9 MII 10baseT      */
 127         PCNET32_PORT_MII | PCNET32_PORT_FD,     /* 10 MII 10baseT-FD   */
 128         PCNET32_PORT_MII,                       /* 11 MII (autosel)    */
 129         PCNET32_PORT_10BT,                      /* 12 10BaseT          */
 130         PCNET32_PORT_MII | PCNET32_PORT_100,    /* 13 MII 100BaseTx    */
 131                                                 /* 14 MII 100BaseTx-FD */
 132         PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
 133         PCNET32_PORT_ASEL                       /* 15 not supported    */
 134 };
 135
 136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
 137         "Loopback test  (offline)"
 138 };
 139
 140 #define PCNET32_TEST_LEN        ARRAY_SIZE(pcnet32_gstrings_test)
 141
 142 #define PCNET32_NUM_REGS 136
 143
 144 #define MAX_UNITS 8             /* More are supported, limit only on options */
 145 static int options[MAX_UNITS];
 146 static int full_duplex[MAX_UNITS];
 147 static int homepna[MAX_UNITS];
 148
 149 /*
 150  *                              Theory of Operation
 151  *
 152  * This driver uses the same software structure as the normal lance
 153  * driver. So look for a verbose description in lance.c. The differences
 154  * to the normal lance driver is the use of the 32bit mode of PCnet32
 155  * and PCnetPCI chips. Because these chips are 32bit chips, there is no
 156  * 16MB limitation and we don't need bounce buffers.
 157  */
 158
 159 /*
 160  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
 161  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
 162  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
 163  */
 164 #ifndef PCNET32_LOG_TX_BUFFERS
 165 #define PCNET32_LOG_TX_BUFFERS          4
 166 #define PCNET32_LOG_RX_BUFFERS          5
 167 #define PCNET32_LOG_MAX_TX_BUFFERS      9       /* 2^9 == 512 */
 168 #define PCNET32_LOG_MAX_RX_BUFFERS      9
 169 #endif
 170
 171 #define TX_RING_SIZE            (1 << (PCNET32_LOG_TX_BUFFERS))
 172 #define TX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
 173
 174 #define RX_RING_SIZE            (1 << (PCNET32_LOG_RX_BUFFERS))
 175 #define RX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
 176
 177 #define PKT_BUF_SKB             1544
 178 /* actual buffer length after being aligned */
 179 #define PKT_BUF_SIZE            (PKT_BUF_SKB - NET_IP_ALIGN)
 180 /* chip wants twos complement of the (aligned) buffer length */
 181 #define NEG_BUF_SIZE            (NET_IP_ALIGN - PKT_BUF_SKB)
 182
 183 /* Offsets from base I/O address. */
 184 #define PCNET32_WIO_RDP         0x10
 185 #define PCNET32_WIO_RAP         0x12
 186 #define PCNET32_WIO_RESET       0x14
 187 #define PCNET32_WIO_BDP         0x16
 188
 189 #define PCNET32_DWIO_RDP        0x10
 190 #define PCNET32_DWIO_RAP        0x14
 191 #define PCNET32_DWIO_RESET      0x18
 192 #define PCNET32_DWIO_BDP        0x1C
 193
 194 #define PCNET32_TOTAL_SIZE      0x20
 195
 196 #define CSR0            0
 197 #define CSR0_INIT       0x1
 198 #define CSR0_START      0x2
 199 #define CSR0_STOP       0x4
 200 #define CSR0_TXPOLL     0x8
 201 #define CSR0_INTEN      0x40
 202 #define CSR0_IDON       0x0100
 203 #define CSR0_NORMAL     (CSR0_START | CSR0_INTEN)
 204 #define PCNET32_INIT_LOW        1
 205 #define PCNET32_INIT_HIGH       2
 206 #define CSR3            3
 207 #define CSR4            4
 208 #define CSR5            5
 209 #define CSR5_SUSPEND    0x0001
 210 #define CSR15           15
 211 #define PCNET32_MC_FILTER       8
 212
 213 #define PCNET32_79C970A 0x2621
 214
 215 /* The PCNET32 Rx and Tx ring descriptors. */
 216 struct pcnet32_rx_head {
 217         __le32  base;
 218         __le16  buf_length;     /* two`s complement of length */
 219         __le16  status;
 220         __le32  msg_length;
 221         __le32  reserved;
 222 };
 223
 224 struct pcnet32_tx_head {
 225         __le32  base;
 226         __le16  length;         /* two`s complement of length */
 227         __le16  status;
 228         __le32  misc;
 229         __le32  reserved;
 230 };
 231
 232 /* The PCNET32 32-Bit initialization block, described in databook. */
 233 struct pcnet32_init_block {
 234         __le16  mode;
 235         __le16  tlen_rlen;
 236         u8      phys_addr[6];
 237         __le16  reserved;
 238         __le32  filter[2];
 239         /* Receive and transmit ring base, along with extra bits. */
 240         __le32  rx_ring;
 241         __le32  tx_ring;
 242 };
 243
 244 /* PCnet32 access functions */
 245 struct pcnet32_access {
 246         u16     (*read_csr) (unsigned long, int);
 247         void    (*write_csr) (unsigned long, int, u16);
 248         u16     (*read_bcr) (unsigned long, int);
 249         void    (*write_bcr) (unsigned long, int, u16);
 250         u16     (*read_rap) (unsigned long);
 251         void    (*write_rap) (unsigned long, u16);
 252         void    (*reset) (unsigned long);
 253 };
 254
 255 /*
 256  * The first field of pcnet32_private is read by the ethernet device
 257  * so the structure should be allocated using pci_alloc_consistent().
 258  */
 259 struct pcnet32_private {
 260         struct pcnet32_init_block *init_block;
 261         /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
 262         struct pcnet32_rx_head  *rx_ring;
 263         struct pcnet32_tx_head  *tx_ring;
 264         dma_addr_t              init_dma_addr;/* DMA address of beginning of the init block,
 265                                    returned by pci_alloc_consistent */
 266         struct pci_dev          *pci_dev;
 267         const char              *name;
 268         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 269         struct sk_buff          **tx_skbuff;
 270         struct sk_buff          **rx_skbuff;
 271         dma_addr_t              *tx_dma_addr;
 272         dma_addr_t              *rx_dma_addr;
 273         const struct pcnet32_access *a;
 274         spinlock_t              lock;           /* Guard lock */
 275         unsigned int            cur_rx, cur_tx; /* The next free ring entry */
 276         unsigned int            rx_ring_size;   /* current rx ring size */
 277         unsigned int            tx_ring_size;   /* current tx ring size */
 278         unsigned int            rx_mod_mask;    /* rx ring modular mask */
 279         unsigned int            tx_mod_mask;    /* tx ring modular mask */
 280         unsigned short          rx_len_bits;
 281         unsigned short          tx_len_bits;
 282         dma_addr_t              rx_ring_dma_addr;
 283         dma_addr_t              tx_ring_dma_addr;
 284         unsigned int            dirty_rx,       /* ring entries to be freed. */
 285                                 dirty_tx;
 286
 287         struct net_device       *dev;
 288         struct napi_struct      napi;
 289         char                    tx_full;
 290         char                    phycount;       /* number of phys found */
 291         int                     options;
 292         unsigned int            shared_irq:1,   /* shared irq possible */
 293                                 dxsuflo:1,   /* disable transmit stop on uflo */
 294                                 mii:1;          /* mii port available */
 295         struct net_device       *next;
 296         struct mii_if_info      mii_if;
 297         struct timer_list       watchdog_timer;
 298         u32                     msg_enable;     /* debug message level */
 299
 300         /* each bit indicates an available PHY */
 301         u32                     phymask;
 302         unsigned short          chip_version;   /* which variant this is */
 303
 304         /* saved registers during ethtool blink */
 305         u16                     save_regs[4];
 306 };
 307
 308 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
 309 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
 310 static int pcnet32_open(struct net_device *);
 311 static int pcnet32_init_ring(struct net_device *);
 312 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
 313                                       struct net_device *);
 314 static void pcnet32_tx_timeout(struct net_device *dev);
 315 static irqreturn_t pcnet32_interrupt(int, void *);
 316 static int pcnet32_close(struct net_device *);
 317 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
 318 static void pcnet32_load_multicast(struct net_device *dev);
 319 static void pcnet32_set_multicast_list(struct net_device *);
 320 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
 321 static void pcnet32_watchdog(struct net_device *);
 322 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
 323 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
 324                        int val);
 325 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
 326 static void pcnet32_ethtool_test(struct net_device *dev,
 327                                  struct ethtool_test *eth_test, u64 * data);
 328 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
 329 static int pcnet32_get_regs_len(struct net_device *dev);
 330 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 331                              void *ptr);
 332 static void pcnet32_purge_tx_ring(struct net_device *dev);
 333 static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
 334 static void pcnet32_free_ring(struct net_device *dev);
 335 static void pcnet32_check_media(struct net_device *dev, int verbose);
 336
 337 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
 338 {
 339         outw(index, addr + PCNET32_WIO_RAP);
 340         return inw(addr + PCNET32_WIO_RDP);
 341 }
 342
 343 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
 344 {
 345         outw(index, addr + PCNET32_WIO_RAP);
 346         outw(val, addr + PCNET32_WIO_RDP);
 347 }
 348
 349 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
 350 {
 351         outw(index, addr + PCNET32_WIO_RAP);
 352         return inw(addr + PCNET32_WIO_BDP);
 353 }
 354
 355 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
 356 {
 357         outw(index, addr + PCNET32_WIO_RAP);
 358         outw(val, addr + PCNET32_WIO_BDP);
 359 }
 360
 361 static u16 pcnet32_wio_read_rap(unsigned long addr)
 362 {
 363         return inw(addr + PCNET32_WIO_RAP);
 364 }
 365
 366 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
 367 {
 368         outw(val, addr + PCNET32_WIO_RAP);
 369 }
 370
 371 static void pcnet32_wio_reset(unsigned long addr)
 372 {
 373         inw(addr + PCNET32_WIO_RESET);
 374 }
 375
 376 static int pcnet32_wio_check(unsigned long addr)
 377 {
 378         outw(88, addr + PCNET32_WIO_RAP);
 379         return inw(addr + PCNET32_WIO_RAP) == 88;
 380 }
 381
 382 static const struct pcnet32_access pcnet32_wio = {
 383         .read_csr = pcnet32_wio_read_csr,
 384         .write_csr = pcnet32_wio_write_csr,
 385         .read_bcr = pcnet32_wio_read_bcr,
 386         .write_bcr = pcnet32_wio_write_bcr,
 387         .read_rap = pcnet32_wio_read_rap,
 388         .write_rap = pcnet32_wio_write_rap,
 389         .reset = pcnet32_wio_reset
 390 };
 391
 392 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
 393 {
 394         outl(index, addr + PCNET32_DWIO_RAP);
 395         return inl(addr + PCNET32_DWIO_RDP) & 0xffff;
 396 }
 397
 398 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
 399 {
 400         outl(index, addr + PCNET32_DWIO_RAP);
 401         outl(val, addr + PCNET32_DWIO_RDP);
 402 }
 403
 404 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
 405 {
 406         outl(index, addr + PCNET32_DWIO_RAP);
 407         return inl(addr + PCNET32_DWIO_BDP) & 0xffff;
 408 }
 409
 410 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
 411 {
 412         outl(index, addr + PCNET32_DWIO_RAP);
 413         outl(val, addr + PCNET32_DWIO_BDP);
 414 }
 415
 416 static u16 pcnet32_dwio_read_rap(unsigned long addr)
 417 {
 418         return inl(addr + PCNET32_DWIO_RAP) & 0xffff;
 419 }
 420
 421 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
 422 {
 423         outl(val, addr + PCNET32_DWIO_RAP);
 424 }
 425
 426 static void pcnet32_dwio_reset(unsigned long addr)
 427 {
 428         inl(addr + PCNET32_DWIO_RESET);
 429 }
 430
 431 static int pcnet32_dwio_check(unsigned long addr)
 432 {
 433         outl(88, addr + PCNET32_DWIO_RAP);
 434         return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88;
 435 }
 436
 437 static const struct pcnet32_access pcnet32_dwio = {
 438         .read_csr = pcnet32_dwio_read_csr,
 439         .write_csr = pcnet32_dwio_write_csr,
 440         .read_bcr = pcnet32_dwio_read_bcr,
 441         .write_bcr = pcnet32_dwio_write_bcr,
 442         .read_rap = pcnet32_dwio_read_rap,
 443         .write_rap = pcnet32_dwio_write_rap,
 444         .reset = pcnet32_dwio_reset
 445 };
 446
 447 static void pcnet32_netif_stop(struct net_device *dev)
 448 {
 449         struct pcnet32_private *lp = netdev_priv(dev);
 450
 451         dev->trans_start = jiffies; /* prevent tx timeout */
 452         napi_disable(&lp->napi);
 453         netif_tx_disable(dev);
 454 }
 455
 456 static void pcnet32_netif_start(struct net_device *dev)
 457 {
 458         struct pcnet32_private *lp = netdev_priv(dev);
 459         ulong ioaddr = dev->base_addr;
 460         u16 val;
 461
 462         netif_wake_queue(dev);
 463         val = lp->a->read_csr(ioaddr, CSR3);
 464         val &= 0x00ff;
 465         lp->a->write_csr(ioaddr, CSR3, val);
 466         napi_enable(&lp->napi);
 467 }
 468
 469 /*
 470  * Allocate space for the new sized tx ring.
 471  * Free old resources
 472  * Save new resources.
 473  * Any failure keeps old resources.
 474  * Must be called with lp->lock held.
 475  */
 476 static void pcnet32_realloc_tx_ring(struct net_device *dev,
 477                                     struct pcnet32_private *lp,
 478                                     unsigned int size)
 479 {
 480         dma_addr_t new_ring_dma_addr;
 481         dma_addr_t *new_dma_addr_list;
 482         struct pcnet32_tx_head *new_tx_ring;
 483         struct sk_buff **new_skb_list;
 484
 485         pcnet32_purge_tx_ring(dev);
 486
 487         new_tx_ring = pci_alloc_consistent(lp->pci_dev,
 488                                            sizeof(struct pcnet32_tx_head) *
 489                                            (1 << size),
 490                                            &new_ring_dma_addr);
 491         if (new_tx_ring == NULL) {
 492                 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
 493                 return;
 494         }
 495         memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
 496
 497         new_dma_addr_list = kcalloc(1 << size, sizeof(dma_addr_t),
 498                                     GFP_ATOMIC);
 499         if (!new_dma_addr_list)
 500                 goto free_new_tx_ring;
 501
 502         new_skb_list = kcalloc(1 << size, sizeof(struct sk_buff *),
 503                                GFP_ATOMIC);
 504         if (!new_skb_list)
 505                 goto free_new_lists;
 506
 507         kfree(lp->tx_skbuff);
 508         kfree(lp->tx_dma_addr);
 509         pci_free_consistent(lp->pci_dev,
 510                             sizeof(struct pcnet32_tx_head) *
 511                             lp->tx_ring_size, lp->tx_ring,
 512                             lp->tx_ring_dma_addr);
 513
 514         lp->tx_ring_size = (1 << size);
 515         lp->tx_mod_mask = lp->tx_ring_size - 1;
 516         lp->tx_len_bits = (size << 12);
 517         lp->tx_ring = new_tx_ring;
 518         lp->tx_ring_dma_addr = new_ring_dma_addr;
 519         lp->tx_dma_addr = new_dma_addr_list;
 520         lp->tx_skbuff = new_skb_list;
 521         return;
 522
 523 free_new_lists:
 524         kfree(new_dma_addr_list);
 525 free_new_tx_ring:
 526         pci_free_consistent(lp->pci_dev,
 527                             sizeof(struct pcnet32_tx_head) *
 528                             (1 << size),
 529                             new_tx_ring,
 530                             new_ring_dma_addr);
 531 }
 532
 533 /*
 534  * Allocate space for the new sized rx ring.
 535  * Re-use old receive buffers.
 536  *   alloc extra buffers
 537  *   free unneeded buffers
 538  *   free unneeded buffers
 539  * Save new resources.
 540  * Any failure keeps old resources.
 541  * Must be called with lp->lock held.
 542  */
 543 static void pcnet32_realloc_rx_ring(struct net_device *dev,
 544                                     struct pcnet32_private *lp,
 545                                     unsigned int size)
 546 {
 547         dma_addr_t new_ring_dma_addr;
 548         dma_addr_t *new_dma_addr_list;
 549         struct pcnet32_rx_head *new_rx_ring;
 550         struct sk_buff **new_skb_list;
 551         int new, overlap;
 552
 553         new_rx_ring = pci_alloc_consistent(lp->pci_dev,
 554                                            sizeof(struct pcnet32_rx_head) *
 555                                            (1 << size),
 556                                            &new_ring_dma_addr);
 557         if (new_rx_ring == NULL) {
 558                 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
 559                 return;
 560         }
 561         memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
 562
 563         new_dma_addr_list = kcalloc(1 << size, sizeof(dma_addr_t), GFP_ATOMIC);
 564         if (!new_dma_addr_list)
 565                 goto free_new_rx_ring;
 566
 567         new_skb_list = kcalloc(1 << size, sizeof(struct sk_buff *),
 568                                GFP_ATOMIC);
 569         if (!new_skb_list)
 570                 goto free_new_lists;
 571
 572         /* first copy the current receive buffers */
 573         overlap = min(size, lp->rx_ring_size);
 574         for (new = 0; new < overlap; new++) {
 575                 new_rx_ring[new] = lp->rx_ring[new];
 576                 new_dma_addr_list[new] = lp->rx_dma_addr[new];
 577                 new_skb_list[new] = lp->rx_skbuff[new];
 578         }
 579         /* now allocate any new buffers needed */
 580         for (; new < size; new++) {
 581                 struct sk_buff *rx_skbuff;
 582                 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB);
 583                 rx_skbuff = new_skb_list[new];
 584                 if (!rx_skbuff) {
 585                         /* keep the original lists and buffers */
 586                         netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
 587                                   __func__);
 588                         goto free_all_new;
 589                 }
 590                 skb_reserve(rx_skbuff, NET_IP_ALIGN);
 591
 592                 new_dma_addr_list[new] =
 593                             pci_map_single(lp->pci_dev, rx_skbuff->data,
 594                                            PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 595                 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
 596                 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
 597                 new_rx_ring[new].status = cpu_to_le16(0x8000);
 598         }
 599         /* and free any unneeded buffers */
 600         for (; new < lp->rx_ring_size; new++) {
 601                 if (lp->rx_skbuff[new]) {
 602                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
 603                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 604                         dev_kfree_skb(lp->rx_skbuff[new]);
 605                 }
 606         }
 607
 608         kfree(lp->rx_skbuff);
 609         kfree(lp->rx_dma_addr);
 610         pci_free_consistent(lp->pci_dev,
 611                             sizeof(struct pcnet32_rx_head) *
 612                             lp->rx_ring_size, lp->rx_ring,
 613                             lp->rx_ring_dma_addr);
 614
 615         lp->rx_ring_size = (1 << size);
 616         lp->rx_mod_mask = lp->rx_ring_size - 1;
 617         lp->rx_len_bits = (size << 4);
 618         lp->rx_ring = new_rx_ring;
 619         lp->rx_ring_dma_addr = new_ring_dma_addr;
 620         lp->rx_dma_addr = new_dma_addr_list;
 621         lp->rx_skbuff = new_skb_list;
 622         return;
 623
 624 free_all_new:
 625         while (--new >= lp->rx_ring_size) {
 626                 if (new_skb_list[new]) {
 627                         pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
 628                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 629                         dev_kfree_skb(new_skb_list[new]);
 630                 }
 631         }
 632         kfree(new_skb_list);
 633 free_new_lists:
 634         kfree(new_dma_addr_list);
 635 free_new_rx_ring:
 636         pci_free_consistent(lp->pci_dev,
 637                             sizeof(struct pcnet32_rx_head) *
 638                             (1 << size),
 639                             new_rx_ring,
 640                             new_ring_dma_addr);
 641 }
 642
 643 static void pcnet32_purge_rx_ring(struct net_device *dev)
 644 {
 645         struct pcnet32_private *lp = netdev_priv(dev);
 646         int i;
 647
 648         /* free all allocated skbuffs */
 649         for (i = 0; i < lp->rx_ring_size; i++) {
 650                 lp->rx_ring[i].status = 0;      /* CPU owns buffer */
 651                 wmb();          /* Make sure adapter sees owner change */
 652                 if (lp->rx_skbuff[i]) {
 653                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
 654                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 655                         dev_kfree_skb_any(lp->rx_skbuff[i]);
 656                 }
 657                 lp->rx_skbuff[i] = NULL;
 658                 lp->rx_dma_addr[i] = 0;
 659         }
 660 }
 661
 662 #ifdef CONFIG_NET_POLL_CONTROLLER
 663 static void pcnet32_poll_controller(struct net_device *dev)
 664 {
 665         disable_irq(dev->irq);
 666         pcnet32_interrupt(0, dev);
 667         enable_irq(dev->irq);
 668 }
 669 #endif
 670
 671 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 672 {
 673         struct pcnet32_private *lp = netdev_priv(dev);
 674         unsigned long flags;
 675         int r = -EOPNOTSUPP;
 676
 677         if (lp->mii) {
 678                 spin_lock_irqsave(&lp->lock, flags);
 679                 mii_ethtool_gset(&lp->mii_if, cmd);
 680                 spin_unlock_irqrestore(&lp->lock, flags);
 681                 r = 0;
 682         }
 683         return r;
 684 }
 685
 686 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 687 {
 688         struct pcnet32_private *lp = netdev_priv(dev);
 689         unsigned long flags;
 690         int r = -EOPNOTSUPP;
 691
 692         if (lp->mii) {
 693                 spin_lock_irqsave(&lp->lock, flags);
 694                 r = mii_ethtool_sset(&lp->mii_if, cmd);
 695                 spin_unlock_irqrestore(&lp->lock, flags);
 696         }
 697         return r;
 698 }
 699
 700 static void pcnet32_get_drvinfo(struct net_device *dev,
 701                                 struct ethtool_drvinfo *info)
 702 {
 703         struct pcnet32_private *lp = netdev_priv(dev);
 704
 705         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
 706         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
 707         if (lp->pci_dev)
 708                 strlcpy(info->bus_info, pci_name(lp->pci_dev),
 709                         sizeof(info->bus_info));
 710         else
 711                 snprintf(info->bus_info, sizeof(info->bus_info),
 712                         "VLB 0x%lx", dev->base_addr);
 713 }
 714
 715 static u32 pcnet32_get_link(struct net_device *dev)
 716 {
 717         struct pcnet32_private *lp = netdev_priv(dev);
 718         unsigned long flags;
 719         int r;
 720
 721         spin_lock_irqsave(&lp->lock, flags);
 722         if (lp->mii) {
 723                 r = mii_link_ok(&lp->mii_if);
 724         } else if (lp->chip_version >= PCNET32_79C970A) {
 725                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
 726                 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
 727         } else {        /* can not detect link on really old chips */
 728                 r = 1;
 729         }
 730         spin_unlock_irqrestore(&lp->lock, flags);
 731
 732         return r;
 733 }
 734
 735 static u32 pcnet32_get_msglevel(struct net_device *dev)
 736 {
 737         struct pcnet32_private *lp = netdev_priv(dev);
 738         return lp->msg_enable;
 739 }
 740
 741 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
 742 {
 743         struct pcnet32_private *lp = netdev_priv(dev);
 744         lp->msg_enable = value;
 745 }
 746
 747 static int pcnet32_nway_reset(struct net_device *dev)
 748 {
 749         struct pcnet32_private *lp = netdev_priv(dev);
 750         unsigned long flags;
 751         int r = -EOPNOTSUPP;
 752
 753         if (lp->mii) {
 754                 spin_lock_irqsave(&lp->lock, flags);
 755                 r = mii_nway_restart(&lp->mii_if);
 756                 spin_unlock_irqrestore(&lp->lock, flags);
 757         }
 758         return r;
 759 }
 760
 761 static void pcnet32_get_ringparam(struct net_device *dev,
 762                                   struct ethtool_ringparam *ering)
 763 {
 764         struct pcnet32_private *lp = netdev_priv(dev);
 765
 766         ering->tx_max_pending = TX_MAX_RING_SIZE;
 767         ering->tx_pending = lp->tx_ring_size;
 768         ering->rx_max_pending = RX_MAX_RING_SIZE;
 769         ering->rx_pending = lp->rx_ring_size;
 770 }
 771
 772 static int pcnet32_set_ringparam(struct net_device *dev,
 773                                  struct ethtool_ringparam *ering)
 774 {
 775         struct pcnet32_private *lp = netdev_priv(dev);
 776         unsigned long flags;
 777         unsigned int size;
 778         ulong ioaddr = dev->base_addr;
 779         int i;
 780
 781         if (ering->rx_mini_pending || ering->rx_jumbo_pending)
 782                 return -EINVAL;
 783
 784         if (netif_running(dev))
 785                 pcnet32_netif_stop(dev);
 786
 787         spin_lock_irqsave(&lp->lock, flags);
 788         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* stop the chip */
 789
 790         size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
 791
 792         /* set the minimum ring size to 4, to allow the loopback test to work
 793          * unchanged.
 794          */
 795         for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
 796                 if (size <= (1 << i))
 797                         break;
 798         }
 799         if ((1 << i) != lp->tx_ring_size)
 800                 pcnet32_realloc_tx_ring(dev, lp, i);
 801
 802         size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
 803         for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
 804                 if (size <= (1 << i))
 805                         break;
 806         }
 807         if ((1 << i) != lp->rx_ring_size)
 808                 pcnet32_realloc_rx_ring(dev, lp, i);
 809
 810         lp->napi.weight = lp->rx_ring_size / 2;
 811
 812         if (netif_running(dev)) {
 813                 pcnet32_netif_start(dev);
 814                 pcnet32_restart(dev, CSR0_NORMAL);
 815         }
 816
 817         spin_unlock_irqrestore(&lp->lock, flags);
 818
 819         netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",
 820                    lp->rx_ring_size, lp->tx_ring_size);
 821
 822         return 0;
 823 }
 824
 825 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
 826                                 u8 *data)
 827 {
 828         memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
 829 }
 830
 831 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
 832 {
 833         switch (sset) {
 834         case ETH_SS_TEST:
 835                 return PCNET32_TEST_LEN;
 836         default:
 837                 return -EOPNOTSUPP;
 838         }
 839 }
 840
 841 static void pcnet32_ethtool_test(struct net_device *dev,
 842                                  struct ethtool_test *test, u64 * data)
 843 {
 844         struct pcnet32_private *lp = netdev_priv(dev);
 845         int rc;
 846
 847         if (test->flags == ETH_TEST_FL_OFFLINE) {
 848                 rc = pcnet32_loopback_test(dev, data);
 849                 if (rc) {
 850                         netif_printk(lp, hw, KERN_DEBUG, dev,
 851                                      "Loopback test failed\n");
 852                         test->flags |= ETH_TEST_FL_FAILED;
 853                 } else
 854                         netif_printk(lp, hw, KERN_DEBUG, dev,
 855                                      "Loopback test passed\n");
 856         } else
 857                 netif_printk(lp, hw, KERN_DEBUG, dev,
 858                              "No tests to run (specify 'Offline' on ethtool)\n");
 859 }                               /* end pcnet32_ethtool_test */
 860
 861 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
 862 {
 863         struct pcnet32_private *lp = netdev_priv(dev);
 864         const struct pcnet32_access *a = lp->a; /* access to registers */
 865         ulong ioaddr = dev->base_addr;  /* card base I/O address */
 866         struct sk_buff *skb;    /* sk buff */
 867         int x, i;               /* counters */
 868         int numbuffs = 4;       /* number of TX/RX buffers and descs */
 869         u16 status = 0x8300;    /* TX ring status */
 870         __le16 teststatus;      /* test of ring status */
 871         int rc;                 /* return code */
 872         int size;               /* size of packets */
 873         unsigned char *packet;  /* source packet data */
 874         static const int data_len = 60; /* length of source packets */
 875         unsigned long flags;
 876         unsigned long ticks;
 877
 878         rc = 1;                 /* default to fail */
 879
 880         if (netif_running(dev))
 881                 pcnet32_netif_stop(dev);
 882
 883         spin_lock_irqsave(&lp->lock, flags);
 884         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* stop the chip */
 885
 886         numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
 887
 888         /* Reset the PCNET32 */
 889         lp->a->reset(ioaddr);
 890         lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
 891
 892         /* switch pcnet32 to 32bit mode */
 893         lp->a->write_bcr(ioaddr, 20, 2);
 894
 895         /* purge & init rings but don't actually restart */
 896         pcnet32_restart(dev, 0x0000);
 897
 898         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* Set STOP bit */
 899
 900         /* Initialize Transmit buffers. */
 901         size = data_len + 15;
 902         for (x = 0; x < numbuffs; x++) {
 903                 skb = netdev_alloc_skb(dev, size);
 904                 if (!skb) {
 905                         netif_printk(lp, hw, KERN_DEBUG, dev,
 906                                      "Cannot allocate skb at line: %d!\n",
 907                                      __LINE__);
 908                         goto clean_up;
 909                 }
 910                 packet = skb->data;
 911                 skb_put(skb, size);     /* create space for data */
 912                 lp->tx_skbuff[x] = skb;
 913                 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
 914                 lp->tx_ring[x].misc = 0;
 915
 916                 /* put DA and SA into the skb */
 917                 for (i = 0; i < 6; i++)
 918                         *packet++ = dev->dev_addr[i];
 919                 for (i = 0; i < 6; i++)
 920                         *packet++ = dev->dev_addr[i];
 921                 /* type */
 922                 *packet++ = 0x08;
 923                 *packet++ = 0x06;
 924                 /* packet number */
 925                 *packet++ = x;
 926                 /* fill packet with data */
 927                 for (i = 0; i < data_len; i++)
 928                         *packet++ = i;
 929
 930                 lp->tx_dma_addr[x] =
 931                         pci_map_single(lp->pci_dev, skb->data, skb->len,
 932                                        PCI_DMA_TODEVICE);
 933                 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
 934                 wmb();  /* Make sure owner changes after all others are visible */
 935                 lp->tx_ring[x].status = cpu_to_le16(status);
 936         }
 937
 938         x = a->read_bcr(ioaddr, 32);    /* set internal loopback in BCR32 */
 939         a->write_bcr(ioaddr, 32, x | 0x0002);
 940
 941         /* set int loopback in CSR15 */
 942         x = a->read_csr(ioaddr, CSR15) & 0xfffc;
 943         lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
 944
 945         teststatus = cpu_to_le16(0x8000);
 946         lp->a->write_csr(ioaddr, CSR0, CSR0_START);     /* Set STRT bit */
 947
 948         /* Check status of descriptors */
 949         for (x = 0; x < numbuffs; x++) {
 950                 ticks = 0;
 951                 rmb();
 952                 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
 953                         spin_unlock_irqrestore(&lp->lock, flags);
 954                         msleep(1);
 955                         spin_lock_irqsave(&lp->lock, flags);
 956                         rmb();
 957                         ticks++;
 958                 }
 959                 if (ticks == 200) {
 960                         netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);
 961                         break;
 962                 }
 963         }
 964
 965         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* Set STOP bit */
 966         wmb();
 967         if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
 968                 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");
 969
 970                 for (x = 0; x < numbuffs; x++) {
 971                         netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);
 972                         skb = lp->rx_skbuff[x];
 973                         for (i = 0; i < size; i++)
 974                                 pr_cont(" %02x", *(skb->data + i));
 975                         pr_cont("\n");
 976                 }
 977         }
 978
 979         x = 0;
 980         rc = 0;
 981         while (x < numbuffs && !rc) {
 982                 skb = lp->rx_skbuff[x];
 983                 packet = lp->tx_skbuff[x]->data;
 984                 for (i = 0; i < size; i++) {
 985                         if (*(skb->data + i) != packet[i]) {
 986                                 netif_printk(lp, hw, KERN_DEBUG, dev,
 987                                              "Error in compare! %2x - %02x %02x\n",
 988                                              i, *(skb->data + i), packet[i]);
 989                                 rc = 1;
 990                                 break;
 991                         }
 992                 }
 993                 x++;
 994         }
 995
 996 clean_up:
 997         *data1 = rc;
 998         pcnet32_purge_tx_ring(dev);
 999
1000         x = a->read_csr(ioaddr, CSR15);
1001         a->write_csr(ioaddr, CSR15, (x & ~0x0044));     /* reset bits 6 and 2 */
1002
1003         x = a->read_bcr(ioaddr, 32);    /* reset internal loopback */
1004         a->write_bcr(ioaddr, 32, (x & ~0x0002));
1005
1006         if (netif_running(dev)) {
1007                 pcnet32_netif_start(dev);
1008                 pcnet32_restart(dev, CSR0_NORMAL);
1009         } else {
1010                 pcnet32_purge_rx_ring(dev);
1011                 lp->a->write_bcr(ioaddr, 20, 4);        /* return to 16bit mode */
1012         }
1013         spin_unlock_irqrestore(&lp->lock, flags);
1014
1015         return rc;
1016 }                               /* end pcnet32_loopback_test  */
1017
1018 static int pcnet32_set_phys_id(struct net_device *dev,
1019                                enum ethtool_phys_id_state state)
1020 {
1021         struct pcnet32_private *lp = netdev_priv(dev);
1022         const struct pcnet32_access *a = lp->a;
1023         ulong ioaddr = dev->base_addr;
1024         unsigned long flags;
1025         int i;
1026
1027         switch (state) {
1028         case ETHTOOL_ID_ACTIVE:
1029                 /* Save the current value of the bcrs */
1030                 spin_lock_irqsave(&lp->lock, flags);
1031                 for (i = 4; i < 8; i++)
1032                         lp->save_regs[i - 4] = a->read_bcr(ioaddr, i);
1033                 spin_unlock_irqrestore(&lp->lock, flags);
1034                 return 2;       /* cycle on/off twice per second */
1035
1036         case ETHTOOL_ID_ON:
1037         case ETHTOOL_ID_OFF:
1038                 /* Blink the led */
1039                 spin_lock_irqsave(&lp->lock, flags);
1040                 for (i = 4; i < 8; i++)
1041                         a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1042                 spin_unlock_irqrestore(&lp->lock, flags);
1043                 break;
1044
1045         case ETHTOOL_ID_INACTIVE:
1046                 /* Restore the original value of the bcrs */
1047                 spin_lock_irqsave(&lp->lock, flags);
1048                 for (i = 4; i < 8; i++)
1049                         a->write_bcr(ioaddr, i, lp->save_regs[i - 4]);
1050                 spin_unlock_irqrestore(&lp->lock, flags);
1051         }
1052         return 0;
1053 }
1054
1055 /*
1056  * lp->lock must be held.
1057  */
1058 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1059                 int can_sleep)
1060 {
1061         int csr5;
1062         struct pcnet32_private *lp = netdev_priv(dev);
1063         const struct pcnet32_access *a = lp->a;
1064         ulong ioaddr = dev->base_addr;
1065         int ticks;
1066
1067         /* really old chips have to be stopped. */
1068         if (lp->chip_version < PCNET32_79C970A)
1069                 return 0;
1070
1071         /* set SUSPEND (SPND) - CSR5 bit 0 */
1072         csr5 = a->read_csr(ioaddr, CSR5);
1073         a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1074
1075         /* poll waiting for bit to be set */
1076         ticks = 0;
1077         while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1078                 spin_unlock_irqrestore(&lp->lock, *flags);
1079                 if (can_sleep)
1080                         msleep(1);
1081                 else
1082                         mdelay(1);
1083                 spin_lock_irqsave(&lp->lock, *flags);
1084                 ticks++;
1085                 if (ticks > 200) {
1086                         netif_printk(lp, hw, KERN_DEBUG, dev,
1087                                      "Error getting into suspend!\n");
1088                         return 0;
1089                 }
1090         }
1091         return 1;
1092 }
1093
1094 /*
1095  * process one receive descriptor entry
1096  */
1097
1098 static void pcnet32_rx_entry(struct net_device *dev,
1099                              struct pcnet32_private *lp,
1100                              struct pcnet32_rx_head *rxp,
1101                              int entry)
1102 {
1103         int status = (short)le16_to_cpu(rxp->status) >> 8;
1104         int rx_in_place = 0;
1105         struct sk_buff *skb;
1106         short pkt_len;
1107
1108         if (status != 0x03) {   /* There was an error. */
1109                 /*
1110                  * There is a tricky error noted by John Murphy,
1111                  * <murf@perftech.com> to Russ Nelson: Even with full-sized
1112                  * buffers it's possible for a jabber packet to use two
1113                  * buffers, with only the last correctly noting the error.
1114                  */
1115                 if (status & 0x01)      /* Only count a general error at the */
1116                         dev->stats.rx_errors++; /* end of a packet. */
1117                 if (status & 0x20)
1118                         dev->stats.rx_frame_errors++;
1119                 if (status & 0x10)
1120                         dev->stats.rx_over_errors++;
1121                 if (status & 0x08)
1122                         dev->stats.rx_crc_errors++;
1123                 if (status & 0x04)
1124                         dev->stats.rx_fifo_errors++;
1125                 return;
1126         }
1127
1128         pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1129
1130         /* Discard oversize frames. */
1131         if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1132                 netif_err(lp, drv, dev, "Impossible packet size %d!\n",
1133                           pkt_len);
1134                 dev->stats.rx_errors++;
1135                 return;
1136         }
1137         if (pkt_len < 60) {
1138                 netif_err(lp, rx_err, dev, "Runt packet!\n");
1139                 dev->stats.rx_errors++;
1140                 return;
1141         }
1142
1143         if (pkt_len > rx_copybreak) {
1144                 struct sk_buff *newskb;
1145
1146                 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB);
1147                 if (newskb) {
1148                         skb_reserve(newskb, NET_IP_ALIGN);
1149                         skb = lp->rx_skbuff[entry];
1150                         pci_unmap_single(lp->pci_dev,
1151                                          lp->rx_dma_addr[entry],
1152                                          PKT_BUF_SIZE,
1153                                          PCI_DMA_FROMDEVICE);
1154                         skb_put(skb, pkt_len);
1155                         lp->rx_skbuff[entry] = newskb;
1156                         lp->rx_dma_addr[entry] =
1157                                             pci_map_single(lp->pci_dev,
1158                                                            newskb->data,
1159                                                            PKT_BUF_SIZE,
1160                                                            PCI_DMA_FROMDEVICE);
1161                         rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
1162                         rx_in_place = 1;
1163                 } else
1164                         skb = NULL;
1165         } else
1166                 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN);
1167
1168         if (skb == NULL) {
1169                 dev->stats.rx_dropped++;
1170                 return;
1171         }
1172         if (!rx_in_place) {
1173                 skb_reserve(skb, NET_IP_ALIGN);
1174                 skb_put(skb, pkt_len);  /* Make room */
1175                 pci_dma_sync_single_for_cpu(lp->pci_dev,
1176                                             lp->rx_dma_addr[entry],
1177                                             pkt_len,
1178                                             PCI_DMA_FROMDEVICE);
1179                 skb_copy_to_linear_data(skb,
1180                                  (unsigned char *)(lp->rx_skbuff[entry]->data),
1181                                  pkt_len);
1182                 pci_dma_sync_single_for_device(lp->pci_dev,
1183                                                lp->rx_dma_addr[entry],
1184                                                pkt_len,
1185                                                PCI_DMA_FROMDEVICE);
1186         }
1187         dev->stats.rx_bytes += skb->len;
1188         skb->protocol = eth_type_trans(skb, dev);
1189         netif_receive_skb(skb);
1190         dev->stats.rx_packets++;
1191 }
1192
1193 static int pcnet32_rx(struct net_device *dev, int budget)
1194 {
1195         struct pcnet32_private *lp = netdev_priv(dev);
1196         int entry = lp->cur_rx & lp->rx_mod_mask;
1197         struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1198         int npackets = 0;
1199
1200         /* If we own the next entry, it's a new packet. Send it up. */
1201         while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1202                 pcnet32_rx_entry(dev, lp, rxp, entry);
1203                 npackets += 1;
1204                 /*
1205                  * The docs say that the buffer length isn't touched, but Andrew
1206                  * Boyd of QNX reports that some revs of the 79C965 clear it.
1207                  */
1208                 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1209                 wmb();  /* Make sure owner changes after others are visible */
1210                 rxp->status = cpu_to_le16(0x8000);
1211                 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1212                 rxp = &lp->rx_ring[entry];
1213         }
1214
1215         return npackets;
1216 }
1217
1218 static int pcnet32_tx(struct net_device *dev)
1219 {
1220         struct pcnet32_private *lp = netdev_priv(dev);
1221         unsigned int dirty_tx = lp->dirty_tx;
1222         int delta;
1223         int must_restart = 0;
1224
1225         while (dirty_tx != lp->cur_tx) {
1226                 int entry = dirty_tx & lp->tx_mod_mask;
1227                 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1228
1229                 if (status < 0)
1230                         break;  /* It still hasn't been Txed */
1231
1232                 lp->tx_ring[entry].base = 0;
1233
1234                 if (status & 0x4000) {
1235                         /* There was a major error, log it. */
1236                         int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1237                         dev->stats.tx_errors++;
1238                         netif_err(lp, tx_err, dev,
1239                                   "Tx error status=%04x err_status=%08x\n",
1240                                   status, err_status);
1241                         if (err_status & 0x04000000)
1242                                 dev->stats.tx_aborted_errors++;
1243                         if (err_status & 0x08000000)
1244                                 dev->stats.tx_carrier_errors++;
1245                         if (err_status & 0x10000000)
1246                                 dev->stats.tx_window_errors++;
1247 #ifndef DO_DXSUFLO
1248                         if (err_status & 0x40000000) {
1249                                 dev->stats.tx_fifo_errors++;
1250                                 /* Ackk!  On FIFO errors the Tx unit is turned off! */
1251                                 /* Remove this verbosity later! */
1252                                 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1253                                 must_restart = 1;
1254                         }
1255 #else
1256                         if (err_status & 0x40000000) {
1257                                 dev->stats.tx_fifo_errors++;
1258                                 if (!lp->dxsuflo) {     /* If controller doesn't recover ... */
1259                                         /* Ackk!  On FIFO errors the Tx unit is turned off! */
1260                                         /* Remove this verbosity later! */
1261                                         netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1262                                         must_restart = 1;
1263                                 }
1264                         }
1265 #endif
1266                 } else {
1267                         if (status & 0x1800)
1268                                 dev->stats.collisions++;
1269                         dev->stats.tx_packets++;
1270                 }
1271
1272                 /* We must free the original skb */
1273                 if (lp->tx_skbuff[entry]) {
1274                         pci_unmap_single(lp->pci_dev,
1275                                          lp->tx_dma_addr[entry],
1276                                          lp->tx_skbuff[entry]->
1277                                          len, PCI_DMA_TODEVICE);
1278                         dev_kfree_skb_any(lp->tx_skbuff[entry]);
1279                         lp->tx_skbuff[entry] = NULL;
1280                         lp->tx_dma_addr[entry] = 0;
1281                 }
1282                 dirty_tx++;
1283         }
1284
1285         delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1286         if (delta > lp->tx_ring_size) {
1287                 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1288                           dirty_tx, lp->cur_tx, lp->tx_full);
1289                 dirty_tx += lp->tx_ring_size;
1290                 delta -= lp->tx_ring_size;
1291         }
1292
1293         if (lp->tx_full &&
1294             netif_queue_stopped(dev) &&
1295             delta < lp->tx_ring_size - 2) {
1296                 /* The ring is no longer full, clear tbusy. */
1297                 lp->tx_full = 0;
1298                 netif_wake_queue(dev);
1299         }
1300         lp->dirty_tx = dirty_tx;
1301
1302         return must_restart;
1303 }
1304
1305 static int pcnet32_poll(struct napi_struct *napi, int budget)
1306 {
1307         struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1308         struct net_device *dev = lp->dev;
1309         unsigned long ioaddr = dev->base_addr;
1310         unsigned long flags;
1311         int work_done;
1312         u16 val;
1313
1314         work_done = pcnet32_rx(dev, budget);
1315
1316         spin_lock_irqsave(&lp->lock, flags);
1317         if (pcnet32_tx(dev)) {
1318                 /* reset the chip to clear the error condition, then restart */
1319                 lp->a->reset(ioaddr);
1320                 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1321                 pcnet32_restart(dev, CSR0_START);
1322                 netif_wake_queue(dev);
1323         }
1324         spin_unlock_irqrestore(&lp->lock, flags);
1325
1326         if (work_done < budget) {
1327                 spin_lock_irqsave(&lp->lock, flags);
1328
1329                 __napi_complete(napi);
1330
1331                 /* clear interrupt masks */
1332                 val = lp->a->read_csr(ioaddr, CSR3);
1333                 val &= 0x00ff;
1334                 lp->a->write_csr(ioaddr, CSR3, val);
1335
1336                 /* Set interrupt enable. */
1337                 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
1338
1339                 spin_unlock_irqrestore(&lp->lock, flags);
1340         }
1341         return work_done;
1342 }
1343
1344 #define PCNET32_REGS_PER_PHY    32
1345 #define PCNET32_MAX_PHYS        32
1346 static int pcnet32_get_regs_len(struct net_device *dev)
1347 {
1348         struct pcnet32_private *lp = netdev_priv(dev);
1349         int j = lp->phycount * PCNET32_REGS_PER_PHY;
1350
1351         return (PCNET32_NUM_REGS + j) * sizeof(u16);
1352 }
1353
1354 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1355                              void *ptr)
1356 {
1357         int i, csr0;
1358         u16 *buff = ptr;
1359         struct pcnet32_private *lp = netdev_priv(dev);
1360         const struct pcnet32_access *a = lp->a;
1361         ulong ioaddr = dev->base_addr;
1362         unsigned long flags;
1363
1364         spin_lock_irqsave(&lp->lock, flags);
1365
1366         csr0 = a->read_csr(ioaddr, CSR0);
1367         if (!(csr0 & CSR0_STOP))        /* If not stopped */
1368                 pcnet32_suspend(dev, &flags, 1);
1369
1370         /* read address PROM */
1371         for (i = 0; i < 16; i += 2)
1372                 *buff++ = inw(ioaddr + i);
1373
1374         /* read control and status registers */
1375         for (i = 0; i < 90; i++)
1376                 *buff++ = a->read_csr(ioaddr, i);
1377
1378         *buff++ = a->read_csr(ioaddr, 112);
1379         *buff++ = a->read_csr(ioaddr, 114);
1380
1381         /* read bus configuration registers */
1382         for (i = 0; i < 30; i++)
1383                 *buff++ = a->read_bcr(ioaddr, i);
1384
1385         *buff++ = 0;            /* skip bcr30 so as not to hang 79C976 */
1386
1387         for (i = 31; i < 36; i++)
1388                 *buff++ = a->read_bcr(ioaddr, i);
1389
1390         /* read mii phy registers */
1391         if (lp->mii) {
1392                 int j;
1393                 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1394                         if (lp->phymask & (1 << j)) {
1395                                 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1396                                         lp->a->write_bcr(ioaddr, 33,
1397                                                         (j << 5) | i);
1398                                         *buff++ = lp->a->read_bcr(ioaddr, 34);
1399                                 }
1400                         }
1401                 }
1402         }
1403
1404         if (!(csr0 & CSR0_STOP)) {      /* If not stopped */
1405                 int csr5;
1406
1407                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1408                 csr5 = a->read_csr(ioaddr, CSR5);
1409                 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1410         }
1411
1412         spin_unlock_irqrestore(&lp->lock, flags);
1413 }
1414
1415 static const struct ethtool_ops pcnet32_ethtool_ops = {
1416         .get_settings           = pcnet32_get_settings,
1417         .set_settings           = pcnet32_set_settings,
1418         .get_drvinfo            = pcnet32_get_drvinfo,
1419         .get_msglevel           = pcnet32_get_msglevel,
1420         .set_msglevel           = pcnet32_set_msglevel,
1421         .nway_reset             = pcnet32_nway_reset,
1422         .get_link               = pcnet32_get_link,
1423         .get_ringparam          = pcnet32_get_ringparam,
1424         .set_ringparam          = pcnet32_set_ringparam,
1425         .get_strings            = pcnet32_get_strings,
1426         .self_test              = pcnet32_ethtool_test,
1427         .set_phys_id            = pcnet32_set_phys_id,
1428         .get_regs_len           = pcnet32_get_regs_len,
1429         .get_regs               = pcnet32_get_regs,
1430         .get_sset_count         = pcnet32_get_sset_count,
1431 };
1432
1433 /* only probes for non-PCI devices, the rest are handled by
1434  * pci_register_driver via pcnet32_probe_pci */
1435
1436 static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1437 {
1438         unsigned int *port, ioaddr;
1439
1440         /* search for PCnet32 VLB cards at known addresses */
1441         for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1442                 if (request_region
1443                     (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1444                         /* check if there is really a pcnet chip on that ioaddr */
1445                         if ((inb(ioaddr + 14) == 0x57) &&
1446                             (inb(ioaddr + 15) == 0x57)) {
1447                                 pcnet32_probe1(ioaddr, 0, NULL);
1448                         } else {
1449                                 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1450                         }
1451                 }
1452         }
1453 }
1454
1455 static int
1456 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1457 {
1458         unsigned long ioaddr;
1459         int err;
1460
1461         err = pci_enable_device(pdev);
1462         if (err < 0) {
1463                 if (pcnet32_debug & NETIF_MSG_PROBE)
1464                         pr_err("failed to enable device -- err=%d\n", err);
1465                 return err;
1466         }
1467         pci_set_master(pdev);
1468
1469         ioaddr = pci_resource_start(pdev, 0);
1470         if (!ioaddr) {
1471                 if (pcnet32_debug & NETIF_MSG_PROBE)
1472                         pr_err("card has no PCI IO resources, aborting\n");
1473                 return -ENODEV;
1474         }
1475
1476         if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1477                 if (pcnet32_debug & NETIF_MSG_PROBE)
1478                         pr_err("architecture does not support 32bit PCI busmaster DMA\n");
1479                 return -ENODEV;
1480         }
1481         if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) {
1482                 if (pcnet32_debug & NETIF_MSG_PROBE)
1483                         pr_err("io address range already allocated\n");
1484                 return -EBUSY;
1485         }
1486
1487         err = pcnet32_probe1(ioaddr, 1, pdev);
1488         if (err < 0)
1489                 pci_disable_device(pdev);
1490
1491         return err;
1492 }
1493
1494 static const struct net_device_ops pcnet32_netdev_ops = {
1495         .ndo_open               = pcnet32_open,
1496         .ndo_stop               = pcnet32_close,
1497         .ndo_start_xmit         = pcnet32_start_xmit,
1498         .ndo_tx_timeout         = pcnet32_tx_timeout,
1499         .ndo_get_stats          = pcnet32_get_stats,
1500         .ndo_set_rx_mode        = pcnet32_set_multicast_list,
1501         .ndo_do_ioctl           = pcnet32_ioctl,
1502         .ndo_change_mtu         = eth_change_mtu,
1503         .ndo_set_mac_address    = eth_mac_addr,
1504         .ndo_validate_addr      = eth_validate_addr,
1505 #ifdef CONFIG_NET_POLL_CONTROLLER
1506         .ndo_poll_controller    = pcnet32_poll_controller,
1507 #endif
1508 };
1509
1510 /* pcnet32_probe1
1511  *  Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1512  *  pdev will be NULL when called from pcnet32_probe_vlbus.
1513  */
1514 static int
1515 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1516 {
1517         struct pcnet32_private *lp;
1518         int i, media;
1519         int fdx, mii, fset, dxsuflo;
1520         int chip_version;
1521         char *chipname;
1522         struct net_device *dev;
1523         const struct pcnet32_access *a = NULL;
1524         u8 promaddr[ETH_ALEN];
1525         int ret = -ENODEV;
1526
1527         /* reset the chip */
1528         pcnet32_wio_reset(ioaddr);
1529
1530         /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1531         if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1532                 a = &pcnet32_wio;
1533         } else {
1534                 pcnet32_dwio_reset(ioaddr);
1535                 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1536                     pcnet32_dwio_check(ioaddr)) {
1537                         a = &pcnet32_dwio;
1538                 } else {
1539                         if (pcnet32_debug & NETIF_MSG_PROBE)
1540                                 pr_err("No access methods\n");
1541                         goto err_release_region;
1542                 }
1543         }
1544
1545         chip_version =
1546             a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1547         if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1548                 pr_info("  PCnet chip version is %#x\n", chip_version);
1549         if ((chip_version & 0xfff) != 0x003) {
1550                 if (pcnet32_debug & NETIF_MSG_PROBE)
1551                         pr_info("Unsupported chip version\n");
1552                 goto err_release_region;
1553         }
1554
1555         /* initialize variables */
1556         fdx = mii = fset = dxsuflo = 0;
1557         chip_version = (chip_version >> 12) & 0xffff;
1558
1559         switch (chip_version) {
1560         case 0x2420:
1561                 chipname = "PCnet/PCI 79C970";  /* PCI */
1562                 break;
1563         case 0x2430:
1564                 if (shared)
1565                         chipname = "PCnet/PCI 79C970";  /* 970 gives the wrong chip id back */
1566                 else
1567                         chipname = "PCnet/32 79C965";   /* 486/VL bus */
1568                 break;
1569         case 0x2621:
1570                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
1571                 fdx = 1;
1572                 break;
1573         case 0x2623:
1574                 chipname = "PCnet/FAST 79C971"; /* PCI */
1575                 fdx = 1;
1576                 mii = 1;
1577                 fset = 1;
1578                 break;
1579         case 0x2624:
1580                 chipname = "PCnet/FAST+ 79C972";        /* PCI */
1581                 fdx = 1;
1582                 mii = 1;
1583                 fset = 1;
1584                 break;
1585         case 0x2625:
1586                 chipname = "PCnet/FAST III 79C973";     /* PCI */
1587                 fdx = 1;
1588                 mii = 1;
1589                 break;
1590         case 0x2626:
1591                 chipname = "PCnet/Home 79C978"; /* PCI */
1592                 fdx = 1;
1593                 /*
1594                  * This is based on specs published at www.amd.com.  This section
1595                  * assumes that a card with a 79C978 wants to go into standard
1596                  * ethernet mode.  The 79C978 can also go into 1Mb HomePNA mode,
1597                  * and the module option homepna=1 can select this instead.
1598                  */
1599                 media = a->read_bcr(ioaddr, 49);
1600                 media &= ~3;    /* default to 10Mb ethernet */
1601                 if (cards_found < MAX_UNITS && homepna[cards_found])
1602                         media |= 1;     /* switch to home wiring mode */
1603                 if (pcnet32_debug & NETIF_MSG_PROBE)
1604                         printk(KERN_DEBUG PFX "media set to %sMbit mode\n",
1605                                (media & 1) ? "1" : "10");
1606                 a->write_bcr(ioaddr, 49, media);
1607                 break;
1608         case 0x2627:
1609                 chipname = "PCnet/FAST III 79C975";     /* PCI */
1610                 fdx = 1;
1611                 mii = 1;
1612                 break;
1613         case 0x2628:
1614                 chipname = "PCnet/PRO 79C976";
1615                 fdx = 1;
1616                 mii = 1;
1617                 break;
1618         default:
1619                 if (pcnet32_debug & NETIF_MSG_PROBE)
1620                         pr_info("PCnet version %#x, no PCnet32 chip\n",
1621                                 chip_version);
1622                 goto err_release_region;
1623         }
1624
1625         /*
1626          *  On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1627          *  starting until the packet is loaded. Strike one for reliability, lose
1628          *  one for latency - although on PCI this isn't a big loss. Older chips
1629          *  have FIFO's smaller than a packet, so you can't do this.
1630          *  Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1631          */
1632
1633         if (fset) {
1634                 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1635                 a->write_csr(ioaddr, 80,
1636                              (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1637                 dxsuflo = 1;
1638         }
1639
1640         dev = alloc_etherdev(sizeof(*lp));
1641         if (!dev) {
1642                 ret = -ENOMEM;
1643                 goto err_release_region;
1644         }
1645
1646         if (pdev)
1647                 SET_NETDEV_DEV(dev, &pdev->dev);
1648
1649         if (pcnet32_debug & NETIF_MSG_PROBE)
1650                 pr_info("%s at %#3lx,", chipname, ioaddr);
1651
1652         /* In most chips, after a chip reset, the ethernet address is read from the
1653          * station address PROM at the base address and programmed into the
1654          * "Physical Address Registers" CSR12-14.
1655          * As a precautionary measure, we read the PROM values and complain if
1656          * they disagree with the CSRs.  If they miscompare, and the PROM addr
1657          * is valid, then the PROM addr is used.
1658          */
1659         for (i = 0; i < 3; i++) {
1660                 unsigned int val;
1661                 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1662                 /* There may be endianness issues here. */
1663                 dev->dev_addr[2 * i] = val & 0x0ff;
1664                 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1665         }
1666
1667         /* read PROM address and compare with CSR address */
1668         for (i = 0; i < ETH_ALEN; i++)
1669                 promaddr[i] = inb(ioaddr + i);
1670
1671         if (memcmp(promaddr, dev->dev_addr, ETH_ALEN) ||
1672             !is_valid_ether_addr(dev->dev_addr)) {
1673                 if (is_valid_ether_addr(promaddr)) {
1674                         if (pcnet32_debug & NETIF_MSG_PROBE) {
1675                                 pr_cont(" warning: CSR address invalid,\n");
1676                                 pr_info("    using instead PROM address of");
1677                         }
1678                         memcpy(dev->dev_addr, promaddr, ETH_ALEN);
1679                 }
1680         }
1681
1682         /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1683         if (!is_valid_ether_addr(dev->dev_addr))
1684                 memset(dev->dev_addr, 0, ETH_ALEN);
1685
1686         if (pcnet32_debug & NETIF_MSG_PROBE) {
1687                 pr_cont(" %pM", dev->dev_addr);
1688
1689                 /* Version 0x2623 and 0x2624 */
1690                 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1691                         i = a->read_csr(ioaddr, 80) & 0x0C00;   /* Check tx_start_pt */
1692                         pr_info("    tx_start_pt(0x%04x):", i);
1693                         switch (i >> 10) {
1694                         case 0:
1695                                 pr_cont("  20 bytes,");
1696                                 break;
1697                         case 1:
1698                                 pr_cont("  64 bytes,");
1699                                 break;
1700                         case 2:
1701                                 pr_cont(" 128 bytes,");
1702                                 break;
1703                         case 3:
1704                                 pr_cont("~220 bytes,");
1705                                 break;
1706                         }
1707                         i = a->read_bcr(ioaddr, 18);    /* Check Burst/Bus control */
1708                         pr_cont(" BCR18(%x):", i & 0xffff);
1709                         if (i & (1 << 5))
1710                                 pr_cont("BurstWrEn ");
1711                         if (i & (1 << 6))
1712                                 pr_cont("BurstRdEn ");
1713                         if (i & (1 << 7))
1714                                 pr_cont("DWordIO ");
1715                         if (i & (1 << 11))
1716                                 pr_cont("NoUFlow ");
1717                         i = a->read_bcr(ioaddr, 25);
1718                         pr_info("    SRAMSIZE=0x%04x,", i << 8);
1719                         i = a->read_bcr(ioaddr, 26);
1720                         pr_cont(" SRAM_BND=0x%04x,", i << 8);
1721                         i = a->read_bcr(ioaddr, 27);
1722                         if (i & (1 << 14))
1723                                 pr_cont("LowLatRx");
1724                 }
1725         }
1726
1727         dev->base_addr = ioaddr;
1728         lp = netdev_priv(dev);
1729         /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1730         lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block),
1731                                               &lp->init_dma_addr);
1732         if (!lp->init_block) {
1733                 if (pcnet32_debug & NETIF_MSG_PROBE)
1734                         pr_err("Consistent memory allocation failed\n");
1735                 ret = -ENOMEM;
1736                 goto err_free_netdev;
1737         }
1738         lp->pci_dev = pdev;
1739
1740         lp->dev = dev;
1741
1742         spin_lock_init(&lp->lock);
1743
1744         lp->name = chipname;
1745         lp->shared_irq = shared;
1746         lp->tx_ring_size = TX_RING_SIZE;        /* default tx ring size */
1747         lp->rx_ring_size = RX_RING_SIZE;        /* default rx ring size */
1748         lp->tx_mod_mask = lp->tx_ring_size - 1;
1749         lp->rx_mod_mask = lp->rx_ring_size - 1;
1750         lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1751         lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1752         lp->mii_if.full_duplex = fdx;
1753         lp->mii_if.phy_id_mask = 0x1f;
1754         lp->mii_if.reg_num_mask = 0x1f;
1755         lp->dxsuflo = dxsuflo;
1756         lp->mii = mii;
1757         lp->chip_version = chip_version;
1758         lp->msg_enable = pcnet32_debug;
1759         if ((cards_found >= MAX_UNITS) ||
1760             (options[cards_found] >= sizeof(options_mapping)))
1761                 lp->options = PCNET32_PORT_ASEL;
1762         else
1763                 lp->options = options_mapping[options[cards_found]];
1764         lp->mii_if.dev = dev;
1765         lp->mii_if.mdio_read = mdio_read;
1766         lp->mii_if.mdio_write = mdio_write;
1767
1768         /* napi.weight is used in both the napi and non-napi cases */
1769         lp->napi.weight = lp->rx_ring_size / 2;
1770
1771         netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1772
1773         if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1774             ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1775                 lp->options |= PCNET32_PORT_FD;
1776
1777         lp->a = a;
1778
1779         /* prior to register_netdev, dev->name is not yet correct */
1780         if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1781                 ret = -ENOMEM;
1782                 goto err_free_ring;
1783         }
1784         /* detect special T1/E1 WAN card by checking for MAC address */
1785         if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1786             dev->dev_addr[2] == 0x75)
1787                 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1788
1789         lp->init_block->mode = cpu_to_le16(0x0003);     /* Disable Rx and Tx. */
1790         lp->init_block->tlen_rlen =
1791             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1792         for (i = 0; i < 6; i++)
1793                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1794         lp->init_block->filter[0] = 0x00000000;
1795         lp->init_block->filter[1] = 0x00000000;
1796         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1797         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1798
1799         /* switch pcnet32 to 32bit mode */
1800         a->write_bcr(ioaddr, 20, 2);
1801
1802         a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1803         a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1804
1805         if (pdev) {             /* use the IRQ provided by PCI */
1806                 dev->irq = pdev->irq;
1807                 if (pcnet32_debug & NETIF_MSG_PROBE)
1808                         pr_cont(" assigned IRQ %d\n", dev->irq);
1809         } else {
1810                 unsigned long irq_mask = probe_irq_on();
1811
1812                 /*
1813                  * To auto-IRQ we enable the initialization-done and DMA error
1814                  * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1815                  * boards will work.
1816                  */
1817                 /* Trigger an initialization just for the interrupt. */
1818                 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1819                 mdelay(1);
1820
1821                 dev->irq = probe_irq_off(irq_mask);
1822                 if (!dev->irq) {
1823                         if (pcnet32_debug & NETIF_MSG_PROBE)
1824                                 pr_cont(", failed to detect IRQ line\n");
1825                         ret = -ENODEV;
1826                         goto err_free_ring;
1827                 }
1828                 if (pcnet32_debug & NETIF_MSG_PROBE)
1829                         pr_cont(", probed IRQ %d\n", dev->irq);
1830         }
1831
1832         /* Set the mii phy_id so that we can query the link state */
1833         if (lp->mii) {
1834                 /* lp->phycount and lp->phymask are set to 0 by memset above */
1835
1836                 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1837                 /* scan for PHYs */
1838                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1839                         unsigned short id1, id2;
1840
1841                         id1 = mdio_read(dev, i, MII_PHYSID1);
1842                         if (id1 == 0xffff)
1843                                 continue;
1844                         id2 = mdio_read(dev, i, MII_PHYSID2);
1845                         if (id2 == 0xffff)
1846                                 continue;
1847                         if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1848                                 continue;       /* 79C971 & 79C972 have phantom phy at id 31 */
1849                         lp->phycount++;
1850                         lp->phymask |= (1 << i);
1851                         lp->mii_if.phy_id = i;
1852                         if (pcnet32_debug & NETIF_MSG_PROBE)
1853                                 pr_info("Found PHY %04x:%04x at address %d\n",
1854                                         id1, id2, i);
1855                 }
1856                 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1857                 if (lp->phycount > 1)
1858                         lp->options |= PCNET32_PORT_MII;
1859         }
1860
1861         init_timer(&lp->watchdog_timer);
1862         lp->watchdog_timer.data = (unsigned long)dev;
1863         lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1864
1865         /* The PCNET32-specific entries in the device structure. */
1866         dev->netdev_ops = &pcnet32_netdev_ops;
1867         dev->ethtool_ops = &pcnet32_ethtool_ops;
1868         dev->watchdog_timeo = (5 * HZ);
1869
1870         /* Fill in the generic fields of the device structure. */
1871         if (register_netdev(dev))
1872                 goto err_free_ring;
1873
1874         if (pdev) {
1875                 pci_set_drvdata(pdev, dev);
1876         } else {
1877                 lp->next = pcnet32_dev;
1878                 pcnet32_dev = dev;
1879         }
1880
1881         if (pcnet32_debug & NETIF_MSG_PROBE)
1882                 pr_info("%s: registered as %s\n", dev->name, lp->name);
1883         cards_found++;
1884
1885         /* enable LED writes */
1886         a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1887
1888         return 0;
1889
1890 err_free_ring:
1891         pcnet32_free_ring(dev);
1892         pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
1893                             lp->init_block, lp->init_dma_addr);
1894 err_free_netdev:
1895         free_netdev(dev);
1896 err_release_region:
1897         release_region(ioaddr, PCNET32_TOTAL_SIZE);
1898         return ret;
1899 }
1900
1901 /* if any allocation fails, caller must also call pcnet32_free_ring */
1902 static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
1903 {
1904         struct pcnet32_private *lp = netdev_priv(dev);
1905
1906         lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1907                                            sizeof(struct pcnet32_tx_head) *
1908                                            lp->tx_ring_size,
1909                                            &lp->tx_ring_dma_addr);
1910         if (lp->tx_ring == NULL) {
1911                 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
1912                 return -ENOMEM;
1913         }
1914
1915         lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1916                                            sizeof(struct pcnet32_rx_head) *
1917                                            lp->rx_ring_size,
1918                                            &lp->rx_ring_dma_addr);
1919         if (lp->rx_ring == NULL) {
1920                 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
1921                 return -ENOMEM;
1922         }
1923
1924         lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
1925                                   GFP_ATOMIC);
1926         if (!lp->tx_dma_addr)
1927                 return -ENOMEM;
1928
1929         lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
1930                                   GFP_ATOMIC);
1931         if (!lp->rx_dma_addr)
1932                 return -ENOMEM;
1933
1934         lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
1935                                 GFP_ATOMIC);
1936         if (!lp->tx_skbuff)
1937                 return -ENOMEM;
1938
1939         lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
1940                                 GFP_ATOMIC);
1941         if (!lp->rx_skbuff)
1942                 return -ENOMEM;
1943
1944         return 0;
1945 }
1946
1947 static void pcnet32_free_ring(struct net_device *dev)
1948 {
1949         struct pcnet32_private *lp = netdev_priv(dev);
1950
1951         kfree(lp->tx_skbuff);
1952         lp->tx_skbuff = NULL;
1953
1954         kfree(lp->rx_skbuff);
1955         lp->rx_skbuff = NULL;
1956
1957         kfree(lp->tx_dma_addr);
1958         lp->tx_dma_addr = NULL;
1959
1960         kfree(lp->rx_dma_addr);
1961         lp->rx_dma_addr = NULL;
1962
1963         if (lp->tx_ring) {
1964                 pci_free_consistent(lp->pci_dev,
1965                                     sizeof(struct pcnet32_tx_head) *
1966                                     lp->tx_ring_size, lp->tx_ring,
1967                                     lp->tx_ring_dma_addr);
1968                 lp->tx_ring = NULL;
1969         }
1970
1971         if (lp->rx_ring) {
1972                 pci_free_consistent(lp->pci_dev,
1973                                     sizeof(struct pcnet32_rx_head) *
1974                                     lp->rx_ring_size, lp->rx_ring,
1975                                     lp->rx_ring_dma_addr);
1976                 lp->rx_ring = NULL;
1977         }
1978 }
1979
1980 static int pcnet32_open(struct net_device *dev)
1981 {
1982         struct pcnet32_private *lp = netdev_priv(dev);
1983         struct pci_dev *pdev = lp->pci_dev;
1984         unsigned long ioaddr = dev->base_addr;
1985         u16 val;
1986         int i;
1987         int rc;
1988         unsigned long flags;
1989
1990         if (request_irq(dev->irq, pcnet32_interrupt,
1991                         lp->shared_irq ? IRQF_SHARED : 0, dev->name,
1992                         (void *)dev)) {
1993                 return -EAGAIN;
1994         }
1995
1996         spin_lock_irqsave(&lp->lock, flags);
1997         /* Check for a valid station address */
1998         if (!is_valid_ether_addr(dev->dev_addr)) {
1999                 rc = -EINVAL;
2000                 goto err_free_irq;
2001         }
2002
2003         /* Reset the PCNET32 */
2004         lp->a->reset(ioaddr);
2005
2006         /* switch pcnet32 to 32bit mode */
2007         lp->a->write_bcr(ioaddr, 20, 2);
2008
2009         netif_printk(lp, ifup, KERN_DEBUG, dev,
2010                      "%s() irq %d tx/rx rings %#x/%#x init %#x\n",
2011                      __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),
2012                      (u32) (lp->rx_ring_dma_addr),
2013                      (u32) (lp->init_dma_addr));
2014
2015         /* set/reset autoselect bit */
2016         val = lp->a->read_bcr(ioaddr, 2) & ~2;
2017         if (lp->options & PCNET32_PORT_ASEL)
2018                 val |= 2;
2019         lp->a->write_bcr(ioaddr, 2, val);
2020
2021         /* handle full duplex setting */
2022         if (lp->mii_if.full_duplex) {
2023                 val = lp->a->read_bcr(ioaddr, 9) & ~3;
2024                 if (lp->options & PCNET32_PORT_FD) {
2025                         val |= 1;
2026                         if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2027                                 val |= 2;
2028                 } else if (lp->options & PCNET32_PORT_ASEL) {
2029                         /* workaround of xSeries250, turn on for 79C975 only */
2030                         if (lp->chip_version == 0x2627)
2031                                 val |= 3;
2032                 }
2033                 lp->a->write_bcr(ioaddr, 9, val);
2034         }
2035
2036         /* set/reset GPSI bit in test register */
2037         val = lp->a->read_csr(ioaddr, 124) & ~0x10;
2038         if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2039                 val |= 0x10;
2040         lp->a->write_csr(ioaddr, 124, val);
2041
2042         /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2043         if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2044             (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2045              pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2046                 if (lp->options & PCNET32_PORT_ASEL) {
2047                         lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2048                         netif_printk(lp, link, KERN_DEBUG, dev,
2049                                      "Setting 100Mb-Full Duplex\n");
2050                 }
2051         }
2052         if (lp->phycount < 2) {
2053                 /*
2054                  * 24 Jun 2004 according AMD, in order to change the PHY,
2055                  * DANAS (or DISPM for 79C976) must be set; then select the speed,
2056                  * duplex, and/or enable auto negotiation, and clear DANAS
2057                  */
2058                 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2059                         lp->a->write_bcr(ioaddr, 32,
2060                                         lp->a->read_bcr(ioaddr, 32) | 0x0080);
2061                         /* disable Auto Negotiation, set 10Mpbs, HD */
2062                         val = lp->a->read_bcr(ioaddr, 32) & ~0xb8;
2063                         if (lp->options & PCNET32_PORT_FD)
2064                                 val |= 0x10;
2065                         if (lp->options & PCNET32_PORT_100)
2066                                 val |= 0x08;
2067                         lp->a->write_bcr(ioaddr, 32, val);
2068                 } else {
2069                         if (lp->options & PCNET32_PORT_ASEL) {
2070                                 lp->a->write_bcr(ioaddr, 32,
2071                                                 lp->a->read_bcr(ioaddr,
2072                                                                32) | 0x0080);
2073                                 /* enable auto negotiate, setup, disable fd */
2074                                 val = lp->a->read_bcr(ioaddr, 32) & ~0x98;
2075                                 val |= 0x20;
2076                                 lp->a->write_bcr(ioaddr, 32, val);
2077                         }
2078                 }
2079         } else {
2080                 int first_phy = -1;
2081                 u16 bmcr;
2082                 u32 bcr9;
2083                 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
2084
2085                 /*
2086                  * There is really no good other way to handle multiple PHYs
2087                  * other than turning off all automatics
2088                  */
2089                 val = lp->a->read_bcr(ioaddr, 2);
2090                 lp->a->write_bcr(ioaddr, 2, val & ~2);
2091                 val = lp->a->read_bcr(ioaddr, 32);
2092                 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7));  /* stop MII manager */
2093
2094                 if (!(lp->options & PCNET32_PORT_ASEL)) {
2095                         /* setup ecmd */
2096                         ecmd.port = PORT_MII;
2097                         ecmd.transceiver = XCVR_INTERNAL;
2098                         ecmd.autoneg = AUTONEG_DISABLE;
2099                         ethtool_cmd_speed_set(&ecmd,
2100                                               (lp->options & PCNET32_PORT_100) ?
2101                                               SPEED_100 : SPEED_10);
2102                         bcr9 = lp->a->read_bcr(ioaddr, 9);
2103
2104                         if (lp->options & PCNET32_PORT_FD) {
2105                                 ecmd.duplex = DUPLEX_FULL;
2106                                 bcr9 |= (1 << 0);
2107                         } else {
2108                                 ecmd.duplex = DUPLEX_HALF;
2109                                 bcr9 |= ~(1 << 0);
2110                         }
2111                         lp->a->write_bcr(ioaddr, 9, bcr9);
2112                 }
2113
2114                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2115                         if (lp->phymask & (1 << i)) {
2116                                 /* isolate all but the first PHY */
2117                                 bmcr = mdio_read(dev, i, MII_BMCR);
2118                                 if (first_phy == -1) {
2119                                         first_phy = i;
2120                                         mdio_write(dev, i, MII_BMCR,
2121                                                    bmcr & ~BMCR_ISOLATE);
2122                                 } else {
2123                                         mdio_write(dev, i, MII_BMCR,
2124                                                    bmcr | BMCR_ISOLATE);
2125                                 }
2126                                 /* use mii_ethtool_sset to setup PHY */
2127                                 lp->mii_if.phy_id = i;
2128                                 ecmd.phy_address = i;
2129                                 if (lp->options & PCNET32_PORT_ASEL) {
2130                                         mii_ethtool_gset(&lp->mii_if, &ecmd);
2131                                         ecmd.autoneg = AUTONEG_ENABLE;
2132                                 }
2133                                 mii_ethtool_sset(&lp->mii_if, &ecmd);
2134                         }
2135                 }
2136                 lp->mii_if.phy_id = first_phy;
2137                 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);
2138         }
2139
2140 #ifdef DO_DXSUFLO
2141         if (lp->dxsuflo) {      /* Disable transmit stop on underflow */
2142                 val = lp->a->read_csr(ioaddr, CSR3);
2143                 val |= 0x40;
2144                 lp->a->write_csr(ioaddr, CSR3, val);
2145         }
2146 #endif
2147
2148         lp->init_block->mode =
2149             cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2150         pcnet32_load_multicast(dev);
2151
2152         if (pcnet32_init_ring(dev)) {
2153                 rc = -ENOMEM;
2154                 goto err_free_ring;
2155         }
2156
2157         napi_enable(&lp->napi);
2158
2159         /* Re-initialize the PCNET32, and start it when done. */
2160         lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2161         lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2162
2163         lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2164         lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2165
2166         netif_start_queue(dev);
2167
2168         if (lp->chip_version >= PCNET32_79C970A) {
2169                 /* Print the link status and start the watchdog */
2170                 pcnet32_check_media(dev, 1);
2171                 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
2172         }
2173
2174         i = 0;
2175         while (i++ < 100)
2176                 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2177                         break;
2178         /*
2179          * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2180          * reports that doing so triggers a bug in the '974.
2181          */
2182         lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
2183
2184         netif_printk(lp, ifup, KERN_DEBUG, dev,
2185                      "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",
2186                      i,
2187                      (u32) (lp->init_dma_addr),
2188                      lp->a->read_csr(ioaddr, CSR0));
2189
2190         spin_unlock_irqrestore(&lp->lock, flags);
2191
2192         return 0;               /* Always succeed */
2193
2194 err_free_ring:
2195         /* free any allocated skbuffs */
2196         pcnet32_purge_rx_ring(dev);
2197
2198         /*
2199          * Switch back to 16bit mode to avoid problems with dumb
2200          * DOS packet driver after a warm reboot
2201          */
2202         lp->a->write_bcr(ioaddr, 20, 4);
2203
2204 err_free_irq:
2205         spin_unlock_irqrestore(&lp->lock, flags);
2206         free_irq(dev->irq, dev);
2207         return rc;
2208 }
2209
2210 /*
2211  * The LANCE has been halted for one reason or another (busmaster memory
2212  * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2213  * etc.).  Modern LANCE variants always reload their ring-buffer
2214  * configuration when restarted, so we must reinitialize our ring
2215  * context before restarting.  As part of this reinitialization,
2216  * find all packets still on the Tx ring and pretend that they had been
2217  * sent (in effect, drop the packets on the floor) - the higher-level
2218  * protocols will time out and retransmit.  It'd be better to shuffle
2219  * these skbs to a temp list and then actually re-Tx them after
2220  * restarting the chip, but I'm too lazy to do so right now.  dplatt@3do.com
2221  */
2222
2223 static void pcnet32_purge_tx_ring(struct net_device *dev)
2224 {
2225         struct pcnet32_private *lp = netdev_priv(dev);
2226         int i;
2227
2228         for (i = 0; i < lp->tx_ring_size; i++) {
2229                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2230                 wmb();          /* Make sure adapter sees owner change */
2231                 if (lp->tx_skbuff[i]) {
2232                         pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2233                                          lp->tx_skbuff[i]->len,
2234                                          PCI_DMA_TODEVICE);
2235                         dev_kfree_skb_any(lp->tx_skbuff[i]);
2236                 }
2237                 lp->tx_skbuff[i] = NULL;
2238                 lp->tx_dma_addr[i] = 0;
2239         }
2240 }
2241
2242 /* Initialize the PCNET32 Rx and Tx rings. */
2243 static int pcnet32_init_ring(struct net_device *dev)
2244 {
2245         struct pcnet32_private *lp = netdev_priv(dev);
2246         int i;
2247
2248         lp->tx_full = 0;
2249         lp->cur_rx = lp->cur_tx = 0;
2250         lp->dirty_rx = lp->dirty_tx = 0;
2251
2252         for (i = 0; i < lp->rx_ring_size; i++) {
2253                 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2254                 if (rx_skbuff == NULL) {
2255                         lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB);
2256                         rx_skbuff = lp->rx_skbuff[i];
2257                         if (!rx_skbuff) {
2258                                 /* there is not much we can do at this point */
2259                                 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
2260                                           __func__);
2261                                 return -1;
2262                         }
2263                         skb_reserve(rx_skbuff, NET_IP_ALIGN);
2264                 }
2265
2266                 rmb();
2267                 if (lp->rx_dma_addr[i] == 0)
2268                         lp->rx_dma_addr[i] =
2269                             pci_map_single(lp->pci_dev, rx_skbuff->data,
2270                                            PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
2271                 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2272                 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2273                 wmb();          /* Make sure owner changes after all others are visible */
2274                 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2275         }
2276         /* The Tx buffer address is filled in as needed, but we do need to clear
2277          * the upper ownership bit. */
2278         for (i = 0; i < lp->tx_ring_size; i++) {
2279                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2280                 wmb();          /* Make sure adapter sees owner change */
2281                 lp->tx_ring[i].base = 0;
2282                 lp->tx_dma_addr[i] = 0;
2283         }
2284
2285         lp->init_block->tlen_rlen =
2286             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2287         for (i = 0; i < 6; i++)
2288                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2289         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2290         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2291         wmb();                  /* Make sure all changes are visible */
2292         return 0;
2293 }
2294
2295 /* the pcnet32 has been issued a stop or reset.  Wait for the stop bit
2296  * then flush the pending transmit operations, re-initialize the ring,
2297  * and tell the chip to initialize.
2298  */
2299 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2300 {
2301         struct pcnet32_private *lp = netdev_priv(dev);
2302         unsigned long ioaddr = dev->base_addr;
2303         int i;
2304
2305         /* wait for stop */
2306         for (i = 0; i < 100; i++)
2307                 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
2308                         break;
2309
2310         if (i >= 100)
2311                 netif_err(lp, drv, dev, "%s timed out waiting for stop\n",
2312                           __func__);
2313
2314         pcnet32_purge_tx_ring(dev);
2315         if (pcnet32_init_ring(dev))
2316                 return;
2317
2318         /* ReInit Ring */
2319         lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2320         i = 0;
2321         while (i++ < 1000)
2322                 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2323                         break;
2324
2325         lp->a->write_csr(ioaddr, CSR0, csr0_bits);
2326 }
2327
2328 static void pcnet32_tx_timeout(struct net_device *dev)
2329 {
2330         struct pcnet32_private *lp = netdev_priv(dev);
2331         unsigned long ioaddr = dev->base_addr, flags;
2332
2333         spin_lock_irqsave(&lp->lock, flags);
2334         /* Transmitter timeout, serious problems. */
2335         if (pcnet32_debug & NETIF_MSG_DRV)
2336                 pr_err("%s: transmit timed out, status %4.4x, resetting\n",
2337                        dev->name, lp->a->read_csr(ioaddr, CSR0));
2338         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2339         dev->stats.tx_errors++;
2340         if (netif_msg_tx_err(lp)) {
2341                 int i;
2342                 printk(KERN_DEBUG
2343                        " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2344                        lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2345                        lp->cur_rx);
2346                 for (i = 0; i < lp->rx_ring_size; i++)
2347                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2348                                le32_to_cpu(lp->rx_ring[i].base),
2349                                (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2350                                0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2351                                le16_to_cpu(lp->rx_ring[i].status));
2352                 for (i = 0; i < lp->tx_ring_size; i++)
2353                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2354                                le32_to_cpu(lp->tx_ring[i].base),
2355                                (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2356                                le32_to_cpu(lp->tx_ring[i].misc),
2357                                le16_to_cpu(lp->tx_ring[i].status));
2358                 printk("\n");
2359         }
2360         pcnet32_restart(dev, CSR0_NORMAL);
2361
2362         dev->trans_start = jiffies; /* prevent tx timeout */
2363         netif_wake_queue(dev);
2364
2365         spin_unlock_irqrestore(&lp->lock, flags);
2366 }
2367
2368 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2369                                       struct net_device *dev)
2370 {
2371         struct pcnet32_private *lp = netdev_priv(dev);
2372         unsigned long ioaddr = dev->base_addr;
2373         u16 status;
2374         int entry;
2375         unsigned long flags;
2376
2377         spin_lock_irqsave(&lp->lock, flags);
2378
2379         netif_printk(lp, tx_queued, KERN_DEBUG, dev,
2380                      "%s() called, csr0 %4.4x\n",
2381                      __func__, lp->a->read_csr(ioaddr, CSR0));
2382
2383         /* Default status -- will not enable Successful-TxDone
2384          * interrupt when that option is available to us.
2385          */
2386         status = 0x8300;
2387
2388         /* Fill in a Tx ring entry */
2389
2390         /* Mask to ring buffer boundary. */
2391         entry = lp->cur_tx & lp->tx_mod_mask;
2392
2393         /* Caution: the write order is important here, set the status
2394          * with the "ownership" bits last. */
2395
2396         lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2397
2398         lp->tx_ring[entry].misc = 0x00000000;
2399
2400         lp->tx_skbuff[entry] = skb;
2401         lp->tx_dma_addr[entry] =
2402             pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2403         lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2404         wmb();                  /* Make sure owner changes after all others are visible */
2405         lp->tx_ring[entry].status = cpu_to_le16(status);
2406
2407         lp->cur_tx++;
2408         dev->stats.tx_bytes += skb->len;
2409
2410         /* Trigger an immediate send poll. */
2411         lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2412
2413         if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2414                 lp->tx_full = 1;
2415                 netif_stop_queue(dev);
2416         }
2417         spin_unlock_irqrestore(&lp->lock, flags);
2418         return NETDEV_TX_OK;
2419 }
2420
2421 /* The PCNET32 interrupt handler. */
2422 static irqreturn_t
2423 pcnet32_interrupt(int irq, void *dev_id)
2424 {
2425         struct net_device *dev = dev_id;
2426         struct pcnet32_private *lp;
2427         unsigned long ioaddr;
2428         u16 csr0;
2429         int boguscnt = max_interrupt_work;
2430
2431         ioaddr = dev->base_addr;
2432         lp = netdev_priv(dev);
2433
2434         spin_lock(&lp->lock);
2435
2436         csr0 = lp->a->read_csr(ioaddr, CSR0);
2437         while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2438                 if (csr0 == 0xffff)
2439                         break;  /* PCMCIA remove happened */
2440                 /* Acknowledge all of the current interrupt sources ASAP. */
2441                 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2442
2443                 netif_printk(lp, intr, KERN_DEBUG, dev,
2444                              "interrupt  csr0=%#2.2x new csr=%#2.2x\n",
2445                              csr0, lp->a->read_csr(ioaddr, CSR0));
2446
2447                 /* Log misc errors. */
2448                 if (csr0 & 0x4000)
2449                         dev->stats.tx_errors++; /* Tx babble. */
2450                 if (csr0 & 0x1000) {
2451                         /*
2452                          * This happens when our receive ring is full. This
2453                          * shouldn't be a problem as we will see normal rx
2454                          * interrupts for the frames in the receive ring.  But
2455                          * there are some PCI chipsets (I can reproduce this
2456                          * on SP3G with Intel saturn chipset) which have
2457                          * sometimes problems and will fill up the receive
2458                          * ring with error descriptors.  In this situation we
2459                          * don't get a rx interrupt, but a missed frame
2460                          * interrupt sooner or later.
2461                          */
2462                         dev->stats.rx_errors++; /* Missed a Rx frame. */
2463                 }
2464                 if (csr0 & 0x0800) {
2465                         netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",
2466                                   csr0);
2467                         /* unlike for the lance, there is no restart needed */
2468                 }
2469                 if (napi_schedule_prep(&lp->napi)) {
2470                         u16 val;
2471                         /* set interrupt masks */
2472                         val = lp->a->read_csr(ioaddr, CSR3);
2473                         val |= 0x5f00;
2474                         lp->a->write_csr(ioaddr, CSR3, val);
2475
2476                         __napi_schedule(&lp->napi);
2477                         break;
2478                 }
2479                 csr0 = lp->a->read_csr(ioaddr, CSR0);
2480         }
2481
2482         netif_printk(lp, intr, KERN_DEBUG, dev,
2483                      "exiting interrupt, csr0=%#4.4x\n",
2484                      lp->a->read_csr(ioaddr, CSR0));
2485
2486         spin_unlock(&lp->lock);
2487
2488         return IRQ_HANDLED;
2489 }
2490
2491 static int pcnet32_close(struct net_device *dev)
2492 {
2493         unsigned long ioaddr = dev->base_addr;
2494         struct pcnet32_private *lp = netdev_priv(dev);
2495         unsigned long flags;
2496
2497         del_timer_sync(&lp->watchdog_timer);
2498
2499         netif_stop_queue(dev);
2500         napi_disable(&lp->napi);
2501
2502         spin_lock_irqsave(&lp->lock, flags);
2503
2504         dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2505
2506         netif_printk(lp, ifdown, KERN_DEBUG, dev,
2507                      "Shutting down ethercard, status was %2.2x\n",
2508                      lp->a->read_csr(ioaddr, CSR0));
2509
2510         /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2511         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2512
2513         /*
2514          * Switch back to 16bit mode to avoid problems with dumb
2515          * DOS packet driver after a warm reboot
2516          */
2517         lp->a->write_bcr(ioaddr, 20, 4);
2518
2519         spin_unlock_irqrestore(&lp->lock, flags);
2520
2521         free_irq(dev->irq, dev);
2522
2523         spin_lock_irqsave(&lp->lock, flags);
2524
2525         pcnet32_purge_rx_ring(dev);
2526         pcnet32_purge_tx_ring(dev);
2527
2528         spin_unlock_irqrestore(&lp->lock, flags);
2529
2530         return 0;
2531 }
2532
2533 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2534 {
2535         struct pcnet32_private *lp = netdev_priv(dev);
2536         unsigned long ioaddr = dev->base_addr;
2537         unsigned long flags;
2538
2539         spin_lock_irqsave(&lp->lock, flags);
2540         dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2541         spin_unlock_irqrestore(&lp->lock, flags);
2542
2543         return &dev->stats;
2544 }
2545
2546 /* taken from the sunlance driver, which it took from the depca driver */
2547 static void pcnet32_load_multicast(struct net_device *dev)
2548 {
2549         struct pcnet32_private *lp = netdev_priv(dev);
2550         volatile struct pcnet32_init_block *ib = lp->init_block;
2551         volatile __le16 *mcast_table = (__le16 *)ib->filter;
2552         struct netdev_hw_addr *ha;
2553         unsigned long ioaddr = dev->base_addr;
2554         int i;
2555         u32 crc;
2556
2557         /* set all multicast bits */
2558         if (dev->flags & IFF_ALLMULTI) {
2559                 ib->filter[0] = cpu_to_le32(~0U);
2560                 ib->filter[1] = cpu_to_le32(~0U);
2561                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2562                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2563                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2564                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2565                 return;
2566         }
2567         /* clear the multicast filter */
2568         ib->filter[0] = 0;
2569         ib->filter[1] = 0;
2570
2571         /* Add addresses */
2572         netdev_for_each_mc_addr(ha, dev) {
2573                 crc = ether_crc_le(6, ha->addr);
2574                 crc = crc >> 26;
2575                 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2576         }
2577         for (i = 0; i < 4; i++)
2578                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,
2579                                 le16_to_cpu(mcast_table[i]));
2580 }
2581
2582 /*
2583  * Set or clear the multicast filter for this adaptor.
2584  */
2585 static void pcnet32_set_multicast_list(struct net_device *dev)
2586 {
2587         unsigned long ioaddr = dev->base_addr, flags;
2588         struct pcnet32_private *lp = netdev_priv(dev);
2589         int csr15, suspended;
2590
2591         spin_lock_irqsave(&lp->lock, flags);
2592         suspended = pcnet32_suspend(dev, &flags, 0);
2593         csr15 = lp->a->read_csr(ioaddr, CSR15);
2594         if (dev->flags & IFF_PROMISC) {
2595                 /* Log any net taps. */
2596                 netif_info(lp, hw, dev, "Promiscuous mode enabled\n");
2597                 lp->init_block->mode =
2598                     cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2599                                 7);
2600                 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
2601         } else {
2602                 lp->init_block->mode =
2603                     cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2604                 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2605                 pcnet32_load_multicast(dev);
2606         }
2607
2608         if (suspended) {
2609                 int csr5;
2610                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2611                 csr5 = lp->a->read_csr(ioaddr, CSR5);
2612                 lp->a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2613         } else {
2614                 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2615                 pcnet32_restart(dev, CSR0_NORMAL);
2616                 netif_wake_queue(dev);
2617         }
2618
2619         spin_unlock_irqrestore(&lp->lock, flags);
2620 }
2621
2622 /* This routine assumes that the lp->lock is held */
2623 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2624 {
2625         struct pcnet32_private *lp = netdev_priv(dev);
2626         unsigned long ioaddr = dev->base_addr;
2627         u16 val_out;
2628
2629         if (!lp->mii)
2630                 return 0;
2631
2632         lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2633         val_out = lp->a->read_bcr(ioaddr, 34);
2634
2635         return val_out;
2636 }
2637
2638 /* This routine assumes that the lp->lock is held */
2639 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2640 {
2641         struct pcnet32_private *lp = netdev_priv(dev);
2642         unsigned long ioaddr = dev->base_addr;
2643
2644         if (!lp->mii)
2645                 return;
2646
2647         lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2648         lp->a->write_bcr(ioaddr, 34, val);
2649 }
2650
2651 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2652 {
2653         struct pcnet32_private *lp = netdev_priv(dev);
2654         int rc;
2655         unsigned long flags;
2656
2657         /* SIOC[GS]MIIxxx ioctls */
2658         if (lp->mii) {
2659                 spin_lock_irqsave(&lp->lock, flags);
2660                 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2661                 spin_unlock_irqrestore(&lp->lock, flags);
2662         } else {
2663                 rc = -EOPNOTSUPP;
2664         }
2665
2666         return rc;
2667 }
2668
2669 static int pcnet32_check_otherphy(struct net_device *dev)
2670 {
2671         struct pcnet32_private *lp = netdev_priv(dev);
2672         struct mii_if_info mii = lp->mii_if;
2673         u16 bmcr;
2674         int i;
2675
2676         for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2677                 if (i == lp->mii_if.phy_id)
2678                         continue;       /* skip active phy */
2679                 if (lp->phymask & (1 << i)) {
2680                         mii.phy_id = i;
2681                         if (mii_link_ok(&mii)) {
2682                                 /* found PHY with active link */
2683                                 netif_info(lp, link, dev, "Using PHY number %d\n",
2684                                            i);
2685
2686                                 /* isolate inactive phy */
2687                                 bmcr =
2688                                     mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2689                                 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2690                                            bmcr | BMCR_ISOLATE);
2691
2692                                 /* de-isolate new phy */
2693                                 bmcr = mdio_read(dev, i, MII_BMCR);
2694                                 mdio_write(dev, i, MII_BMCR,
2695                                            bmcr & ~BMCR_ISOLATE);
2696
2697                                 /* set new phy address */
2698                                 lp->mii_if.phy_id = i;
2699                                 return 1;
2700                         }
2701                 }
2702         }
2703         return 0;
2704 }
2705
2706 /*
2707  * Show the status of the media.  Similar to mii_check_media however it
2708  * correctly shows the link speed for all (tested) pcnet32 variants.
2709  * Devices with no mii just report link state without speed.
2710  *
2711  * Caller is assumed to hold and release the lp->lock.
2712  */
2713
2714 static void pcnet32_check_media(struct net_device *dev, int verbose)
2715 {
2716         struct pcnet32_private *lp = netdev_priv(dev);
2717         int curr_link;
2718         int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2719         u32 bcr9;
2720
2721         if (lp->mii) {
2722                 curr_link = mii_link_ok(&lp->mii_if);
2723         } else {
2724                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
2725                 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2726         }
2727         if (!curr_link) {
2728                 if (prev_link || verbose) {
2729                         netif_carrier_off(dev);
2730                         netif_info(lp, link, dev, "link down\n");
2731                 }
2732                 if (lp->phycount > 1) {
2733                         curr_link = pcnet32_check_otherphy(dev);
2734                         prev_link = 0;
2735                 }
2736         } else if (verbose || !prev_link) {
2737                 netif_carrier_on(dev);
2738                 if (lp->mii) {
2739                         if (netif_msg_link(lp)) {
2740                                 struct ethtool_cmd ecmd = {
2741                                         .cmd = ETHTOOL_GSET };
2742                                 mii_ethtool_gset(&lp->mii_if, &ecmd);
2743                                 netdev_info(dev, "link up, %uMbps, %s-duplex\n",
2744                                             ethtool_cmd_speed(&ecmd),
2745                                             (ecmd.duplex == DUPLEX_FULL)
2746                                             ? "full" : "half");
2747                         }
2748                         bcr9 = lp->a->read_bcr(dev->base_addr, 9);
2749                         if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2750                                 if (lp->mii_if.full_duplex)
2751                                         bcr9 |= (1 << 0);
2752                                 else
2753                                         bcr9 &= ~(1 << 0);
2754                                 lp->a->write_bcr(dev->base_addr, 9, bcr9);
2755                         }
2756                 } else {
2757                         netif_info(lp, link, dev, "link up\n");
2758                 }
2759         }
2760 }
2761
2762 /*
2763  * Check for loss of link and link establishment.
2764  * Can not use mii_check_media because it does nothing if mode is forced.
2765  */
2766
2767 static void pcnet32_watchdog(struct net_device *dev)
2768 {
2769         struct pcnet32_private *lp = netdev_priv(dev);
2770         unsigned long flags;
2771
2772         /* Print the link status if it has changed */
2773         spin_lock_irqsave(&lp->lock, flags);
2774         pcnet32_check_media(dev, 0);
2775         spin_unlock_irqrestore(&lp->lock, flags);
2776
2777         mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
2778 }
2779
2780 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2781 {
2782         struct net_device *dev = pci_get_drvdata(pdev);
2783
2784         if (netif_running(dev)) {
2785                 netif_device_detach(dev);
2786                 pcnet32_close(dev);
2787         }
2788         pci_save_state(pdev);
2789         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2790         return 0;
2791 }
2792
2793 static int pcnet32_pm_resume(struct pci_dev *pdev)
2794 {
2795         struct net_device *dev = pci_get_drvdata(pdev);
2796
2797         pci_set_power_state(pdev, PCI_D0);
2798         pci_restore_state(pdev);
2799
2800         if (netif_running(dev)) {
2801                 pcnet32_open(dev);
2802                 netif_device_attach(dev);
2803         }
2804         return 0;
2805 }
2806
2807 static void pcnet32_remove_one(struct pci_dev *pdev)
2808 {
2809         struct net_device *dev = pci_get_drvdata(pdev);
2810
2811         if (dev) {
2812                 struct pcnet32_private *lp = netdev_priv(dev);
2813
2814                 unregister_netdev(dev);
2815                 pcnet32_free_ring(dev);
2816                 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2817                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2818                                     lp->init_block, lp->init_dma_addr);
2819                 free_netdev(dev);
2820                 pci_disable_device(pdev);
2821         }
2822 }
2823
2824 static struct pci_driver pcnet32_driver = {
2825         .name = DRV_NAME,
2826         .probe = pcnet32_probe_pci,
2827         .remove = pcnet32_remove_one,
2828         .id_table = pcnet32_pci_tbl,
2829         .suspend = pcnet32_pm_suspend,
2830         .resume = pcnet32_pm_resume,
2831 };
2832
2833 /* An additional parameter that may be passed in... */
2834 static int debug = -1;
2835 static int tx_start_pt = -1;
2836 static int pcnet32_have_pci;
2837
2838 module_param(debug, int, 0);
2839 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2840 module_param(max_interrupt_work, int, 0);
2841 MODULE_PARM_DESC(max_interrupt_work,
2842                  DRV_NAME " maximum events handled per interrupt");
2843 module_param(rx_copybreak, int, 0);
2844 MODULE_PARM_DESC(rx_copybreak,
2845                  DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2846 module_param(tx_start_pt, int, 0);
2847 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2848 module_param(pcnet32vlb, int, 0);
2849 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2850 module_param_array(options, int, NULL, 0);
2851 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2852 module_param_array(full_duplex, int, NULL, 0);
2853 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2854 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2855 module_param_array(homepna, int, NULL, 0);
2856 MODULE_PARM_DESC(homepna,
2857                  DRV_NAME
2858                  " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2859
2860 MODULE_AUTHOR("Thomas Bogendoerfer");
2861 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2862 MODULE_LICENSE("GPL");
2863
2864 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2865
2866 static int __init pcnet32_init_module(void)
2867 {
2868         pr_info("%s", version);
2869
2870         pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2871
2872         if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2873                 tx_start = tx_start_pt;
2874
2875         /* find the PCI devices */
2876         if (!pci_register_driver(&pcnet32_driver))
2877                 pcnet32_have_pci = 1;
2878
2879         /* should we find any remaining VLbus devices ? */
2880         if (pcnet32vlb)
2881                 pcnet32_probe_vlbus(pcnet32_portlist);
2882
2883         if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2884                 pr_info("%d cards_found\n", cards_found);
2885
2886         return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2887 }
2888
2889 static void __exit pcnet32_cleanup_module(void)
2890 {
2891         struct net_device *next_dev;
2892
2893         while (pcnet32_dev) {
2894                 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
2895                 next_dev = lp->next;
2896                 unregister_netdev(pcnet32_dev);
2897                 pcnet32_free_ring(pcnet32_dev);
2898                 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2899                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2900                                     lp->init_block, lp->init_dma_addr);
2901                 free_netdev(pcnet32_dev);
2902                 pcnet32_dev = next_dev;
2903         }
2904
2905         if (pcnet32_have_pci)
2906                 pci_unregister_driver(&pcnet32_driver);
2907 }
2908
2909 module_init(pcnet32_init_module);
2910 module_exit(pcnet32_cleanup_module);
2911
2912 /*
2913  * Local variables:
2914  *  c-indent-level: 4
2915  *  tab-width: 8
2916  * End:
2917  */