2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/ptrace.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/icmp.h>
44 #include <linux/spinlock.h>
45 #include <linux/workqueue.h>
46 #include <linux/bitops.h>
48 #include <linux/irq.h>
49 #include <linux/clk.h>
50 #include <linux/platform_device.h>
51 #include <linux/phy.h>
52 #include <linux/fec.h>
54 #include <linux/of_device.h>
55 #include <linux/of_gpio.h>
56 #include <linux/of_mdio.h>
57 #include <linux/of_net.h>
58 #include <linux/regulator/consumer.h>
59 #include <linux/if_vlan.h>
60 #include <linux/pinctrl/consumer.h>
61 #include <linux/prefetch.h>
63 #include <asm/cacheflush.h>
67 static void set_multicast_list(struct net_device *ndev);
68 static void fec_enet_itr_coal_init(struct net_device *ndev);
69 static void fec_reset_phy(struct platform_device *pdev);
71 #define DRIVER_NAME "fec"
73 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
75 /* Pause frame feild and FIFO threshold */
76 #define FEC_ENET_FCE (1 << 5)
77 #define FEC_ENET_RSEM_V 0x84
78 #define FEC_ENET_RSFL_V 16
79 #define FEC_ENET_RAEM_V 0x8
80 #define FEC_ENET_RAFL_V 0x8
81 #define FEC_ENET_OPD_V 0xFFF0
82 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
84 static struct platform_device_id fec_devtype[] = {
86 /* keep it for coldfire */
91 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC,
94 .driver_data = FEC_QUIRK_HAS_RACC,
97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
98 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
102 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
103 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
106 .name = "mvf600-fec",
107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
109 .name = "imx6sx-fec",
110 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
111 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
112 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
113 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
119 MODULE_DEVICE_TABLE(platform, fec_devtype);
122 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
123 IMX27_FEC, /* runs on i.mx27/35/51 */
130 static const struct of_device_id fec_dt_ids[] = {
131 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
132 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
133 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
134 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
135 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
136 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
139 MODULE_DEVICE_TABLE(of, fec_dt_ids);
141 static unsigned char macaddr[ETH_ALEN];
142 module_param_array(macaddr, byte, NULL, 0);
143 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
145 #if defined(CONFIG_M5272)
147 * Some hardware gets it MAC address out of local flash memory.
148 * if this is non-zero then assume it is the address to get MAC from.
150 #if defined(CONFIG_NETtel)
151 #define FEC_FLASHMAC 0xf0006006
152 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
153 #define FEC_FLASHMAC 0xf0006000
154 #elif defined(CONFIG_CANCam)
155 #define FEC_FLASHMAC 0xf0020000
156 #elif defined (CONFIG_M5272C3)
157 #define FEC_FLASHMAC (0xffe04000 + 4)
158 #elif defined(CONFIG_MOD5272)
159 #define FEC_FLASHMAC 0xffc0406b
161 #define FEC_FLASHMAC 0
163 #endif /* CONFIG_M5272 */
165 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
167 #define PKT_MAXBUF_SIZE 1522
168 #define PKT_MINBUF_SIZE 64
169 #define PKT_MAXBLR_SIZE 1536
171 /* FEC receive acceleration */
172 #define FEC_RACC_IPDIS (1 << 1)
173 #define FEC_RACC_PRODIS (1 << 2)
174 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
177 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
178 * size bits. Other FEC hardware does not, so we need to take that into
179 * account when setting it.
181 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
182 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
183 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
185 #define OPT_FRAME_SIZE 0
188 /* FEC MII MMFR bits definition */
189 #define FEC_MMFR_ST (1 << 30)
190 #define FEC_MMFR_OP_READ (2 << 28)
191 #define FEC_MMFR_OP_WRITE (1 << 28)
192 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
193 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
194 #define FEC_MMFR_TA (2 << 16)
195 #define FEC_MMFR_DATA(v) (v & 0xffff)
196 /* FEC ECR bits definition */
197 #define FEC_ECR_MAGICEN (1 << 2)
198 #define FEC_ECR_SLEEP (1 << 3)
200 #define FEC_MII_TIMEOUT 30000 /* us */
202 /* Transmitter timeout */
203 #define TX_TIMEOUT (2 * HZ)
205 #define FEC_PAUSE_FLAG_AUTONEG 0x1
206 #define FEC_PAUSE_FLAG_ENABLE 0x2
207 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
208 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
209 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
211 #define COPYBREAK_DEFAULT 256
213 #define TSO_HEADER_SIZE 128
214 /* Max number of allowed TCP segments for software TSO */
215 #define FEC_MAX_TSO_SEGS 100
216 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
218 #define IS_TSO_HEADER(txq, addr) \
219 ((addr >= txq->tso_hdrs_dma) && \
220 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
225 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
226 struct fec_enet_private *fep,
229 struct bufdesc *new_bd = bdp + 1;
230 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
231 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
232 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
233 struct bufdesc_ex *ex_base;
234 struct bufdesc *base;
237 if (bdp >= txq->tx_bd_base) {
238 base = txq->tx_bd_base;
239 ring_size = txq->tx_ring_size;
240 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
242 base = rxq->rx_bd_base;
243 ring_size = rxq->rx_ring_size;
244 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
248 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
249 ex_base : ex_new_bd);
251 return (new_bd >= (base + ring_size)) ?
256 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
257 struct fec_enet_private *fep,
260 struct bufdesc *new_bd = bdp - 1;
261 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
262 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
263 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
264 struct bufdesc_ex *ex_base;
265 struct bufdesc *base;
268 if (bdp >= txq->tx_bd_base) {
269 base = txq->tx_bd_base;
270 ring_size = txq->tx_ring_size;
271 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
273 base = rxq->rx_bd_base;
274 ring_size = rxq->rx_ring_size;
275 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
279 return (struct bufdesc *)((ex_new_bd < ex_base) ?
280 (ex_new_bd + ring_size) : ex_new_bd);
282 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
285 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
286 struct fec_enet_private *fep)
288 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
291 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
292 struct fec_enet_priv_tx_q *txq)
296 entries = ((const char *)txq->dirty_tx -
297 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
299 return entries > 0 ? entries : entries + txq->tx_ring_size;
302 static void swap_buffer(void *bufaddr, int len)
305 unsigned int *buf = bufaddr;
307 for (i = 0; i < len; i += 4, buf++)
311 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
314 unsigned int *src = src_buf;
315 unsigned int *dst = dst_buf;
317 for (i = 0; i < len; i += 4, src++, dst++)
321 static void fec_dump(struct net_device *ndev)
323 struct fec_enet_private *fep = netdev_priv(ndev);
325 struct fec_enet_priv_tx_q *txq;
328 netdev_info(ndev, "TX ring dump\n");
329 pr_info("Nr SC addr len SKB\n");
331 txq = fep->tx_queue[0];
332 bdp = txq->tx_bd_base;
335 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
337 bdp == txq->cur_tx ? 'S' : ' ',
338 bdp == txq->dirty_tx ? 'H' : ' ',
339 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
340 txq->tx_skbuff[index]);
341 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
343 } while (bdp != txq->tx_bd_base);
346 static inline bool is_ipv4_pkt(struct sk_buff *skb)
348 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
352 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
354 /* Only run for packets requiring a checksum. */
355 if (skb->ip_summed != CHECKSUM_PARTIAL)
358 if (unlikely(skb_cow_head(skb, 0)))
361 if (is_ipv4_pkt(skb))
362 ip_hdr(skb)->check = 0;
363 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
368 static struct bufdesc *
369 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
371 struct net_device *ndev)
373 struct fec_enet_private *fep = netdev_priv(ndev);
374 struct bufdesc *bdp = txq->cur_tx;
375 struct bufdesc_ex *ebdp;
376 int nr_frags = skb_shinfo(skb)->nr_frags;
377 unsigned short queue = skb_get_queue_mapping(skb);
379 unsigned short status;
380 unsigned int estatus = 0;
381 skb_frag_t *this_frag;
387 for (frag = 0; frag < nr_frags; frag++) {
388 this_frag = &skb_shinfo(skb)->frags[frag];
389 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
390 ebdp = (struct bufdesc_ex *)bdp;
392 status = bdp->cbd_sc;
393 status &= ~BD_ENET_TX_STATS;
394 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
395 frag_len = skb_shinfo(skb)->frags[frag].size;
397 /* Handle the last BD specially */
398 if (frag == nr_frags - 1) {
399 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
400 if (fep->bufdesc_ex) {
401 estatus |= BD_ENET_TX_INT;
402 if (unlikely(skb_shinfo(skb)->tx_flags &
403 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
404 estatus |= BD_ENET_TX_TS;
408 if (fep->bufdesc_ex) {
409 if (fep->quirks & FEC_QUIRK_HAS_AVB)
410 estatus |= FEC_TX_BD_FTYPE(queue);
411 if (skb->ip_summed == CHECKSUM_PARTIAL)
412 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
414 ebdp->cbd_esc = estatus;
417 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
419 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
420 if (((unsigned long) bufaddr) & fep->tx_align ||
421 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
422 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
423 bufaddr = txq->tx_bounce[index];
425 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
426 swap_buffer(bufaddr, frag_len);
429 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
431 if (dma_mapping_error(&fep->pdev->dev, addr)) {
432 dev_kfree_skb_any(skb);
434 netdev_err(ndev, "Tx DMA memory map failed\n");
435 goto dma_mapping_error;
438 bdp->cbd_bufaddr = addr;
439 bdp->cbd_datlen = frag_len;
440 bdp->cbd_sc = status;
446 for (i = 0; i < frag; i++) {
447 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
448 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
449 bdp->cbd_datlen, DMA_TO_DEVICE);
451 return ERR_PTR(-ENOMEM);
454 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
455 struct sk_buff *skb, struct net_device *ndev)
457 struct fec_enet_private *fep = netdev_priv(ndev);
458 int nr_frags = skb_shinfo(skb)->nr_frags;
459 struct bufdesc *bdp, *last_bdp;
462 unsigned short status;
463 unsigned short buflen;
464 unsigned short queue;
465 unsigned int estatus = 0;
469 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
470 if (entries_free < MAX_SKB_FRAGS + 1) {
471 dev_kfree_skb_any(skb);
473 netdev_err(ndev, "NOT enough BD for SG!\n");
477 /* Protocol checksum off-load for TCP and UDP. */
478 if (fec_enet_clear_csum(skb, ndev)) {
479 dev_kfree_skb_any(skb);
483 /* Fill in a Tx ring entry */
486 status = bdp->cbd_sc;
487 status &= ~BD_ENET_TX_STATS;
489 /* Set buffer length and buffer pointer */
491 buflen = skb_headlen(skb);
493 queue = skb_get_queue_mapping(skb);
494 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
495 if (((unsigned long) bufaddr) & fep->tx_align ||
496 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
497 memcpy(txq->tx_bounce[index], skb->data, buflen);
498 bufaddr = txq->tx_bounce[index];
500 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
501 swap_buffer(bufaddr, buflen);
504 /* Push the data cache so the CPM does not get stale memory data. */
505 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
506 if (dma_mapping_error(&fep->pdev->dev, addr)) {
507 dev_kfree_skb_any(skb);
509 netdev_err(ndev, "Tx DMA memory map failed\n");
514 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
515 if (IS_ERR(last_bdp))
518 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
519 if (fep->bufdesc_ex) {
520 estatus = BD_ENET_TX_INT;
521 if (unlikely(skb_shinfo(skb)->tx_flags &
522 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
523 estatus |= BD_ENET_TX_TS;
527 if (fep->bufdesc_ex) {
529 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
531 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
533 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
535 if (fep->quirks & FEC_QUIRK_HAS_AVB)
536 estatus |= FEC_TX_BD_FTYPE(queue);
538 if (skb->ip_summed == CHECKSUM_PARTIAL)
539 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
542 ebdp->cbd_esc = estatus;
545 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
546 /* Save skb pointer */
547 txq->tx_skbuff[index] = skb;
549 bdp->cbd_datlen = buflen;
550 bdp->cbd_bufaddr = addr;
552 /* Send it on its way. Tell FEC it's ready, interrupt when done,
553 * it's the last BD of the frame, and to put the CRC on the end.
555 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
556 bdp->cbd_sc = status;
558 /* If this was the last BD in the ring, start at the beginning again. */
559 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
561 skb_tx_timestamp(skb);
563 /* Make sure the update to bdp and tx_skbuff are performed before
569 /* Trigger transmission start */
570 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
576 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
577 struct net_device *ndev,
578 struct bufdesc *bdp, int index, char *data,
579 int size, bool last_tcp, bool is_last)
581 struct fec_enet_private *fep = netdev_priv(ndev);
582 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
583 unsigned short queue = skb_get_queue_mapping(skb);
584 unsigned short status;
585 unsigned int estatus = 0;
588 status = bdp->cbd_sc;
589 status &= ~BD_ENET_TX_STATS;
591 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
593 if (((unsigned long) data) & fep->tx_align ||
594 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
595 memcpy(txq->tx_bounce[index], data, size);
596 data = txq->tx_bounce[index];
598 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
599 swap_buffer(data, size);
602 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
603 if (dma_mapping_error(&fep->pdev->dev, addr)) {
604 dev_kfree_skb_any(skb);
606 netdev_err(ndev, "Tx DMA memory map failed\n");
607 return NETDEV_TX_BUSY;
610 bdp->cbd_datlen = size;
611 bdp->cbd_bufaddr = addr;
613 if (fep->bufdesc_ex) {
614 if (fep->quirks & FEC_QUIRK_HAS_AVB)
615 estatus |= FEC_TX_BD_FTYPE(queue);
616 if (skb->ip_summed == CHECKSUM_PARTIAL)
617 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
619 ebdp->cbd_esc = estatus;
622 /* Handle the last BD specially */
624 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
626 status |= BD_ENET_TX_INTR;
628 ebdp->cbd_esc |= BD_ENET_TX_INT;
631 bdp->cbd_sc = status;
637 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
638 struct sk_buff *skb, struct net_device *ndev,
639 struct bufdesc *bdp, int index)
641 struct fec_enet_private *fep = netdev_priv(ndev);
642 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
643 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
644 unsigned short queue = skb_get_queue_mapping(skb);
646 unsigned long dmabuf;
647 unsigned short status;
648 unsigned int estatus = 0;
650 status = bdp->cbd_sc;
651 status &= ~BD_ENET_TX_STATS;
652 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
654 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
655 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
656 if (((unsigned long)bufaddr) & fep->tx_align ||
657 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
658 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
659 bufaddr = txq->tx_bounce[index];
661 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
662 swap_buffer(bufaddr, hdr_len);
664 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
665 hdr_len, DMA_TO_DEVICE);
666 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
667 dev_kfree_skb_any(skb);
669 netdev_err(ndev, "Tx DMA memory map failed\n");
670 return NETDEV_TX_BUSY;
674 bdp->cbd_bufaddr = dmabuf;
675 bdp->cbd_datlen = hdr_len;
677 if (fep->bufdesc_ex) {
678 if (fep->quirks & FEC_QUIRK_HAS_AVB)
679 estatus |= FEC_TX_BD_FTYPE(queue);
680 if (skb->ip_summed == CHECKSUM_PARTIAL)
681 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
683 ebdp->cbd_esc = estatus;
686 bdp->cbd_sc = status;
691 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
693 struct net_device *ndev)
695 struct fec_enet_private *fep = netdev_priv(ndev);
696 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
697 int total_len, data_left;
698 struct bufdesc *bdp = txq->cur_tx;
699 unsigned short queue = skb_get_queue_mapping(skb);
701 unsigned int index = 0;
704 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
705 dev_kfree_skb_any(skb);
707 netdev_err(ndev, "NOT enough BD for TSO!\n");
711 /* Protocol checksum off-load for TCP and UDP. */
712 if (fec_enet_clear_csum(skb, ndev)) {
713 dev_kfree_skb_any(skb);
717 /* Initialize the TSO handler, and prepare the first payload */
718 tso_start(skb, &tso);
720 total_len = skb->len - hdr_len;
721 while (total_len > 0) {
724 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
725 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
726 total_len -= data_left;
728 /* prepare packet headers: MAC + IP + TCP */
729 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
730 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
731 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
735 while (data_left > 0) {
738 size = min_t(int, tso.size, data_left);
739 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
740 index = fec_enet_get_bd_index(txq->tx_bd_base,
742 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
751 tso_build_data(skb, &tso, size);
754 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
757 /* Save skb pointer */
758 txq->tx_skbuff[index] = skb;
760 skb_tx_timestamp(skb);
763 /* Trigger transmission start */
764 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
765 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
766 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
767 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
768 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
769 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
774 /* TODO: Release all used data descriptors for TSO */
779 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
781 struct fec_enet_private *fep = netdev_priv(ndev);
783 unsigned short queue;
784 struct fec_enet_priv_tx_q *txq;
785 struct netdev_queue *nq;
788 queue = skb_get_queue_mapping(skb);
789 txq = fep->tx_queue[queue];
790 nq = netdev_get_tx_queue(ndev, queue);
793 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
795 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
799 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
800 if (entries_free <= txq->tx_stop_threshold)
801 netif_tx_stop_queue(nq);
806 /* Init RX & TX buffer descriptors
808 static void fec_enet_bd_init(struct net_device *dev)
810 struct fec_enet_private *fep = netdev_priv(dev);
811 struct fec_enet_priv_tx_q *txq;
812 struct fec_enet_priv_rx_q *rxq;
817 for (q = 0; q < fep->num_rx_queues; q++) {
818 /* Initialize the receive buffer descriptors. */
819 rxq = fep->rx_queue[q];
820 bdp = rxq->rx_bd_base;
822 for (i = 0; i < rxq->rx_ring_size; i++) {
824 /* Initialize the BD for every fragment in the page. */
825 if (bdp->cbd_bufaddr)
826 bdp->cbd_sc = BD_ENET_RX_EMPTY;
829 bdp = fec_enet_get_nextdesc(bdp, fep, q);
832 /* Set the last buffer to wrap */
833 bdp = fec_enet_get_prevdesc(bdp, fep, q);
834 bdp->cbd_sc |= BD_SC_WRAP;
836 rxq->cur_rx = rxq->rx_bd_base;
839 for (q = 0; q < fep->num_tx_queues; q++) {
840 /* ...and the same for transmit */
841 txq = fep->tx_queue[q];
842 bdp = txq->tx_bd_base;
845 for (i = 0; i < txq->tx_ring_size; i++) {
846 /* Initialize the BD for every fragment in the page. */
848 if (txq->tx_skbuff[i]) {
849 dev_kfree_skb_any(txq->tx_skbuff[i]);
850 txq->tx_skbuff[i] = NULL;
852 bdp->cbd_bufaddr = 0;
853 bdp = fec_enet_get_nextdesc(bdp, fep, q);
856 /* Set the last buffer to wrap */
857 bdp = fec_enet_get_prevdesc(bdp, fep, q);
858 bdp->cbd_sc |= BD_SC_WRAP;
863 static void fec_enet_active_rxring(struct net_device *ndev)
865 struct fec_enet_private *fep = netdev_priv(ndev);
868 for (i = 0; i < fep->num_rx_queues; i++)
869 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
872 static void fec_enet_enable_ring(struct net_device *ndev)
874 struct fec_enet_private *fep = netdev_priv(ndev);
875 struct fec_enet_priv_tx_q *txq;
876 struct fec_enet_priv_rx_q *rxq;
879 for (i = 0; i < fep->num_rx_queues; i++) {
880 rxq = fep->rx_queue[i];
881 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
882 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
886 writel(RCMR_MATCHEN | RCMR_CMP(i),
887 fep->hwp + FEC_RCMR(i));
890 for (i = 0; i < fep->num_tx_queues; i++) {
891 txq = fep->tx_queue[i];
892 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
896 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
897 fep->hwp + FEC_DMA_CFG(i));
901 static void fec_enet_reset_skb(struct net_device *ndev)
903 struct fec_enet_private *fep = netdev_priv(ndev);
904 struct fec_enet_priv_tx_q *txq;
907 for (i = 0; i < fep->num_tx_queues; i++) {
908 txq = fep->tx_queue[i];
910 for (j = 0; j < txq->tx_ring_size; j++) {
911 if (txq->tx_skbuff[j]) {
912 dev_kfree_skb_any(txq->tx_skbuff[j]);
913 txq->tx_skbuff[j] = NULL;
920 * This function is called to start or restart the FEC during a link
921 * change, transmit timeout, or to reconfigure the FEC. The network
922 * packet processing for this device must be stopped before this call.
925 fec_restart(struct net_device *ndev)
927 struct fec_enet_private *fep = netdev_priv(ndev);
930 u32 rcntl = OPT_FRAME_SIZE | 0x04;
931 u32 ecntl = 0x2; /* ETHEREN */
933 /* Whack a reset. We should wait for this.
934 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
935 * instead of reset MAC itself.
937 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
938 writel(0, fep->hwp + FEC_ECNTRL);
940 writel(1, fep->hwp + FEC_ECNTRL);
945 * enet-mac reset will reset mac address registers too,
946 * so need to reconfigure it.
948 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
949 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
950 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
951 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
954 /* Clear any outstanding interrupt. */
955 writel(0xffffffff, fep->hwp + FEC_IEVENT);
957 fec_enet_bd_init(ndev);
959 fec_enet_enable_ring(ndev);
961 /* Reset tx SKB buffers. */
962 fec_enet_reset_skb(ndev);
964 /* Enable MII mode */
965 if (fep->full_duplex == DUPLEX_FULL) {
967 writel(0x04, fep->hwp + FEC_X_CNTRL);
971 writel(0x0, fep->hwp + FEC_X_CNTRL);
975 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
977 #if !defined(CONFIG_M5272)
978 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
979 /* set RX checksum */
980 val = readl(fep->hwp + FEC_RACC);
981 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
982 val |= FEC_RACC_OPTIONS;
984 val &= ~FEC_RACC_OPTIONS;
985 writel(val, fep->hwp + FEC_RACC);
990 * The phy interface and speed need to get configured
991 * differently on enet-mac.
993 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
994 /* Enable flow control and length check */
995 rcntl |= 0x40000000 | 0x00000020;
997 /* RGMII, RMII or MII */
998 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
999 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1000 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1001 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1003 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1008 /* 1G, 100M or 10M */
1010 if (fep->phy_dev->speed == SPEED_1000)
1012 else if (fep->phy_dev->speed == SPEED_100)
1018 #ifdef FEC_MIIGSK_ENR
1019 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1021 /* disable the gasket and wait */
1022 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1023 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1027 * configure the gasket:
1028 * RMII, 50 MHz, no loopback, no echo
1029 * MII, 25 MHz, no loopback, no echo
1031 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1032 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1033 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1034 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1035 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1037 /* re-enable the gasket */
1038 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1043 #if !defined(CONFIG_M5272)
1044 /* enable pause frame*/
1045 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1046 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1047 fep->phy_dev && fep->phy_dev->pause)) {
1048 rcntl |= FEC_ENET_FCE;
1050 /* set FIFO threshold parameter to reduce overrun */
1051 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1052 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1053 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1054 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1057 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1059 rcntl &= ~FEC_ENET_FCE;
1061 #endif /* !defined(CONFIG_M5272) */
1063 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1065 /* Setup multicast filter. */
1066 set_multicast_list(ndev);
1067 #ifndef CONFIG_M5272
1068 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1069 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1072 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1073 /* enable ENET endian swap */
1075 /* enable ENET store and forward mode */
1076 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1079 if (fep->bufdesc_ex)
1082 #ifndef CONFIG_M5272
1083 /* Enable the MIB statistic event counters */
1084 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1087 /* And last, enable the transmit and receive processing */
1088 writel(ecntl, fep->hwp + FEC_ECNTRL);
1089 fec_enet_active_rxring(ndev);
1091 if (fep->bufdesc_ex)
1092 fec_ptp_start_cyclecounter(ndev);
1094 /* Enable interrupts we wish to service */
1096 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1098 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1100 /* Init the interrupt coalescing */
1101 fec_enet_itr_coal_init(ndev);
1106 fec_stop(struct net_device *ndev)
1108 struct fec_enet_private *fep = netdev_priv(ndev);
1109 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1110 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1113 /* We cannot expect a graceful transmit stop without link !!! */
1115 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1117 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1118 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1121 /* Whack a reset. We should wait for this.
1122 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1123 * instead of reset MAC itself.
1125 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1126 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1127 writel(0, fep->hwp + FEC_ECNTRL);
1129 writel(1, fep->hwp + FEC_ECNTRL);
1132 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1134 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1135 val = readl(fep->hwp + FEC_ECNTRL);
1136 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1137 writel(val, fep->hwp + FEC_ECNTRL);
1139 if (pdata && pdata->sleep_mode_enable)
1140 pdata->sleep_mode_enable(true);
1142 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1144 /* We have to keep ENET enabled to have MII interrupt stay working */
1145 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1146 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1147 writel(2, fep->hwp + FEC_ECNTRL);
1148 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1154 fec_timeout(struct net_device *ndev)
1156 struct fec_enet_private *fep = netdev_priv(ndev);
1160 ndev->stats.tx_errors++;
1162 schedule_work(&fep->tx_timeout_work);
1165 static void fec_enet_timeout_work(struct work_struct *work)
1167 struct fec_enet_private *fep =
1168 container_of(work, struct fec_enet_private, tx_timeout_work);
1169 struct net_device *ndev = fep->netdev;
1172 if (netif_device_present(ndev) || netif_running(ndev)) {
1173 napi_disable(&fep->napi);
1174 netif_tx_lock_bh(ndev);
1176 netif_wake_queue(ndev);
1177 netif_tx_unlock_bh(ndev);
1178 napi_enable(&fep->napi);
1184 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1185 struct skb_shared_hwtstamps *hwtstamps)
1187 unsigned long flags;
1190 spin_lock_irqsave(&fep->tmreg_lock, flags);
1191 ns = timecounter_cyc2time(&fep->tc, ts);
1192 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1194 memset(hwtstamps, 0, sizeof(*hwtstamps));
1195 hwtstamps->hwtstamp = ns_to_ktime(ns);
1199 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1201 struct fec_enet_private *fep;
1202 struct bufdesc *bdp;
1203 unsigned short status;
1204 struct sk_buff *skb;
1205 struct fec_enet_priv_tx_q *txq;
1206 struct netdev_queue *nq;
1210 fep = netdev_priv(ndev);
1212 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1214 txq = fep->tx_queue[queue_id];
1215 /* get next bdp of dirty_tx */
1216 nq = netdev_get_tx_queue(ndev, queue_id);
1217 bdp = txq->dirty_tx;
1219 /* get next bdp of dirty_tx */
1220 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1222 while (bdp != READ_ONCE(txq->cur_tx)) {
1223 /* Order the load of cur_tx and cbd_sc */
1225 status = READ_ONCE(bdp->cbd_sc);
1226 if (status & BD_ENET_TX_READY)
1229 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1231 skb = txq->tx_skbuff[index];
1232 txq->tx_skbuff[index] = NULL;
1233 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1234 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1235 bdp->cbd_datlen, DMA_TO_DEVICE);
1236 bdp->cbd_bufaddr = 0;
1238 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1242 /* Check for errors. */
1243 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1244 BD_ENET_TX_RL | BD_ENET_TX_UN |
1246 ndev->stats.tx_errors++;
1247 if (status & BD_ENET_TX_HB) /* No heartbeat */
1248 ndev->stats.tx_heartbeat_errors++;
1249 if (status & BD_ENET_TX_LC) /* Late collision */
1250 ndev->stats.tx_window_errors++;
1251 if (status & BD_ENET_TX_RL) /* Retrans limit */
1252 ndev->stats.tx_aborted_errors++;
1253 if (status & BD_ENET_TX_UN) /* Underrun */
1254 ndev->stats.tx_fifo_errors++;
1255 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1256 ndev->stats.tx_carrier_errors++;
1258 ndev->stats.tx_packets++;
1259 ndev->stats.tx_bytes += skb->len;
1262 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1264 struct skb_shared_hwtstamps shhwtstamps;
1265 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1267 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
1268 skb_tstamp_tx(skb, &shhwtstamps);
1271 /* Deferred means some collisions occurred during transmit,
1272 * but we eventually sent the packet OK.
1274 if (status & BD_ENET_TX_DEF)
1275 ndev->stats.collisions++;
1277 /* Free the sk buffer associated with this last transmit */
1278 dev_kfree_skb_any(skb);
1280 /* Make sure the update to bdp and tx_skbuff are performed
1284 txq->dirty_tx = bdp;
1286 /* Update pointer to next buffer descriptor to be transmitted */
1287 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1289 /* Since we have freed up a buffer, the ring is no longer full
1291 if (netif_queue_stopped(ndev)) {
1292 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1293 if (entries_free >= txq->tx_wake_threshold)
1294 netif_tx_wake_queue(nq);
1298 /* ERR006538: Keep the transmitter going */
1299 if (bdp != txq->cur_tx &&
1300 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1301 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1305 fec_enet_tx(struct net_device *ndev)
1307 struct fec_enet_private *fep = netdev_priv(ndev);
1309 /* First process class A queue, then Class B and Best Effort queue */
1310 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1311 clear_bit(queue_id, &fep->work_tx);
1312 fec_enet_tx_queue(ndev, queue_id);
1318 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1320 struct fec_enet_private *fep = netdev_priv(ndev);
1323 off = ((unsigned long)skb->data) & fep->rx_align;
1325 skb_reserve(skb, fep->rx_align + 1 - off);
1327 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1328 FEC_ENET_RX_FRSIZE - fep->rx_align,
1330 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1331 if (net_ratelimit())
1332 netdev_err(ndev, "Rx DMA memory map failed\n");
1339 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1340 struct bufdesc *bdp, u32 length, bool swap)
1342 struct fec_enet_private *fep = netdev_priv(ndev);
1343 struct sk_buff *new_skb;
1345 if (length > fep->rx_copybreak)
1348 new_skb = netdev_alloc_skb(ndev, length);
1352 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1353 FEC_ENET_RX_FRSIZE - fep->rx_align,
1356 memcpy(new_skb->data, (*skb)->data, length);
1358 swap_buffer2(new_skb->data, (*skb)->data, length);
1364 /* During a receive, the cur_rx points to the current incoming buffer.
1365 * When we update through the ring, if the next incoming buffer has
1366 * not been given to the system, we just set the empty indicator,
1367 * effectively tossing the packet.
1370 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1372 struct fec_enet_private *fep = netdev_priv(ndev);
1373 struct fec_enet_priv_rx_q *rxq;
1374 struct bufdesc *bdp;
1375 unsigned short status;
1376 struct sk_buff *skb_new = NULL;
1377 struct sk_buff *skb;
1380 int pkt_received = 0;
1381 struct bufdesc_ex *ebdp = NULL;
1382 bool vlan_packet_rcvd = false;
1386 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1391 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1392 rxq = fep->rx_queue[queue_id];
1394 /* First, grab all of the stats for the incoming packet.
1395 * These get messed up if we get called due to a busy condition.
1399 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1401 if (pkt_received >= budget)
1405 /* Since we have allocated space to hold a complete frame,
1406 * the last indicator should be set.
1408 if ((status & BD_ENET_RX_LAST) == 0)
1409 netdev_err(ndev, "rcv is not +last\n");
1411 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1413 /* Check for errors. */
1414 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1415 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1416 ndev->stats.rx_errors++;
1417 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1418 /* Frame too long or too short. */
1419 ndev->stats.rx_length_errors++;
1421 if (status & BD_ENET_RX_NO) /* Frame alignment */
1422 ndev->stats.rx_frame_errors++;
1423 if (status & BD_ENET_RX_CR) /* CRC Error */
1424 ndev->stats.rx_crc_errors++;
1425 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1426 ndev->stats.rx_fifo_errors++;
1429 /* Report late collisions as a frame error.
1430 * On this error, the BD is closed, but we don't know what we
1431 * have in the buffer. So, just drop this frame on the floor.
1433 if (status & BD_ENET_RX_CL) {
1434 ndev->stats.rx_errors++;
1435 ndev->stats.rx_frame_errors++;
1436 goto rx_processing_done;
1439 /* Process the incoming frame. */
1440 ndev->stats.rx_packets++;
1441 pkt_len = bdp->cbd_datlen;
1442 ndev->stats.rx_bytes += pkt_len;
1444 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1445 skb = rxq->rx_skbuff[index];
1447 /* The packet length includes FCS, but we don't want to
1448 * include that when passing upstream as it messes up
1449 * bridging applications.
1451 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1453 if (!is_copybreak) {
1454 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1455 if (unlikely(!skb_new)) {
1456 ndev->stats.rx_dropped++;
1457 goto rx_processing_done;
1459 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1460 FEC_ENET_RX_FRSIZE - fep->rx_align,
1464 prefetch(skb->data - NET_IP_ALIGN);
1465 skb_put(skb, pkt_len - 4);
1467 if (!is_copybreak && need_swap)
1468 swap_buffer(data, pkt_len);
1470 /* Extract the enhanced buffer descriptor */
1472 if (fep->bufdesc_ex)
1473 ebdp = (struct bufdesc_ex *)bdp;
1475 /* If this is a VLAN packet remove the VLAN Tag */
1476 vlan_packet_rcvd = false;
1477 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1478 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1479 /* Push and remove the vlan tag */
1480 struct vlan_hdr *vlan_header =
1481 (struct vlan_hdr *) (data + ETH_HLEN);
1482 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1484 vlan_packet_rcvd = true;
1486 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1487 skb_pull(skb, VLAN_HLEN);
1490 skb->protocol = eth_type_trans(skb, ndev);
1492 /* Get receive timestamp from the skb */
1493 if (fep->hwts_rx_en && fep->bufdesc_ex)
1494 fec_enet_hwtstamp(fep, ebdp->ts,
1495 skb_hwtstamps(skb));
1497 if (fep->bufdesc_ex &&
1498 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1499 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1500 /* don't check it */
1501 skb->ip_summed = CHECKSUM_UNNECESSARY;
1503 skb_checksum_none_assert(skb);
1507 /* Handle received VLAN packets */
1508 if (vlan_packet_rcvd)
1509 __vlan_hwaccel_put_tag(skb,
1513 napi_gro_receive(&fep->napi, skb);
1516 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1517 FEC_ENET_RX_FRSIZE - fep->rx_align,
1520 rxq->rx_skbuff[index] = skb_new;
1521 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1525 /* Clear the status flags for this buffer */
1526 status &= ~BD_ENET_RX_STATS;
1528 /* Mark the buffer empty */
1529 status |= BD_ENET_RX_EMPTY;
1530 bdp->cbd_sc = status;
1532 if (fep->bufdesc_ex) {
1533 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1535 ebdp->cbd_esc = BD_ENET_RX_INT;
1540 /* Update BD pointer to next entry */
1541 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1543 /* Doing this here will keep the FEC running while we process
1544 * incoming frames. On a heavily loaded network, we should be
1545 * able to keep up at the expense of system resources.
1547 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1550 return pkt_received;
1554 fec_enet_rx(struct net_device *ndev, int budget)
1556 int pkt_received = 0;
1558 struct fec_enet_private *fep = netdev_priv(ndev);
1560 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1563 ret = fec_enet_rx_queue(ndev,
1564 budget - pkt_received, queue_id);
1566 if (ret < budget - pkt_received)
1567 clear_bit(queue_id, &fep->work_rx);
1569 pkt_received += ret;
1571 return pkt_received;
1575 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1577 if (int_events == 0)
1580 if (int_events & FEC_ENET_RXF)
1581 fep->work_rx |= (1 << 2);
1582 if (int_events & FEC_ENET_RXF_1)
1583 fep->work_rx |= (1 << 0);
1584 if (int_events & FEC_ENET_RXF_2)
1585 fep->work_rx |= (1 << 1);
1587 if (int_events & FEC_ENET_TXF)
1588 fep->work_tx |= (1 << 2);
1589 if (int_events & FEC_ENET_TXF_1)
1590 fep->work_tx |= (1 << 0);
1591 if (int_events & FEC_ENET_TXF_2)
1592 fep->work_tx |= (1 << 1);
1598 fec_enet_interrupt(int irq, void *dev_id)
1600 struct net_device *ndev = dev_id;
1601 struct fec_enet_private *fep = netdev_priv(ndev);
1603 irqreturn_t ret = IRQ_NONE;
1605 int_events = readl(fep->hwp + FEC_IEVENT);
1606 writel(int_events, fep->hwp + FEC_IEVENT);
1607 fec_enet_collect_events(fep, int_events);
1609 if ((fep->work_tx || fep->work_rx) && fep->link) {
1612 if (napi_schedule_prep(&fep->napi)) {
1613 /* Disable the NAPI interrupts */
1614 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1615 __napi_schedule(&fep->napi);
1619 if (int_events & FEC_ENET_MII) {
1621 complete(&fep->mdio_done);
1625 fec_ptp_check_pps_event(fep);
1630 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1632 struct net_device *ndev = napi->dev;
1633 struct fec_enet_private *fep = netdev_priv(ndev);
1636 pkts = fec_enet_rx(ndev, budget);
1640 if (pkts < budget) {
1641 napi_complete(napi);
1642 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1647 /* ------------------------------------------------------------------------- */
1648 static void fec_get_mac(struct net_device *ndev)
1650 struct fec_enet_private *fep = netdev_priv(ndev);
1651 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1652 unsigned char *iap, tmpaddr[ETH_ALEN];
1655 * try to get mac address in following order:
1657 * 1) module parameter via kernel command line in form
1658 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1663 * 2) from device tree data
1665 if (!is_valid_ether_addr(iap)) {
1666 struct device_node *np = fep->pdev->dev.of_node;
1668 const char *mac = of_get_mac_address(np);
1670 iap = (unsigned char *) mac;
1675 * 3) from flash or fuse (via platform data)
1677 if (!is_valid_ether_addr(iap)) {
1680 iap = (unsigned char *)FEC_FLASHMAC;
1683 iap = (unsigned char *)&pdata->mac;
1688 * 4) FEC mac registers set by bootloader
1690 if (!is_valid_ether_addr(iap)) {
1691 *((__be32 *) &tmpaddr[0]) =
1692 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1693 *((__be16 *) &tmpaddr[4]) =
1694 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1699 * 5) random mac address
1701 if (!is_valid_ether_addr(iap)) {
1702 /* Report it and use a random ethernet address instead */
1703 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1704 eth_hw_addr_random(ndev);
1705 netdev_info(ndev, "Using random MAC address: %pM\n",
1710 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1712 /* Adjust MAC if using macaddr */
1714 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1717 /* ------------------------------------------------------------------------- */
1722 static void fec_enet_adjust_link(struct net_device *ndev)
1724 struct fec_enet_private *fep = netdev_priv(ndev);
1725 struct phy_device *phy_dev = fep->phy_dev;
1726 int status_change = 0;
1728 /* Prevent a state halted on mii error */
1729 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1730 phy_dev->state = PHY_RESUMING;
1735 * If the netdev is down, or is going down, we're not interested
1736 * in link state events, so just mark our idea of the link as down
1737 * and ignore the event.
1739 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1741 } else if (phy_dev->link) {
1743 fep->link = phy_dev->link;
1747 if (fep->full_duplex != phy_dev->duplex) {
1748 fep->full_duplex = phy_dev->duplex;
1752 if (phy_dev->speed != fep->speed) {
1753 fep->speed = phy_dev->speed;
1757 /* if any of the above changed restart the FEC */
1758 if (status_change) {
1759 napi_disable(&fep->napi);
1760 netif_tx_lock_bh(ndev);
1762 netif_wake_queue(ndev);
1763 netif_tx_unlock_bh(ndev);
1764 napi_enable(&fep->napi);
1768 napi_disable(&fep->napi);
1769 netif_tx_lock_bh(ndev);
1771 netif_tx_unlock_bh(ndev);
1772 napi_enable(&fep->napi);
1773 fep->link = phy_dev->link;
1779 phy_print_status(phy_dev);
1782 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1784 struct fec_enet_private *fep = bus->priv;
1785 struct device *dev = &fep->pdev->dev;
1786 unsigned long time_left;
1789 ret = pm_runtime_get_sync(dev);
1793 fep->mii_timeout = 0;
1794 reinit_completion(&fep->mdio_done);
1796 /* start a read op */
1797 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1798 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1799 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1801 /* wait for end of transfer */
1802 time_left = wait_for_completion_timeout(&fep->mdio_done,
1803 usecs_to_jiffies(FEC_MII_TIMEOUT));
1804 if (time_left == 0) {
1805 fep->mii_timeout = 1;
1806 netdev_err(fep->netdev, "MDIO read timeout\n");
1811 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1814 pm_runtime_mark_last_busy(dev);
1815 pm_runtime_put_autosuspend(dev);
1820 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1823 struct fec_enet_private *fep = bus->priv;
1824 struct device *dev = &fep->pdev->dev;
1825 unsigned long time_left;
1828 ret = pm_runtime_get_sync(dev);
1834 fep->mii_timeout = 0;
1835 reinit_completion(&fep->mdio_done);
1837 /* start a write op */
1838 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1839 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1840 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1841 fep->hwp + FEC_MII_DATA);
1843 /* wait for end of transfer */
1844 time_left = wait_for_completion_timeout(&fep->mdio_done,
1845 usecs_to_jiffies(FEC_MII_TIMEOUT));
1846 if (time_left == 0) {
1847 fep->mii_timeout = 1;
1848 netdev_err(fep->netdev, "MDIO write timeout\n");
1852 pm_runtime_mark_last_busy(dev);
1853 pm_runtime_put_autosuspend(dev);
1858 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1860 struct fec_enet_private *fep = netdev_priv(ndev);
1864 ret = clk_prepare_enable(fep->clk_ahb);
1867 if (fep->clk_enet_out) {
1868 ret = clk_prepare_enable(fep->clk_enet_out);
1870 goto failed_clk_enet_out;
1872 fec_reset_phy(fep->pdev);
1875 mutex_lock(&fep->ptp_clk_mutex);
1876 ret = clk_prepare_enable(fep->clk_ptp);
1878 mutex_unlock(&fep->ptp_clk_mutex);
1879 goto failed_clk_ptp;
1881 fep->ptp_clk_on = true;
1883 mutex_unlock(&fep->ptp_clk_mutex);
1886 ret = clk_prepare_enable(fep->clk_ref);
1888 goto failed_clk_ref;
1890 clk_disable_unprepare(fep->clk_ahb);
1891 clk_disable_unprepare(fep->clk_enet_out);
1893 mutex_lock(&fep->ptp_clk_mutex);
1894 clk_disable_unprepare(fep->clk_ptp);
1895 fep->ptp_clk_on = false;
1896 mutex_unlock(&fep->ptp_clk_mutex);
1898 clk_disable_unprepare(fep->clk_ref);
1904 clk_disable_unprepare(fep->clk_ref);
1906 clk_disable_unprepare(fep->clk_enet_out);
1907 failed_clk_enet_out:
1908 clk_disable_unprepare(fep->clk_ahb);
1913 static int fec_enet_mii_probe(struct net_device *ndev)
1915 struct fec_enet_private *fep = netdev_priv(ndev);
1916 struct phy_device *phy_dev = NULL;
1917 char mdio_bus_id[MII_BUS_ID_SIZE];
1918 char phy_name[MII_BUS_ID_SIZE + 3];
1920 int dev_id = fep->dev_id;
1922 fep->phy_dev = NULL;
1924 if (fep->phy_node) {
1925 phy_dev = of_phy_connect(ndev, fep->phy_node,
1926 &fec_enet_adjust_link, 0,
1927 fep->phy_interface);
1931 /* check for attached phy */
1932 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1933 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1935 if (fep->mii_bus->phy_map[phy_id] == NULL)
1937 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1941 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1945 if (phy_id >= PHY_MAX_ADDR) {
1946 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1947 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1951 snprintf(phy_name, sizeof(phy_name),
1952 PHY_ID_FMT, mdio_bus_id, phy_id);
1953 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1954 fep->phy_interface);
1957 if (IS_ERR(phy_dev)) {
1958 netdev_err(ndev, "could not attach to PHY\n");
1959 return PTR_ERR(phy_dev);
1962 /* mask with MAC supported features */
1963 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1964 phy_dev->supported &= PHY_GBIT_FEATURES;
1965 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1966 #if !defined(CONFIG_M5272)
1967 phy_dev->supported |= SUPPORTED_Pause;
1971 phy_dev->supported &= PHY_BASIC_FEATURES;
1973 phy_dev->advertising = phy_dev->supported;
1975 fep->phy_dev = phy_dev;
1977 fep->full_duplex = 0;
1979 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1980 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1986 static int fec_enet_mii_init(struct platform_device *pdev)
1988 static struct mii_bus *fec0_mii_bus;
1989 struct net_device *ndev = platform_get_drvdata(pdev);
1990 struct fec_enet_private *fep = netdev_priv(ndev);
1991 struct device_node *node;
1992 int err = -ENXIO, i;
1993 u32 mii_speed, holdtime;
1996 * The i.MX28 dual fec interfaces are not equal.
1997 * Here are the differences:
1999 * - fec0 supports MII & RMII modes while fec1 only supports RMII
2000 * - fec0 acts as the 1588 time master while fec1 is slave
2001 * - external phys can only be configured by fec0
2003 * That is to say fec1 can not work independently. It only works
2004 * when fec0 is working. The reason behind this design is that the
2005 * second interface is added primarily for Switch mode.
2007 * Because of the last point above, both phys are attached on fec0
2008 * mdio interface in board design, and need to be configured by
2011 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2012 /* fec1 uses fec0 mii_bus */
2013 if (mii_cnt && fec0_mii_bus) {
2014 fep->mii_bus = fec0_mii_bus;
2021 fep->mii_timeout = 0;
2024 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2026 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2027 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2028 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2031 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2032 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2034 if (mii_speed > 63) {
2036 "fec clock (%lu) to fast to get right mii speed\n",
2037 clk_get_rate(fep->clk_ipg));
2043 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2044 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2045 * versions are RAZ there, so just ignore the difference and write the
2047 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2048 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2050 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2051 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2052 * holdtime cannot result in a value greater than 3.
2054 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2056 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2058 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2060 fep->mii_bus = mdiobus_alloc();
2061 if (fep->mii_bus == NULL) {
2066 fep->mii_bus->name = "fec_enet_mii_bus";
2067 fep->mii_bus->read = fec_enet_mdio_read;
2068 fep->mii_bus->write = fec_enet_mdio_write;
2069 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2070 pdev->name, fep->dev_id + 1);
2071 fep->mii_bus->priv = fep;
2072 fep->mii_bus->parent = &pdev->dev;
2074 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
2075 if (!fep->mii_bus->irq) {
2077 goto err_out_free_mdiobus;
2080 for (i = 0; i < PHY_MAX_ADDR; i++)
2081 fep->mii_bus->irq[i] = PHY_POLL;
2083 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2085 err = of_mdiobus_register(fep->mii_bus, node);
2088 err = mdiobus_register(fep->mii_bus);
2092 goto err_out_free_mdio_irq;
2096 /* save fec0 mii_bus */
2097 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2098 fec0_mii_bus = fep->mii_bus;
2102 err_out_free_mdio_irq:
2103 kfree(fep->mii_bus->irq);
2104 err_out_free_mdiobus:
2105 mdiobus_free(fep->mii_bus);
2110 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2112 if (--mii_cnt == 0) {
2113 mdiobus_unregister(fep->mii_bus);
2114 kfree(fep->mii_bus->irq);
2115 mdiobus_free(fep->mii_bus);
2119 static int fec_enet_get_settings(struct net_device *ndev,
2120 struct ethtool_cmd *cmd)
2122 struct fec_enet_private *fep = netdev_priv(ndev);
2123 struct phy_device *phydev = fep->phy_dev;
2128 return phy_ethtool_gset(phydev, cmd);
2131 static int fec_enet_set_settings(struct net_device *ndev,
2132 struct ethtool_cmd *cmd)
2134 struct fec_enet_private *fep = netdev_priv(ndev);
2135 struct phy_device *phydev = fep->phy_dev;
2140 return phy_ethtool_sset(phydev, cmd);
2143 static void fec_enet_get_drvinfo(struct net_device *ndev,
2144 struct ethtool_drvinfo *info)
2146 struct fec_enet_private *fep = netdev_priv(ndev);
2148 strlcpy(info->driver, fep->pdev->dev.driver->name,
2149 sizeof(info->driver));
2150 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2151 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2154 static int fec_enet_get_regs_len(struct net_device *ndev)
2156 struct fec_enet_private *fep = netdev_priv(ndev);
2160 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2162 s = resource_size(r);
2167 /* List of registers that can be safety be read to dump them with ethtool */
2168 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2169 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
2170 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
2171 static u32 fec_enet_register_offset[] = {
2172 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2173 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2174 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2175 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2176 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2177 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2178 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2179 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2180 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2181 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2182 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2183 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2184 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2185 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2186 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2187 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2188 RMON_T_P_GTE2048, RMON_T_OCTETS,
2189 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2190 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2191 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2192 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2193 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2194 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2195 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2196 RMON_R_P_GTE2048, RMON_R_OCTETS,
2197 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2198 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2201 static u32 fec_enet_register_offset[] = {
2202 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2203 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2204 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2205 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2206 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2207 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2208 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2209 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2210 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2214 static void fec_enet_get_regs(struct net_device *ndev,
2215 struct ethtool_regs *regs, void *regbuf)
2217 struct fec_enet_private *fep = netdev_priv(ndev);
2218 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2219 u32 *buf = (u32 *)regbuf;
2222 memset(buf, 0, regs->len);
2224 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2225 off = fec_enet_register_offset[i] / 4;
2226 buf[off] = readl(&theregs[off]);
2230 static int fec_enet_get_ts_info(struct net_device *ndev,
2231 struct ethtool_ts_info *info)
2233 struct fec_enet_private *fep = netdev_priv(ndev);
2235 if (fep->bufdesc_ex) {
2237 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2238 SOF_TIMESTAMPING_RX_SOFTWARE |
2239 SOF_TIMESTAMPING_SOFTWARE |
2240 SOF_TIMESTAMPING_TX_HARDWARE |
2241 SOF_TIMESTAMPING_RX_HARDWARE |
2242 SOF_TIMESTAMPING_RAW_HARDWARE;
2244 info->phc_index = ptp_clock_index(fep->ptp_clock);
2246 info->phc_index = -1;
2248 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2249 (1 << HWTSTAMP_TX_ON);
2251 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2252 (1 << HWTSTAMP_FILTER_ALL);
2255 return ethtool_op_get_ts_info(ndev, info);
2259 #if !defined(CONFIG_M5272)
2261 static void fec_enet_get_pauseparam(struct net_device *ndev,
2262 struct ethtool_pauseparam *pause)
2264 struct fec_enet_private *fep = netdev_priv(ndev);
2266 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2267 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2268 pause->rx_pause = pause->tx_pause;
2271 static int fec_enet_set_pauseparam(struct net_device *ndev,
2272 struct ethtool_pauseparam *pause)
2274 struct fec_enet_private *fep = netdev_priv(ndev);
2279 if (pause->tx_pause != pause->rx_pause) {
2281 "hardware only support enable/disable both tx and rx");
2285 fep->pause_flag = 0;
2287 /* tx pause must be same as rx pause */
2288 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2289 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2291 if (pause->rx_pause || pause->autoneg) {
2292 fep->phy_dev->supported |= ADVERTISED_Pause;
2293 fep->phy_dev->advertising |= ADVERTISED_Pause;
2295 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2296 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2299 if (pause->autoneg) {
2300 if (netif_running(ndev))
2302 phy_start_aneg(fep->phy_dev);
2304 if (netif_running(ndev)) {
2305 napi_disable(&fep->napi);
2306 netif_tx_lock_bh(ndev);
2308 netif_wake_queue(ndev);
2309 netif_tx_unlock_bh(ndev);
2310 napi_enable(&fep->napi);
2316 static const struct fec_stat {
2317 char name[ETH_GSTRING_LEN];
2321 { "tx_dropped", RMON_T_DROP },
2322 { "tx_packets", RMON_T_PACKETS },
2323 { "tx_broadcast", RMON_T_BC_PKT },
2324 { "tx_multicast", RMON_T_MC_PKT },
2325 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2326 { "tx_undersize", RMON_T_UNDERSIZE },
2327 { "tx_oversize", RMON_T_OVERSIZE },
2328 { "tx_fragment", RMON_T_FRAG },
2329 { "tx_jabber", RMON_T_JAB },
2330 { "tx_collision", RMON_T_COL },
2331 { "tx_64byte", RMON_T_P64 },
2332 { "tx_65to127byte", RMON_T_P65TO127 },
2333 { "tx_128to255byte", RMON_T_P128TO255 },
2334 { "tx_256to511byte", RMON_T_P256TO511 },
2335 { "tx_512to1023byte", RMON_T_P512TO1023 },
2336 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2337 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2338 { "tx_octets", RMON_T_OCTETS },
2341 { "IEEE_tx_drop", IEEE_T_DROP },
2342 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2343 { "IEEE_tx_1col", IEEE_T_1COL },
2344 { "IEEE_tx_mcol", IEEE_T_MCOL },
2345 { "IEEE_tx_def", IEEE_T_DEF },
2346 { "IEEE_tx_lcol", IEEE_T_LCOL },
2347 { "IEEE_tx_excol", IEEE_T_EXCOL },
2348 { "IEEE_tx_macerr", IEEE_T_MACERR },
2349 { "IEEE_tx_cserr", IEEE_T_CSERR },
2350 { "IEEE_tx_sqe", IEEE_T_SQE },
2351 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2352 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2355 { "rx_packets", RMON_R_PACKETS },
2356 { "rx_broadcast", RMON_R_BC_PKT },
2357 { "rx_multicast", RMON_R_MC_PKT },
2358 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2359 { "rx_undersize", RMON_R_UNDERSIZE },
2360 { "rx_oversize", RMON_R_OVERSIZE },
2361 { "rx_fragment", RMON_R_FRAG },
2362 { "rx_jabber", RMON_R_JAB },
2363 { "rx_64byte", RMON_R_P64 },
2364 { "rx_65to127byte", RMON_R_P65TO127 },
2365 { "rx_128to255byte", RMON_R_P128TO255 },
2366 { "rx_256to511byte", RMON_R_P256TO511 },
2367 { "rx_512to1023byte", RMON_R_P512TO1023 },
2368 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2369 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2370 { "rx_octets", RMON_R_OCTETS },
2373 { "IEEE_rx_drop", IEEE_R_DROP },
2374 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2375 { "IEEE_rx_crc", IEEE_R_CRC },
2376 { "IEEE_rx_align", IEEE_R_ALIGN },
2377 { "IEEE_rx_macerr", IEEE_R_MACERR },
2378 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2379 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2382 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2383 struct ethtool_stats *stats, u64 *data)
2385 struct fec_enet_private *fep = netdev_priv(dev);
2388 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2389 data[i] = readl(fep->hwp + fec_stats[i].offset);
2392 static void fec_enet_get_strings(struct net_device *netdev,
2393 u32 stringset, u8 *data)
2396 switch (stringset) {
2398 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2399 memcpy(data + i * ETH_GSTRING_LEN,
2400 fec_stats[i].name, ETH_GSTRING_LEN);
2405 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2409 return ARRAY_SIZE(fec_stats);
2414 #endif /* !defined(CONFIG_M5272) */
2416 static int fec_enet_nway_reset(struct net_device *dev)
2418 struct fec_enet_private *fep = netdev_priv(dev);
2419 struct phy_device *phydev = fep->phy_dev;
2424 return genphy_restart_aneg(phydev);
2427 /* ITR clock source is enet system clock (clk_ahb).
2428 * TCTT unit is cycle_ns * 64 cycle
2429 * So, the ICTT value = X us / (cycle_ns * 64)
2431 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2433 struct fec_enet_private *fep = netdev_priv(ndev);
2435 return us * (fep->itr_clk_rate / 64000) / 1000;
2438 /* Set threshold for interrupt coalescing */
2439 static void fec_enet_itr_coal_set(struct net_device *ndev)
2441 struct fec_enet_private *fep = netdev_priv(ndev);
2444 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2447 /* Must be greater than zero to avoid unpredictable behavior */
2448 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2449 !fep->tx_time_itr || !fep->tx_pkts_itr)
2452 /* Select enet system clock as Interrupt Coalescing
2453 * timer Clock Source
2455 rx_itr = FEC_ITR_CLK_SEL;
2456 tx_itr = FEC_ITR_CLK_SEL;
2458 /* set ICFT and ICTT */
2459 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2460 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2461 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2462 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2464 rx_itr |= FEC_ITR_EN;
2465 tx_itr |= FEC_ITR_EN;
2467 writel(tx_itr, fep->hwp + FEC_TXIC0);
2468 writel(rx_itr, fep->hwp + FEC_RXIC0);
2469 writel(tx_itr, fep->hwp + FEC_TXIC1);
2470 writel(rx_itr, fep->hwp + FEC_RXIC1);
2471 writel(tx_itr, fep->hwp + FEC_TXIC2);
2472 writel(rx_itr, fep->hwp + FEC_RXIC2);
2476 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2478 struct fec_enet_private *fep = netdev_priv(ndev);
2480 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2483 ec->rx_coalesce_usecs = fep->rx_time_itr;
2484 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2486 ec->tx_coalesce_usecs = fep->tx_time_itr;
2487 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2493 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2495 struct fec_enet_private *fep = netdev_priv(ndev);
2498 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2501 if (ec->rx_max_coalesced_frames > 255) {
2502 pr_err("Rx coalesced frames exceed hardware limiation");
2506 if (ec->tx_max_coalesced_frames > 255) {
2507 pr_err("Tx coalesced frame exceed hardware limiation");
2511 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2512 if (cycle > 0xFFFF) {
2513 pr_err("Rx coalesed usec exceeed hardware limiation");
2517 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2518 if (cycle > 0xFFFF) {
2519 pr_err("Rx coalesed usec exceeed hardware limiation");
2523 fep->rx_time_itr = ec->rx_coalesce_usecs;
2524 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2526 fep->tx_time_itr = ec->tx_coalesce_usecs;
2527 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2529 fec_enet_itr_coal_set(ndev);
2534 static void fec_enet_itr_coal_init(struct net_device *ndev)
2536 struct ethtool_coalesce ec;
2538 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2539 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2541 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2542 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2544 fec_enet_set_coalesce(ndev, &ec);
2547 static int fec_enet_get_tunable(struct net_device *netdev,
2548 const struct ethtool_tunable *tuna,
2551 struct fec_enet_private *fep = netdev_priv(netdev);
2555 case ETHTOOL_RX_COPYBREAK:
2556 *(u32 *)data = fep->rx_copybreak;
2566 static int fec_enet_set_tunable(struct net_device *netdev,
2567 const struct ethtool_tunable *tuna,
2570 struct fec_enet_private *fep = netdev_priv(netdev);
2574 case ETHTOOL_RX_COPYBREAK:
2575 fep->rx_copybreak = *(u32 *)data;
2586 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2588 struct fec_enet_private *fep = netdev_priv(ndev);
2590 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2591 wol->supported = WAKE_MAGIC;
2592 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2594 wol->supported = wol->wolopts = 0;
2599 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2601 struct fec_enet_private *fep = netdev_priv(ndev);
2603 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2606 if (wol->wolopts & ~WAKE_MAGIC)
2609 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2610 if (device_may_wakeup(&ndev->dev)) {
2611 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2612 if (fep->irq[0] > 0)
2613 enable_irq_wake(fep->irq[0]);
2615 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2616 if (fep->irq[0] > 0)
2617 disable_irq_wake(fep->irq[0]);
2623 static const struct ethtool_ops fec_enet_ethtool_ops = {
2624 .get_settings = fec_enet_get_settings,
2625 .set_settings = fec_enet_set_settings,
2626 .get_drvinfo = fec_enet_get_drvinfo,
2627 .get_regs_len = fec_enet_get_regs_len,
2628 .get_regs = fec_enet_get_regs,
2629 .nway_reset = fec_enet_nway_reset,
2630 .get_link = ethtool_op_get_link,
2631 .get_coalesce = fec_enet_get_coalesce,
2632 .set_coalesce = fec_enet_set_coalesce,
2633 #ifndef CONFIG_M5272
2634 .get_pauseparam = fec_enet_get_pauseparam,
2635 .set_pauseparam = fec_enet_set_pauseparam,
2636 .get_strings = fec_enet_get_strings,
2637 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2638 .get_sset_count = fec_enet_get_sset_count,
2640 .get_ts_info = fec_enet_get_ts_info,
2641 .get_tunable = fec_enet_get_tunable,
2642 .set_tunable = fec_enet_set_tunable,
2643 .get_wol = fec_enet_get_wol,
2644 .set_wol = fec_enet_set_wol,
2647 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2649 struct fec_enet_private *fep = netdev_priv(ndev);
2650 struct phy_device *phydev = fep->phy_dev;
2652 if (!netif_running(ndev))
2658 if (fep->bufdesc_ex) {
2659 if (cmd == SIOCSHWTSTAMP)
2660 return fec_ptp_set(ndev, rq);
2661 if (cmd == SIOCGHWTSTAMP)
2662 return fec_ptp_get(ndev, rq);
2665 return phy_mii_ioctl(phydev, rq, cmd);
2668 static void fec_enet_free_buffers(struct net_device *ndev)
2670 struct fec_enet_private *fep = netdev_priv(ndev);
2672 struct sk_buff *skb;
2673 struct bufdesc *bdp;
2674 struct fec_enet_priv_tx_q *txq;
2675 struct fec_enet_priv_rx_q *rxq;
2678 for (q = 0; q < fep->num_rx_queues; q++) {
2679 rxq = fep->rx_queue[q];
2680 bdp = rxq->rx_bd_base;
2681 for (i = 0; i < rxq->rx_ring_size; i++) {
2682 skb = rxq->rx_skbuff[i];
2683 rxq->rx_skbuff[i] = NULL;
2685 dma_unmap_single(&fep->pdev->dev,
2687 FEC_ENET_RX_FRSIZE - fep->rx_align,
2691 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2695 for (q = 0; q < fep->num_tx_queues; q++) {
2696 txq = fep->tx_queue[q];
2697 bdp = txq->tx_bd_base;
2698 for (i = 0; i < txq->tx_ring_size; i++) {
2699 kfree(txq->tx_bounce[i]);
2700 txq->tx_bounce[i] = NULL;
2701 skb = txq->tx_skbuff[i];
2702 txq->tx_skbuff[i] = NULL;
2708 static void fec_enet_free_queue(struct net_device *ndev)
2710 struct fec_enet_private *fep = netdev_priv(ndev);
2712 struct fec_enet_priv_tx_q *txq;
2714 for (i = 0; i < fep->num_tx_queues; i++)
2715 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2716 txq = fep->tx_queue[i];
2717 dma_free_coherent(NULL,
2718 txq->tx_ring_size * TSO_HEADER_SIZE,
2723 for (i = 0; i < fep->num_rx_queues; i++)
2724 kfree(fep->rx_queue[i]);
2725 for (i = 0; i < fep->num_tx_queues; i++)
2726 kfree(fep->tx_queue[i]);
2729 static int fec_enet_alloc_queue(struct net_device *ndev)
2731 struct fec_enet_private *fep = netdev_priv(ndev);
2734 struct fec_enet_priv_tx_q *txq;
2736 for (i = 0; i < fep->num_tx_queues; i++) {
2737 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2743 fep->tx_queue[i] = txq;
2744 txq->tx_ring_size = TX_RING_SIZE;
2745 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2747 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2748 txq->tx_wake_threshold =
2749 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2751 txq->tso_hdrs = dma_alloc_coherent(NULL,
2752 txq->tx_ring_size * TSO_HEADER_SIZE,
2755 if (!txq->tso_hdrs) {
2761 for (i = 0; i < fep->num_rx_queues; i++) {
2762 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2764 if (!fep->rx_queue[i]) {
2769 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2770 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2775 fec_enet_free_queue(ndev);
2780 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2782 struct fec_enet_private *fep = netdev_priv(ndev);
2784 struct sk_buff *skb;
2785 struct bufdesc *bdp;
2786 struct fec_enet_priv_rx_q *rxq;
2788 rxq = fep->rx_queue[queue];
2789 bdp = rxq->rx_bd_base;
2790 for (i = 0; i < rxq->rx_ring_size; i++) {
2791 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2795 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2800 rxq->rx_skbuff[i] = skb;
2801 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2803 if (fep->bufdesc_ex) {
2804 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2805 ebdp->cbd_esc = BD_ENET_RX_INT;
2808 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2811 /* Set the last buffer to wrap. */
2812 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2813 bdp->cbd_sc |= BD_SC_WRAP;
2817 fec_enet_free_buffers(ndev);
2822 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2824 struct fec_enet_private *fep = netdev_priv(ndev);
2826 struct bufdesc *bdp;
2827 struct fec_enet_priv_tx_q *txq;
2829 txq = fep->tx_queue[queue];
2830 bdp = txq->tx_bd_base;
2831 for (i = 0; i < txq->tx_ring_size; i++) {
2832 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2833 if (!txq->tx_bounce[i])
2837 bdp->cbd_bufaddr = 0;
2839 if (fep->bufdesc_ex) {
2840 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2841 ebdp->cbd_esc = BD_ENET_TX_INT;
2844 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2847 /* Set the last buffer to wrap. */
2848 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2849 bdp->cbd_sc |= BD_SC_WRAP;
2854 fec_enet_free_buffers(ndev);
2858 static int fec_enet_alloc_buffers(struct net_device *ndev)
2860 struct fec_enet_private *fep = netdev_priv(ndev);
2863 for (i = 0; i < fep->num_rx_queues; i++)
2864 if (fec_enet_alloc_rxq_buffers(ndev, i))
2867 for (i = 0; i < fep->num_tx_queues; i++)
2868 if (fec_enet_alloc_txq_buffers(ndev, i))
2874 fec_enet_open(struct net_device *ndev)
2876 struct fec_enet_private *fep = netdev_priv(ndev);
2879 ret = pm_runtime_get_sync(&fep->pdev->dev);
2883 pinctrl_pm_select_default_state(&fep->pdev->dev);
2884 ret = fec_enet_clk_enable(ndev, true);
2888 /* I should reset the ring buffers here, but I don't yet know
2889 * a simple way to do that.
2892 ret = fec_enet_alloc_buffers(ndev);
2894 goto err_enet_alloc;
2896 /* Init MAC prior to mii bus probe */
2899 /* Probe and connect to PHY when open the interface */
2900 ret = fec_enet_mii_probe(ndev);
2902 goto err_enet_mii_probe;
2904 napi_enable(&fep->napi);
2905 phy_start(fep->phy_dev);
2906 netif_tx_start_all_queues(ndev);
2908 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2909 FEC_WOL_FLAG_ENABLE);
2914 fec_enet_free_buffers(ndev);
2916 fec_enet_clk_enable(ndev, false);
2918 pm_runtime_mark_last_busy(&fep->pdev->dev);
2919 pm_runtime_put_autosuspend(&fep->pdev->dev);
2920 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2925 fec_enet_close(struct net_device *ndev)
2927 struct fec_enet_private *fep = netdev_priv(ndev);
2929 phy_stop(fep->phy_dev);
2931 if (netif_device_present(ndev)) {
2932 napi_disable(&fep->napi);
2933 netif_tx_disable(ndev);
2937 phy_disconnect(fep->phy_dev);
2938 fep->phy_dev = NULL;
2940 fec_enet_clk_enable(ndev, false);
2941 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2942 pm_runtime_mark_last_busy(&fep->pdev->dev);
2943 pm_runtime_put_autosuspend(&fep->pdev->dev);
2945 fec_enet_free_buffers(ndev);
2950 /* Set or clear the multicast filter for this adaptor.
2951 * Skeleton taken from sunlance driver.
2952 * The CPM Ethernet implementation allows Multicast as well as individual
2953 * MAC address filtering. Some of the drivers check to make sure it is
2954 * a group multicast address, and discard those that are not. I guess I
2955 * will do the same for now, but just remove the test if you want
2956 * individual filtering as well (do the upper net layers want or support
2957 * this kind of feature?).
2960 #define HASH_BITS 6 /* #bits in hash */
2961 #define CRC32_POLY 0xEDB88320
2963 static void set_multicast_list(struct net_device *ndev)
2965 struct fec_enet_private *fep = netdev_priv(ndev);
2966 struct netdev_hw_addr *ha;
2967 unsigned int i, bit, data, crc, tmp;
2970 if (ndev->flags & IFF_PROMISC) {
2971 tmp = readl(fep->hwp + FEC_R_CNTRL);
2973 writel(tmp, fep->hwp + FEC_R_CNTRL);
2977 tmp = readl(fep->hwp + FEC_R_CNTRL);
2979 writel(tmp, fep->hwp + FEC_R_CNTRL);
2981 if (ndev->flags & IFF_ALLMULTI) {
2982 /* Catch all multicast addresses, so set the
2985 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2986 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2991 /* Clear filter and add the addresses in hash register
2993 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2994 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2996 netdev_for_each_mc_addr(ha, ndev) {
2997 /* calculate crc32 value of mac address */
3000 for (i = 0; i < ndev->addr_len; i++) {
3002 for (bit = 0; bit < 8; bit++, data >>= 1) {
3004 (((crc ^ data) & 1) ? CRC32_POLY : 0);
3008 /* only upper 6 bits (HASH_BITS) are used
3009 * which point to specific bit in he hash registers
3011 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
3014 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3015 tmp |= 1 << (hash - 32);
3016 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3018 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3020 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3025 /* Set a MAC change in hardware. */
3027 fec_set_mac_address(struct net_device *ndev, void *p)
3029 struct fec_enet_private *fep = netdev_priv(ndev);
3030 struct sockaddr *addr = p;
3033 if (!is_valid_ether_addr(addr->sa_data))
3034 return -EADDRNOTAVAIL;
3035 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3038 /* Add netif status check here to avoid system hang in below case:
3039 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3040 * After ethx down, fec all clocks are gated off and then register
3041 * access causes system hang.
3043 if (!netif_running(ndev))
3046 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3047 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3048 fep->hwp + FEC_ADDR_LOW);
3049 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3050 fep->hwp + FEC_ADDR_HIGH);
3054 #ifdef CONFIG_NET_POLL_CONTROLLER
3056 * fec_poll_controller - FEC Poll controller function
3057 * @dev: The FEC network adapter
3059 * Polled functionality used by netconsole and others in non interrupt mode
3062 static void fec_poll_controller(struct net_device *dev)
3065 struct fec_enet_private *fep = netdev_priv(dev);
3067 for (i = 0; i < FEC_IRQ_NUM; i++) {
3068 if (fep->irq[i] > 0) {
3069 disable_irq(fep->irq[i]);
3070 fec_enet_interrupt(fep->irq[i], dev);
3071 enable_irq(fep->irq[i]);
3077 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3078 netdev_features_t features)
3080 struct fec_enet_private *fep = netdev_priv(netdev);
3081 netdev_features_t changed = features ^ netdev->features;
3083 netdev->features = features;
3085 /* Receive checksum has been changed */
3086 if (changed & NETIF_F_RXCSUM) {
3087 if (features & NETIF_F_RXCSUM)
3088 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3090 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3094 static int fec_set_features(struct net_device *netdev,
3095 netdev_features_t features)
3097 struct fec_enet_private *fep = netdev_priv(netdev);
3098 netdev_features_t changed = features ^ netdev->features;
3100 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3101 napi_disable(&fep->napi);
3102 netif_tx_lock_bh(netdev);
3104 fec_enet_set_netdev_features(netdev, features);
3105 fec_restart(netdev);
3106 netif_tx_wake_all_queues(netdev);
3107 netif_tx_unlock_bh(netdev);
3108 napi_enable(&fep->napi);
3110 fec_enet_set_netdev_features(netdev, features);
3116 static const struct net_device_ops fec_netdev_ops = {
3117 .ndo_open = fec_enet_open,
3118 .ndo_stop = fec_enet_close,
3119 .ndo_start_xmit = fec_enet_start_xmit,
3120 .ndo_set_rx_mode = set_multicast_list,
3121 .ndo_change_mtu = eth_change_mtu,
3122 .ndo_validate_addr = eth_validate_addr,
3123 .ndo_tx_timeout = fec_timeout,
3124 .ndo_set_mac_address = fec_set_mac_address,
3125 .ndo_do_ioctl = fec_enet_ioctl,
3126 #ifdef CONFIG_NET_POLL_CONTROLLER
3127 .ndo_poll_controller = fec_poll_controller,
3129 .ndo_set_features = fec_set_features,
3133 * XXX: We need to clean up on failure exits here.
3136 static int fec_enet_init(struct net_device *ndev)
3138 struct fec_enet_private *fep = netdev_priv(ndev);
3139 struct fec_enet_priv_tx_q *txq;
3140 struct fec_enet_priv_rx_q *rxq;
3141 struct bufdesc *cbd_base;
3146 #if defined(CONFIG_ARM)
3147 fep->rx_align = 0xf;
3148 fep->tx_align = 0xf;
3150 fep->rx_align = 0x3;
3151 fep->tx_align = 0x3;
3154 fec_enet_alloc_queue(ndev);
3156 if (fep->bufdesc_ex)
3157 fep->bufdesc_size = sizeof(struct bufdesc_ex);
3159 fep->bufdesc_size = sizeof(struct bufdesc);
3160 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
3163 /* Allocate memory for buffer descriptors. */
3164 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3170 memset(cbd_base, 0, bd_size);
3172 /* Get the Ethernet address */
3174 /* make sure MAC we just acquired is programmed into the hw */
3175 fec_set_mac_address(ndev, NULL);
3177 /* Set receive and transmit descriptor base. */
3178 for (i = 0; i < fep->num_rx_queues; i++) {
3179 rxq = fep->rx_queue[i];
3181 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
3182 rxq->bd_dma = bd_dma;
3183 if (fep->bufdesc_ex) {
3184 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
3185 cbd_base = (struct bufdesc *)
3186 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
3188 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
3189 cbd_base += rxq->rx_ring_size;
3193 for (i = 0; i < fep->num_tx_queues; i++) {
3194 txq = fep->tx_queue[i];
3196 txq->tx_bd_base = (struct bufdesc *)cbd_base;
3197 txq->bd_dma = bd_dma;
3198 if (fep->bufdesc_ex) {
3199 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3200 cbd_base = (struct bufdesc *)
3201 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3203 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3204 cbd_base += txq->tx_ring_size;
3209 /* The FEC Ethernet specific entries in the device structure */
3210 ndev->watchdog_timeo = TX_TIMEOUT;
3211 ndev->netdev_ops = &fec_netdev_ops;
3212 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3214 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3215 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3217 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3218 /* enable hw VLAN support */
3219 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3221 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3222 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3224 /* enable hw accelerator */
3225 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3226 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3227 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3230 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3232 fep->rx_align = 0x3f;
3235 ndev->hw_features = ndev->features;
3243 static void fec_reset_phy(struct platform_device *pdev)
3245 struct net_device *ndev = platform_get_drvdata(pdev);
3246 struct fec_enet_private *fep = netdev_priv(ndev);
3248 if (!gpio_is_valid(fep->phy_reset_gpio))
3251 gpio_set_value_cansleep(fep->phy_reset_gpio, 0);
3252 msleep(fep->phy_reset_duration);
3253 gpio_set_value_cansleep(fep->phy_reset_gpio, 1);
3256 static int fec_get_reset_gpio(struct platform_device *pdev)
3260 struct device_node *np = pdev->dev.of_node;
3261 struct net_device *ndev = platform_get_drvdata(pdev);
3262 struct fec_enet_private *fep = netdev_priv(ndev);
3264 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3265 if (!gpio_is_valid(phy_reset))
3268 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3269 GPIOF_OUT_INIT_LOW, "phy-reset");
3271 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3275 of_property_read_u32(np, "phy-reset-duration", &msec);
3276 /* A sane reset duration should not be longer than 1s */
3279 fep->phy_reset_duration = msec;
3283 #else /* CONFIG_OF */
3284 static void fec_reset_phy(struct platform_device *pdev)
3287 * In case of platform probe, the reset has been done
3292 static inline int fec_get_reset_gpio(struct platform_device *pdev)
3296 #endif /* CONFIG_OF */
3299 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3301 struct device_node *np = pdev->dev.of_node;
3304 *num_tx = *num_rx = 1;
3306 if (!np || !of_device_is_available(np))
3309 /* parse the num of tx and rx queues */
3310 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3314 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3318 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3319 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3325 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3326 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3335 fec_probe(struct platform_device *pdev)
3337 struct fec_enet_private *fep;
3338 struct fec_platform_data *pdata;
3339 struct net_device *ndev;
3340 int i, irq, ret = 0;
3342 const struct of_device_id *of_id;
3344 struct device_node *np = pdev->dev.of_node, *phy_node;
3348 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3350 /* Init network device */
3351 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3352 num_tx_qs, num_rx_qs);
3356 SET_NETDEV_DEV(ndev, &pdev->dev);
3358 /* setup board info structure */
3359 fep = netdev_priv(ndev);
3361 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3363 pdev->id_entry = of_id->data;
3364 fep->quirks = pdev->id_entry->driver_data;
3367 fep->num_rx_queues = num_rx_qs;
3368 fep->num_tx_queues = num_tx_qs;
3370 #if !defined(CONFIG_M5272)
3371 /* default enable pause frame auto negotiation */
3372 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3373 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3376 /* Select default pin state */
3377 pinctrl_pm_select_default_state(&pdev->dev);
3379 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3380 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3381 if (IS_ERR(fep->hwp)) {
3382 ret = PTR_ERR(fep->hwp);
3383 goto failed_ioremap;
3387 fep->dev_id = dev_id++;
3389 platform_set_drvdata(pdev, ndev);
3391 ret = fec_get_reset_gpio(pdev);
3392 if (ret == -EPROBE_DEFER)
3394 fep->phy_reset_gpio = ret;
3396 if (of_get_property(np, "fsl,magic-packet", NULL))
3397 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3399 phy_node = of_parse_phandle(np, "phy-handle", 0);
3400 if (!phy_node && of_phy_is_fixed_link(np)) {
3401 ret = of_phy_register_fixed_link(np);
3404 "broken fixed-link specification\n");
3407 phy_node = of_node_get(np);
3409 fep->phy_node = phy_node;
3411 ret = of_get_phy_mode(pdev->dev.of_node);
3413 pdata = dev_get_platdata(&pdev->dev);
3415 fep->phy_interface = pdata->phy;
3417 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3419 fep->phy_interface = ret;
3422 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3423 if (IS_ERR(fep->clk_ipg)) {
3424 ret = PTR_ERR(fep->clk_ipg);
3428 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3429 if (IS_ERR(fep->clk_ahb)) {
3430 ret = PTR_ERR(fep->clk_ahb);
3434 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3436 /* enet_out is optional, depends on board */
3437 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3438 if (IS_ERR(fep->clk_enet_out))
3439 fep->clk_enet_out = NULL;
3441 fep->ptp_clk_on = false;
3442 mutex_init(&fep->ptp_clk_mutex);
3444 /* clk_ref is optional, depends on board */
3445 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3446 if (IS_ERR(fep->clk_ref))
3447 fep->clk_ref = NULL;
3449 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3450 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3451 if (IS_ERR(fep->clk_ptp)) {
3452 fep->clk_ptp = NULL;
3453 fep->bufdesc_ex = false;
3456 ret = fec_enet_clk_enable(ndev, true);
3460 ret = clk_prepare_enable(fep->clk_ipg);
3462 goto failed_clk_ipg;
3464 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3465 if (!IS_ERR(fep->reg_phy)) {
3466 ret = regulator_enable(fep->reg_phy);
3469 "Failed to enable phy regulator: %d\n", ret);
3470 goto failed_regulator;
3473 fep->reg_phy = NULL;
3476 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3477 pm_runtime_use_autosuspend(&pdev->dev);
3478 pm_runtime_get_noresume(&pdev->dev);
3479 pm_runtime_set_active(&pdev->dev);
3480 pm_runtime_enable(&pdev->dev);
3482 fec_reset_phy(pdev);
3484 if (fep->bufdesc_ex)
3487 ret = fec_enet_init(ndev);
3491 for (i = 0; i < FEC_IRQ_NUM; i++) {
3492 irq = platform_get_irq(pdev, i);
3499 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3500 0, pdev->name, ndev);
3507 init_completion(&fep->mdio_done);
3508 ret = fec_enet_mii_init(pdev);
3510 goto failed_mii_init;
3512 /* Carrier starts down, phylib will bring it up */
3513 netif_carrier_off(ndev);
3514 fec_enet_clk_enable(ndev, false);
3515 pinctrl_pm_select_sleep_state(&pdev->dev);
3517 ret = register_netdev(ndev);
3519 goto failed_register;
3521 device_init_wakeup(&ndev->dev, fep->wol_flag &
3522 FEC_WOL_HAS_MAGIC_PACKET);
3524 if (fep->bufdesc_ex && fep->ptp_clock)
3525 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3527 fep->rx_copybreak = COPYBREAK_DEFAULT;
3528 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3530 pm_runtime_mark_last_busy(&pdev->dev);
3531 pm_runtime_put_autosuspend(&pdev->dev);
3536 fec_enet_mii_remove(fep);
3542 regulator_disable(fep->reg_phy);
3544 clk_disable_unprepare(fep->clk_ipg);
3546 fec_enet_clk_enable(ndev, false);
3549 of_node_put(phy_node);
3558 fec_drv_remove(struct platform_device *pdev)
3560 struct net_device *ndev = platform_get_drvdata(pdev);
3561 struct fec_enet_private *fep = netdev_priv(ndev);
3563 cancel_work_sync(&fep->tx_timeout_work);
3565 unregister_netdev(ndev);
3566 fec_enet_mii_remove(fep);
3568 regulator_disable(fep->reg_phy);
3569 of_node_put(fep->phy_node);
3575 static int __maybe_unused fec_suspend(struct device *dev)
3577 struct net_device *ndev = dev_get_drvdata(dev);
3578 struct fec_enet_private *fep = netdev_priv(ndev);
3581 if (netif_running(ndev)) {
3582 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3583 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3584 phy_stop(fep->phy_dev);
3585 napi_disable(&fep->napi);
3586 netif_tx_lock_bh(ndev);
3587 netif_device_detach(ndev);
3588 netif_tx_unlock_bh(ndev);
3590 fec_enet_clk_enable(ndev, false);
3591 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3592 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3596 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3597 regulator_disable(fep->reg_phy);
3599 /* SOC supply clock to phy, when clock is disabled, phy link down
3600 * SOC control phy regulator, when regulator is disabled, phy link down
3602 if (fep->clk_enet_out || fep->reg_phy)
3608 static int __maybe_unused fec_resume(struct device *dev)
3610 struct net_device *ndev = dev_get_drvdata(dev);
3611 struct fec_enet_private *fep = netdev_priv(ndev);
3612 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3616 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3617 ret = regulator_enable(fep->reg_phy);
3623 if (netif_running(ndev)) {
3624 ret = fec_enet_clk_enable(ndev, true);
3629 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3630 if (pdata && pdata->sleep_mode_enable)
3631 pdata->sleep_mode_enable(false);
3632 val = readl(fep->hwp + FEC_ECNTRL);
3633 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3634 writel(val, fep->hwp + FEC_ECNTRL);
3635 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3637 pinctrl_pm_select_default_state(&fep->pdev->dev);
3640 netif_tx_lock_bh(ndev);
3641 netif_device_attach(ndev);
3642 netif_tx_unlock_bh(ndev);
3643 napi_enable(&fep->napi);
3644 phy_start(fep->phy_dev);
3652 regulator_disable(fep->reg_phy);
3656 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3658 struct net_device *ndev = dev_get_drvdata(dev);
3659 struct fec_enet_private *fep = netdev_priv(ndev);
3661 clk_disable_unprepare(fep->clk_ipg);
3666 static int __maybe_unused fec_runtime_resume(struct device *dev)
3668 struct net_device *ndev = dev_get_drvdata(dev);
3669 struct fec_enet_private *fep = netdev_priv(ndev);
3671 return clk_prepare_enable(fep->clk_ipg);
3674 static const struct dev_pm_ops fec_pm_ops = {
3675 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3676 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3679 static struct platform_driver fec_driver = {
3681 .name = DRIVER_NAME,
3683 .of_match_table = fec_dt_ids,
3685 .id_table = fec_devtype,
3687 .remove = fec_drv_remove,
3690 module_platform_driver(fec_driver);
3692 MODULE_ALIAS("platform:"DRIVER_NAME);
3693 MODULE_LICENSE("GPL");